cache.hh revision 5699:ab3067124402 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 *          Dave Greene
30 *          Steve Reinhardt
31 *          Ron Dreslinski
32 */
33
34/**
35 * @file
36 * Describes a cache based on template policies.
37 */
38
39#ifndef __CACHE_HH__
40#define __CACHE_HH__
41
42#include "base/misc.hh" // fatal, panic, and warn
43
44#include "mem/cache/base.hh"
45#include "mem/cache/blk.hh"
46#include "mem/cache/mshr.hh"
47
48#include "sim/eventq.hh"
49
50//Forward decleration
51class BasePrefetcher;
52
53/**
54 * A template-policy based cache. The behavior of the cache can be altered by
55 * supplying different template policies. TagStore handles all tag and data
56 * storage @sa TagStore.
57 */
58template <class TagStore>
59class Cache : public BaseCache
60{
61  public:
62    /** Define the type of cache block to use. */
63    typedef typename TagStore::BlkType BlkType;
64    /** A typedef for a list of BlkType pointers. */
65    typedef typename TagStore::BlkList BlkList;
66
67    bool prefetchAccess;
68
69  protected:
70
71    class CpuSidePort : public CachePort
72    {
73      public:
74        CpuSidePort(const std::string &_name,
75                    Cache<TagStore> *_cache,
76                    const std::string &_label,
77                    std::vector<Range<Addr> > filterRanges);
78
79        // BaseCache::CachePort just has a BaseCache *; this function
80        // lets us get back the type info we lost when we stored the
81        // cache pointer there.
82        Cache<TagStore> *myCache() {
83            return static_cast<Cache<TagStore> *>(cache);
84        }
85
86        virtual void getDeviceAddressRanges(AddrRangeList &resp,
87                                            bool &snoop);
88
89        virtual bool recvTiming(PacketPtr pkt);
90
91        virtual Tick recvAtomic(PacketPtr pkt);
92
93        virtual void recvFunctional(PacketPtr pkt);
94    };
95
96    class MemSidePort : public CachePort
97    {
98      public:
99        MemSidePort(const std::string &_name,
100                    Cache<TagStore> *_cache,
101                    const std::string &_label,
102                    std::vector<Range<Addr> > filterRanges);
103
104        // BaseCache::CachePort just has a BaseCache *; this function
105        // lets us get back the type info we lost when we stored the
106        // cache pointer there.
107        Cache<TagStore> *myCache() {
108            return static_cast<Cache<TagStore> *>(cache);
109        }
110
111        void sendPacket();
112
113        void processSendEvent();
114
115        virtual void getDeviceAddressRanges(AddrRangeList &resp,
116                                            bool &snoop);
117
118        virtual bool recvTiming(PacketPtr pkt);
119
120        virtual void recvRetry();
121
122        virtual Tick recvAtomic(PacketPtr pkt);
123
124        virtual void recvFunctional(PacketPtr pkt);
125
126        typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
127                SendEvent;
128    };
129
130    /** Tag and data Storage */
131    TagStore *tags;
132
133    /** Prefetcher */
134    BasePrefetcher *prefetcher;
135
136    /** Temporary cache block for occasional transitory use */
137    BlkType *tempBlock;
138
139    /**
140     * Can this cache should allocate a block on a line-sized write miss.
141     */
142    const bool doFastWrites;
143
144    const bool prefetchMiss;
145
146    /**
147     * Does all the processing necessary to perform the provided request.
148     * @param pkt The memory request to perform.
149     * @param lat The latency of the access.
150     * @param writebacks List for any writebacks that need to be performed.
151     * @param update True if the replacement data should be updated.
152     * @return Pointer to the cache block touched by the request. NULL if it
153     * was a miss.
154     */
155    bool access(PacketPtr pkt, BlkType *&blk,
156                int &lat, PacketList &writebacks);
157
158    /**
159     *Handle doing the Compare and Swap function for SPARC.
160     */
161    void cmpAndSwap(BlkType *blk, PacketPtr pkt);
162
163    /**
164     * Find a block frame for new block at address addr, assuming that
165     * the block is not currently in the cache.  Append writebacks if
166     * any to provided packet list.  Return free block frame.  May
167     * return NULL if there are no replaceable blocks at the moment.
168     */
169    BlkType *allocateBlock(Addr addr, PacketList &writebacks);
170
171    /**
172     * Populates a cache block and handles all outstanding requests for the
173     * satisfied fill request. This version takes two memory requests. One
174     * contains the fill data, the other is an optional target to satisfy.
175     * Used for Cache::probe.
176     * @param pkt The memory request with the fill data.
177     * @param blk The cache block if it already exists.
178     * @param writebacks List for any writebacks that need to be performed.
179     * @return Pointer to the new cache block.
180     */
181    BlkType *handleFill(PacketPtr pkt, BlkType *blk,
182                        PacketList &writebacks);
183
184    void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
185    bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
186
187    void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
188                                bool already_copied, bool pending_inval);
189
190    /**
191     * Sets the blk to the new state.
192     * @param blk The cache block being snooped.
193     * @param new_state The new coherence state for the block.
194     */
195    void handleSnoop(PacketPtr ptk, BlkType *blk,
196                     bool is_timing, bool is_deferred, bool pending_inval);
197
198    /**
199     * Create a writeback request for the given block.
200     * @param blk The block to writeback.
201     * @return The writeback request for the block.
202     */
203    PacketPtr writebackBlk(BlkType *blk);
204
205  public:
206    /** Instantiates a basic cache object. */
207    Cache(const Params *p, TagStore *tags, BasePrefetcher *prefetcher);
208
209    virtual Port *getPort(const std::string &if_name, int idx = -1);
210    virtual void deletePortRefs(Port *p);
211
212    void regStats();
213
214    /**
215     * Performs the access specified by the request.
216     * @param pkt The request to perform.
217     * @return The result of the access.
218     */
219    bool timingAccess(PacketPtr pkt);
220
221    /**
222     * Performs the access specified by the request.
223     * @param pkt The request to perform.
224     * @return The result of the access.
225     */
226    Tick atomicAccess(PacketPtr pkt);
227
228    /**
229     * Performs the access specified by the request.
230     * @param pkt The request to perform.
231     * @return The result of the access.
232     */
233    void functionalAccess(PacketPtr pkt, CachePort *incomingPort,
234                          CachePort *otherSidePort);
235
236    /**
237     * Handles a response (cache line fill/write ack) from the bus.
238     * @param pkt The request being responded to.
239     */
240    void handleResponse(PacketPtr pkt);
241
242    /**
243     * Snoops bus transactions to maintain coherence.
244     * @param pkt The current bus transaction.
245     */
246    void snoopTiming(PacketPtr pkt);
247
248    /**
249     * Snoop for the provided request in the cache and return the estimated
250     * time of completion.
251     * @param pkt The memory request to snoop
252     * @return The estimated completion time.
253     */
254    Tick snoopAtomic(PacketPtr pkt);
255
256    /**
257     * Squash all requests associated with specified thread.
258     * intended for use by I-cache.
259     * @param threadNum The thread to squash.
260     */
261    void squash(int threadNum);
262
263    /**
264     * Generate an appropriate downstream bus request packet for the
265     * given parameters.
266     * @param cpu_pkt  The upstream request that needs to be satisfied.
267     * @param blk The block currently in the cache corresponding to
268     * cpu_pkt (NULL if none).
269     * @param needsExclusive  Indicates that an exclusive copy is required
270     * even if the request in cpu_pkt doesn't indicate that.
271     * @return A new Packet containing the request, or NULL if the
272     * current request in cpu_pkt should just be forwarded on.
273     */
274    PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
275                           bool needsExclusive);
276
277    /**
278     * Return the next MSHR to service, either a pending miss from the
279     * mshrQueue, a buffered write from the write buffer, or something
280     * from the prefetcher.  This function is responsible for
281     * prioritizing among those sources on the fly.
282     */
283    MSHR *getNextMSHR();
284
285    /**
286     * Selects an outstanding request to service.  Called when the
287     * cache gets granted the downstream bus in timing mode.
288     * @return The request to service, NULL if none found.
289     */
290    PacketPtr getTimingPacket();
291
292    /**
293     * Marks a request as in service (sent on the bus). This can have side
294     * effect since storage for no response commands is deallocated once they
295     * are successfully sent.
296     * @param pkt The request that was sent on the bus.
297     */
298    void markInService(MSHR *mshr);
299
300    /**
301     * Perform the given writeback request.
302     * @param pkt The writeback request.
303     */
304    void doWriteback(PacketPtr pkt);
305
306    /**
307     * Return whether there are any outstanding misses.
308     */
309    bool outstandingMisses() const
310    {
311        return mshrQueue.allocated != 0;
312    }
313
314    CacheBlk *findBlock(Addr addr) {
315        return tags->findBlock(addr);
316    }
317
318    bool inCache(Addr addr) {
319        return (tags->findBlock(addr) != 0);
320    }
321
322    bool inMissQueue(Addr addr) {
323        return (mshrQueue.findMatch(addr) != 0);
324    }
325};
326
327#endif // __CACHE_HH__
328