cache.hh revision 5365
12623SN/A/* 27725SAli.Saidi@ARM.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 37725SAli.Saidi@ARM.com * All rights reserved. 47725SAli.Saidi@ARM.com * 57725SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67725SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77725SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87725SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97725SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107725SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117725SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127725SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137725SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272623SN/A * 282623SN/A * Authors: Erik Hallnor 292623SN/A * Dave Greene 302623SN/A * Steve Reinhardt 312623SN/A * Ron Dreslinski 322623SN/A */ 332623SN/A 342623SN/A/** 352623SN/A * @file 362623SN/A * Describes a cache based on template policies. 372623SN/A */ 382623SN/A 392665Ssaidi@eecs.umich.edu#ifndef __CACHE_HH__ 402665Ssaidi@eecs.umich.edu#define __CACHE_HH__ 412623SN/A 422623SN/A#include "base/misc.hh" // fatal, panic, and warn 433170Sstever@eecs.umich.edu 448105Sgblack@eecs.umich.edu#include "mem/cache/base.hh" 452623SN/A#include "mem/cache/blk.hh" 464040Ssaidi@eecs.umich.edu#include "mem/cache/mshr.hh" 476658Snate@binkert.org 488229Snate@binkert.org#include "sim/eventq.hh" 492623SN/A 508232Snate@binkert.org//Forward decleration 518232Snate@binkert.orgclass BasePrefetcher; 528232Snate@binkert.org 533348Sbinkertn@umich.edu/** 543348Sbinkertn@umich.edu * A template-policy based cache. The behavior of the cache can be altered by 554762Snate@binkert.org * supplying different template policies. TagStore handles all tag and data 567678Sgblack@eecs.umich.edu * storage @sa TagStore. 572901Ssaidi@eecs.umich.edu */ 582623SN/Atemplate <class TagStore> 592623SN/Aclass Cache : public BaseCache 602623SN/A{ 612623SN/A public: 622856Srdreslin@umich.edu /** Define the type of cache block to use. */ 632856Srdreslin@umich.edu typedef typename TagStore::BlkType BlkType; 642856Srdreslin@umich.edu /** A typedef for a list of BlkType pointers. */ 652856Srdreslin@umich.edu typedef typename TagStore::BlkList BlkList; 662856Srdreslin@umich.edu 672856Srdreslin@umich.edu bool prefetchAccess; 682856Srdreslin@umich.edu 692856Srdreslin@umich.edu protected: 702856Srdreslin@umich.edu 712856Srdreslin@umich.edu class CpuSidePort : public CachePort 722623SN/A { 732623SN/A public: 742623SN/A CpuSidePort(const std::string &_name, 752623SN/A Cache<TagStore> *_cache, 762623SN/A const std::string &_label, 772623SN/A std::vector<Range<Addr> > filterRanges); 782680Sktlim@umich.edu 792680Sktlim@umich.edu // BaseCache::CachePort just has a BaseCache *; this function 802623SN/A // lets us get back the type info we lost when we stored the 812623SN/A // cache pointer there. 825712Shsul@eecs.umich.edu Cache<TagStore> *myCache() { 832623SN/A return static_cast<Cache<TagStore> *>(cache); 848706Sandreas.hansson@arm.com } 858706Sandreas.hansson@arm.com 868706Sandreas.hansson@arm.com virtual void getDeviceAddressRanges(AddrRangeList &resp, 872623SN/A bool &snoop); 882623SN/A 892623SN/A virtual bool recvTiming(PacketPtr pkt); 902623SN/A 913349Sbinkertn@umich.edu virtual Tick recvAtomic(PacketPtr pkt); 922623SN/A 932623SN/A virtual void recvFunctional(PacketPtr pkt); 947823Ssteve.reinhardt@amd.com }; 952623SN/A 962623SN/A class MemSidePort : public CachePort 972623SN/A { 983349Sbinkertn@umich.edu public: 992623SN/A MemSidePort(const std::string &_name, 1003184Srdreslin@umich.edu Cache<TagStore> *_cache, 1013184Srdreslin@umich.edu const std::string &_label, 1022623SN/A std::vector<Range<Addr> > filterRanges); 1032623SN/A 1042623SN/A // BaseCache::CachePort just has a BaseCache *; this function 1052623SN/A // lets us get back the type info we lost when we stored the 1062623SN/A // cache pointer there. 1073647Srdreslin@umich.edu Cache<TagStore> *myCache() { 1083647Srdreslin@umich.edu return static_cast<Cache<TagStore> *>(cache); 1093647Srdreslin@umich.edu } 1103647Srdreslin@umich.edu 1113647Srdreslin@umich.edu void sendPacket(); 1122631SN/A 1133647Srdreslin@umich.edu void processSendEvent(); 1142631SN/A 1152623SN/A virtual void getDeviceAddressRanges(AddrRangeList &resp, 1162623SN/A bool &snoop); 1172623SN/A 1182948Ssaidi@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 1192948Ssaidi@eecs.umich.edu 1203349Sbinkertn@umich.edu virtual void recvRetry(); 1212948Ssaidi@eecs.umich.edu 1222948Ssaidi@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 1235606Snate@binkert.org 1242948Ssaidi@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 1252948Ssaidi@eecs.umich.edu 1265529Snate@binkert.org typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent> 1275894Sgblack@eecs.umich.edu SendEvent; 1285894Sgblack@eecs.umich.edu }; 1292623SN/A 1302623SN/A /** Tag and data Storage */ 1313647Srdreslin@umich.edu TagStore *tags; 1323647Srdreslin@umich.edu 1333647Srdreslin@umich.edu /** Prefetcher */ 1343647Srdreslin@umich.edu BasePrefetcher *prefetcher; 1352623SN/A 1362839Sktlim@umich.edu /** Temporary cache block for occasional transitory use */ 1373222Sktlim@umich.edu BlkType *tempBlock; 1382901Ssaidi@eecs.umich.edu 1397897Shestness@cs.utexas.edu /** 1402623SN/A * Can this cache should allocate a block on a line-sized write miss. 1412623SN/A */ 1422623SN/A const bool doFastWrites; 1432623SN/A 1442623SN/A const bool prefetchMiss; 1452623SN/A 1462623SN/A /** 1472623SN/A * Handle a replacement for the given request. 1482623SN/A * @param blk A pointer to the block, usually NULL 1492623SN/A * @param pkt The memory request to satisfy. 1502915Sktlim@umich.edu * @param new_state The new state of the block. 1512915Sktlim@umich.edu * @param writebacks A list to store any generated writebacks. 1522623SN/A */ 1532623SN/A BlkType* doReplacement(BlkType *blk, PacketPtr pkt, 1542623SN/A CacheBlk::State new_state, PacketList &writebacks); 1552623SN/A 1562623SN/A /** 1572623SN/A * Does all the processing necessary to perform the provided request. 1582915Sktlim@umich.edu * @param pkt The memory request to perform. 1592915Sktlim@umich.edu * @param lat The latency of the access. 1602623SN/A * @param writebacks List for any writebacks that need to be performed. 1612798Sktlim@umich.edu * @param update True if the replacement data should be updated. 1622798Sktlim@umich.edu * @return Pointer to the cache block touched by the request. NULL if it 1632901Ssaidi@eecs.umich.edu * was a miss. 1642839Sktlim@umich.edu */ 1652798Sktlim@umich.edu bool access(PacketPtr pkt, BlkType *&blk, int &lat); 1662839Sktlim@umich.edu 1672798Sktlim@umich.edu /** 1685496Ssaidi@eecs.umich.edu *Handle doing the Compare and Swap function for SPARC. 1692901Ssaidi@eecs.umich.edu */ 1702901Ssaidi@eecs.umich.edu void cmpAndSwap(BlkType *blk, PacketPtr pkt); 1712798Sktlim@umich.edu 1722839Sktlim@umich.edu /** 1732839Sktlim@umich.edu * Find a block frame for new block at address addr, assuming that 1742901Ssaidi@eecs.umich.edu * the block is not currently in the cache. Append writebacks if 1752798Sktlim@umich.edu * any to provided packet list. Return free block frame. May 1762623SN/A * return NULL if there are no replaceable blocks at the moment. 1772623SN/A */ 1782623SN/A BlkType *allocateBlock(Addr addr, PacketList &writebacks); 1792798Sktlim@umich.edu 1802623SN/A /** 1815221Ssaidi@eecs.umich.edu * Populates a cache block and handles all outstanding requests for the 1822798Sktlim@umich.edu * satisfied fill request. This version takes two memory requests. One 1834762Snate@binkert.org * contains the fill data, the other is an optional target to satisfy. 1843201Shsul@eecs.umich.edu * Used for Cache::probe. 1855710Scws3k@cs.virginia.edu * @param pkt The memory request with the fill data. 1865710Scws3k@cs.virginia.edu * @param blk The cache block if it already exists. 1872915Sktlim@umich.edu * @param writebacks List for any writebacks that need to be performed. 1885710Scws3k@cs.virginia.edu * @return Pointer to the new cache block. 1892623SN/A */ 1902798Sktlim@umich.edu BlkType *handleFill(PacketPtr pkt, BlkType *blk, 1912901Ssaidi@eecs.umich.edu PacketList &writebacks); 1922798Sktlim@umich.edu 1932798Sktlim@umich.edu void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk); 1942798Sktlim@umich.edu bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk); 1952798Sktlim@umich.edu 1962798Sktlim@umich.edu void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data, 1975496Ssaidi@eecs.umich.edu bool already_copied, bool pending_inval); 1982798Sktlim@umich.edu 1997823Ssteve.reinhardt@amd.com /** 2002867Sktlim@umich.edu * Sets the blk to the new state. 2012867Sktlim@umich.edu * @param blk The cache block being snooped. 2022867Sktlim@umich.edu * @param new_state The new coherence state for the block. 2035710Scws3k@cs.virginia.edu */ 2045606Snate@binkert.org void handleSnoop(PacketPtr ptk, BlkType *blk, 2052623SN/A bool is_timing, bool is_deferred, bool pending_inval); 2062623SN/A 2072623SN/A /** 2082623SN/A * Create a writeback request for the given block. 2092623SN/A * @param blk The block to writeback. 2102623SN/A * @return The writeback request for the block. 2114192Sktlim@umich.edu */ 2122623SN/A PacketPtr writebackBlk(BlkType *blk); 2132680Sktlim@umich.edu 2142623SN/A public: 2152680Sktlim@umich.edu /** Instantiates a basic cache object. */ 2162680Sktlim@umich.edu Cache(const Params *p, TagStore *tags, BasePrefetcher *prefetcher); 2172680Sktlim@umich.edu 2182623SN/A virtual Port *getPort(const std::string &if_name, int idx = -1); 2192623SN/A virtual void deletePortRefs(Port *p); 2202623SN/A 2212623SN/A void regStats(); 2223201Shsul@eecs.umich.edu 2233201Shsul@eecs.umich.edu /** 2243201Shsul@eecs.umich.edu * Performs the access specified by the request. 2253201Shsul@eecs.umich.edu * @param pkt The request to perform. 2265169Ssaidi@eecs.umich.edu * @return The result of the access. 2277823Ssteve.reinhardt@amd.com */ 2282623SN/A bool timingAccess(PacketPtr pkt); 2292623SN/A 2302623SN/A /** 2312623SN/A * Performs the access specified by the request. 2322623SN/A * @param pkt The request to perform. 2332623SN/A * @return The result of the access. 2345221Ssaidi@eecs.umich.edu */ 2355221Ssaidi@eecs.umich.edu Tick atomicAccess(PacketPtr pkt); 2362623SN/A 2372683Sktlim@umich.edu /** 2382623SN/A * Performs the access specified by the request. 2392623SN/A * @param pkt The request to perform. 2402623SN/A * @return The result of the access. 2412623SN/A */ 2422623SN/A void functionalAccess(PacketPtr pkt, CachePort *incomingPort, 2433686Sktlim@umich.edu CachePort *otherSidePort); 2442623SN/A 2457823Ssteve.reinhardt@amd.com /** 2462623SN/A * Handles a response (cache line fill/write ack) from the bus. 2472623SN/A * @param pkt The request being responded to. 2482623SN/A */ 2492623SN/A void handleResponse(PacketPtr pkt); 2502623SN/A 2512623SN/A /** 2525221Ssaidi@eecs.umich.edu * Snoops bus transactions to maintain coherence. 2535221Ssaidi@eecs.umich.edu * @param pkt The current bus transaction. 2542623SN/A */ 2552683Sktlim@umich.edu void snoopTiming(PacketPtr pkt); 2562623SN/A 2576043Sgblack@eecs.umich.edu /** 2586043Sgblack@eecs.umich.edu * Snoop for the provided request in the cache and return the estimated 2596043Sgblack@eecs.umich.edu * time of completion. 2602644Sstever@eecs.umich.edu * @param pkt The memory request to snoop 2612623SN/A * @return The estimated completion time. 2622644Sstever@eecs.umich.edu */ 2632644Sstever@eecs.umich.edu Tick snoopAtomic(PacketPtr pkt); 2642623SN/A 2652623SN/A /** 2662623SN/A * Squash all requests associated with specified thread. 2672623SN/A * intended for use by I-cache. 2682623SN/A * @param threadNum The thread to squash. 2695728Sgblack@eecs.umich.edu */ 2705728Sgblack@eecs.umich.edu void squash(int threadNum); 2715728Sgblack@eecs.umich.edu 2725728Sgblack@eecs.umich.edu /** 2738105Sgblack@eecs.umich.edu * Generate an appropriate downstream bus request packet for the 2745728Sgblack@eecs.umich.edu * given parameters. 2755728Sgblack@eecs.umich.edu * @param cpu_pkt The upstream request that needs to be satisfied. 2767823Ssteve.reinhardt@amd.com * @param blk The block currently in the cache corresponding to 2775728Sgblack@eecs.umich.edu * cpu_pkt (NULL if none). 2785728Sgblack@eecs.umich.edu * @param needsExclusive Indicates that an exclusive copy is required 2795728Sgblack@eecs.umich.edu * even if the request in cpu_pkt doesn't indicate that. 2805728Sgblack@eecs.umich.edu * @return A new Packet containing the request, or NULL if the 2815728Sgblack@eecs.umich.edu * current request in cpu_pkt should just be forwarded on. 2825728Sgblack@eecs.umich.edu */ 2835728Sgblack@eecs.umich.edu PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk, 2845728Sgblack@eecs.umich.edu bool needsExclusive); 2855728Sgblack@eecs.umich.edu 2865728Sgblack@eecs.umich.edu /** 2875728Sgblack@eecs.umich.edu * Return the next MSHR to service, either a pending miss from the 2885728Sgblack@eecs.umich.edu * mshrQueue, a buffered write from the write buffer, or something 2892623SN/A * from the prefetcher. This function is responsible for 2905894Sgblack@eecs.umich.edu * prioritizing among those sources on the fly. 2916973Stjones1@inf.ed.ac.uk */ 2926973Stjones1@inf.ed.ac.uk MSHR *getNextMSHR(); 2935744Sgblack@eecs.umich.edu 2945894Sgblack@eecs.umich.edu /** 2955894Sgblack@eecs.umich.edu * Selects an outstanding request to service. Called when the 2967691SAli.Saidi@ARM.com * cache gets granted the downstream bus in timing mode. 2975894Sgblack@eecs.umich.edu * @return The request to service, NULL if none found. 2985894Sgblack@eecs.umich.edu */ 2995894Sgblack@eecs.umich.edu PacketPtr getTimingPacket(); 3005894Sgblack@eecs.umich.edu 3015894Sgblack@eecs.umich.edu /** 3025894Sgblack@eecs.umich.edu * Marks a request as in service (sent on the bus). This can have side 3035894Sgblack@eecs.umich.edu * effect since storage for no response commands is deallocated once they 3045894Sgblack@eecs.umich.edu * are successfully sent. 3055894Sgblack@eecs.umich.edu * @param pkt The request that was sent on the bus. 3066102Sgblack@eecs.umich.edu */ 3075894Sgblack@eecs.umich.edu void markInService(MSHR *mshr); 3085894Sgblack@eecs.umich.edu 3095894Sgblack@eecs.umich.edu /** 3105894Sgblack@eecs.umich.edu * Perform the given writeback request. 3115894Sgblack@eecs.umich.edu * @param pkt The writeback request. 3125894Sgblack@eecs.umich.edu */ 3135894Sgblack@eecs.umich.edu void doWriteback(PacketPtr pkt); 3145894Sgblack@eecs.umich.edu 3155894Sgblack@eecs.umich.edu /** 3165894Sgblack@eecs.umich.edu * Return whether there are any outstanding misses. 3175894Sgblack@eecs.umich.edu */ 3185894Sgblack@eecs.umich.edu bool outstandingMisses() const 3195894Sgblack@eecs.umich.edu { 3205894Sgblack@eecs.umich.edu return mshrQueue.allocated != 0; 3215894Sgblack@eecs.umich.edu } 3225894Sgblack@eecs.umich.edu 3235894Sgblack@eecs.umich.edu CacheBlk *findBlock(Addr addr) { 3246973Stjones1@inf.ed.ac.uk return tags->findBlock(addr); 3256973Stjones1@inf.ed.ac.uk } 3265894Sgblack@eecs.umich.edu 3275894Sgblack@eecs.umich.edu bool inCache(Addr addr) { 3285894Sgblack@eecs.umich.edu return (tags->findBlock(addr) != 0); 3295894Sgblack@eecs.umich.edu } 3305894Sgblack@eecs.umich.edu 3315894Sgblack@eecs.umich.edu bool inMissQueue(Addr addr) { 3325894Sgblack@eecs.umich.edu return (mshrQueue.findMatch(addr) != 0); 3335894Sgblack@eecs.umich.edu } 3347911Shestness@cs.utexas.edu}; 3357911Shestness@cs.utexas.edu 3365894Sgblack@eecs.umich.edu#endif // __CACHE_HH__ 3375894Sgblack@eecs.umich.edu