cache.hh revision 4905:0ccda2bb3be7 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 *          Dave Greene
30 *          Steve Reinhardt
31 *          Ron Dreslinski
32 */
33
34/**
35 * @file
36 * Describes a cache based on template policies.
37 */
38
39#ifndef __CACHE_HH__
40#define __CACHE_HH__
41
42#include "base/misc.hh" // fatal, panic, and warn
43
44#include "mem/cache/base_cache.hh"
45#include "mem/cache/cache_blk.hh"
46#include "mem/cache/miss/mshr.hh"
47
48#include "sim/eventq.hh"
49
50//Forward decleration
51class BasePrefetcher;
52
53/**
54 * A template-policy based cache. The behavior of the cache can be altered by
55 * supplying different template policies. TagStore handles all tag and data
56 * storage @sa TagStore.
57 */
58template <class TagStore>
59class Cache : public BaseCache
60{
61  public:
62    /** Define the type of cache block to use. */
63    typedef typename TagStore::BlkType BlkType;
64    /** A typedef for a list of BlkType pointers. */
65    typedef typename TagStore::BlkList BlkList;
66
67    bool prefetchAccess;
68
69  protected:
70
71    class CpuSidePort : public CachePort
72    {
73      public:
74        CpuSidePort(const std::string &_name,
75                    Cache<TagStore> *_cache);
76
77        // BaseCache::CachePort just has a BaseCache *; this function
78        // lets us get back the type info we lost when we stored the
79        // cache pointer there.
80        Cache<TagStore> *myCache() {
81            return static_cast<Cache<TagStore> *>(cache);
82        }
83
84        virtual void getDeviceAddressRanges(AddrRangeList &resp,
85                                            bool &snoop);
86
87        virtual bool recvTiming(PacketPtr pkt);
88
89        virtual Tick recvAtomic(PacketPtr pkt);
90
91        virtual void recvFunctional(PacketPtr pkt);
92    };
93
94    class MemSidePort : public CachePort
95    {
96      public:
97        MemSidePort(const std::string &_name,
98                    Cache<TagStore> *_cache);
99
100        // BaseCache::CachePort just has a BaseCache *; this function
101        // lets us get back the type info we lost when we stored the
102        // cache pointer there.
103        Cache<TagStore> *myCache() {
104            return static_cast<Cache<TagStore> *>(cache);
105        }
106
107        void sendPacket();
108
109        void processSendEvent();
110
111        virtual void getDeviceAddressRanges(AddrRangeList &resp,
112                                            bool &snoop);
113
114        virtual bool recvTiming(PacketPtr pkt);
115
116        virtual void recvRetry();
117
118        virtual Tick recvAtomic(PacketPtr pkt);
119
120        virtual void recvFunctional(PacketPtr pkt);
121
122        typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
123                SendEvent;
124    };
125
126    /** Tag and data Storage */
127    TagStore *tags;
128
129    /** Prefetcher */
130    BasePrefetcher *prefetcher;
131
132    /** Temporary cache block for occasional transitory use */
133    BlkType *tempBlock;
134
135    /**
136     * Can this cache should allocate a block on a line-sized write miss.
137     */
138    const bool doFastWrites;
139
140    const bool prefetchMiss;
141
142    /**
143     * Handle a replacement for the given request.
144     * @param blk A pointer to the block, usually NULL
145     * @param pkt The memory request to satisfy.
146     * @param new_state The new state of the block.
147     * @param writebacks A list to store any generated writebacks.
148     */
149    BlkType* doReplacement(BlkType *blk, PacketPtr pkt,
150                           CacheBlk::State new_state, PacketList &writebacks);
151
152    /**
153     * Does all the processing necessary to perform the provided request.
154     * @param pkt The memory request to perform.
155     * @param lat The latency of the access.
156     * @param writebacks List for any writebacks that need to be performed.
157     * @param update True if the replacement data should be updated.
158     * @return Pointer to the cache block touched by the request. NULL if it
159     * was a miss.
160     */
161    bool access(PacketPtr pkt, BlkType *&blk, int &lat);
162
163    /**
164     *Handle doing the Compare and Swap function for SPARC.
165     */
166    void cmpAndSwap(BlkType *blk, PacketPtr pkt);
167
168    /**
169     * Populates a cache block and handles all outstanding requests for the
170     * satisfied fill request. This version takes two memory requests. One
171     * contains the fill data, the other is an optional target to satisfy.
172     * Used for Cache::probe.
173     * @param pkt The memory request with the fill data.
174     * @param blk The cache block if it already exists.
175     * @param writebacks List for any writebacks that need to be performed.
176     * @return Pointer to the new cache block.
177     */
178    BlkType *handleFill(PacketPtr pkt, BlkType *blk,
179                        PacketList &writebacks);
180
181    void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
182    bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
183
184    void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
185                                bool already_copied);
186
187    /**
188     * Sets the blk to the new state.
189     * @param blk The cache block being snooped.
190     * @param new_state The new coherence state for the block.
191     */
192    void handleSnoop(PacketPtr ptk, BlkType *blk,
193                     bool is_timing, bool is_deferred,
194                     bool lower_mshr_pending);
195
196    /**
197     * Create a writeback request for the given block.
198     * @param blk The block to writeback.
199     * @return The writeback request for the block.
200     */
201    PacketPtr writebackBlk(BlkType *blk);
202
203  public:
204
205    class Params
206    {
207      public:
208        TagStore *tags;
209        BaseCache::Params baseParams;
210        BasePrefetcher*prefetcher;
211        bool prefetchAccess;
212        const bool doFastWrites;
213        const bool prefetchMiss;
214
215        Params(TagStore *_tags,
216               BaseCache::Params params,
217               BasePrefetcher *_prefetcher,
218               bool prefetch_access, int hit_latency,
219               bool do_fast_writes,
220               bool prefetch_miss)
221            : tags(_tags),
222              baseParams(params),
223              prefetcher(_prefetcher), prefetchAccess(prefetch_access),
224              doFastWrites(do_fast_writes),
225              prefetchMiss(prefetch_miss)
226        {
227        }
228    };
229
230    /** Instantiates a basic cache object. */
231    Cache(const std::string &_name, Params &params);
232
233    virtual Port *getPort(const std::string &if_name, int idx = -1);
234    virtual void deletePortRefs(Port *p);
235
236    void regStats();
237
238    /**
239     * Performs the access specified by the request.
240     * @param pkt The request to perform.
241     * @return The result of the access.
242     */
243    bool timingAccess(PacketPtr pkt);
244
245    /**
246     * Performs the access specified by the request.
247     * @param pkt The request to perform.
248     * @return The result of the access.
249     */
250    Tick atomicAccess(PacketPtr pkt);
251
252    /**
253     * Performs the access specified by the request.
254     * @param pkt The request to perform.
255     * @return The result of the access.
256     */
257    void functionalAccess(PacketPtr pkt, CachePort *otherSidePort);
258
259    /**
260     * Handles a response (cache line fill/write ack) from the bus.
261     * @param pkt The request being responded to.
262     */
263    void handleResponse(PacketPtr pkt);
264
265    /**
266     * Snoops bus transactions to maintain coherence.
267     * @param pkt The current bus transaction.
268     */
269    void snoopTiming(PacketPtr pkt);
270
271    /**
272     * Snoop for the provided request in the cache and return the estimated
273     * time of completion.
274     * @param pkt The memory request to snoop
275     * @return The estimated completion time.
276     */
277    Tick snoopAtomic(PacketPtr pkt);
278
279    /**
280     * Squash all requests associated with specified thread.
281     * intended for use by I-cache.
282     * @param threadNum The thread to squash.
283     */
284    void squash(int threadNum);
285
286    /**
287     * Selects a outstanding request to service.
288     * @return The request to service, NULL if none found.
289     */
290    PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
291                           bool needsExclusive);
292    MSHR *getNextMSHR();
293    PacketPtr getTimingPacket();
294
295    /**
296     * Marks a request as in service (sent on the bus). This can have side
297     * effect since storage for no response commands is deallocated once they
298     * are successfully sent.
299     * @param pkt The request that was sent on the bus.
300     */
301    void markInService(MSHR *mshr);
302
303    /**
304     * Perform the given writeback request.
305     * @param pkt The writeback request.
306     */
307    void doWriteback(PacketPtr pkt);
308
309    /**
310     * Return whether there are any outstanding misses.
311     */
312    bool outstandingMisses() const
313    {
314        return mshrQueue.allocated != 0;
315    }
316
317    CacheBlk *findBlock(Addr addr) {
318        return tags->findBlock(addr);
319    }
320
321    bool inCache(Addr addr) {
322        return (tags->findBlock(addr) != 0);
323    }
324
325    bool inMissQueue(Addr addr) {
326        return (mshrQueue.findMatch(addr) != 0);
327    }
328};
329
330#endif // __CACHE_HH__
331