cache.hh revision 4628:17b3ce796176
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 * Dave Greene 30 * Steve Reinhardt 31 * Ron Dreslinski 32 */ 33 34/** 35 * @file 36 * Describes a cache based on template policies. 37 */ 38 39#ifndef __CACHE_HH__ 40#define __CACHE_HH__ 41 42#include "base/compression/base.hh" 43#include "base/misc.hh" // fatal, panic, and warn 44#include "cpu/smt.hh" // SMT_MAX_THREADS 45 46#include "mem/cache/base_cache.hh" 47#include "mem/cache/cache_blk.hh" 48#include "mem/cache/miss/mshr.hh" 49 50#include "sim/eventq.hh" 51 52//Forward decleration 53class BasePrefetcher; 54 55/** 56 * A template-policy based cache. The behavior of the cache can be altered by 57 * supplying different template policies. TagStore handles all tag and data 58 * storage @sa TagStore. Buffering handles all misses and writes/writebacks 59 * @sa MissQueue. Coherence handles all coherence policy details @sa 60 * UniCoherence, SimpleMultiCoherence. 61 */ 62template <class TagStore, class Coherence> 63class Cache : public BaseCache 64{ 65 public: 66 /** Define the type of cache block to use. */ 67 typedef typename TagStore::BlkType BlkType; 68 /** A typedef for a list of BlkType pointers. */ 69 typedef typename TagStore::BlkList BlkList; 70 71 bool prefetchAccess; 72 73 protected: 74 75 class CpuSidePort : public CachePort 76 { 77 public: 78 CpuSidePort(const std::string &_name, 79 Cache<TagStore,Coherence> *_cache); 80 81 // BaseCache::CachePort just has a BaseCache *; this function 82 // lets us get back the type info we lost when we stored the 83 // cache pointer there. 84 Cache<TagStore,Coherence> *myCache() { 85 return static_cast<Cache<TagStore,Coherence> *>(cache); 86 } 87 88 virtual void getDeviceAddressRanges(AddrRangeList &resp, 89 bool &snoop); 90 91 virtual bool recvTiming(PacketPtr pkt); 92 93 virtual Tick recvAtomic(PacketPtr pkt); 94 95 virtual void recvFunctional(PacketPtr pkt); 96 }; 97 98 class MemSidePort : public CachePort 99 { 100 public: 101 MemSidePort(const std::string &_name, 102 Cache<TagStore,Coherence> *_cache); 103 104 // BaseCache::CachePort just has a BaseCache *; this function 105 // lets us get back the type info we lost when we stored the 106 // cache pointer there. 107 Cache<TagStore,Coherence> *myCache() { 108 return static_cast<Cache<TagStore,Coherence> *>(cache); 109 } 110 111 void sendPacket(); 112 113 void processSendEvent(); 114 115 virtual void getDeviceAddressRanges(AddrRangeList &resp, 116 bool &snoop); 117 118 virtual bool recvTiming(PacketPtr pkt); 119 120 virtual void recvRetry(); 121 122 virtual Tick recvAtomic(PacketPtr pkt); 123 124 virtual void recvFunctional(PacketPtr pkt); 125 126 typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent> 127 SendEvent; 128 }; 129 130 /** Tag and data Storage */ 131 TagStore *tags; 132 133 /** Coherence protocol. */ 134 Coherence *coherence; 135 136 /** Prefetcher */ 137 BasePrefetcher *prefetcher; 138 139 /** 140 * The clock ratio of the outgoing bus. 141 * Used for calculating critical word first. 142 */ 143 int busRatio; 144 145 /** 146 * The bus width in bytes of the outgoing bus. 147 * Used for calculating critical word first. 148 */ 149 int busWidth; 150 151 /** 152 * The latency of a hit in this device. 153 */ 154 int hitLatency; 155 156 /** 157 * Can this cache should allocate a block on a line-sized write miss. 158 */ 159 const bool doFastWrites; 160 161 const bool prefetchMiss; 162 163 /** 164 * Handle a replacement for the given request. 165 * @param blk A pointer to the block, usually NULL 166 * @param pkt The memory request to satisfy. 167 * @param new_state The new state of the block. 168 * @param writebacks A list to store any generated writebacks. 169 */ 170 BlkType* doReplacement(BlkType *blk, PacketPtr pkt, 171 CacheBlk::State new_state, PacketList &writebacks); 172 173 /** 174 * Does all the processing necessary to perform the provided request. 175 * @param pkt The memory request to perform. 176 * @param lat The latency of the access. 177 * @param writebacks List for any writebacks that need to be performed. 178 * @param update True if the replacement data should be updated. 179 * @return Pointer to the cache block touched by the request. NULL if it 180 * was a miss. 181 */ 182 bool access(PacketPtr pkt, BlkType *&blk, int &lat); 183 184 /** 185 *Handle doing the Compare and Swap function for SPARC. 186 */ 187 void cmpAndSwap(BlkType *blk, PacketPtr pkt); 188 189 /** 190 * Populates a cache block and handles all outstanding requests for the 191 * satisfied fill request. This version takes two memory requests. One 192 * contains the fill data, the other is an optional target to satisfy. 193 * Used for Cache::probe. 194 * @param pkt The memory request with the fill data. 195 * @param blk The cache block if it already exists. 196 * @param writebacks List for any writebacks that need to be performed. 197 * @return Pointer to the new cache block. 198 */ 199 BlkType *handleFill(PacketPtr pkt, BlkType *blk, 200 PacketList &writebacks); 201 202 bool satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk); 203 bool satisfyTarget(MSHR::Target *target, BlkType *blk); 204 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk); 205 206 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data); 207 208 /** 209 * Sets the blk to the new state. 210 * @param blk The cache block being snooped. 211 * @param new_state The new coherence state for the block. 212 */ 213 void handleSnoop(PacketPtr ptk, BlkType *blk, bool is_timing); 214 215 /** 216 * Create a writeback request for the given block. 217 * @param blk The block to writeback. 218 * @return The writeback request for the block. 219 */ 220 PacketPtr writebackBlk(BlkType *blk); 221 222 public: 223 224 class Params 225 { 226 public: 227 TagStore *tags; 228 Coherence *coherence; 229 BaseCache::Params baseParams; 230 BasePrefetcher*prefetcher; 231 bool prefetchAccess; 232 const bool doFastWrites; 233 const bool prefetchMiss; 234 235 Params(TagStore *_tags, Coherence *coh, 236 BaseCache::Params params, 237 BasePrefetcher *_prefetcher, 238 bool prefetch_access, int hit_latency, 239 bool do_fast_writes, 240 bool prefetch_miss) 241 : tags(_tags), coherence(coh), 242 baseParams(params), 243 prefetcher(_prefetcher), prefetchAccess(prefetch_access), 244 doFastWrites(do_fast_writes), 245 prefetchMiss(prefetch_miss) 246 { 247 } 248 }; 249 250 /** Instantiates a basic cache object. */ 251 Cache(const std::string &_name, Params ¶ms); 252 253 virtual Port *getPort(const std::string &if_name, int idx = -1); 254 virtual void deletePortRefs(Port *p); 255 256 void regStats(); 257 258 /** 259 * Performs the access specified by the request. 260 * @param pkt The request to perform. 261 * @return The result of the access. 262 */ 263 bool timingAccess(PacketPtr pkt); 264 265 /** 266 * Performs the access specified by the request. 267 * @param pkt The request to perform. 268 * @return The result of the access. 269 */ 270 Tick atomicAccess(PacketPtr pkt); 271 272 /** 273 * Performs the access specified by the request. 274 * @param pkt The request to perform. 275 * @return The result of the access. 276 */ 277 void functionalAccess(PacketPtr pkt, CachePort *otherSidePort); 278 279 /** 280 * Handles a response (cache line fill/write ack) from the bus. 281 * @param pkt The request being responded to. 282 */ 283 void handleResponse(PacketPtr pkt); 284 285 /** 286 * Snoops bus transactions to maintain coherence. 287 * @param pkt The current bus transaction. 288 */ 289 void snoopTiming(PacketPtr pkt); 290 291 /** 292 * Snoop for the provided request in the cache and return the estimated 293 * time of completion. 294 * @param pkt The memory request to snoop 295 * @return The estimated completion time. 296 */ 297 Tick snoopAtomic(PacketPtr pkt); 298 299 /** 300 * Squash all requests associated with specified thread. 301 * intended for use by I-cache. 302 * @param threadNum The thread to squash. 303 */ 304 void squash(int threadNum); 305 306 /** 307 * Allocate a new MSHR or write buffer to handle a miss. 308 * @param pkt The access that missed. 309 * @param time The time to continue processing the miss. 310 * @param isFill Whether to fetch & allocate a block 311 * or just forward the request. 312 */ 313 MSHR *allocateBuffer(PacketPtr pkt, Tick time, bool requestBus); 314 315 /** 316 * Selects a outstanding request to service. 317 * @return The request to service, NULL if none found. 318 */ 319 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk, 320 bool needsExclusive); 321 MSHR *getNextMSHR(); 322 PacketPtr getTimingPacket(); 323 324 /** 325 * Marks a request as in service (sent on the bus). This can have side 326 * effect since storage for no response commands is deallocated once they 327 * are successfully sent. 328 * @param pkt The request that was sent on the bus. 329 */ 330 void markInService(MSHR *mshr); 331 332 /** 333 * Perform the given writeback request. 334 * @param pkt The writeback request. 335 */ 336 void doWriteback(PacketPtr pkt); 337 338 /** 339 * Return whether there are any outstanding misses. 340 */ 341 bool outstandingMisses() const 342 { 343 return mshrQueue.allocated != 0; 344 } 345 346 CacheBlk *findBlock(Addr addr) { 347 return tags->findBlock(addr); 348 } 349 350 bool inCache(Addr addr) { 351 return (tags->findBlock(addr) != 0); 352 } 353 354 bool inMissQueue(Addr addr) { 355 return (mshrQueue.findMatch(addr) != 0); 356 } 357}; 358 359#endif // __CACHE_HH__ 360