cache.hh revision 4478:33c4bf0ab4b9
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 * Dave Greene 30 * Steve Reinhardt 31 * Ron Dreslinski 32 */ 33 34/** 35 * @file 36 * Describes a cache based on template policies. 37 */ 38 39#ifndef __CACHE_HH__ 40#define __CACHE_HH__ 41 42#include "base/compression/base.hh" 43#include "base/misc.hh" // fatal, panic, and warn 44#include "cpu/smt.hh" // SMT_MAX_THREADS 45 46#include "mem/cache/base_cache.hh" 47#include "mem/cache/cache_blk.hh" 48#include "mem/cache/miss/miss_buffer.hh" 49 50#include "sim/eventq.hh" 51 52//Forward decleration 53class MSHR; 54class BasePrefetcher; 55 56/** 57 * A template-policy based cache. The behavior of the cache can be altered by 58 * supplying different template policies. TagStore handles all tag and data 59 * storage @sa TagStore. Buffering handles all misses and writes/writebacks 60 * @sa MissQueue. Coherence handles all coherence policy details @sa 61 * UniCoherence, SimpleMultiCoherence. 62 */ 63template <class TagStore, class Coherence> 64class Cache : public BaseCache 65{ 66 public: 67 /** Define the type of cache block to use. */ 68 typedef typename TagStore::BlkType BlkType; 69 /** A typedef for a list of BlkType pointers. */ 70 typedef typename TagStore::BlkList BlkList; 71 72 bool prefetchAccess; 73 74 protected: 75 76 class CpuSidePort : public CachePort 77 { 78 public: 79 CpuSidePort(const std::string &_name, 80 Cache<TagStore,Coherence> *_cache); 81 82 // BaseCache::CachePort just has a BaseCache *; this function 83 // lets us get back the type info we lost when we stored the 84 // cache pointer there. 85 Cache<TagStore,Coherence> *myCache() { 86 return static_cast<Cache<TagStore,Coherence> *>(cache); 87 } 88 89 void processRequestEvent(); 90 void processResponseEvent(); 91 92 virtual void getDeviceAddressRanges(AddrRangeList &resp, 93 bool &snoop); 94 95 virtual bool recvTiming(PacketPtr pkt); 96 97 virtual void recvRetry(); 98 99 virtual Tick recvAtomic(PacketPtr pkt); 100 101 virtual void recvFunctional(PacketPtr pkt); 102 103 typedef EventWrapper<CpuSidePort, &CpuSidePort::processResponseEvent> 104 ResponseEvent; 105 106 typedef EventWrapper<CpuSidePort, &CpuSidePort::processRequestEvent> 107 RequestEvent; 108 109 virtual void scheduleRequestEvent(Tick t) { 110 new RequestEvent(this, t); 111 } 112 }; 113 114 class MemSidePort : public CachePort 115 { 116 public: 117 MemSidePort(const std::string &_name, 118 Cache<TagStore,Coherence> *_cache); 119 120 // BaseCache::CachePort just has a BaseCache *; this function 121 // lets us get back the type info we lost when we stored the 122 // cache pointer there. 123 Cache<TagStore,Coherence> *myCache() { 124 return static_cast<Cache<TagStore,Coherence> *>(cache); 125 } 126 127 void processRequestEvent(); 128 void processResponseEvent(); 129 130 virtual void getDeviceAddressRanges(AddrRangeList &resp, 131 bool &snoop); 132 133 virtual bool recvTiming(PacketPtr pkt); 134 135 virtual void recvRetry(); 136 137 virtual Tick recvAtomic(PacketPtr pkt); 138 139 virtual void recvFunctional(PacketPtr pkt); 140 141 typedef EventWrapper<MemSidePort, &MemSidePort::processResponseEvent> 142 ResponseEvent; 143 144 typedef EventWrapper<MemSidePort, &MemSidePort::processRequestEvent> 145 RequestEvent; 146 147 virtual void scheduleRequestEvent(Tick t) { 148 new RequestEvent(this, t); 149 } 150 }; 151 152 /** Tag and data Storage */ 153 TagStore *tags; 154 /** Miss and Writeback handler */ 155 MissBuffer *missQueue; 156 /** Coherence protocol. */ 157 Coherence *coherence; 158 159 /** Prefetcher */ 160 BasePrefetcher *prefetcher; 161 162 /** 163 * The clock ratio of the outgoing bus. 164 * Used for calculating critical word first. 165 */ 166 int busRatio; 167 168 /** 169 * The bus width in bytes of the outgoing bus. 170 * Used for calculating critical word first. 171 */ 172 int busWidth; 173 174 /** 175 * The latency of a hit in this device. 176 */ 177 int hitLatency; 178 179 /** 180 * A permanent mem req to always be used to cause invalidations. 181 * Used to append to target list, to cause an invalidation. 182 */ 183 PacketPtr invalidatePkt; 184 Request *invalidateReq; 185 186 /** 187 * Policy class for performing compression. 188 */ 189 CompressionAlgorithm *compressionAlg; 190 191 /** 192 * The block size of this cache. Set to value in the Tags object. 193 */ 194 const int16_t blkSize; 195 196 /** 197 * Can this cache should allocate a block on a line-sized write miss. 198 */ 199 const bool doFastWrites; 200 201 const bool prefetchMiss; 202 203 /** 204 * Can the data can be stored in a compressed form. 205 */ 206 const bool storeCompressed; 207 208 /** 209 * Do we need to compress blocks on writebacks (i.e. because 210 * writeback bus is compressed but storage is not)? 211 */ 212 const bool compressOnWriteback; 213 214 /** 215 * The latency of a compression operation. 216 */ 217 const int16_t compLatency; 218 219 /** 220 * Should we use an adaptive compression scheme. 221 */ 222 const bool adaptiveCompression; 223 224 /** 225 * Do writebacks need to be compressed (i.e. because writeback bus 226 * is compressed), whether or not they're already compressed for 227 * storage. 228 */ 229 const bool writebackCompressed; 230 231 /** 232 * Compare the internal block data to the fast access block data. 233 * @param blk The cache block to check. 234 * @return True if the data is the same. 235 */ 236 bool verifyData(BlkType *blk); 237 238 /** 239 * Update the internal data of the block. The data to write is assumed to 240 * be in the fast access data. 241 * @param blk The block with the data to update. 242 * @param writebacks A list to store any generated writebacks. 243 * @param compress_block True if we should compress this block 244 */ 245 void updateData(BlkType *blk, PacketList &writebacks, bool compress_block); 246 247 /** 248 * Handle a replacement for the given request. 249 * @param blk A pointer to the block, usually NULL 250 * @param pkt The memory request to satisfy. 251 * @param new_state The new state of the block. 252 * @param writebacks A list to store any generated writebacks. 253 */ 254 BlkType* doReplacement(BlkType *blk, PacketPtr &pkt, 255 CacheBlk::State new_state, PacketList &writebacks); 256 257 /** 258 * Does all the processing necessary to perform the provided request. 259 * @param pkt The memory request to perform. 260 * @param lat The latency of the access. 261 * @param writebacks List for any writebacks that need to be performed. 262 * @param update True if the replacement data should be updated. 263 * @return Pointer to the cache block touched by the request. NULL if it 264 * was a miss. 265 */ 266 BlkType* handleAccess(PacketPtr &pkt, int & lat, 267 PacketList & writebacks, bool update = true); 268 269 270 /** 271 *Handle doing the Compare and Swap function for SPARC. 272 */ 273 void cmpAndSwap(BlkType *blk, PacketPtr &pkt); 274 275 /** 276 * Populates a cache block and handles all outstanding requests for the 277 * satisfied fill request. This version takes an MSHR pointer and uses its 278 * request to fill the cache block, while repsonding to its targets. 279 * @param blk The cache block if it already exists. 280 * @param mshr The MSHR that contains the fill data and targets to satisfy. 281 * @param new_state The state of the new cache block. 282 * @param writebacks List for any writebacks that need to be performed. 283 * @return Pointer to the new cache block. 284 */ 285 BlkType* handleFill(BlkType *blk, MSHR * mshr, CacheBlk::State new_state, 286 PacketList & writebacks, PacketPtr pkt); 287 288 /** 289 * Populates a cache block and handles all outstanding requests for the 290 * satisfied fill request. This version takes two memory requests. One 291 * contains the fill data, the other is an optional target to satisfy. 292 * Used for Cache::probe. 293 * @param blk The cache block if it already exists. 294 * @param pkt The memory request with the fill data. 295 * @param new_state The state of the new cache block. 296 * @param writebacks List for any writebacks that need to be performed. 297 * @param target The memory request to perform after the fill. 298 * @return Pointer to the new cache block. 299 */ 300 BlkType* handleFill(BlkType *blk, PacketPtr &pkt, 301 CacheBlk::State new_state, 302 PacketList & writebacks, PacketPtr target = NULL); 303 304 /** 305 * Sets the blk to the new state and handles the given request. 306 * @param blk The cache block being snooped. 307 * @param new_state The new coherence state for the block. 308 * @param pkt The request to satisfy 309 */ 310 void handleSnoop(BlkType *blk, CacheBlk::State new_state, 311 PacketPtr &pkt); 312 313 /** 314 * Sets the blk to the new state. 315 * @param blk The cache block being snooped. 316 * @param new_state The new coherence state for the block. 317 */ 318 void handleSnoop(BlkType *blk, CacheBlk::State new_state); 319 320 /** 321 * Create a writeback request for the given block. 322 * @param blk The block to writeback. 323 * @return The writeback request for the block. 324 */ 325 PacketPtr writebackBlk(BlkType *blk); 326 327 public: 328 329 class Params 330 { 331 public: 332 TagStore *tags; 333 MissBuffer *missQueue; 334 Coherence *coherence; 335 BaseCache::Params baseParams; 336 BasePrefetcher*prefetcher; 337 bool prefetchAccess; 338 int hitLatency; 339 CompressionAlgorithm *compressionAlg; 340 const int16_t blkSize; 341 const bool doFastWrites; 342 const bool prefetchMiss; 343 const bool storeCompressed; 344 const bool compressOnWriteback; 345 const int16_t compLatency; 346 const bool adaptiveCompression; 347 const bool writebackCompressed; 348 349 Params(TagStore *_tags, MissBuffer *mq, Coherence *coh, 350 BaseCache::Params params, 351 BasePrefetcher *_prefetcher, 352 bool prefetch_access, int hit_latency, 353 bool do_fast_writes, 354 bool store_compressed, bool adaptive_compression, 355 bool writeback_compressed, 356 CompressionAlgorithm *_compressionAlg, int comp_latency, 357 bool prefetch_miss) 358 : tags(_tags), missQueue(mq), coherence(coh), 359 baseParams(params), 360 prefetcher(_prefetcher), prefetchAccess(prefetch_access), 361 hitLatency(hit_latency), 362 compressionAlg(_compressionAlg), 363 blkSize(_tags->getBlockSize()), 364 doFastWrites(do_fast_writes), 365 prefetchMiss(prefetch_miss), 366 storeCompressed(store_compressed), 367 compressOnWriteback(!store_compressed && writeback_compressed), 368 compLatency(comp_latency), 369 adaptiveCompression(adaptive_compression), 370 writebackCompressed(writeback_compressed) 371 { 372 } 373 }; 374 375 /** Instantiates a basic cache object. */ 376 Cache(const std::string &_name, Params ¶ms); 377 378 virtual Port *getPort(const std::string &if_name, int idx = -1); 379 virtual void deletePortRefs(Port *p); 380 381 void regStats(); 382 383 /** 384 * Performs the access specified by the request. 385 * @param pkt The request to perform. 386 * @return The result of the access. 387 */ 388 bool access(PacketPtr &pkt); 389 390 /** 391 * Selects a request to send on the bus. 392 * @return The memory request to service. 393 */ 394 PacketPtr getPacket(); 395 396 /** 397 * Was the request was sent successfully? 398 * @param pkt The request. 399 * @param success True if the request was sent successfully. 400 */ 401 void sendResult(PacketPtr &pkt, MSHR* mshr, bool success); 402 403 /** 404 * Handles a response (cache line fill/write ack) from the bus. 405 * @param pkt The request being responded to. 406 */ 407 void handleResponse(PacketPtr &pkt); 408 409 /** 410 * Snoops bus transactions to maintain coherence. 411 * @param pkt The current bus transaction. 412 */ 413 void snoop(PacketPtr &pkt); 414 415 void snoopResponse(PacketPtr &pkt); 416 417 /** 418 * Squash all requests associated with specified thread. 419 * intended for use by I-cache. 420 * @param threadNum The thread to squash. 421 */ 422 void squash(int threadNum) 423 { 424 missQueue->squash(threadNum); 425 } 426 427 /** 428 * Return the number of outstanding misses in a Cache. 429 * Default returns 0. 430 * 431 * @retval unsigned The number of missing still outstanding. 432 */ 433 unsigned outstandingMisses() const 434 { 435 return missQueue->getMisses(); 436 } 437 438 /** 439 * Perform the access specified in the request and return the estimated 440 * time of completion. This function can either update the hierarchy state 441 * or just perform the access wherever the data is found depending on the 442 * state of the update flag. 443 * @param pkt The memory request to satisfy 444 * @param update If true, update the hierarchy, otherwise just perform the 445 * request. 446 * @return The estimated completion time. 447 */ 448 Tick probe(PacketPtr &pkt, bool update, CachePort * otherSidePort); 449 450 /** 451 * Snoop for the provided request in the cache and return the estimated 452 * time of completion. 453 * @todo Can a snoop probe not change state? 454 * @param pkt The memory request to satisfy 455 * @param update If true, update the hierarchy, otherwise just perform the 456 * request. 457 * @return The estimated completion time. 458 */ 459 Tick snoopProbe(PacketPtr &pkt); 460 461 bool inCache(Addr addr) { 462 return (tags->findBlock(addr) != 0); 463 } 464 465 bool inMissQueue(Addr addr) { 466 return (missQueue->findMSHR(addr) != 0); 467 } 468}; 469 470#endif // __CACHE_HH__ 471