cache.hh revision 3293:4ac3d9486d6e
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 * Dave Greene 30 * Steve Reinhardt 31 */ 32 33/** 34 * @file 35 * Describes a cache based on template policies. 36 */ 37 38#ifndef __CACHE_HH__ 39#define __CACHE_HH__ 40 41#include "base/misc.hh" // fatal, panic, and warn 42#include "cpu/smt.hh" // SMT_MAX_THREADS 43 44#include "mem/cache/base_cache.hh" 45#include "mem/cache/prefetch/prefetcher.hh" 46 47//Forward decleration 48class MSHR; 49 50 51/** 52 * A template-policy based cache. The behavior of the cache can be altered by 53 * supplying different template policies. TagStore handles all tag and data 54 * storage @sa TagStore. Buffering handles all misses and writes/writebacks 55 * @sa MissQueue. Coherence handles all coherence policy details @sa 56 * UniCoherence, SimpleMultiCoherence. 57 */ 58template <class TagStore, class Buffering, class Coherence> 59class Cache : public BaseCache 60{ 61 public: 62 /** Define the type of cache block to use. */ 63 typedef typename TagStore::BlkType BlkType; 64 65 bool prefetchAccess; 66 protected: 67 68 /** Tag and data Storage */ 69 TagStore *tags; 70 /** Miss and Writeback handler */ 71 Buffering *missQueue; 72 /** Coherence protocol. */ 73 Coherence *coherence; 74 75 /** Prefetcher */ 76 Prefetcher<TagStore, Buffering> *prefetcher; 77 78 /** Do fast copies in this cache. */ 79 bool doCopy; 80 81 /** Block on a delayed copy. */ 82 bool blockOnCopy; 83 84 /** 85 * The clock ratio of the outgoing bus. 86 * Used for calculating critical word first. 87 */ 88 int busRatio; 89 90 /** 91 * The bus width in bytes of the outgoing bus. 92 * Used for calculating critical word first. 93 */ 94 int busWidth; 95 96 /** 97 * The latency of a hit in this device. 98 */ 99 int hitLatency; 100 101 /** 102 * A permanent mem req to always be used to cause invalidations. 103 * Used to append to target list, to cause an invalidation. 104 */ 105 Packet * invalidatePkt; 106 Request *invalidateReq; 107 108 /** 109 * Temporarily move a block into a MSHR. 110 * @todo Remove this when LSQ/SB are fixed and implemented in memtest. 111 */ 112 void pseudoFill(Addr addr); 113 114 /** 115 * Temporarily move a block into an existing MSHR. 116 * @todo Remove this when LSQ/SB are fixed and implemented in memtest. 117 */ 118 void pseudoFill(MSHR *mshr); 119 120 public: 121 122 class Params 123 { 124 public: 125 TagStore *tags; 126 Buffering *missQueue; 127 Coherence *coherence; 128 bool doCopy; 129 bool blockOnCopy; 130 BaseCache::Params baseParams; 131 Prefetcher<TagStore, Buffering> *prefetcher; 132 bool prefetchAccess; 133 int hitLatency; 134 135 Params(TagStore *_tags, Buffering *mq, Coherence *coh, 136 bool do_copy, BaseCache::Params params, 137 Prefetcher<TagStore, Buffering> *_prefetcher, 138 bool prefetch_access, int hit_latency) 139 : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy), 140 blockOnCopy(false), baseParams(params), 141 prefetcher(_prefetcher), prefetchAccess(prefetch_access), 142 hitLatency(hit_latency) 143 { 144 } 145 }; 146 147 /** Instantiates a basic cache object. */ 148 Cache(const std::string &_name, Params ¶ms); 149 150 virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, 151 bool isCpuSide); 152 153 virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide); 154 155 virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide); 156 157 virtual void recvStatusChange(Port::Status status, bool isCpuSide); 158 159 void regStats(); 160 161 /** 162 * Performs the access specified by the request. 163 * @param pkt The request to perform. 164 * @return The result of the access. 165 */ 166 bool access(Packet * &pkt); 167 168 /** 169 * Selects a request to send on the bus. 170 * @return The memory request to service. 171 */ 172 virtual Packet * getPacket(); 173 174 /** 175 * Was the request was sent successfully? 176 * @param pkt The request. 177 * @param success True if the request was sent successfully. 178 */ 179 virtual void sendResult(Packet * &pkt, MSHR* mshr, bool success); 180 181 /** 182 * Was the CSHR request was sent successfully? 183 * @param pkt The request. 184 * @param success True if the request was sent successfully. 185 */ 186 virtual void sendCoherenceResult(Packet * &pkt, MSHR* cshr, bool success); 187 188 /** 189 * Handles a response (cache line fill/write ack) from the bus. 190 * @param pkt The request being responded to. 191 */ 192 void handleResponse(Packet * &pkt); 193 194 /** 195 * Start handling a copy transaction. 196 * @param pkt The copy request to perform. 197 */ 198 void startCopy(Packet * &pkt); 199 200 /** 201 * Handle a delayed copy transaction. 202 * @param pkt The delayed copy request to continue. 203 * @param addr The address being responded to. 204 * @param blk The block of the current response. 205 * @param mshr The mshr being handled. 206 */ 207 void handleCopy(Packet * &pkt, Addr addr, BlkType *blk, MSHR *mshr); 208 209 /** 210 * Selects a coherence message to forward to lower levels of the hierarchy. 211 * @return The coherence message to forward. 212 */ 213 virtual Packet * getCoherencePacket(); 214 215 /** 216 * Snoops bus transactions to maintain coherence. 217 * @param pkt The current bus transaction. 218 */ 219 void snoop(Packet * &pkt); 220 221 void snoopResponse(Packet * &pkt); 222 223 /** 224 * Invalidates the block containing address if found. 225 * @param addr The address to look for. 226 * @param asid The address space ID of the address. 227 * @todo Is this function necessary? 228 */ 229 void invalidateBlk(Addr addr); 230 231 /** 232 * Squash all requests associated with specified thread. 233 * intended for use by I-cache. 234 * @param threadNum The thread to squash. 235 */ 236 void squash(int threadNum) 237 { 238 missQueue->squash(threadNum); 239 } 240 241 /** 242 * Return the number of outstanding misses in a Cache. 243 * Default returns 0. 244 * 245 * @retval unsigned The number of missing still outstanding. 246 */ 247 unsigned outstandingMisses() const 248 { 249 return missQueue->getMisses(); 250 } 251 252 /** 253 * Perform the access specified in the request and return the estimated 254 * time of completion. This function can either update the hierarchy state 255 * or just perform the access wherever the data is found depending on the 256 * state of the update flag. 257 * @param pkt The memory request to satisfy 258 * @param update If true, update the hierarchy, otherwise just perform the 259 * request. 260 * @return The estimated completion time. 261 */ 262 Tick probe(Packet * &pkt, bool update, CachePort * otherSidePort); 263 264 /** 265 * Snoop for the provided request in the cache and return the estimated 266 * time of completion. 267 * @todo Can a snoop probe not change state? 268 * @param pkt The memory request to satisfy 269 * @param update If true, update the hierarchy, otherwise just perform the 270 * request. 271 * @return The estimated completion time. 272 */ 273 Tick snoopProbe(Packet * &pkt); 274}; 275 276#endif // __CACHE_HH__ 277