cache.hh revision 3208:97d9cc1e626f 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 *          Dave Greene
30 *          Steve Reinhardt
31 */
32
33/**
34 * @file
35 * Describes a cache based on template policies.
36 */
37
38#ifndef __CACHE_HH__
39#define __CACHE_HH__
40
41#include "base/misc.hh" // fatal, panic, and warn
42#include "cpu/smt.hh" // SMT_MAX_THREADS
43
44#include "mem/cache/base_cache.hh"
45#include "mem/cache/prefetch/prefetcher.hh"
46
47//Forward decleration
48class MSHR;
49
50
51/**
52 * A template-policy based cache. The behavior of the cache can be altered by
53 * supplying different template policies. TagStore handles all tag and data
54 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
55 * @sa MissQueue. Coherence handles all coherence policy details @sa
56 * UniCoherence, SimpleMultiCoherence.
57 */
58template <class TagStore, class Buffering, class Coherence>
59class Cache : public BaseCache
60{
61  public:
62    /** Define the type of cache block to use. */
63    typedef typename TagStore::BlkType BlkType;
64
65    bool prefetchAccess;
66  protected:
67
68    /** Tag and data Storage */
69    TagStore *tags;
70    /** Miss and Writeback handler */
71    Buffering *missQueue;
72    /** Coherence protocol. */
73    Coherence *coherence;
74
75    /** Prefetcher */
76    Prefetcher<TagStore, Buffering> *prefetcher;
77
78    /** Do fast copies in this cache. */
79    bool doCopy;
80
81    /** Block on a delayed copy. */
82    bool blockOnCopy;
83
84    /**
85     * The clock ratio of the outgoing bus.
86     * Used for calculating critical word first.
87     */
88    int busRatio;
89
90     /**
91      * The bus width in bytes of the outgoing bus.
92      * Used for calculating critical word first.
93      */
94    int busWidth;
95
96    /**
97     * The latency of a hit in this device.
98     */
99    int hitLatency;
100
101     /**
102      * A permanent mem req to always be used to cause invalidations.
103      * Used to append to target list, to cause an invalidation.
104      */
105    Packet * invalidatePkt;
106    Request *invalidateReq;
107
108    /**
109     * Temporarily move a block into a MSHR.
110     * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
111     */
112    void pseudoFill(Addr addr);
113
114    /**
115     * Temporarily move a block into an existing MSHR.
116     * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
117     */
118    void pseudoFill(MSHR *mshr);
119
120  public:
121
122    class Params
123    {
124      public:
125        TagStore *tags;
126        Buffering *missQueue;
127        Coherence *coherence;
128        bool doCopy;
129        bool blockOnCopy;
130        BaseCache::Params baseParams;
131        Prefetcher<TagStore, Buffering> *prefetcher;
132        bool prefetchAccess;
133        int hitLatency;
134
135        Params(TagStore *_tags, Buffering *mq, Coherence *coh,
136               bool do_copy, BaseCache::Params params,
137               Prefetcher<TagStore, Buffering> *_prefetcher,
138               bool prefetch_access, int hit_latency)
139            : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy),
140              blockOnCopy(false), baseParams(params),
141              prefetcher(_prefetcher), prefetchAccess(prefetch_access),
142              hitLatency(hit_latency)
143        {
144        }
145    };
146
147    /** Instantiates a basic cache object. */
148    Cache(const std::string &_name, Params &params);
149
150    virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort,
151                        bool isCpuSide);
152
153    virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide);
154
155    virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
156
157    virtual void recvStatusChange(Port::Status status, bool isCpuSide);
158
159    void regStats();
160
161    /**
162     * Performs the access specified by the request.
163     * @param pkt The request to perform.
164     * @return The result of the access.
165     */
166    bool access(Packet * &pkt);
167
168    /**
169     * Selects a request to send on the bus.
170     * @return The memory request to service.
171     */
172    virtual Packet * getPacket();
173
174    /**
175     * Was the request was sent successfully?
176     * @param pkt The request.
177     * @param success True if the request was sent successfully.
178     */
179    virtual void sendResult(Packet * &pkt, MSHR* mshr, bool success);
180
181    /**
182     * Handles a response (cache line fill/write ack) from the bus.
183     * @param pkt The request being responded to.
184     */
185    void handleResponse(Packet * &pkt);
186
187    /**
188     * Start handling a copy transaction.
189     * @param pkt The copy request to perform.
190     */
191    void startCopy(Packet * &pkt);
192
193    /**
194     * Handle a delayed copy transaction.
195     * @param pkt The delayed copy request to continue.
196     * @param addr The address being responded to.
197     * @param blk The block of the current response.
198     * @param mshr The mshr being handled.
199     */
200    void handleCopy(Packet * &pkt, Addr addr, BlkType *blk, MSHR *mshr);
201
202    /**
203     * Selects a coherence message to forward to lower levels of the hierarchy.
204     * @return The coherence message to forward.
205     */
206    virtual Packet * getCoherencePacket();
207
208    /**
209     * Snoops bus transactions to maintain coherence.
210     * @param pkt The current bus transaction.
211     */
212    void snoop(Packet * &pkt);
213
214    void snoopResponse(Packet * &pkt);
215
216    /**
217     * Invalidates the block containing address if found.
218     * @param addr The address to look for.
219     * @param asid The address space ID of the address.
220     * @todo Is this function necessary?
221     */
222    void invalidateBlk(Addr addr);
223
224    /**
225     * Squash all requests associated with specified thread.
226     * intended for use by I-cache.
227     * @param threadNum The thread to squash.
228     */
229    void squash(int threadNum)
230    {
231        missQueue->squash(threadNum);
232    }
233
234    /**
235     * Return the number of outstanding misses in a Cache.
236     * Default returns 0.
237     *
238     * @retval unsigned The number of missing still outstanding.
239     */
240    unsigned outstandingMisses() const
241    {
242        return missQueue->getMisses();
243    }
244
245    /**
246     * Perform the access specified in the request and return the estimated
247     * time of completion. This function can either update the hierarchy state
248     * or just perform the access wherever the data is found depending on the
249     * state of the update flag.
250     * @param pkt The memory request to satisfy
251     * @param update If true, update the hierarchy, otherwise just perform the
252     * request.
253     * @return The estimated completion time.
254     */
255    Tick probe(Packet * &pkt, bool update, CachePort * otherSidePort);
256
257    /**
258     * Snoop for the provided request in the cache and return the estimated
259     * time of completion.
260     * @todo Can a snoop probe not change state?
261     * @param pkt The memory request to satisfy
262     * @param update If true, update the hierarchy, otherwise just perform the
263     * request.
264     * @return The estimated completion time.
265     */
266    Tick snoopProbe(Packet * &pkt);
267};
268
269#endif // __CACHE_HH__
270