cache.hh revision 2813:89d9196456ac 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 *          Dave Greene
30 *          Steve Reinhardt
31 */
32
33/**
34 * @file
35 * Describes a cache based on template policies.
36 */
37
38#ifndef __CACHE_HH__
39#define __CACHE_HH__
40
41#include "base/misc.hh" // fatal, panic, and warn
42#include "cpu/smt.hh" // SMT_MAX_THREADS
43
44#include "mem/cache/base_cache.hh"
45#include "mem/cache/prefetch/prefetcher.hh"
46
47//Forward decleration
48class MSHR;
49
50
51/**
52 * A template-policy based cache. The behavior of the cache can be altered by
53 * supplying different template policies. TagStore handles all tag and data
54 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
55 * @sa MissQueue. Coherence handles all coherence policy details @sa
56 * UniCoherence, SimpleMultiCoherence.
57 */
58template <class TagStore, class Buffering, class Coherence>
59class Cache : public BaseCache
60{
61  public:
62    /** Define the type of cache block to use. */
63    typedef typename TagStore::BlkType BlkType;
64
65    bool prefetchAccess;
66  protected:
67
68    /** Tag and data Storage */
69    TagStore *tags;
70    /** Miss and Writeback handler */
71    Buffering *missQueue;
72    /** Coherence protocol. */
73    Coherence *coherence;
74
75    /** Prefetcher */
76    Prefetcher<TagStore, Buffering> *prefetcher;
77
78    /** Do fast copies in this cache. */
79    bool doCopy;
80
81    /** Block on a delayed copy. */
82    bool blockOnCopy;
83
84    /**
85     * The clock ratio of the outgoing bus.
86     * Used for calculating critical word first.
87     */
88    int busRatio;
89
90     /**
91      * The bus width in bytes of the outgoing bus.
92      * Used for calculating critical word first.
93      */
94    int busWidth;
95
96    /**
97     * The latency of a hit in this device.
98     */
99    int hitLatency;
100
101     /**
102      * A permanent mem req to always be used to cause invalidations.
103      * Used to append to target list, to cause an invalidation.
104      */
105    Packet * invalidatePkt;
106
107    /**
108     * Temporarily move a block into a MSHR.
109     * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
110     */
111    void pseudoFill(Addr addr, int asid);
112
113    /**
114     * Temporarily move a block into an existing MSHR.
115     * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
116     */
117    void pseudoFill(MSHR *mshr);
118
119  public:
120
121    class Params
122    {
123      public:
124        TagStore *tags;
125        Buffering *missQueue;
126        Coherence *coherence;
127        bool doCopy;
128        bool blockOnCopy;
129        BaseCache::Params baseParams;
130        Prefetcher<TagStore, Buffering> *prefetcher;
131        bool prefetchAccess;
132        int hitLatency;
133
134        Params(TagStore *_tags, Buffering *mq, Coherence *coh,
135               bool do_copy, BaseCache::Params params,
136               Prefetcher<TagStore, Buffering> *_prefetcher,
137               bool prefetch_access, int hit_latency)
138            : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy),
139              blockOnCopy(false), baseParams(params),
140              prefetcher(_prefetcher), prefetchAccess(prefetch_access),
141              hitLatency(hit_latency)
142        {
143        }
144    };
145
146    /** Instantiates a basic cache object. */
147    Cache(const std::string &_name, Params &params);
148
149    bool doTimingAccess(Packet *pkt, CachePort *cachePort,
150                        bool isCpuSide);
151
152    Tick doAtomicAccess(Packet *pkt, CachePort *cachePort,
153                        bool isCpuSide);
154
155    void doFunctionalAccess(Packet *pkt, CachePort *cachePort,
156                            bool isCpuSide);
157
158    void recvStatusChange(Port::Status status, bool isCpuSide);
159
160    void regStats();
161
162    /**
163     * Performs the access specified by the request.
164     * @param req The request to perform.
165     * @return The result of the access.
166     */
167    bool access(Packet * &pkt);
168
169    /**
170     * Selects a request to send on the bus.
171     * @return The memory request to service.
172     */
173    Packet * getPacket();
174
175    /**
176     * Was the request was sent successfully?
177     * @param req The request.
178     * @param success True if the request was sent successfully.
179     */
180    void sendResult(Packet * &pkt, bool success);
181
182    /**
183     * Handles a response (cache line fill/write ack) from the bus.
184     * @param req The request being responded to.
185     */
186    void handleResponse(Packet * &pkt);
187
188    /**
189     * Start handling a copy transaction.
190     * @param req The copy request to perform.
191     */
192    void startCopy(Packet * &pkt);
193
194    /**
195     * Handle a delayed copy transaction.
196     * @param req The delayed copy request to continue.
197     * @param addr The address being responded to.
198     * @param blk The block of the current response.
199     * @param mshr The mshr being handled.
200     */
201    void handleCopy(Packet * &pkt, Addr addr, BlkType *blk, MSHR *mshr);
202
203    /**
204     * Selects a coherence message to forward to lower levels of the hierarchy.
205     * @return The coherence message to forward.
206     */
207    Packet * getCoherenceReq();
208
209    /**
210     * Snoops bus transactions to maintain coherence.
211     * @param req The current bus transaction.
212     */
213    void snoop(Packet * &pkt);
214
215    void snoopResponse(Packet * &pkt);
216
217    /**
218     * Invalidates the block containing address if found.
219     * @param addr The address to look for.
220     * @param asid The address space ID of the address.
221     * @todo Is this function necessary?
222     */
223    void invalidateBlk(Addr addr, int asid);
224
225    /**
226     * Aquash all requests associated with specified thread.
227     * intended for use by I-cache.
228     * @param req->getThreadNum()ber The thread to squash.
229     */
230    void squash(int threadNum)
231    {
232        missQueue->squash(threadNum);
233    }
234
235    /**
236     * Return the number of outstanding misses in a Cache.
237     * Default returns 0.
238     *
239     * @retval unsigned The number of missing still outstanding.
240     */
241    unsigned outstandingMisses() const
242    {
243        return missQueue->getMisses();
244    }
245
246    /**
247     * Send a response to the slave interface.
248     * @param req The request being responded to.
249     * @param time The time the response is ready.
250     */
251    void respond(Packet * &pkt, Tick time)
252    {
253        //si->respond(pkt,time);
254        cpuSidePort->sendAtomic(pkt);
255    }
256
257    /**
258     * Perform the access specified in the request and return the estimated
259     * time of completion. This function can either update the hierarchy state
260     * or just perform the access wherever the data is found depending on the
261     * state of the update flag.
262     * @param req The memory request to satisfy
263     * @param update If true, update the hierarchy, otherwise just perform the
264     * request.
265     * @return The estimated completion time.
266     */
267    Tick probe(Packet * &pkt, bool update);
268
269    /**
270     * Snoop for the provided request in the cache and return the estimated
271     * time of completion.
272     * @todo Can a snoop probe not change state?
273     * @param req The memory request to satisfy
274     * @param update If true, update the hierarchy, otherwise just perform the
275     * request.
276     * @return The estimated completion time.
277     */
278    Tick snoopProbe(Packet * &pkt, bool update);
279};
280
281#endif // __CACHE_HH__
282