cache.hh revision 11869:aa9d04c7e3bb
1/* 2 * Copyright (c) 2012-2016 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Dave Greene 42 * Steve Reinhardt 43 * Ron Dreslinski 44 * Andreas Hansson 45 */ 46 47/** 48 * @file 49 * Describes a cache based on template policies. 50 */ 51 52#ifndef __MEM_CACHE_CACHE_HH__ 53#define __MEM_CACHE_CACHE_HH__ 54 55#include <unordered_set> 56 57#include "base/misc.hh" // fatal, panic, and warn 58#include "enums/Clusivity.hh" 59#include "mem/cache/base.hh" 60#include "mem/cache/blk.hh" 61#include "mem/cache/mshr.hh" 62#include "mem/cache/tags/base.hh" 63#include "params/Cache.hh" 64#include "sim/eventq.hh" 65 66//Forward decleration 67class BasePrefetcher; 68 69/** 70 * A template-policy based cache. The behavior of the cache can be altered by 71 * supplying different template policies. TagStore handles all tag and data 72 * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System" 73 */ 74class Cache : public BaseCache 75{ 76 protected: 77 78 /** 79 * The CPU-side port extends the base cache slave port with access 80 * functions for functional, atomic and timing requests. 81 */ 82 class CpuSidePort : public CacheSlavePort 83 { 84 private: 85 86 // a pointer to our specific cache implementation 87 Cache *cache; 88 89 protected: 90 91 virtual bool recvTimingSnoopResp(PacketPtr pkt); 92 93 virtual bool recvTimingReq(PacketPtr pkt); 94 95 virtual Tick recvAtomic(PacketPtr pkt); 96 97 virtual void recvFunctional(PacketPtr pkt); 98 99 virtual AddrRangeList getAddrRanges() const; 100 101 public: 102 103 CpuSidePort(const std::string &_name, Cache *_cache, 104 const std::string &_label); 105 106 }; 107 108 /** 109 * Override the default behaviour of sendDeferredPacket to enable 110 * the memory-side cache port to also send requests based on the 111 * current MSHR status. This queue has a pointer to our specific 112 * cache implementation and is used by the MemSidePort. 113 */ 114 class CacheReqPacketQueue : public ReqPacketQueue 115 { 116 117 protected: 118 119 Cache &cache; 120 SnoopRespPacketQueue &snoopRespQueue; 121 122 public: 123 124 CacheReqPacketQueue(Cache &cache, MasterPort &port, 125 SnoopRespPacketQueue &snoop_resp_queue, 126 const std::string &label) : 127 ReqPacketQueue(cache, port, label), cache(cache), 128 snoopRespQueue(snoop_resp_queue) { } 129 130 /** 131 * Override the normal sendDeferredPacket and do not only 132 * consider the transmit list (used for responses), but also 133 * requests. 134 */ 135 virtual void sendDeferredPacket(); 136 137 /** 138 * Check if there is a conflicting snoop response about to be 139 * send out, and if so simply stall any requests, and schedule 140 * a send event at the same time as the next snoop response is 141 * being sent out. 142 */ 143 bool checkConflictingSnoop(Addr addr) 144 { 145 if (snoopRespQueue.hasAddr(addr)) { 146 DPRINTF(CachePort, "Waiting for snoop response to be " 147 "sent\n"); 148 Tick when = snoopRespQueue.deferredPacketReadyTime(); 149 schedSendEvent(when); 150 return true; 151 } 152 return false; 153 } 154 }; 155 156 /** 157 * The memory-side port extends the base cache master port with 158 * access functions for functional, atomic and timing snoops. 159 */ 160 class MemSidePort : public CacheMasterPort 161 { 162 private: 163 164 /** The cache-specific queue. */ 165 CacheReqPacketQueue _reqQueue; 166 167 SnoopRespPacketQueue _snoopRespQueue; 168 169 // a pointer to our specific cache implementation 170 Cache *cache; 171 172 protected: 173 174 virtual void recvTimingSnoopReq(PacketPtr pkt); 175 176 virtual bool recvTimingResp(PacketPtr pkt); 177 178 virtual Tick recvAtomicSnoop(PacketPtr pkt); 179 180 virtual void recvFunctionalSnoop(PacketPtr pkt); 181 182 public: 183 184 MemSidePort(const std::string &_name, Cache *_cache, 185 const std::string &_label); 186 }; 187 188 /** Tag and data Storage */ 189 BaseTags *tags; 190 191 /** Prefetcher */ 192 BasePrefetcher *prefetcher; 193 194 /** Temporary cache block for occasional transitory use */ 195 CacheBlk *tempBlock; 196 197 /** 198 * This cache should allocate a block on a line-sized write miss. 199 */ 200 const bool doFastWrites; 201 202 /** 203 * Turn line-sized writes into WriteInvalidate transactions. 204 */ 205 void promoteWholeLineWrites(PacketPtr pkt); 206 207 /** 208 * Notify the prefetcher on every access, not just misses. 209 */ 210 const bool prefetchOnAccess; 211 212 /** 213 * Clusivity with respect to the upstream cache, determining if we 214 * fill into both this cache and the cache above on a miss. Note 215 * that we currently do not support strict clusivity policies. 216 */ 217 const Enums::Clusivity clusivity; 218 219 /** 220 * Determine if clean lines should be written back or not. In 221 * cases where a downstream cache is mostly inclusive we likely 222 * want it to act as a victim cache also for lines that have not 223 * been modified. Hence, we cannot simply drop the line (or send a 224 * clean evict), but rather need to send the actual data. 225 */ 226 const bool writebackClean; 227 228 /** 229 * Upstream caches need this packet until true is returned, so 230 * hold it for deletion until a subsequent call 231 */ 232 std::unique_ptr<Packet> pendingDelete; 233 234 /** 235 * Writebacks from the tempBlock, resulting on the response path 236 * in atomic mode, must happen after the call to recvAtomic has 237 * finished (for the right ordering of the packets). We therefore 238 * need to hold on to the packets, and have a method and an event 239 * to send them. 240 */ 241 PacketPtr tempBlockWriteback; 242 243 /** 244 * Send the outstanding tempBlock writeback. To be called after 245 * recvAtomic finishes in cases where the block we filled is in 246 * fact the tempBlock, and now needs to be written back. 247 */ 248 void writebackTempBlockAtomic() { 249 assert(tempBlockWriteback != nullptr); 250 PacketList writebacks{tempBlockWriteback}; 251 doWritebacksAtomic(writebacks); 252 tempBlockWriteback = nullptr; 253 } 254 255 /** 256 * An event to writeback the tempBlock after recvAtomic 257 * finishes. To avoid other calls to recvAtomic getting in 258 * between, we create this event with a higher priority. 259 */ 260 EventWrapper<Cache, &Cache::writebackTempBlockAtomic> \ 261 writebackTempBlockAtomicEvent; 262 263 /** 264 * Store the outstanding requests that we are expecting snoop 265 * responses from so we can determine which snoop responses we 266 * generated and which ones were merely forwarded. 267 */ 268 std::unordered_set<RequestPtr> outstandingSnoop; 269 270 /** 271 * Does all the processing necessary to perform the provided request. 272 * @param pkt The memory request to perform. 273 * @param blk The cache block to be updated. 274 * @param lat The latency of the access. 275 * @param writebacks List for any writebacks that need to be performed. 276 * @return Boolean indicating whether the request was satisfied. 277 */ 278 bool access(PacketPtr pkt, CacheBlk *&blk, 279 Cycles &lat, PacketList &writebacks); 280 281 /** 282 *Handle doing the Compare and Swap function for SPARC. 283 */ 284 void cmpAndSwap(CacheBlk *blk, PacketPtr pkt); 285 286 /** 287 * Find a block frame for new block at address addr targeting the 288 * given security space, assuming that the block is not currently 289 * in the cache. Append writebacks if any to provided packet 290 * list. Return free block frame. May return nullptr if there are 291 * no replaceable blocks at the moment. 292 */ 293 CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks); 294 295 /** 296 * Invalidate a cache block. 297 * 298 * @param blk Block to invalidate 299 */ 300 void invalidateBlock(CacheBlk *blk); 301 302 /** 303 * Maintain the clusivity of this cache by potentially 304 * invalidating a block. This method works in conjunction with 305 * satisfyRequest, but is separate to allow us to handle all MSHR 306 * targets before potentially dropping a block. 307 * 308 * @param from_cache Whether we have dealt with a packet from a cache 309 * @param blk The block that should potentially be dropped 310 */ 311 void maintainClusivity(bool from_cache, CacheBlk *blk); 312 313 /** 314 * Populates a cache block and handles all outstanding requests for the 315 * satisfied fill request. This version takes two memory requests. One 316 * contains the fill data, the other is an optional target to satisfy. 317 * @param pkt The memory request with the fill data. 318 * @param blk The cache block if it already exists. 319 * @param writebacks List for any writebacks that need to be performed. 320 * @param allocate Whether to allocate a block or use the temp block 321 * @return Pointer to the new cache block. 322 */ 323 CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk, 324 PacketList &writebacks, bool allocate); 325 326 /** 327 * Determine whether we should allocate on a fill or not. If this 328 * cache is mostly inclusive with regards to the upstream cache(s) 329 * we always allocate (for any non-forwarded and cacheable 330 * requests). In the case of a mostly exclusive cache, we allocate 331 * on fill if the packet did not come from a cache, thus if we: 332 * are dealing with a whole-line write (the latter behaves much 333 * like a writeback), the original target packet came from a 334 * non-caching source, or if we are performing a prefetch or LLSC. 335 * 336 * @param cmd Command of the incoming requesting packet 337 * @return Whether we should allocate on the fill 338 */ 339 inline bool allocOnFill(MemCmd cmd) const override 340 { 341 return clusivity == Enums::mostly_incl || 342 cmd == MemCmd::WriteLineReq || 343 cmd == MemCmd::ReadReq || 344 cmd == MemCmd::WriteReq || 345 cmd.isPrefetch() || 346 cmd.isLLSC(); 347 } 348 349 /** 350 * Performs the access specified by the request. 351 * @param pkt The request to perform. 352 * @return The result of the access. 353 */ 354 bool recvTimingReq(PacketPtr pkt); 355 356 /** 357 * Insert writebacks into the write buffer 358 */ 359 void doWritebacks(PacketList& writebacks, Tick forward_time); 360 361 /** 362 * Send writebacks down the memory hierarchy in atomic mode 363 */ 364 void doWritebacksAtomic(PacketList& writebacks); 365 366 /** 367 * Handling the special case of uncacheable write responses to 368 * make recvTimingResp less cluttered. 369 */ 370 void handleUncacheableWriteResp(PacketPtr pkt); 371 372 /** 373 * Handles a response (cache line fill/write ack) from the bus. 374 * @param pkt The response packet 375 */ 376 void recvTimingResp(PacketPtr pkt); 377 378 /** 379 * Snoops bus transactions to maintain coherence. 380 * @param pkt The current bus transaction. 381 */ 382 void recvTimingSnoopReq(PacketPtr pkt); 383 384 /** 385 * Handle a snoop response. 386 * @param pkt Snoop response packet 387 */ 388 void recvTimingSnoopResp(PacketPtr pkt); 389 390 /** 391 * Performs the access specified by the request. 392 * @param pkt The request to perform. 393 * @return The number of ticks required for the access. 394 */ 395 Tick recvAtomic(PacketPtr pkt); 396 397 /** 398 * Snoop for the provided request in the cache and return the estimated 399 * time taken. 400 * @param pkt The memory request to snoop 401 * @return The number of ticks required for the snoop. 402 */ 403 Tick recvAtomicSnoop(PacketPtr pkt); 404 405 /** 406 * Performs the access specified by the request. 407 * @param pkt The request to perform. 408 * @param fromCpuSide from the CPU side port or the memory side port 409 */ 410 void functionalAccess(PacketPtr pkt, bool fromCpuSide); 411 412 /** 413 * Perform any necessary updates to the block and perform any data 414 * exchange between the packet and the block. The flags of the 415 * packet are also set accordingly. 416 * 417 * @param pkt Request packet from upstream that hit a block 418 * @param blk Cache block that the packet hit 419 * @param deferred_response Whether this hit is to block that 420 * originally missed 421 * @param pending_downgrade Whether the writable flag is to be removed 422 * 423 * @return True if the block is to be invalidated 424 */ 425 void satisfyRequest(PacketPtr pkt, CacheBlk *blk, 426 bool deferred_response = false, 427 bool pending_downgrade = false); 428 429 void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 430 bool already_copied, bool pending_inval); 431 432 /** 433 * Perform an upward snoop if needed, and update the block state 434 * (possibly invalidating the block). Also create a response if required. 435 * 436 * @param pkt Snoop packet 437 * @param blk Cache block being snooped 438 * @param is_timing Timing or atomic for the response 439 * @param is_deferred Is this a deferred snoop or not? 440 * @param pending_inval Do we have a pending invalidation? 441 * 442 * @return The snoop delay incurred by the upwards snoop 443 */ 444 uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk, 445 bool is_timing, bool is_deferred, bool pending_inval); 446 447 /** 448 * Create a writeback request for the given block. 449 * @param blk The block to writeback. 450 * @return The writeback request for the block. 451 */ 452 PacketPtr writebackBlk(CacheBlk *blk); 453 454 /** 455 * Create a CleanEvict request for the given block. 456 * @param blk The block to evict. 457 * @return The CleanEvict request for the block. 458 */ 459 PacketPtr cleanEvictBlk(CacheBlk *blk); 460 461 462 void memWriteback() override; 463 void memInvalidate() override; 464 bool isDirty() const override; 465 466 /** 467 * Cache block visitor that writes back dirty cache blocks using 468 * functional writes. 469 * 470 * \return Always returns true. 471 */ 472 bool writebackVisitor(CacheBlk &blk); 473 /** 474 * Cache block visitor that invalidates all blocks in the cache. 475 * 476 * @warn Dirty cache lines will not be written back to memory. 477 * 478 * \return Always returns true. 479 */ 480 bool invalidateVisitor(CacheBlk &blk); 481 482 /** 483 * Create an appropriate downstream bus request packet for the 484 * given parameters. 485 * @param cpu_pkt The miss that needs to be satisfied. 486 * @param blk The block currently in the cache corresponding to 487 * cpu_pkt (nullptr if none). 488 * @param needsWritable Indicates that the block must be writable 489 * even if the request in cpu_pkt doesn't indicate that. 490 * @return A new Packet containing the request, or nullptr if the 491 * current request in cpu_pkt should just be forwarded on. 492 */ 493 PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 494 bool needsWritable) const; 495 496 /** 497 * Return the next queue entry to service, either a pending miss 498 * from the MSHR queue, a buffered write from the write buffer, or 499 * something from the prefetcher. This function is responsible 500 * for prioritizing among those sources on the fly. 501 */ 502 QueueEntry* getNextQueueEntry(); 503 504 /** 505 * Send up a snoop request and find cached copies. If cached copies are 506 * found, set the BLOCK_CACHED flag in pkt. 507 */ 508 bool isCachedAbove(PacketPtr pkt, bool is_timing = true) const; 509 510 /** 511 * Return whether there are any outstanding misses. 512 */ 513 bool outstandingMisses() const 514 { 515 return !mshrQueue.isEmpty(); 516 } 517 518 CacheBlk *findBlock(Addr addr, bool is_secure) const { 519 return tags->findBlock(addr, is_secure); 520 } 521 522 bool inCache(Addr addr, bool is_secure) const override { 523 return (tags->findBlock(addr, is_secure) != 0); 524 } 525 526 bool inMissQueue(Addr addr, bool is_secure) const override { 527 return (mshrQueue.findMatch(addr, is_secure) != 0); 528 } 529 530 /** 531 * Find next request ready time from among possible sources. 532 */ 533 Tick nextQueueReadyTime() const; 534 535 public: 536 /** Instantiates a basic cache object. */ 537 Cache(const CacheParams *p); 538 539 /** Non-default destructor is needed to deallocate memory. */ 540 virtual ~Cache(); 541 542 void regStats() override; 543 544 /** 545 * Take an MSHR, turn it into a suitable downstream packet, and 546 * send it out. This construct allows a queue entry to choose a suitable 547 * approach based on its type. 548 * 549 * @param mshr The MSHR to turn into a packet and send 550 * @return True if the port is waiting for a retry 551 */ 552 bool sendMSHRQueuePacket(MSHR* mshr); 553 554 /** 555 * Similar to sendMSHR, but for a write-queue entry 556 * instead. Create the packet, and send it, and if successful also 557 * mark the entry in service. 558 * 559 * @param wq_entry The write-queue entry to turn into a packet and send 560 * @return True if the port is waiting for a retry 561 */ 562 bool sendWriteQueuePacket(WriteQueueEntry* wq_entry); 563 564 /** serialize the state of the caches 565 * We currently don't support checkpointing cache state, so this panics. 566 */ 567 void serialize(CheckpointOut &cp) const override; 568 void unserialize(CheckpointIn &cp) override; 569}; 570 571/** 572 * Wrap a method and present it as a cache block visitor. 573 * 574 * For example the forEachBlk method in the tag arrays expects a 575 * callable object/function as their parameter. This class wraps a 576 * method in an object and presents callable object that adheres to 577 * the cache block visitor protocol. 578 */ 579class CacheBlkVisitorWrapper : public CacheBlkVisitor 580{ 581 public: 582 typedef bool (Cache::*VisitorPtr)(CacheBlk &blk); 583 584 CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor) 585 : cache(_cache), visitor(_visitor) {} 586 587 bool operator()(CacheBlk &blk) override { 588 return (cache.*visitor)(blk); 589 } 590 591 private: 592 Cache &cache; 593 VisitorPtr visitor; 594}; 595 596/** 597 * Cache block visitor that determines if there are dirty blocks in a 598 * cache. 599 * 600 * Use with the forEachBlk method in the tag array to determine if the 601 * array contains dirty blocks. 602 */ 603class CacheBlkIsDirtyVisitor : public CacheBlkVisitor 604{ 605 public: 606 CacheBlkIsDirtyVisitor() 607 : _isDirty(false) {} 608 609 bool operator()(CacheBlk &blk) override { 610 if (blk.isDirty()) { 611 _isDirty = true; 612 return false; 613 } else { 614 return true; 615 } 616 } 617 618 /** 619 * Does the array contain a dirty line? 620 * 621 * \return true if yes, false otherwise. 622 */ 623 bool isDirty() const { return _isDirty; }; 624 625 private: 626 bool _isDirty; 627}; 628 629#endif // __MEM_CACHE_CACHE_HH__ 630