cache.hh revision 11197:f8fdd931e674
1/* 2 * Copyright (c) 2012-2015 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Dave Greene 42 * Steve Reinhardt 43 * Ron Dreslinski 44 * Andreas Hansson 45 */ 46 47/** 48 * @file 49 * Describes a cache based on template policies. 50 */ 51 52#ifndef __MEM_CACHE_CACHE_HH__ 53#define __MEM_CACHE_CACHE_HH__ 54 55#include "base/misc.hh" // fatal, panic, and warn 56#include "enums/Clusivity.hh" 57#include "mem/cache/base.hh" 58#include "mem/cache/blk.hh" 59#include "mem/cache/mshr.hh" 60#include "mem/cache/tags/base.hh" 61#include "params/Cache.hh" 62#include "sim/eventq.hh" 63 64//Forward decleration 65class BasePrefetcher; 66 67/** 68 * A template-policy based cache. The behavior of the cache can be altered by 69 * supplying different template policies. TagStore handles all tag and data 70 * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System" 71 */ 72class Cache : public BaseCache 73{ 74 public: 75 76 /** A typedef for a list of CacheBlk pointers. */ 77 typedef std::list<CacheBlk*> BlkList; 78 79 protected: 80 81 /** 82 * The CPU-side port extends the base cache slave port with access 83 * functions for functional, atomic and timing requests. 84 */ 85 class CpuSidePort : public CacheSlavePort 86 { 87 private: 88 89 // a pointer to our specific cache implementation 90 Cache *cache; 91 92 protected: 93 94 virtual bool recvTimingSnoopResp(PacketPtr pkt); 95 96 virtual bool recvTimingReq(PacketPtr pkt); 97 98 virtual Tick recvAtomic(PacketPtr pkt); 99 100 virtual void recvFunctional(PacketPtr pkt); 101 102 virtual AddrRangeList getAddrRanges() const; 103 104 public: 105 106 CpuSidePort(const std::string &_name, Cache *_cache, 107 const std::string &_label); 108 109 }; 110 111 /** 112 * Override the default behaviour of sendDeferredPacket to enable 113 * the memory-side cache port to also send requests based on the 114 * current MSHR status. This queue has a pointer to our specific 115 * cache implementation and is used by the MemSidePort. 116 */ 117 class CacheReqPacketQueue : public ReqPacketQueue 118 { 119 120 protected: 121 122 Cache &cache; 123 SnoopRespPacketQueue &snoopRespQueue; 124 125 public: 126 127 CacheReqPacketQueue(Cache &cache, MasterPort &port, 128 SnoopRespPacketQueue &snoop_resp_queue, 129 const std::string &label) : 130 ReqPacketQueue(cache, port, label), cache(cache), 131 snoopRespQueue(snoop_resp_queue) { } 132 133 /** 134 * Override the normal sendDeferredPacket and do not only 135 * consider the transmit list (used for responses), but also 136 * requests. 137 */ 138 virtual void sendDeferredPacket(); 139 140 }; 141 142 /** 143 * The memory-side port extends the base cache master port with 144 * access functions for functional, atomic and timing snoops. 145 */ 146 class MemSidePort : public CacheMasterPort 147 { 148 private: 149 150 /** The cache-specific queue. */ 151 CacheReqPacketQueue _reqQueue; 152 153 SnoopRespPacketQueue _snoopRespQueue; 154 155 // a pointer to our specific cache implementation 156 Cache *cache; 157 158 protected: 159 160 virtual void recvTimingSnoopReq(PacketPtr pkt); 161 162 virtual bool recvTimingResp(PacketPtr pkt); 163 164 virtual Tick recvAtomicSnoop(PacketPtr pkt); 165 166 virtual void recvFunctionalSnoop(PacketPtr pkt); 167 168 public: 169 170 MemSidePort(const std::string &_name, Cache *_cache, 171 const std::string &_label); 172 }; 173 174 /** Tag and data Storage */ 175 BaseTags *tags; 176 177 /** Prefetcher */ 178 BasePrefetcher *prefetcher; 179 180 /** Temporary cache block for occasional transitory use */ 181 CacheBlk *tempBlock; 182 183 /** 184 * This cache should allocate a block on a line-sized write miss. 185 */ 186 const bool doFastWrites; 187 188 /** 189 * Turn line-sized writes into WriteInvalidate transactions. 190 */ 191 void promoteWholeLineWrites(PacketPtr pkt); 192 193 /** 194 * Notify the prefetcher on every access, not just misses. 195 */ 196 const bool prefetchOnAccess; 197 198 /** 199 * Clusivity with respect to the upstream cache, determining if we 200 * fill into both this cache and the cache above on a miss. Note 201 * that we currently do not support strict clusivity policies. 202 */ 203 const Enums::Clusivity clusivity; 204 205 /** 206 * Upstream caches need this packet until true is returned, so 207 * hold it for deletion until a subsequent call 208 */ 209 std::unique_ptr<Packet> pendingDelete; 210 211 /** 212 * Writebacks from the tempBlock, resulting on the response path 213 * in atomic mode, must happen after the call to recvAtomic has 214 * finished (for the right ordering of the packets). We therefore 215 * need to hold on to the packets, and have a method and an event 216 * to send them. 217 */ 218 PacketPtr tempBlockWriteback; 219 220 /** 221 * Send the outstanding tempBlock writeback. To be called after 222 * recvAtomic finishes in cases where the block we filled is in 223 * fact the tempBlock, and now needs to be written back. 224 */ 225 void writebackTempBlockAtomic() { 226 assert(tempBlockWriteback != nullptr); 227 PacketList writebacks{tempBlockWriteback}; 228 doWritebacksAtomic(writebacks); 229 tempBlockWriteback = nullptr; 230 } 231 232 /** 233 * An event to writeback the tempBlock after recvAtomic 234 * finishes. To avoid other calls to recvAtomic getting in 235 * between, we create this event with a higher priority. 236 */ 237 EventWrapper<Cache, &Cache::writebackTempBlockAtomic> \ 238 writebackTempBlockAtomicEvent; 239 240 /** 241 * Does all the processing necessary to perform the provided request. 242 * @param pkt The memory request to perform. 243 * @param blk The cache block to be updated. 244 * @param lat The latency of the access. 245 * @param writebacks List for any writebacks that need to be performed. 246 * @return Boolean indicating whether the request was satisfied. 247 */ 248 bool access(PacketPtr pkt, CacheBlk *&blk, 249 Cycles &lat, PacketList &writebacks); 250 251 /** 252 *Handle doing the Compare and Swap function for SPARC. 253 */ 254 void cmpAndSwap(CacheBlk *blk, PacketPtr pkt); 255 256 /** 257 * Find a block frame for new block at address addr targeting the 258 * given security space, assuming that the block is not currently 259 * in the cache. Append writebacks if any to provided packet 260 * list. Return free block frame. May return NULL if there are 261 * no replaceable blocks at the moment. 262 */ 263 CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks); 264 265 /** 266 * Invalidate a cache block. 267 * 268 * @param blk Block to invalidate 269 */ 270 void invalidateBlock(CacheBlk *blk); 271 272 /** 273 * Populates a cache block and handles all outstanding requests for the 274 * satisfied fill request. This version takes two memory requests. One 275 * contains the fill data, the other is an optional target to satisfy. 276 * @param pkt The memory request with the fill data. 277 * @param blk The cache block if it already exists. 278 * @param writebacks List for any writebacks that need to be performed. 279 * @param allocate Whether to allocate a block or use the temp block 280 * @return Pointer to the new cache block. 281 */ 282 CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk, 283 PacketList &writebacks, bool allocate); 284 285 /** 286 * Determine whether we should allocate on a fill or not. If this 287 * cache is mostly inclusive with regards to the upstream cache(s) 288 * we always allocate (for any non-forwarded and cacheable 289 * requests). In the case of a mostly exclusive cache, we allocate 290 * on fill if the packet did not come from a cache, thus if we: 291 * are dealing with a whole-line write (the latter behaves much 292 * like a writeback), the original target packet came from a 293 * non-caching source, or if we are performing a prefetch or LLSC. 294 * 295 * @param cmd Command of the incoming requesting packet 296 * @return Whether we should allocate on the fill 297 */ 298 inline bool allocOnFill(MemCmd cmd) const 299 { 300 return clusivity == Enums::mostly_incl || 301 cmd == MemCmd::WriteLineReq || 302 cmd == MemCmd::ReadReq || 303 cmd == MemCmd::WriteReq || 304 cmd.isPrefetch() || 305 cmd.isLLSC(); 306 } 307 308 /** 309 * Performs the access specified by the request. 310 * @param pkt The request to perform. 311 * @return The result of the access. 312 */ 313 bool recvTimingReq(PacketPtr pkt); 314 315 /** 316 * Insert writebacks into the write buffer 317 */ 318 void doWritebacks(PacketList& writebacks, Tick forward_time); 319 320 /** 321 * Send writebacks down the memory hierarchy in atomic mode 322 */ 323 void doWritebacksAtomic(PacketList& writebacks); 324 325 /** 326 * Handles a response (cache line fill/write ack) from the bus. 327 * @param pkt The response packet 328 */ 329 void recvTimingResp(PacketPtr pkt); 330 331 /** 332 * Snoops bus transactions to maintain coherence. 333 * @param pkt The current bus transaction. 334 */ 335 void recvTimingSnoopReq(PacketPtr pkt); 336 337 /** 338 * Handle a snoop response. 339 * @param pkt Snoop response packet 340 */ 341 void recvTimingSnoopResp(PacketPtr pkt); 342 343 /** 344 * Performs the access specified by the request. 345 * @param pkt The request to perform. 346 * @return The number of ticks required for the access. 347 */ 348 Tick recvAtomic(PacketPtr pkt); 349 350 /** 351 * Snoop for the provided request in the cache and return the estimated 352 * time taken. 353 * @param pkt The memory request to snoop 354 * @return The number of ticks required for the snoop. 355 */ 356 Tick recvAtomicSnoop(PacketPtr pkt); 357 358 /** 359 * Performs the access specified by the request. 360 * @param pkt The request to perform. 361 * @param fromCpuSide from the CPU side port or the memory side port 362 */ 363 void functionalAccess(PacketPtr pkt, bool fromCpuSide); 364 365 void satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk, 366 bool deferred_response = false, 367 bool pending_downgrade = false); 368 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, CacheBlk *blk); 369 370 void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 371 bool already_copied, bool pending_inval); 372 373 /** 374 * Perform an upward snoop if needed, and update the block state 375 * (possibly invalidating the block). Also create a response if required. 376 * 377 * @param pkt Snoop packet 378 * @param blk Cache block being snooped 379 * @param is_timing Timing or atomic for the response 380 * @param is_deferred Is this a deferred snoop or not? 381 * @param pending_inval Do we have a pending invalidation? 382 * 383 * @return The snoop delay incurred by the upwards snoop 384 */ 385 uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk, 386 bool is_timing, bool is_deferred, bool pending_inval); 387 388 /** 389 * Create a writeback request for the given block. 390 * @param blk The block to writeback. 391 * @return The writeback request for the block. 392 */ 393 PacketPtr writebackBlk(CacheBlk *blk); 394 395 /** 396 * Create a CleanEvict request for the given block. 397 * @param blk The block to evict. 398 * @return The CleanEvict request for the block. 399 */ 400 PacketPtr cleanEvictBlk(CacheBlk *blk); 401 402 403 void memWriteback() override; 404 void memInvalidate() override; 405 bool isDirty() const override; 406 407 /** 408 * Cache block visitor that writes back dirty cache blocks using 409 * functional writes. 410 * 411 * \return Always returns true. 412 */ 413 bool writebackVisitor(CacheBlk &blk); 414 /** 415 * Cache block visitor that invalidates all blocks in the cache. 416 * 417 * @warn Dirty cache lines will not be written back to memory. 418 * 419 * \return Always returns true. 420 */ 421 bool invalidateVisitor(CacheBlk &blk); 422 423 /** 424 * Generate an appropriate downstream bus request packet for the 425 * given parameters. 426 * @param cpu_pkt The upstream request that needs to be satisfied. 427 * @param blk The block currently in the cache corresponding to 428 * cpu_pkt (NULL if none). 429 * @param needsExclusive Indicates that an exclusive copy is required 430 * even if the request in cpu_pkt doesn't indicate that. 431 * @return A new Packet containing the request, or NULL if the 432 * current request in cpu_pkt should just be forwarded on. 433 */ 434 PacketPtr getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk, 435 bool needsExclusive) const; 436 437 /** 438 * Return the next MSHR to service, either a pending miss from the 439 * mshrQueue, a buffered write from the write buffer, or something 440 * from the prefetcher. This function is responsible for 441 * prioritizing among those sources on the fly. 442 */ 443 MSHR *getNextMSHR(); 444 445 /** 446 * Send up a snoop request and find cached copies. If cached copies are 447 * found, set the BLOCK_CACHED flag in pkt. 448 */ 449 bool isCachedAbove(PacketPtr pkt, bool is_timing = true) const; 450 451 /** 452 * Selects an outstanding request to service. Called when the 453 * cache gets granted the downstream bus in timing mode. 454 * @return The request to service, NULL if none found. 455 */ 456 PacketPtr getTimingPacket(); 457 458 /** 459 * Marks a request as in service (sent on the bus). This can have 460 * side effect since storage for no response commands is 461 * deallocated once they are successfully sent. Also remember if 462 * we are expecting a dirty response from another cache, 463 * effectively making this MSHR the ordering point. 464 */ 465 void markInService(MSHR *mshr, bool pending_dirty_resp); 466 467 /** 468 * Return whether there are any outstanding misses. 469 */ 470 bool outstandingMisses() const 471 { 472 return mshrQueue.allocated != 0; 473 } 474 475 CacheBlk *findBlock(Addr addr, bool is_secure) const { 476 return tags->findBlock(addr, is_secure); 477 } 478 479 bool inCache(Addr addr, bool is_secure) const override { 480 return (tags->findBlock(addr, is_secure) != 0); 481 } 482 483 bool inMissQueue(Addr addr, bool is_secure) const override { 484 return (mshrQueue.findMatch(addr, is_secure) != 0); 485 } 486 487 /** 488 * Find next request ready time from among possible sources. 489 */ 490 Tick nextMSHRReadyTime() const; 491 492 public: 493 /** Instantiates a basic cache object. */ 494 Cache(const CacheParams *p); 495 496 /** Non-default destructor is needed to deallocate memory. */ 497 virtual ~Cache(); 498 499 void regStats() override; 500 501 /** serialize the state of the caches 502 * We currently don't support checkpointing cache state, so this panics. 503 */ 504 void serialize(CheckpointOut &cp) const override; 505 void unserialize(CheckpointIn &cp) override; 506}; 507 508/** 509 * Wrap a method and present it as a cache block visitor. 510 * 511 * For example the forEachBlk method in the tag arrays expects a 512 * callable object/function as their parameter. This class wraps a 513 * method in an object and presents callable object that adheres to 514 * the cache block visitor protocol. 515 */ 516class CacheBlkVisitorWrapper : public CacheBlkVisitor 517{ 518 public: 519 typedef bool (Cache::*VisitorPtr)(CacheBlk &blk); 520 521 CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor) 522 : cache(_cache), visitor(_visitor) {} 523 524 bool operator()(CacheBlk &blk) override { 525 return (cache.*visitor)(blk); 526 } 527 528 private: 529 Cache &cache; 530 VisitorPtr visitor; 531}; 532 533/** 534 * Cache block visitor that determines if there are dirty blocks in a 535 * cache. 536 * 537 * Use with the forEachBlk method in the tag array to determine if the 538 * array contains dirty blocks. 539 */ 540class CacheBlkIsDirtyVisitor : public CacheBlkVisitor 541{ 542 public: 543 CacheBlkIsDirtyVisitor() 544 : _isDirty(false) {} 545 546 bool operator()(CacheBlk &blk) override { 547 if (blk.isDirty()) { 548 _isDirty = true; 549 return false; 550 } else { 551 return true; 552 } 553 } 554 555 /** 556 * Does the array contain a dirty line? 557 * 558 * \return true if yes, false otherwise. 559 */ 560 bool isDirty() const { return _isDirty; }; 561 562 private: 563 bool _isDirty; 564}; 565 566#endif // __MEM_CACHE_CACHE_HH__ 567