cache.hh revision 11051:81b1f46061c8
1/* 2 * Copyright (c) 2012-2014 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Dave Greene 42 * Steve Reinhardt 43 * Ron Dreslinski 44 * Andreas Hansson 45 */ 46 47/** 48 * @file 49 * Describes a cache based on template policies. 50 */ 51 52#ifndef __MEM_CACHE_CACHE_HH__ 53#define __MEM_CACHE_CACHE_HH__ 54 55#include "base/misc.hh" // fatal, panic, and warn 56#include "mem/cache/base.hh" 57#include "mem/cache/blk.hh" 58#include "mem/cache/mshr.hh" 59#include "mem/cache/tags/base.hh" 60#include "sim/eventq.hh" 61 62//Forward decleration 63class BasePrefetcher; 64 65/** 66 * A template-policy based cache. The behavior of the cache can be altered by 67 * supplying different template policies. TagStore handles all tag and data 68 * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System" 69 */ 70class Cache : public BaseCache 71{ 72 public: 73 74 /** A typedef for a list of CacheBlk pointers. */ 75 typedef std::list<CacheBlk*> BlkList; 76 77 protected: 78 79 /** 80 * The CPU-side port extends the base cache slave port with access 81 * functions for functional, atomic and timing requests. 82 */ 83 class CpuSidePort : public CacheSlavePort 84 { 85 private: 86 87 // a pointer to our specific cache implementation 88 Cache *cache; 89 90 protected: 91 92 virtual bool recvTimingSnoopResp(PacketPtr pkt); 93 94 virtual bool recvTimingReq(PacketPtr pkt); 95 96 virtual Tick recvAtomic(PacketPtr pkt); 97 98 virtual void recvFunctional(PacketPtr pkt); 99 100 virtual AddrRangeList getAddrRanges() const; 101 102 public: 103 104 CpuSidePort(const std::string &_name, Cache *_cache, 105 const std::string &_label); 106 107 }; 108 109 /** 110 * Override the default behaviour of sendDeferredPacket to enable 111 * the memory-side cache port to also send requests based on the 112 * current MSHR status. This queue has a pointer to our specific 113 * cache implementation and is used by the MemSidePort. 114 */ 115 class CacheReqPacketQueue : public ReqPacketQueue 116 { 117 118 protected: 119 120 Cache &cache; 121 SnoopRespPacketQueue &snoopRespQueue; 122 123 public: 124 125 CacheReqPacketQueue(Cache &cache, MasterPort &port, 126 SnoopRespPacketQueue &snoop_resp_queue, 127 const std::string &label) : 128 ReqPacketQueue(cache, port, label), cache(cache), 129 snoopRespQueue(snoop_resp_queue) { } 130 131 /** 132 * Override the normal sendDeferredPacket and do not only 133 * consider the transmit list (used for responses), but also 134 * requests. 135 */ 136 virtual void sendDeferredPacket(); 137 138 }; 139 140 /** 141 * The memory-side port extends the base cache master port with 142 * access functions for functional, atomic and timing snoops. 143 */ 144 class MemSidePort : public CacheMasterPort 145 { 146 private: 147 148 /** The cache-specific queue. */ 149 CacheReqPacketQueue _reqQueue; 150 151 SnoopRespPacketQueue _snoopRespQueue; 152 153 // a pointer to our specific cache implementation 154 Cache *cache; 155 156 protected: 157 158 virtual void recvTimingSnoopReq(PacketPtr pkt); 159 160 virtual bool recvTimingResp(PacketPtr pkt); 161 162 virtual Tick recvAtomicSnoop(PacketPtr pkt); 163 164 virtual void recvFunctionalSnoop(PacketPtr pkt); 165 166 public: 167 168 MemSidePort(const std::string &_name, Cache *_cache, 169 const std::string &_label); 170 }; 171 172 /** Tag and data Storage */ 173 BaseTags *tags; 174 175 /** Prefetcher */ 176 BasePrefetcher *prefetcher; 177 178 /** Temporary cache block for occasional transitory use */ 179 CacheBlk *tempBlock; 180 181 /** 182 * This cache should allocate a block on a line-sized write miss. 183 */ 184 const bool doFastWrites; 185 186 /** 187 * Turn line-sized writes into WriteInvalidate transactions. 188 */ 189 void promoteWholeLineWrites(PacketPtr pkt); 190 191 /** 192 * Notify the prefetcher on every access, not just misses. 193 */ 194 const bool prefetchOnAccess; 195 196 /** 197 * @todo this is a temporary workaround until the 4-phase code is committed. 198 * upstream caches need this packet until true is returned, so hold it for 199 * deletion until a subsequent call 200 */ 201 std::vector<PacketPtr> pendingDelete; 202 203 /** 204 * Does all the processing necessary to perform the provided request. 205 * @param pkt The memory request to perform. 206 * @param blk The cache block to be updated. 207 * @param lat The latency of the access. 208 * @param writebacks List for any writebacks that need to be performed. 209 * @return Boolean indicating whether the request was satisfied. 210 */ 211 bool access(PacketPtr pkt, CacheBlk *&blk, 212 Cycles &lat, PacketList &writebacks); 213 214 /** 215 *Handle doing the Compare and Swap function for SPARC. 216 */ 217 void cmpAndSwap(CacheBlk *blk, PacketPtr pkt); 218 219 /** 220 * Find a block frame for new block at address addr targeting the 221 * given security space, assuming that the block is not currently 222 * in the cache. Append writebacks if any to provided packet 223 * list. Return free block frame. May return NULL if there are 224 * no replaceable blocks at the moment. 225 */ 226 CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks); 227 228 /** 229 * Populates a cache block and handles all outstanding requests for the 230 * satisfied fill request. This version takes two memory requests. One 231 * contains the fill data, the other is an optional target to satisfy. 232 * @param pkt The memory request with the fill data. 233 * @param blk The cache block if it already exists. 234 * @param writebacks List for any writebacks that need to be performed. 235 * @return Pointer to the new cache block. 236 */ 237 CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk, 238 PacketList &writebacks); 239 240 241 /** 242 * Performs the access specified by the request. 243 * @param pkt The request to perform. 244 * @return The result of the access. 245 */ 246 bool recvTimingReq(PacketPtr pkt); 247 248 /** 249 * Insert writebacks into the write buffer 250 */ 251 void doWritebacks(PacketList& writebacks, Tick forward_time); 252 253 /** 254 * Handles a response (cache line fill/write ack) from the bus. 255 * @param pkt The response packet 256 */ 257 void recvTimingResp(PacketPtr pkt); 258 259 /** 260 * Snoops bus transactions to maintain coherence. 261 * @param pkt The current bus transaction. 262 */ 263 void recvTimingSnoopReq(PacketPtr pkt); 264 265 /** 266 * Handle a snoop response. 267 * @param pkt Snoop response packet 268 */ 269 void recvTimingSnoopResp(PacketPtr pkt); 270 271 /** 272 * Performs the access specified by the request. 273 * @param pkt The request to perform. 274 * @return The number of ticks required for the access. 275 */ 276 Tick recvAtomic(PacketPtr pkt); 277 278 /** 279 * Snoop for the provided request in the cache and return the estimated 280 * time taken. 281 * @param pkt The memory request to snoop 282 * @return The number of ticks required for the snoop. 283 */ 284 Tick recvAtomicSnoop(PacketPtr pkt); 285 286 /** 287 * Performs the access specified by the request. 288 * @param pkt The request to perform. 289 * @param fromCpuSide from the CPU side port or the memory side port 290 */ 291 void functionalAccess(PacketPtr pkt, bool fromCpuSide); 292 293 void satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk, 294 bool deferred_response = false, 295 bool pending_downgrade = false); 296 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, CacheBlk *blk); 297 298 void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 299 bool already_copied, bool pending_inval); 300 301 /** 302 * Sets the blk to the new state. 303 * @param blk The cache block being snooped. 304 * @param new_state The new coherence state for the block. 305 */ 306 void handleSnoop(PacketPtr ptk, CacheBlk *blk, 307 bool is_timing, bool is_deferred, bool pending_inval); 308 309 /** 310 * Create a writeback request for the given block. 311 * @param blk The block to writeback. 312 * @return The writeback request for the block. 313 */ 314 PacketPtr writebackBlk(CacheBlk *blk); 315 316 /** 317 * Create a CleanEvict request for the given block. 318 * @param blk The block to evict. 319 * @return The CleanEvict request for the block. 320 */ 321 PacketPtr cleanEvictBlk(CacheBlk *blk); 322 323 324 void memWriteback(); 325 void memInvalidate(); 326 bool isDirty() const; 327 328 /** 329 * Cache block visitor that writes back dirty cache blocks using 330 * functional writes. 331 * 332 * \return Always returns true. 333 */ 334 bool writebackVisitor(CacheBlk &blk); 335 /** 336 * Cache block visitor that invalidates all blocks in the cache. 337 * 338 * @warn Dirty cache lines will not be written back to memory. 339 * 340 * \return Always returns true. 341 */ 342 bool invalidateVisitor(CacheBlk &blk); 343 344 /** 345 * Squash all requests associated with specified thread. 346 * intended for use by I-cache. 347 * @param threadNum The thread to squash. 348 */ 349 void squash(int threadNum); 350 351 /** 352 * Generate an appropriate downstream bus request packet for the 353 * given parameters. 354 * @param cpu_pkt The upstream request that needs to be satisfied. 355 * @param blk The block currently in the cache corresponding to 356 * cpu_pkt (NULL if none). 357 * @param needsExclusive Indicates that an exclusive copy is required 358 * even if the request in cpu_pkt doesn't indicate that. 359 * @return A new Packet containing the request, or NULL if the 360 * current request in cpu_pkt should just be forwarded on. 361 */ 362 PacketPtr getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk, 363 bool needsExclusive) const; 364 365 /** 366 * Return the next MSHR to service, either a pending miss from the 367 * mshrQueue, a buffered write from the write buffer, or something 368 * from the prefetcher. This function is responsible for 369 * prioritizing among those sources on the fly. 370 */ 371 MSHR *getNextMSHR(); 372 373 /** 374 * Send up a snoop request and find cached copies. If cached copies are 375 * found, set the BLOCK_CACHED flag in pkt. 376 */ 377 bool isCachedAbove(const PacketPtr pkt) const; 378 379 /** 380 * Selects an outstanding request to service. Called when the 381 * cache gets granted the downstream bus in timing mode. 382 * @return The request to service, NULL if none found. 383 */ 384 PacketPtr getTimingPacket(); 385 386 /** 387 * Marks a request as in service (sent on the bus). This can have 388 * side effect since storage for no response commands is 389 * deallocated once they are successfully sent. Also remember if 390 * we are expecting a dirty response from another cache, 391 * effectively making this MSHR the ordering point. 392 */ 393 void markInService(MSHR *mshr, bool pending_dirty_resp); 394 395 /** 396 * Return whether there are any outstanding misses. 397 */ 398 bool outstandingMisses() const 399 { 400 return mshrQueue.allocated != 0; 401 } 402 403 CacheBlk *findBlock(Addr addr, bool is_secure) const { 404 return tags->findBlock(addr, is_secure); 405 } 406 407 bool inCache(Addr addr, bool is_secure) const { 408 return (tags->findBlock(addr, is_secure) != 0); 409 } 410 411 bool inMissQueue(Addr addr, bool is_secure) const { 412 return (mshrQueue.findMatch(addr, is_secure) != 0); 413 } 414 415 /** 416 * Find next request ready time from among possible sources. 417 */ 418 Tick nextMSHRReadyTime() const; 419 420 public: 421 /** Instantiates a basic cache object. */ 422 Cache(const Params *p); 423 424 /** Non-default destructor is needed to deallocate memory. */ 425 virtual ~Cache(); 426 427 void regStats(); 428 429 /** serialize the state of the caches 430 * We currently don't support checkpointing cache state, so this panics. 431 */ 432 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 433 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; 434}; 435 436/** 437 * Wrap a method and present it as a cache block visitor. 438 * 439 * For example the forEachBlk method in the tag arrays expects a 440 * callable object/function as their parameter. This class wraps a 441 * method in an object and presents callable object that adheres to 442 * the cache block visitor protocol. 443 */ 444class CacheBlkVisitorWrapper : public CacheBlkVisitor 445{ 446 public: 447 typedef bool (Cache::*VisitorPtr)(CacheBlk &blk); 448 449 CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor) 450 : cache(_cache), visitor(_visitor) {} 451 452 bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE { 453 return (cache.*visitor)(blk); 454 } 455 456 private: 457 Cache &cache; 458 VisitorPtr visitor; 459}; 460 461/** 462 * Cache block visitor that determines if there are dirty blocks in a 463 * cache. 464 * 465 * Use with the forEachBlk method in the tag array to determine if the 466 * array contains dirty blocks. 467 */ 468class CacheBlkIsDirtyVisitor : public CacheBlkVisitor 469{ 470 public: 471 CacheBlkIsDirtyVisitor() 472 : _isDirty(false) {} 473 474 bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE { 475 if (blk.isDirty()) { 476 _isDirty = true; 477 return false; 478 } else { 479 return true; 480 } 481 } 482 483 /** 484 * Does the array contain a dirty line? 485 * 486 * \return true if yes, false otherwise. 487 */ 488 bool isDirty() const { return _isDirty; }; 489 490 private: 491 bool _isDirty; 492}; 493 494#endif // __MEM_CACHE_CACHE_HH__ 495