cache.hh revision 10770:c48310de1a51 
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 *          Dave Greene
42 *          Steve Reinhardt
43 *          Ron Dreslinski
44 *          Andreas Hansson
45 */
46
47/**
48 * @file
49 * Describes a cache based on template policies.
50 */
51
52#ifndef __CACHE_HH__
53#define __CACHE_HH__
54
55#include "base/misc.hh" // fatal, panic, and warn
56#include "mem/cache/base.hh"
57#include "mem/cache/blk.hh"
58#include "mem/cache/mshr.hh"
59#include "sim/eventq.hh"
60
61//Forward decleration
62class BasePrefetcher;
63
64/**
65 * A template-policy based cache. The behavior of the cache can be altered by
66 * supplying different template policies. TagStore handles all tag and data
67 * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System"
68 */
69template <class TagStore>
70class Cache : public BaseCache
71{
72  public:
73    /** Define the type of cache block to use. */
74    typedef typename TagStore::BlkType BlkType;
75    /** A typedef for a list of BlkType pointers. */
76    typedef typename TagStore::BlkList BlkList;
77
78  protected:
79    typedef CacheBlkVisitorWrapper<Cache<TagStore>, BlkType> WrappedBlkVisitor;
80
81    /**
82     * The CPU-side port extends the base cache slave port with access
83     * functions for functional, atomic and timing requests.
84     */
85    class CpuSidePort : public CacheSlavePort
86    {
87      private:
88
89        // a pointer to our specific cache implementation
90        Cache<TagStore> *cache;
91
92      protected:
93
94        virtual bool recvTimingSnoopResp(PacketPtr pkt);
95
96        virtual bool recvTimingReq(PacketPtr pkt);
97
98        virtual Tick recvAtomic(PacketPtr pkt);
99
100        virtual void recvFunctional(PacketPtr pkt);
101
102        virtual AddrRangeList getAddrRanges() const;
103
104      public:
105
106        CpuSidePort(const std::string &_name, Cache<TagStore> *_cache,
107                    const std::string &_label);
108
109    };
110
111    /**
112     * Override the default behaviour of sendDeferredPacket to enable
113     * the memory-side cache port to also send requests based on the
114     * current MSHR status. This queue has a pointer to our specific
115     * cache implementation and is used by the MemSidePort.
116     */
117    class CacheReqPacketQueue : public ReqPacketQueue
118    {
119
120      protected:
121
122        Cache<TagStore> &cache;
123        SnoopRespPacketQueue &snoopRespQueue;
124
125      public:
126
127        CacheReqPacketQueue(Cache<TagStore> &cache, MasterPort &port,
128                            SnoopRespPacketQueue &snoop_resp_queue,
129                            const std::string &label) :
130            ReqPacketQueue(cache, port, label), cache(cache),
131            snoopRespQueue(snoop_resp_queue) { }
132
133        /**
134         * Override the normal sendDeferredPacket and do not only
135         * consider the transmit list (used for responses), but also
136         * requests.
137         */
138        virtual void sendDeferredPacket();
139
140    };
141
142    /**
143     * The memory-side port extends the base cache master port with
144     * access functions for functional, atomic and timing snoops.
145     */
146    class MemSidePort : public CacheMasterPort
147    {
148      private:
149
150        /** The cache-specific queue. */
151        CacheReqPacketQueue _reqQueue;
152
153        SnoopRespPacketQueue _snoopRespQueue;
154
155        // a pointer to our specific cache implementation
156        Cache<TagStore> *cache;
157
158      protected:
159
160        virtual void recvTimingSnoopReq(PacketPtr pkt);
161
162        virtual bool recvTimingResp(PacketPtr pkt);
163
164        virtual Tick recvAtomicSnoop(PacketPtr pkt);
165
166        virtual void recvFunctionalSnoop(PacketPtr pkt);
167
168      public:
169
170        MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
171                    const std::string &_label);
172    };
173
174    /** Tag and data Storage */
175    TagStore *tags;
176
177    /** Prefetcher */
178    BasePrefetcher *prefetcher;
179
180    /** Temporary cache block for occasional transitory use */
181    BlkType *tempBlock;
182
183    /**
184     * This cache should allocate a block on a line-sized write miss.
185     */
186    const bool doFastWrites;
187
188    /**
189     * Turn line-sized writes into WriteInvalidate transactions.
190     */
191    void promoteWholeLineWrites(PacketPtr pkt);
192
193    /**
194     * Notify the prefetcher on every access, not just misses.
195     */
196    const bool prefetchOnAccess;
197
198    /**
199     * @todo this is a temporary workaround until the 4-phase code is committed.
200     * upstream caches need this packet until true is returned, so hold it for
201     * deletion until a subsequent call
202     */
203    std::vector<PacketPtr> pendingDelete;
204
205    /**
206     * Does all the processing necessary to perform the provided request.
207     * @param pkt The memory request to perform.
208     * @param blk The cache block to be updated.
209     * @param lat The latency of the access.
210     * @param writebacks List for any writebacks that need to be performed.
211     * @return Boolean indicating whether the request was satisfied.
212     */
213    bool access(PacketPtr pkt, BlkType *&blk,
214                Cycles &lat, PacketList &writebacks);
215
216    /**
217     *Handle doing the Compare and Swap function for SPARC.
218     */
219    void cmpAndSwap(BlkType *blk, PacketPtr pkt);
220
221    /**
222     * Find a block frame for new block at address addr targeting the
223     * given security space, assuming that the block is not currently
224     * in the cache.  Append writebacks if any to provided packet
225     * list.  Return free block frame.  May return NULL if there are
226     * no replaceable blocks at the moment.
227     */
228    BlkType *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
229
230    /**
231     * Populates a cache block and handles all outstanding requests for the
232     * satisfied fill request. This version takes two memory requests. One
233     * contains the fill data, the other is an optional target to satisfy.
234     * @param pkt The memory request with the fill data.
235     * @param blk The cache block if it already exists.
236     * @param writebacks List for any writebacks that need to be performed.
237     * @return Pointer to the new cache block.
238     */
239    BlkType *handleFill(PacketPtr pkt, BlkType *blk,
240                        PacketList &writebacks);
241
242
243    /**
244     * Performs the access specified by the request.
245     * @param pkt The request to perform.
246     * @return The result of the access.
247     */
248    bool recvTimingReq(PacketPtr pkt);
249
250    /**
251     * Handles a response (cache line fill/write ack) from the bus.
252     * @param pkt The response packet
253     */
254    void recvTimingResp(PacketPtr pkt);
255
256    /**
257     * Snoops bus transactions to maintain coherence.
258     * @param pkt The current bus transaction.
259     */
260    void recvTimingSnoopReq(PacketPtr pkt);
261
262    /**
263     * Handle a snoop response.
264     * @param pkt Snoop response packet
265     */
266    void recvTimingSnoopResp(PacketPtr pkt);
267
268    /**
269     * Performs the access specified by the request.
270     * @param pkt The request to perform.
271     * @return The number of ticks required for the access.
272     */
273    Tick recvAtomic(PacketPtr pkt);
274
275    /**
276     * Snoop for the provided request in the cache and return the estimated
277     * time taken.
278     * @param pkt The memory request to snoop
279     * @return The number of ticks required for the snoop.
280     */
281    Tick recvAtomicSnoop(PacketPtr pkt);
282
283    /**
284     * Performs the access specified by the request.
285     * @param pkt The request to perform.
286     * @param fromCpuSide from the CPU side port or the memory side port
287     */
288    void functionalAccess(PacketPtr pkt, bool fromCpuSide);
289
290    void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
291                               bool deferred_response = false,
292                               bool pending_downgrade = false);
293    bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
294
295    void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
296                                bool already_copied, bool pending_inval);
297
298    /**
299     * Sets the blk to the new state.
300     * @param blk The cache block being snooped.
301     * @param new_state The new coherence state for the block.
302     */
303    void handleSnoop(PacketPtr ptk, BlkType *blk,
304                     bool is_timing, bool is_deferred, bool pending_inval);
305
306    /**
307     * Create a writeback request for the given block.
308     * @param blk The block to writeback.
309     * @return The writeback request for the block.
310     */
311    PacketPtr writebackBlk(BlkType *blk);
312
313
314    void memWriteback();
315    void memInvalidate();
316    bool isDirty() const;
317
318    /**
319     * Cache block visitor that writes back dirty cache blocks using
320     * functional writes.
321     *
322     * \return Always returns true.
323     */
324    bool writebackVisitor(BlkType &blk);
325    /**
326     * Cache block visitor that invalidates all blocks in the cache.
327     *
328     * @warn Dirty cache lines will not be written back to memory.
329     *
330     * \return Always returns true.
331     */
332    bool invalidateVisitor(BlkType &blk);
333
334    /**
335     * Squash all requests associated with specified thread.
336     * intended for use by I-cache.
337     * @param threadNum The thread to squash.
338     */
339    void squash(int threadNum);
340
341    /**
342     * Generate an appropriate downstream bus request packet for the
343     * given parameters.
344     * @param cpu_pkt  The upstream request that needs to be satisfied.
345     * @param blk The block currently in the cache corresponding to
346     * cpu_pkt (NULL if none).
347     * @param needsExclusive  Indicates that an exclusive copy is required
348     * even if the request in cpu_pkt doesn't indicate that.
349     * @return A new Packet containing the request, or NULL if the
350     * current request in cpu_pkt should just be forwarded on.
351     */
352    PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
353                           bool needsExclusive) const;
354
355    /**
356     * Return the next MSHR to service, either a pending miss from the
357     * mshrQueue, a buffered write from the write buffer, or something
358     * from the prefetcher.  This function is responsible for
359     * prioritizing among those sources on the fly.
360     */
361    MSHR *getNextMSHR();
362
363    /**
364     * Selects an outstanding request to service.  Called when the
365     * cache gets granted the downstream bus in timing mode.
366     * @return The request to service, NULL if none found.
367     */
368    PacketPtr getTimingPacket();
369
370    /**
371     * Marks a request as in service (sent on the bus). This can have
372     * side effect since storage for no response commands is
373     * deallocated once they are successfully sent. Also remember if
374     * we are expecting a dirty response from another cache,
375     * effectively making this MSHR the ordering point.
376     */
377    void markInService(MSHR *mshr, bool pending_dirty_resp);
378
379    /**
380     * Return whether there are any outstanding misses.
381     */
382    bool outstandingMisses() const
383    {
384        return mshrQueue.allocated != 0;
385    }
386
387    CacheBlk *findBlock(Addr addr, bool is_secure) const {
388        return tags->findBlock(addr, is_secure);
389    }
390
391    bool inCache(Addr addr, bool is_secure) const {
392        return (tags->findBlock(addr, is_secure) != 0);
393    }
394
395    bool inMissQueue(Addr addr, bool is_secure) const {
396        return (mshrQueue.findMatch(addr, is_secure) != 0);
397    }
398
399    /**
400     * Find next request ready time from among possible sources.
401     */
402    Tick nextMSHRReadyTime() const;
403
404  public:
405    /** Instantiates a basic cache object. */
406    Cache(const Params *p);
407
408    /** Non-default destructor is needed to deallocate memory. */
409    virtual ~Cache();
410
411    void regStats();
412
413    /** serialize the state of the caches
414     * We currently don't support checkpointing cache state, so this panics.
415     */
416    virtual void serialize(std::ostream &os);
417    void unserialize(Checkpoint *cp, const std::string &section);
418};
419
420#endif // __CACHE_HH__
421