cache.hh revision 9813
12810Srdreslin@umich.edu/* 22810Srdreslin@umich.edu * Copyright (c) 2012-2013 ARM Limited 32810Srdreslin@umich.edu * All rights reserved. 42810Srdreslin@umich.edu * 52810Srdreslin@umich.edu * The license below extends only to copyright in the software and shall 62810Srdreslin@umich.edu * not be construed as granting a license to any other intellectual 72810Srdreslin@umich.edu * property including but not limited to intellectual property relating 82810Srdreslin@umich.edu * to a hardware implementation of the functionality of the software 92810Srdreslin@umich.edu * licensed hereunder. You may use the software subject to the license 102810Srdreslin@umich.edu * terms below provided that you ensure that this notice is replicated 112810Srdreslin@umich.edu * unmodified and in its entirety in all distributions of the software, 122810Srdreslin@umich.edu * modified or unmodified, in source code or in binary form. 132810Srdreslin@umich.edu * 142810Srdreslin@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 152810Srdreslin@umich.edu * All rights reserved. 162810Srdreslin@umich.edu * 172810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 182810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 192810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 202810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 212810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 222810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 232810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 242810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 252810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 262810Srdreslin@umich.edu * this software without specific prior written permission. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314458Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810Srdreslin@umich.edu * 402810Srdreslin@umich.edu * Authors: Erik Hallnor 412810Srdreslin@umich.edu * Dave Greene 422810Srdreslin@umich.edu * Steve Reinhardt 432810Srdreslin@umich.edu * Ron Dreslinski 442810Srdreslin@umich.edu * Andreas Hansson 453860Sstever@eecs.umich.edu */ 464626Sstever@eecs.umich.edu 472810Srdreslin@umich.edu/** 484458Sstever@eecs.umich.edu * @file 494458Sstever@eecs.umich.edu * Describes a cache based on template policies. 502813Srdreslin@umich.edu */ 513861Sstever@eecs.umich.edu 522810Srdreslin@umich.edu#ifndef __CACHE_HH__ 532810Srdreslin@umich.edu#define __CACHE_HH__ 542810Srdreslin@umich.edu 552810Srdreslin@umich.edu#include "base/misc.hh" // fatal, panic, and warn 564672Sstever@eecs.umich.edu#include "mem/cache/base.hh" 572810Srdreslin@umich.edu#include "mem/cache/blk.hh" 584672Sstever@eecs.umich.edu#include "mem/cache/mshr.hh" 592810Srdreslin@umich.edu#include "sim/eventq.hh" 602810Srdreslin@umich.edu 612810Srdreslin@umich.edu//Forward decleration 622810Srdreslin@umich.educlass BasePrefetcher; 632810Srdreslin@umich.edu 643860Sstever@eecs.umich.edu/** 653860Sstever@eecs.umich.edu * A template-policy based cache. The behavior of the cache can be altered by 662810Srdreslin@umich.edu * supplying different template policies. TagStore handles all tag and data 672810Srdreslin@umich.edu * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System" 683738Sstever@eecs.umich.edu */ 692810Srdreslin@umich.edutemplate <class TagStore> 702810Srdreslin@umich.educlass Cache : public BaseCache 713738Sstever@eecs.umich.edu{ 723738Sstever@eecs.umich.edu public: 733738Sstever@eecs.umich.edu /** Define the type of cache block to use. */ 743738Sstever@eecs.umich.edu typedef typename TagStore::BlkType BlkType; 754672Sstever@eecs.umich.edu /** A typedef for a list of BlkType pointers. */ 763738Sstever@eecs.umich.edu typedef typename TagStore::BlkList BlkList; 773738Sstever@eecs.umich.edu 783738Sstever@eecs.umich.edu protected: 793738Sstever@eecs.umich.edu typedef CacheBlkVisitorWrapper<Cache<TagStore>, BlkType> WrappedBlkVisitor; 804672Sstever@eecs.umich.edu 814672Sstever@eecs.umich.edu /** 823738Sstever@eecs.umich.edu * The CPU-side port extends the base cache slave port with access 833738Sstever@eecs.umich.edu * functions for functional, atomic and timing requests. 844478Sstever@eecs.umich.edu */ 854478Sstever@eecs.umich.edu class CpuSidePort : public CacheSlavePort 864478Sstever@eecs.umich.edu { 873738Sstever@eecs.umich.edu private: 883738Sstever@eecs.umich.edu 893738Sstever@eecs.umich.edu // a pointer to our specific cache implementation 903738Sstever@eecs.umich.edu Cache<TagStore> *cache; 913738Sstever@eecs.umich.edu 923738Sstever@eecs.umich.edu protected: 933738Sstever@eecs.umich.edu 943738Sstever@eecs.umich.edu virtual bool recvTimingSnoopResp(PacketPtr pkt); 953738Sstever@eecs.umich.edu 963738Sstever@eecs.umich.edu virtual bool recvTimingReq(PacketPtr pkt); 973738Sstever@eecs.umich.edu 984672Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 993738Sstever@eecs.umich.edu 1003738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 1013738Sstever@eecs.umich.edu 1023738Sstever@eecs.umich.edu virtual unsigned deviceBlockSize() const 1034672Sstever@eecs.umich.edu { return cache->getBlockSize(); } 1044672Sstever@eecs.umich.edu 1053738Sstever@eecs.umich.edu virtual AddrRangeList getAddrRanges() const; 1063738Sstever@eecs.umich.edu 1074626Sstever@eecs.umich.edu public: 1084626Sstever@eecs.umich.edu 1094626Sstever@eecs.umich.edu CpuSidePort(const std::string &_name, Cache<TagStore> *_cache, 1104458Sstever@eecs.umich.edu const std::string &_label); 1114478Sstever@eecs.umich.edu 1124478Sstever@eecs.umich.edu }; 1134478Sstever@eecs.umich.edu 1143738Sstever@eecs.umich.edu /** 1153738Sstever@eecs.umich.edu * Override the default behaviour of sendDeferredPacket to enable 1164458Sstever@eecs.umich.edu * the memory-side cache port to also send requests based on the 1174458Sstever@eecs.umich.edu * current MSHR status. This queue has a pointer to our specific 1183738Sstever@eecs.umich.edu * cache implementation and is used by the MemSidePort. 1193738Sstever@eecs.umich.edu */ 1203738Sstever@eecs.umich.edu class MemSidePacketQueue : public MasterPacketQueue 1214458Sstever@eecs.umich.edu { 1224626Sstever@eecs.umich.edu 1234626Sstever@eecs.umich.edu protected: 1243738Sstever@eecs.umich.edu 1253738Sstever@eecs.umich.edu Cache<TagStore> &cache; 1262810Srdreslin@umich.edu 1272810Srdreslin@umich.edu public: 1284626Sstever@eecs.umich.edu 1292810Srdreslin@umich.edu MemSidePacketQueue(Cache<TagStore> &cache, MasterPort &port, 1303861Sstever@eecs.umich.edu const std::string &label) : 1312810Srdreslin@umich.edu MasterPacketQueue(cache, port, label), cache(cache) { } 1324671Sstever@eecs.umich.edu 1334671Sstever@eecs.umich.edu /** 1344671Sstever@eecs.umich.edu * Override the normal sendDeferredPacket and do not only 1352810Srdreslin@umich.edu * consider the transmit list (used for responses), but also 1363860Sstever@eecs.umich.edu * requests. 1373860Sstever@eecs.umich.edu */ 1383860Sstever@eecs.umich.edu virtual void sendDeferredPacket(); 1393860Sstever@eecs.umich.edu 1403860Sstever@eecs.umich.edu }; 1413860Sstever@eecs.umich.edu 1423860Sstever@eecs.umich.edu /** 1433860Sstever@eecs.umich.edu * The memory-side port extends the base cache master port with 1443860Sstever@eecs.umich.edu * access functions for functional, atomic and timing snoops. 1453860Sstever@eecs.umich.edu */ 1463860Sstever@eecs.umich.edu class MemSidePort : public CacheMasterPort 1473860Sstever@eecs.umich.edu { 1483860Sstever@eecs.umich.edu private: 1494626Sstever@eecs.umich.edu 1503860Sstever@eecs.umich.edu /** The cache-specific queue. */ 1513860Sstever@eecs.umich.edu MemSidePacketQueue _queue; 1523860Sstever@eecs.umich.edu 1533860Sstever@eecs.umich.edu // a pointer to our specific cache implementation 1543860Sstever@eecs.umich.edu Cache<TagStore> *cache; 1553860Sstever@eecs.umich.edu 1563860Sstever@eecs.umich.edu protected: 1573860Sstever@eecs.umich.edu 1583860Sstever@eecs.umich.edu virtual void recvTimingSnoopReq(PacketPtr pkt); 1593860Sstever@eecs.umich.edu 1603860Sstever@eecs.umich.edu virtual bool recvTimingResp(PacketPtr pkt); 1614628Sstever@eecs.umich.edu 1624219Srdreslin@umich.edu virtual Tick recvAtomicSnoop(PacketPtr pkt); 1634219Srdreslin@umich.edu 1644219Srdreslin@umich.edu virtual void recvFunctionalSnoop(PacketPtr pkt); 1654219Srdreslin@umich.edu 1664626Sstever@eecs.umich.edu virtual unsigned deviceBlockSize() const 1673860Sstever@eecs.umich.edu { return cache->getBlockSize(); } 1683860Sstever@eecs.umich.edu 1693860Sstever@eecs.umich.edu public: 1703860Sstever@eecs.umich.edu 1713860Sstever@eecs.umich.edu MemSidePort(const std::string &_name, Cache<TagStore> *_cache, 1723860Sstever@eecs.umich.edu const std::string &_label); 1734626Sstever@eecs.umich.edu }; 1743860Sstever@eecs.umich.edu 1753860Sstever@eecs.umich.edu /** Tag and data Storage */ 1763860Sstever@eecs.umich.edu TagStore *tags; 1773860Sstever@eecs.umich.edu 1784626Sstever@eecs.umich.edu /** Prefetcher */ 1794626Sstever@eecs.umich.edu BasePrefetcher *prefetcher; 1803860Sstever@eecs.umich.edu 1814665Sstever@eecs.umich.edu /** Temporary cache block for occasional transitory use */ 1824628Sstever@eecs.umich.edu BlkType *tempBlock; 1834626Sstever@eecs.umich.edu 1844670Sstever@eecs.umich.edu /** 1854670Sstever@eecs.umich.edu * This cache should allocate a block on a line-sized write miss. 1863860Sstever@eecs.umich.edu */ 1873860Sstever@eecs.umich.edu const bool doFastWrites; 1883860Sstever@eecs.umich.edu 1893860Sstever@eecs.umich.edu /** 1903860Sstever@eecs.umich.edu * Notify the prefetcher on every access, not just misses. 1913860Sstever@eecs.umich.edu */ 1924670Sstever@eecs.umich.edu const bool prefetchOnAccess; 1934670Sstever@eecs.umich.edu 1943860Sstever@eecs.umich.edu /** 1953860Sstever@eecs.umich.edu * @todo this is a temporary workaround until the 4-phase code is committed. 1963860Sstever@eecs.umich.edu * upstream caches need this packet until true is returned, so hold it for 1973860Sstever@eecs.umich.edu * deletion until a subsequent call 1983860Sstever@eecs.umich.edu */ 1993860Sstever@eecs.umich.edu std::vector<PacketPtr> pendingDelete; 2003860Sstever@eecs.umich.edu 2013860Sstever@eecs.umich.edu /** 2022810Srdreslin@umich.edu * Does all the processing necessary to perform the provided request. 2032810Srdreslin@umich.edu * @param pkt The memory request to perform. 2042810Srdreslin@umich.edu * @param lat The latency of the access. 2052810Srdreslin@umich.edu * @param writebacks List for any writebacks that need to be performed. 2062810Srdreslin@umich.edu * @param update True if the replacement data should be updated. 2072810Srdreslin@umich.edu * @return Boolean indicating whether the request was satisfied. 2082810Srdreslin@umich.edu */ 2093861Sstever@eecs.umich.edu bool access(PacketPtr pkt, BlkType *&blk, 2102810Srdreslin@umich.edu Cycles &lat, PacketList &writebacks); 2113860Sstever@eecs.umich.edu 2123860Sstever@eecs.umich.edu /** 2132810Srdreslin@umich.edu *Handle doing the Compare and Swap function for SPARC. 2144672Sstever@eecs.umich.edu */ 2153315Sstever@eecs.umich.edu void cmpAndSwap(BlkType *blk, PacketPtr pkt); 2163861Sstever@eecs.umich.edu 2173860Sstever@eecs.umich.edu /** 2183860Sstever@eecs.umich.edu * Find a block frame for new block at address addr, assuming that 2193860Sstever@eecs.umich.edu * the block is not currently in the cache. Append writebacks if 2204672Sstever@eecs.umich.edu * any to provided packet list. Return free block frame. May 2213315Sstever@eecs.umich.edu * return NULL if there are no replaceable blocks at the moment. 2222813Srdreslin@umich.edu */ 2233860Sstever@eecs.umich.edu BlkType *allocateBlock(Addr addr, PacketList &writebacks); 2244626Sstever@eecs.umich.edu 2252810Srdreslin@umich.edu /** 2262810Srdreslin@umich.edu * Populates a cache block and handles all outstanding requests for the 2272810Srdreslin@umich.edu * satisfied fill request. This version takes two memory requests. One 2282810Srdreslin@umich.edu * contains the fill data, the other is an optional target to satisfy. 2292810Srdreslin@umich.edu * @param pkt The memory request with the fill data. 2302812Srdreslin@umich.edu * @param blk The cache block if it already exists. 2312810Srdreslin@umich.edu * @param writebacks List for any writebacks that need to be performed. 2323738Sstever@eecs.umich.edu * @return Pointer to the new cache block. 2334190Ssaidi@eecs.umich.edu */ 2342813Srdreslin@umich.edu BlkType *handleFill(PacketPtr pkt, BlkType *blk, 2352810Srdreslin@umich.edu PacketList &writebacks); 2362810Srdreslin@umich.edu 2372810Srdreslin@umich.edu 2382810Srdreslin@umich.edu /** 2392982Sstever@eecs.umich.edu * Performs the access specified by the request. 2402810Srdreslin@umich.edu * @param pkt The request to perform. 2412810Srdreslin@umich.edu * @return The result of the access. 2424626Sstever@eecs.umich.edu */ 2432810Srdreslin@umich.edu bool recvTimingReq(PacketPtr pkt); 2442810Srdreslin@umich.edu 2454626Sstever@eecs.umich.edu /** 2464626Sstever@eecs.umich.edu * Handles a response (cache line fill/write ack) from the bus. 2474626Sstever@eecs.umich.edu * @param pkt The response packet 2482810Srdreslin@umich.edu */ 2494626Sstever@eecs.umich.edu void recvTimingResp(PacketPtr pkt); 2502810Srdreslin@umich.edu 2512810Srdreslin@umich.edu /** 2524626Sstever@eecs.umich.edu * Snoops bus transactions to maintain coherence. 2534626Sstever@eecs.umich.edu * @param pkt The current bus transaction. 2544626Sstever@eecs.umich.edu */ 2552810Srdreslin@umich.edu void recvTimingSnoopReq(PacketPtr pkt); 2564626Sstever@eecs.umich.edu 2573293Srdreslin@umich.edu /** 2583293Srdreslin@umich.edu * Handle a snoop response. 2592810Srdreslin@umich.edu * @param pkt Snoop response packet 2602982Sstever@eecs.umich.edu */ 2612810Srdreslin@umich.edu void recvTimingSnoopResp(PacketPtr pkt); 2624626Sstever@eecs.umich.edu 2632810Srdreslin@umich.edu /** 2642810Srdreslin@umich.edu * Performs the access specified by the request. 2652810Srdreslin@umich.edu * @param pkt The request to perform. 2662982Sstever@eecs.umich.edu * @return The number of ticks required for the access. 2672810Srdreslin@umich.edu */ 2684626Sstever@eecs.umich.edu Tick recvAtomic(PacketPtr pkt); 2692810Srdreslin@umich.edu 2704626Sstever@eecs.umich.edu /** 2714626Sstever@eecs.umich.edu * Snoop for the provided request in the cache and return the estimated 2724626Sstever@eecs.umich.edu * time taken. 2734626Sstever@eecs.umich.edu * @param pkt The memory request to snoop 2744626Sstever@eecs.umich.edu * @return The number of ticks required for the snoop. 2754626Sstever@eecs.umich.edu */ 2764626Sstever@eecs.umich.edu Tick recvAtomicSnoop(PacketPtr pkt); 2772810Srdreslin@umich.edu 2782810Srdreslin@umich.edu /** 2792982Sstever@eecs.umich.edu * Performs the access specified by the request. 2802810Srdreslin@umich.edu * @param pkt The request to perform. 2812982Sstever@eecs.umich.edu * @param fromCpuSide from the CPU side port or the memory side port 2822810Srdreslin@umich.edu */ 2834626Sstever@eecs.umich.edu void functionalAccess(PacketPtr pkt, bool fromCpuSide); 2844626Sstever@eecs.umich.edu 2854626Sstever@eecs.umich.edu void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk, 2864626Sstever@eecs.umich.edu bool deferred_response = false, 2874626Sstever@eecs.umich.edu bool pending_downgrade = false); 2884626Sstever@eecs.umich.edu bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk); 2894628Sstever@eecs.umich.edu 2904628Sstever@eecs.umich.edu void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data, 2914626Sstever@eecs.umich.edu bool already_copied, bool pending_inval); 2924628Sstever@eecs.umich.edu 2934626Sstever@eecs.umich.edu /** 2944626Sstever@eecs.umich.edu * Sets the blk to the new state. 2954626Sstever@eecs.umich.edu * @param blk The cache block being snooped. 2964626Sstever@eecs.umich.edu * @param new_state The new coherence state for the block. 2974626Sstever@eecs.umich.edu */ 2984626Sstever@eecs.umich.edu void handleSnoop(PacketPtr ptk, BlkType *blk, 2994626Sstever@eecs.umich.edu bool is_timing, bool is_deferred, bool pending_inval); 3004626Sstever@eecs.umich.edu 3014626Sstever@eecs.umich.edu /** 3024626Sstever@eecs.umich.edu * Create a writeback request for the given block. 3034626Sstever@eecs.umich.edu * @param blk The block to writeback. 3044626Sstever@eecs.umich.edu * @return The writeback request for the block. 3054626Sstever@eecs.umich.edu */ 3064626Sstever@eecs.umich.edu PacketPtr writebackBlk(BlkType *blk); 3074626Sstever@eecs.umich.edu 3084626Sstever@eecs.umich.edu 3094626Sstever@eecs.umich.edu void memWriteback(); 3104626Sstever@eecs.umich.edu void memInvalidate(); 3114626Sstever@eecs.umich.edu bool isDirty() const; 3122810Srdreslin@umich.edu 3134626Sstever@eecs.umich.edu /** 3142810Srdreslin@umich.edu * Cache block visitor that writes back dirty cache blocks using 3152810Srdreslin@umich.edu * functional writes. 3164626Sstever@eecs.umich.edu * 3174626Sstever@eecs.umich.edu * \return Always returns true. 3182810Srdreslin@umich.edu */ 3192810Srdreslin@umich.edu bool writebackVisitor(BlkType &blk); 3203861Sstever@eecs.umich.edu /** 3213861Sstever@eecs.umich.edu * Cache block visitor that invalidates all blocks in the cache. 3223861Sstever@eecs.umich.edu * 3233861Sstever@eecs.umich.edu * @warn Dirty cache lines will not be written back to memory. 3243861Sstever@eecs.umich.edu * 3254626Sstever@eecs.umich.edu * \return Always returns true. 3263861Sstever@eecs.umich.edu */ 3272810Srdreslin@umich.edu bool invalidateVisitor(BlkType &blk); 3282810Srdreslin@umich.edu 3292810Srdreslin@umich.edu /** 330 * Flush a cache line due to an uncacheable memory access to the 331 * line. 332 * 333 * @note This shouldn't normally happen, but we need to handle it 334 * since some architecture models don't implement cache 335 * maintenance operations. We won't even try to get a decent 336 * timing here since the line should have been flushed earlier by 337 * a cache maintenance operation. 338 */ 339 void uncacheableFlush(PacketPtr pkt); 340 341 /** 342 * Squash all requests associated with specified thread. 343 * intended for use by I-cache. 344 * @param threadNum The thread to squash. 345 */ 346 void squash(int threadNum); 347 348 /** 349 * Generate an appropriate downstream bus request packet for the 350 * given parameters. 351 * @param cpu_pkt The upstream request that needs to be satisfied. 352 * @param blk The block currently in the cache corresponding to 353 * cpu_pkt (NULL if none). 354 * @param needsExclusive Indicates that an exclusive copy is required 355 * even if the request in cpu_pkt doesn't indicate that. 356 * @return A new Packet containing the request, or NULL if the 357 * current request in cpu_pkt should just be forwarded on. 358 */ 359 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk, 360 bool needsExclusive) const; 361 362 /** 363 * Return the next MSHR to service, either a pending miss from the 364 * mshrQueue, a buffered write from the write buffer, or something 365 * from the prefetcher. This function is responsible for 366 * prioritizing among those sources on the fly. 367 */ 368 MSHR *getNextMSHR(); 369 370 /** 371 * Selects an outstanding request to service. Called when the 372 * cache gets granted the downstream bus in timing mode. 373 * @return The request to service, NULL if none found. 374 */ 375 PacketPtr getTimingPacket(); 376 377 /** 378 * Marks a request as in service (sent on the bus). This can have side 379 * effect since storage for no response commands is deallocated once they 380 * are successfully sent. 381 * @param pkt The request that was sent on the bus. 382 */ 383 void markInService(MSHR *mshr, PacketPtr pkt = 0); 384 385 /** 386 * Return whether there are any outstanding misses. 387 */ 388 bool outstandingMisses() const 389 { 390 return mshrQueue.allocated != 0; 391 } 392 393 CacheBlk *findBlock(Addr addr) const { 394 return tags->findBlock(addr); 395 } 396 397 bool inCache(Addr addr) const { 398 return (tags->findBlock(addr) != 0); 399 } 400 401 bool inMissQueue(Addr addr) const { 402 return (mshrQueue.findMatch(addr) != 0); 403 } 404 405 /** 406 * Find next request ready time from among possible sources. 407 */ 408 Tick nextMSHRReadyTime() const; 409 410 public: 411 /** Instantiates a basic cache object. */ 412 Cache(const Params *p); 413 414 /** Non-default destructor is needed to deallocate memory. */ 415 virtual ~Cache(); 416 417 void regStats(); 418 419 /** serialize the state of the caches 420 * We currently don't support checkpointing cache state, so this panics. 421 */ 422 virtual void serialize(std::ostream &os); 423 void unserialize(Checkpoint *cp, const std::string §ion); 424}; 425 426#endif // __CACHE_HH__ 427