cache.hh revision 8856
12810Srdreslin@umich.edu/* 28702Sandreas.hansson@arm.com * Copyright (c) 2012 ARM Limited 38702Sandreas.hansson@arm.com * All rights reserved. 48702Sandreas.hansson@arm.com * 58702Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68702Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78702Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88702Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98702Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108702Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118702Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128702Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138702Sandreas.hansson@arm.com * 142810Srdreslin@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 152810Srdreslin@umich.edu * All rights reserved. 162810Srdreslin@umich.edu * 172810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 182810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 192810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 202810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 212810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 222810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 232810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 242810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 252810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 262810Srdreslin@umich.edu * this software without specific prior written permission. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810Srdreslin@umich.edu * 402810Srdreslin@umich.edu * Authors: Erik Hallnor 412810Srdreslin@umich.edu * Dave Greene 422810Srdreslin@umich.edu * Steve Reinhardt 434458Sstever@eecs.umich.edu * Ron Dreslinski 448856Sandreas.hansson@arm.com * Andreas Hansson 452810Srdreslin@umich.edu */ 462810Srdreslin@umich.edu 472810Srdreslin@umich.edu/** 482810Srdreslin@umich.edu * @file 492810Srdreslin@umich.edu * Describes a cache based on template policies. 502810Srdreslin@umich.edu */ 512810Srdreslin@umich.edu 522810Srdreslin@umich.edu#ifndef __CACHE_HH__ 532810Srdreslin@umich.edu#define __CACHE_HH__ 542810Srdreslin@umich.edu 552810Srdreslin@umich.edu#include "base/misc.hh" // fatal, panic, and warn 565338Sstever@gmail.com#include "mem/cache/base.hh" 575338Sstever@gmail.com#include "mem/cache/blk.hh" 585338Sstever@gmail.com#include "mem/cache/mshr.hh" 594458Sstever@eecs.umich.edu#include "sim/eventq.hh" 604458Sstever@eecs.umich.edu 612813Srdreslin@umich.edu//Forward decleration 623861Sstever@eecs.umich.educlass BasePrefetcher; 632810Srdreslin@umich.edu 642810Srdreslin@umich.edu/** 652810Srdreslin@umich.edu * A template-policy based cache. The behavior of the cache can be altered by 662810Srdreslin@umich.edu * supplying different template policies. TagStore handles all tag and data 674672Sstever@eecs.umich.edu * storage @sa TagStore. 682810Srdreslin@umich.edu */ 694672Sstever@eecs.umich.edutemplate <class TagStore> 702810Srdreslin@umich.educlass Cache : public BaseCache 712810Srdreslin@umich.edu{ 722810Srdreslin@umich.edu public: 732810Srdreslin@umich.edu /** Define the type of cache block to use. */ 742810Srdreslin@umich.edu typedef typename TagStore::BlkType BlkType; 753860Sstever@eecs.umich.edu /** A typedef for a list of BlkType pointers. */ 763860Sstever@eecs.umich.edu typedef typename TagStore::BlkList BlkList; 772810Srdreslin@umich.edu 782810Srdreslin@umich.edu protected: 792810Srdreslin@umich.edu 808856Sandreas.hansson@arm.com /** 818856Sandreas.hansson@arm.com * The CPU-side port extends the base cache slave port with access 828856Sandreas.hansson@arm.com * functions for functional, atomic and timing requests. 838856Sandreas.hansson@arm.com */ 848856Sandreas.hansson@arm.com class CpuSidePort : public CacheSlavePort 853738Sstever@eecs.umich.edu { 868856Sandreas.hansson@arm.com private: 873738Sstever@eecs.umich.edu 888856Sandreas.hansson@arm.com // a pointer to our specific cache implementation 898856Sandreas.hansson@arm.com Cache<TagStore> *cache; 903738Sstever@eecs.umich.edu 918856Sandreas.hansson@arm.com protected: 924478Sstever@eecs.umich.edu 933738Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 943738Sstever@eecs.umich.edu 953738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 963738Sstever@eecs.umich.edu 973738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 988856Sandreas.hansson@arm.com 998856Sandreas.hansson@arm.com virtual unsigned deviceBlockSize() const 1008856Sandreas.hansson@arm.com { return cache->getBlockSize(); } 1018856Sandreas.hansson@arm.com 1028856Sandreas.hansson@arm.com virtual AddrRangeList getAddrRanges(); 1038856Sandreas.hansson@arm.com 1048856Sandreas.hansson@arm.com public: 1058856Sandreas.hansson@arm.com 1068856Sandreas.hansson@arm.com CpuSidePort(const std::string &_name, Cache<TagStore> *_cache, 1078856Sandreas.hansson@arm.com const std::string &_label); 1088856Sandreas.hansson@arm.com 1093738Sstever@eecs.umich.edu }; 1103738Sstever@eecs.umich.edu 1118856Sandreas.hansson@arm.com /** 1128856Sandreas.hansson@arm.com * The memory-side port extends the base cache master port with 1138856Sandreas.hansson@arm.com * access functions for functional, atomic and timing snoops. 1148856Sandreas.hansson@arm.com */ 1158856Sandreas.hansson@arm.com class MemSidePort : public CacheMasterPort 1163738Sstever@eecs.umich.edu { 1178856Sandreas.hansson@arm.com private: 1183738Sstever@eecs.umich.edu 1198856Sandreas.hansson@arm.com // a pointer to our specific cache implementation 1208856Sandreas.hansson@arm.com Cache<TagStore> *cache; 1213738Sstever@eecs.umich.edu 1228856Sandreas.hansson@arm.com protected: 1234478Sstever@eecs.umich.edu 1243738Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 1253738Sstever@eecs.umich.edu 1263738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 1273738Sstever@eecs.umich.edu 1283738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 1294458Sstever@eecs.umich.edu 1308856Sandreas.hansson@arm.com virtual unsigned deviceBlockSize() const 1318856Sandreas.hansson@arm.com { return cache->getBlockSize(); } 1328856Sandreas.hansson@arm.com 1338856Sandreas.hansson@arm.com public: 1348856Sandreas.hansson@arm.com 1358856Sandreas.hansson@arm.com MemSidePort(const std::string &_name, Cache<TagStore> *_cache, 1368856Sandreas.hansson@arm.com const std::string &_label); 1378856Sandreas.hansson@arm.com 1388856Sandreas.hansson@arm.com /** 1398856Sandreas.hansson@arm.com * Overload sendDeferredPacket of SimpleTimingPort. 1408856Sandreas.hansson@arm.com */ 1418856Sandreas.hansson@arm.com virtual void sendDeferredPacket(); 1423738Sstever@eecs.umich.edu }; 1433738Sstever@eecs.umich.edu 1442810Srdreslin@umich.edu /** Tag and data Storage */ 1452810Srdreslin@umich.edu TagStore *tags; 1464626Sstever@eecs.umich.edu 1472810Srdreslin@umich.edu /** Prefetcher */ 1483861Sstever@eecs.umich.edu BasePrefetcher *prefetcher; 1492810Srdreslin@umich.edu 1504671Sstever@eecs.umich.edu /** Temporary cache block for occasional transitory use */ 1514671Sstever@eecs.umich.edu BlkType *tempBlock; 1524671Sstever@eecs.umich.edu 1532810Srdreslin@umich.edu /** 1545707Shsul@eecs.umich.edu * This cache should allocate a block on a line-sized write miss. 1553860Sstever@eecs.umich.edu */ 1563860Sstever@eecs.umich.edu const bool doFastWrites; 1573860Sstever@eecs.umich.edu 1585875Ssteve.reinhardt@amd.com /** 1595875Ssteve.reinhardt@amd.com * Notify the prefetcher on every access, not just misses. 1605875Ssteve.reinhardt@amd.com */ 1615875Ssteve.reinhardt@amd.com const bool prefetchOnAccess; 1623860Sstever@eecs.umich.edu 1633860Sstever@eecs.umich.edu /** 1643860Sstever@eecs.umich.edu * Does all the processing necessary to perform the provided request. 1653860Sstever@eecs.umich.edu * @param pkt The memory request to perform. 1663860Sstever@eecs.umich.edu * @param lat The latency of the access. 1673860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 1683860Sstever@eecs.umich.edu * @param update True if the replacement data should be updated. 1695707Shsul@eecs.umich.edu * @return Boolean indicating whether the request was satisfied. 1703860Sstever@eecs.umich.edu */ 1715388Sstever@gmail.com bool access(PacketPtr pkt, BlkType *&blk, 1725388Sstever@gmail.com int &lat, PacketList &writebacks); 1734219Srdreslin@umich.edu 1744219Srdreslin@umich.edu /** 1754219Srdreslin@umich.edu *Handle doing the Compare and Swap function for SPARC. 1764219Srdreslin@umich.edu */ 1774626Sstever@eecs.umich.edu void cmpAndSwap(BlkType *blk, PacketPtr pkt); 1783860Sstever@eecs.umich.edu 1793860Sstever@eecs.umich.edu /** 1805350Sstever@gmail.com * Find a block frame for new block at address addr, assuming that 1815350Sstever@gmail.com * the block is not currently in the cache. Append writebacks if 1825350Sstever@gmail.com * any to provided packet list. Return free block frame. May 1835350Sstever@gmail.com * return NULL if there are no replaceable blocks at the moment. 1845350Sstever@gmail.com */ 1855350Sstever@gmail.com BlkType *allocateBlock(Addr addr, PacketList &writebacks); 1865350Sstever@gmail.com 1875350Sstever@gmail.com /** 1883860Sstever@eecs.umich.edu * Populates a cache block and handles all outstanding requests for the 1893860Sstever@eecs.umich.edu * satisfied fill request. This version takes two memory requests. One 1903860Sstever@eecs.umich.edu * contains the fill data, the other is an optional target to satisfy. 1914626Sstever@eecs.umich.edu * @param pkt The memory request with the fill data. 1923860Sstever@eecs.umich.edu * @param blk The cache block if it already exists. 1933860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 1943860Sstever@eecs.umich.edu * @return Pointer to the new cache block. 1953860Sstever@eecs.umich.edu */ 1964626Sstever@eecs.umich.edu BlkType *handleFill(PacketPtr pkt, BlkType *blk, 1974626Sstever@eecs.umich.edu PacketList &writebacks); 1983860Sstever@eecs.umich.edu 1997667Ssteve.reinhardt@amd.com void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk, 2007667Ssteve.reinhardt@amd.com bool deferred_response = false, 2017667Ssteve.reinhardt@amd.com bool pending_downgrade = false); 2024628Sstever@eecs.umich.edu bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk); 2034626Sstever@eecs.umich.edu 2044670Sstever@eecs.umich.edu void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data, 2055319Sstever@gmail.com bool already_copied, bool pending_inval); 2063860Sstever@eecs.umich.edu 2073860Sstever@eecs.umich.edu /** 2083860Sstever@eecs.umich.edu * Sets the blk to the new state. 2093860Sstever@eecs.umich.edu * @param blk The cache block being snooped. 2103860Sstever@eecs.umich.edu * @param new_state The new coherence state for the block. 2113860Sstever@eecs.umich.edu */ 2124670Sstever@eecs.umich.edu void handleSnoop(PacketPtr ptk, BlkType *blk, 2135319Sstever@gmail.com bool is_timing, bool is_deferred, bool pending_inval); 2143860Sstever@eecs.umich.edu 2153860Sstever@eecs.umich.edu /** 2163860Sstever@eecs.umich.edu * Create a writeback request for the given block. 2173860Sstever@eecs.umich.edu * @param blk The block to writeback. 2183860Sstever@eecs.umich.edu * @return The writeback request for the block. 2193860Sstever@eecs.umich.edu */ 2203860Sstever@eecs.umich.edu PacketPtr writebackBlk(BlkType *blk); 2213860Sstever@eecs.umich.edu 2222810Srdreslin@umich.edu public: 2232810Srdreslin@umich.edu /** Instantiates a basic cache object. */ 2248831Smrinmoy.ghosh@arm.com Cache(const Params *p, TagStore *tags); 2252810Srdreslin@umich.edu 2263738Sstever@eecs.umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 2272813Srdreslin@umich.edu 2282810Srdreslin@umich.edu void regStats(); 2292810Srdreslin@umich.edu 2302810Srdreslin@umich.edu /** 2312810Srdreslin@umich.edu * Performs the access specified by the request. 2322982Sstever@eecs.umich.edu * @param pkt The request to perform. 2332810Srdreslin@umich.edu * @return The result of the access. 2342810Srdreslin@umich.edu */ 2354626Sstever@eecs.umich.edu bool timingAccess(PacketPtr pkt); 2362810Srdreslin@umich.edu 2372810Srdreslin@umich.edu /** 2384626Sstever@eecs.umich.edu * Performs the access specified by the request. 2394626Sstever@eecs.umich.edu * @param pkt The request to perform. 2404626Sstever@eecs.umich.edu * @return The result of the access. 2412810Srdreslin@umich.edu */ 2424626Sstever@eecs.umich.edu Tick atomicAccess(PacketPtr pkt); 2432810Srdreslin@umich.edu 2442810Srdreslin@umich.edu /** 2454626Sstever@eecs.umich.edu * Performs the access specified by the request. 2464626Sstever@eecs.umich.edu * @param pkt The request to perform. 2478702Sandreas.hansson@arm.com * @param fromCpuSide from the CPU side port or the memory side port 2482810Srdreslin@umich.edu */ 2498702Sandreas.hansson@arm.com void functionalAccess(PacketPtr pkt, bool fromCpuSide); 2503293Srdreslin@umich.edu 2513293Srdreslin@umich.edu /** 2522810Srdreslin@umich.edu * Handles a response (cache line fill/write ack) from the bus. 2532982Sstever@eecs.umich.edu * @param pkt The request being responded to. 2542810Srdreslin@umich.edu */ 2554626Sstever@eecs.umich.edu void handleResponse(PacketPtr pkt); 2562810Srdreslin@umich.edu 2572810Srdreslin@umich.edu /** 2582810Srdreslin@umich.edu * Snoops bus transactions to maintain coherence. 2592982Sstever@eecs.umich.edu * @param pkt The current bus transaction. 2602810Srdreslin@umich.edu */ 2614626Sstever@eecs.umich.edu void snoopTiming(PacketPtr pkt); 2622810Srdreslin@umich.edu 2634626Sstever@eecs.umich.edu /** 2644626Sstever@eecs.umich.edu * Snoop for the provided request in the cache and return the estimated 2654626Sstever@eecs.umich.edu * time of completion. 2664626Sstever@eecs.umich.edu * @param pkt The memory request to snoop 2674626Sstever@eecs.umich.edu * @return The estimated completion time. 2684626Sstever@eecs.umich.edu */ 2694626Sstever@eecs.umich.edu Tick snoopAtomic(PacketPtr pkt); 2702810Srdreslin@umich.edu 2712810Srdreslin@umich.edu /** 2722982Sstever@eecs.umich.edu * Squash all requests associated with specified thread. 2732810Srdreslin@umich.edu * intended for use by I-cache. 2742982Sstever@eecs.umich.edu * @param threadNum The thread to squash. 2752810Srdreslin@umich.edu */ 2764626Sstever@eecs.umich.edu void squash(int threadNum); 2774626Sstever@eecs.umich.edu 2784626Sstever@eecs.umich.edu /** 2795365Sstever@gmail.com * Generate an appropriate downstream bus request packet for the 2805365Sstever@gmail.com * given parameters. 2815365Sstever@gmail.com * @param cpu_pkt The upstream request that needs to be satisfied. 2825365Sstever@gmail.com * @param blk The block currently in the cache corresponding to 2835365Sstever@gmail.com * cpu_pkt (NULL if none). 2845365Sstever@gmail.com * @param needsExclusive Indicates that an exclusive copy is required 2855365Sstever@gmail.com * even if the request in cpu_pkt doesn't indicate that. 2865365Sstever@gmail.com * @return A new Packet containing the request, or NULL if the 2875365Sstever@gmail.com * current request in cpu_pkt should just be forwarded on. 2884626Sstever@eecs.umich.edu */ 2894628Sstever@eecs.umich.edu PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk, 2904628Sstever@eecs.umich.edu bool needsExclusive); 2915365Sstever@gmail.com 2925365Sstever@gmail.com /** 2935365Sstever@gmail.com * Return the next MSHR to service, either a pending miss from the 2945365Sstever@gmail.com * mshrQueue, a buffered write from the write buffer, or something 2955365Sstever@gmail.com * from the prefetcher. This function is responsible for 2965365Sstever@gmail.com * prioritizing among those sources on the fly. 2975365Sstever@gmail.com */ 2984626Sstever@eecs.umich.edu MSHR *getNextMSHR(); 2995365Sstever@gmail.com 3005365Sstever@gmail.com /** 3015365Sstever@gmail.com * Selects an outstanding request to service. Called when the 3025365Sstever@gmail.com * cache gets granted the downstream bus in timing mode. 3035365Sstever@gmail.com * @return The request to service, NULL if none found. 3045365Sstever@gmail.com */ 3054628Sstever@eecs.umich.edu PacketPtr getTimingPacket(); 3064626Sstever@eecs.umich.edu 3074626Sstever@eecs.umich.edu /** 3084626Sstever@eecs.umich.edu * Marks a request as in service (sent on the bus). This can have side 3094626Sstever@eecs.umich.edu * effect since storage for no response commands is deallocated once they 3104626Sstever@eecs.umich.edu * are successfully sent. 3114626Sstever@eecs.umich.edu * @param pkt The request that was sent on the bus. 3124626Sstever@eecs.umich.edu */ 3137667Ssteve.reinhardt@amd.com void markInService(MSHR *mshr, PacketPtr pkt = 0); 3144626Sstever@eecs.umich.edu 3154626Sstever@eecs.umich.edu /** 3164626Sstever@eecs.umich.edu * Perform the given writeback request. 3174626Sstever@eecs.umich.edu * @param pkt The writeback request. 3184626Sstever@eecs.umich.edu */ 3194626Sstever@eecs.umich.edu void doWriteback(PacketPtr pkt); 3204626Sstever@eecs.umich.edu 3214626Sstever@eecs.umich.edu /** 3224626Sstever@eecs.umich.edu * Return whether there are any outstanding misses. 3234626Sstever@eecs.umich.edu */ 3244626Sstever@eecs.umich.edu bool outstandingMisses() const 3252810Srdreslin@umich.edu { 3264626Sstever@eecs.umich.edu return mshrQueue.allocated != 0; 3272810Srdreslin@umich.edu } 3282810Srdreslin@umich.edu 3294626Sstever@eecs.umich.edu CacheBlk *findBlock(Addr addr) { 3304626Sstever@eecs.umich.edu return tags->findBlock(addr); 3312810Srdreslin@umich.edu } 3322810Srdreslin@umich.edu 3333861Sstever@eecs.umich.edu bool inCache(Addr addr) { 3343861Sstever@eecs.umich.edu return (tags->findBlock(addr) != 0); 3353861Sstever@eecs.umich.edu } 3363861Sstever@eecs.umich.edu 3373861Sstever@eecs.umich.edu bool inMissQueue(Addr addr) { 3384626Sstever@eecs.umich.edu return (mshrQueue.findMatch(addr) != 0); 3393861Sstever@eecs.umich.edu } 3405875Ssteve.reinhardt@amd.com 3415875Ssteve.reinhardt@amd.com /** 3425875Ssteve.reinhardt@amd.com * Find next request ready time from among possible sources. 3435875Ssteve.reinhardt@amd.com */ 3445875Ssteve.reinhardt@amd.com Tick nextMSHRReadyTime(); 3452810Srdreslin@umich.edu}; 3462810Srdreslin@umich.edu 3472810Srdreslin@umich.edu#endif // __CACHE_HH__ 348