cache.hh revision 8702
12810Srdreslin@umich.edu/* 28702Sandreas.hansson@arm.com * Copyright (c) 2012 ARM Limited 38702Sandreas.hansson@arm.com * All rights reserved. 48702Sandreas.hansson@arm.com * 58702Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68702Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78702Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88702Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98702Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108702Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118702Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128702Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138702Sandreas.hansson@arm.com * 142810Srdreslin@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 152810Srdreslin@umich.edu * All rights reserved. 162810Srdreslin@umich.edu * 172810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 182810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 192810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 202810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 212810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 222810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 232810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 242810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 252810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 262810Srdreslin@umich.edu * this software without specific prior written permission. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810Srdreslin@umich.edu * 402810Srdreslin@umich.edu * Authors: Erik Hallnor 412810Srdreslin@umich.edu * Dave Greene 422810Srdreslin@umich.edu * Steve Reinhardt 434458Sstever@eecs.umich.edu * Ron Dreslinski 442810Srdreslin@umich.edu */ 452810Srdreslin@umich.edu 462810Srdreslin@umich.edu/** 472810Srdreslin@umich.edu * @file 482810Srdreslin@umich.edu * Describes a cache based on template policies. 492810Srdreslin@umich.edu */ 502810Srdreslin@umich.edu 512810Srdreslin@umich.edu#ifndef __CACHE_HH__ 522810Srdreslin@umich.edu#define __CACHE_HH__ 532810Srdreslin@umich.edu 542810Srdreslin@umich.edu#include "base/misc.hh" // fatal, panic, and warn 555338Sstever@gmail.com#include "mem/cache/base.hh" 565338Sstever@gmail.com#include "mem/cache/blk.hh" 575338Sstever@gmail.com#include "mem/cache/mshr.hh" 584458Sstever@eecs.umich.edu#include "sim/eventq.hh" 594458Sstever@eecs.umich.edu 602813Srdreslin@umich.edu//Forward decleration 613861Sstever@eecs.umich.educlass BasePrefetcher; 622810Srdreslin@umich.edu 632810Srdreslin@umich.edu/** 642810Srdreslin@umich.edu * A template-policy based cache. The behavior of the cache can be altered by 652810Srdreslin@umich.edu * supplying different template policies. TagStore handles all tag and data 664672Sstever@eecs.umich.edu * storage @sa TagStore. 672810Srdreslin@umich.edu */ 684672Sstever@eecs.umich.edutemplate <class TagStore> 692810Srdreslin@umich.educlass Cache : public BaseCache 702810Srdreslin@umich.edu{ 712810Srdreslin@umich.edu public: 722810Srdreslin@umich.edu /** Define the type of cache block to use. */ 732810Srdreslin@umich.edu typedef typename TagStore::BlkType BlkType; 743860Sstever@eecs.umich.edu /** A typedef for a list of BlkType pointers. */ 753860Sstever@eecs.umich.edu typedef typename TagStore::BlkList BlkList; 762810Srdreslin@umich.edu 772810Srdreslin@umich.edu protected: 782810Srdreslin@umich.edu 793738Sstever@eecs.umich.edu class CpuSidePort : public CachePort 803738Sstever@eecs.umich.edu { 813738Sstever@eecs.umich.edu public: 823738Sstever@eecs.umich.edu CpuSidePort(const std::string &_name, 834965Ssaidi@eecs.umich.edu Cache<TagStore> *_cache, 846122SSteve.Reinhardt@amd.com const std::string &_label); 853738Sstever@eecs.umich.edu 863738Sstever@eecs.umich.edu // BaseCache::CachePort just has a BaseCache *; this function 873738Sstever@eecs.umich.edu // lets us get back the type info we lost when we stored the 883738Sstever@eecs.umich.edu // cache pointer there. 894672Sstever@eecs.umich.edu Cache<TagStore> *myCache() { 904672Sstever@eecs.umich.edu return static_cast<Cache<TagStore> *>(cache); 913738Sstever@eecs.umich.edu } 923738Sstever@eecs.umich.edu 934478Sstever@eecs.umich.edu virtual void getDeviceAddressRanges(AddrRangeList &resp, 944478Sstever@eecs.umich.edu bool &snoop); 954478Sstever@eecs.umich.edu 963738Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 973738Sstever@eecs.umich.edu 983738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 993738Sstever@eecs.umich.edu 1003738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 1013738Sstever@eecs.umich.edu }; 1023738Sstever@eecs.umich.edu 1033738Sstever@eecs.umich.edu class MemSidePort : public CachePort 1043738Sstever@eecs.umich.edu { 1053738Sstever@eecs.umich.edu public: 1063738Sstever@eecs.umich.edu MemSidePort(const std::string &_name, 1074965Ssaidi@eecs.umich.edu Cache<TagStore> *_cache, 1086122SSteve.Reinhardt@amd.com const std::string &_label); 1093738Sstever@eecs.umich.edu 1103738Sstever@eecs.umich.edu // BaseCache::CachePort just has a BaseCache *; this function 1113738Sstever@eecs.umich.edu // lets us get back the type info we lost when we stored the 1123738Sstever@eecs.umich.edu // cache pointer there. 1134672Sstever@eecs.umich.edu Cache<TagStore> *myCache() { 1144672Sstever@eecs.umich.edu return static_cast<Cache<TagStore> *>(cache); 1153738Sstever@eecs.umich.edu } 1163738Sstever@eecs.umich.edu 1174626Sstever@eecs.umich.edu void sendPacket(); 1184626Sstever@eecs.umich.edu 1194626Sstever@eecs.umich.edu void processSendEvent(); 1204458Sstever@eecs.umich.edu 1214478Sstever@eecs.umich.edu virtual void getDeviceAddressRanges(AddrRangeList &resp, 1224478Sstever@eecs.umich.edu bool &snoop); 1234478Sstever@eecs.umich.edu 1243738Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 1253738Sstever@eecs.umich.edu 1264458Sstever@eecs.umich.edu virtual void recvRetry(); 1274458Sstever@eecs.umich.edu 1283738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 1293738Sstever@eecs.umich.edu 1303738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 1314458Sstever@eecs.umich.edu 1324626Sstever@eecs.umich.edu typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent> 1334626Sstever@eecs.umich.edu SendEvent; 1343738Sstever@eecs.umich.edu }; 1353738Sstever@eecs.umich.edu 1362810Srdreslin@umich.edu /** Tag and data Storage */ 1372810Srdreslin@umich.edu TagStore *tags; 1384626Sstever@eecs.umich.edu 1392810Srdreslin@umich.edu /** Prefetcher */ 1403861Sstever@eecs.umich.edu BasePrefetcher *prefetcher; 1412810Srdreslin@umich.edu 1424671Sstever@eecs.umich.edu /** Temporary cache block for occasional transitory use */ 1434671Sstever@eecs.umich.edu BlkType *tempBlock; 1444671Sstever@eecs.umich.edu 1452810Srdreslin@umich.edu /** 1465707Shsul@eecs.umich.edu * This cache should allocate a block on a line-sized write miss. 1473860Sstever@eecs.umich.edu */ 1483860Sstever@eecs.umich.edu const bool doFastWrites; 1493860Sstever@eecs.umich.edu 1505875Ssteve.reinhardt@amd.com /** 1515875Ssteve.reinhardt@amd.com * Notify the prefetcher on every access, not just misses. 1525875Ssteve.reinhardt@amd.com */ 1535875Ssteve.reinhardt@amd.com const bool prefetchOnAccess; 1543860Sstever@eecs.umich.edu 1553860Sstever@eecs.umich.edu /** 1563860Sstever@eecs.umich.edu * Does all the processing necessary to perform the provided request. 1573860Sstever@eecs.umich.edu * @param pkt The memory request to perform. 1583860Sstever@eecs.umich.edu * @param lat The latency of the access. 1593860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 1603860Sstever@eecs.umich.edu * @param update True if the replacement data should be updated. 1615707Shsul@eecs.umich.edu * @return Boolean indicating whether the request was satisfied. 1623860Sstever@eecs.umich.edu */ 1635388Sstever@gmail.com bool access(PacketPtr pkt, BlkType *&blk, 1645388Sstever@gmail.com int &lat, PacketList &writebacks); 1654219Srdreslin@umich.edu 1664219Srdreslin@umich.edu /** 1674219Srdreslin@umich.edu *Handle doing the Compare and Swap function for SPARC. 1684219Srdreslin@umich.edu */ 1694626Sstever@eecs.umich.edu void cmpAndSwap(BlkType *blk, PacketPtr pkt); 1703860Sstever@eecs.umich.edu 1713860Sstever@eecs.umich.edu /** 1725350Sstever@gmail.com * Find a block frame for new block at address addr, assuming that 1735350Sstever@gmail.com * the block is not currently in the cache. Append writebacks if 1745350Sstever@gmail.com * any to provided packet list. Return free block frame. May 1755350Sstever@gmail.com * return NULL if there are no replaceable blocks at the moment. 1765350Sstever@gmail.com */ 1775350Sstever@gmail.com BlkType *allocateBlock(Addr addr, PacketList &writebacks); 1785350Sstever@gmail.com 1795350Sstever@gmail.com /** 1803860Sstever@eecs.umich.edu * Populates a cache block and handles all outstanding requests for the 1813860Sstever@eecs.umich.edu * satisfied fill request. This version takes two memory requests. One 1823860Sstever@eecs.umich.edu * contains the fill data, the other is an optional target to satisfy. 1834626Sstever@eecs.umich.edu * @param pkt The memory request with the fill data. 1843860Sstever@eecs.umich.edu * @param blk The cache block if it already exists. 1853860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 1863860Sstever@eecs.umich.edu * @return Pointer to the new cache block. 1873860Sstever@eecs.umich.edu */ 1884626Sstever@eecs.umich.edu BlkType *handleFill(PacketPtr pkt, BlkType *blk, 1894626Sstever@eecs.umich.edu PacketList &writebacks); 1903860Sstever@eecs.umich.edu 1917667Ssteve.reinhardt@amd.com void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk, 1927667Ssteve.reinhardt@amd.com bool deferred_response = false, 1937667Ssteve.reinhardt@amd.com bool pending_downgrade = false); 1944628Sstever@eecs.umich.edu bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk); 1954626Sstever@eecs.umich.edu 1964670Sstever@eecs.umich.edu void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data, 1975319Sstever@gmail.com bool already_copied, bool pending_inval); 1983860Sstever@eecs.umich.edu 1993860Sstever@eecs.umich.edu /** 2003860Sstever@eecs.umich.edu * Sets the blk to the new state. 2013860Sstever@eecs.umich.edu * @param blk The cache block being snooped. 2023860Sstever@eecs.umich.edu * @param new_state The new coherence state for the block. 2033860Sstever@eecs.umich.edu */ 2044670Sstever@eecs.umich.edu void handleSnoop(PacketPtr ptk, BlkType *blk, 2055319Sstever@gmail.com bool is_timing, bool is_deferred, bool pending_inval); 2063860Sstever@eecs.umich.edu 2073860Sstever@eecs.umich.edu /** 2083860Sstever@eecs.umich.edu * Create a writeback request for the given block. 2093860Sstever@eecs.umich.edu * @param blk The block to writeback. 2103860Sstever@eecs.umich.edu * @return The writeback request for the block. 2113860Sstever@eecs.umich.edu */ 2123860Sstever@eecs.umich.edu PacketPtr writebackBlk(BlkType *blk); 2133860Sstever@eecs.umich.edu 2142810Srdreslin@umich.edu public: 2152810Srdreslin@umich.edu /** Instantiates a basic cache object. */ 2165034Smilesck@eecs.umich.edu Cache(const Params *p, TagStore *tags, BasePrefetcher *prefetcher); 2172810Srdreslin@umich.edu 2183738Sstever@eecs.umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 2195494Sstever@gmail.com virtual void deletePortRefs(Port *p); 2202813Srdreslin@umich.edu 2212810Srdreslin@umich.edu void regStats(); 2222810Srdreslin@umich.edu 2232810Srdreslin@umich.edu /** 2242810Srdreslin@umich.edu * Performs the access specified by the request. 2252982Sstever@eecs.umich.edu * @param pkt The request to perform. 2262810Srdreslin@umich.edu * @return The result of the access. 2272810Srdreslin@umich.edu */ 2284626Sstever@eecs.umich.edu bool timingAccess(PacketPtr pkt); 2292810Srdreslin@umich.edu 2302810Srdreslin@umich.edu /** 2314626Sstever@eecs.umich.edu * Performs the access specified by the request. 2324626Sstever@eecs.umich.edu * @param pkt The request to perform. 2334626Sstever@eecs.umich.edu * @return The result of the access. 2342810Srdreslin@umich.edu */ 2354626Sstever@eecs.umich.edu Tick atomicAccess(PacketPtr pkt); 2362810Srdreslin@umich.edu 2372810Srdreslin@umich.edu /** 2384626Sstever@eecs.umich.edu * Performs the access specified by the request. 2394626Sstever@eecs.umich.edu * @param pkt The request to perform. 2408702Sandreas.hansson@arm.com * @param fromCpuSide from the CPU side port or the memory side port 2412810Srdreslin@umich.edu */ 2428702Sandreas.hansson@arm.com void functionalAccess(PacketPtr pkt, bool fromCpuSide); 2433293Srdreslin@umich.edu 2443293Srdreslin@umich.edu /** 2452810Srdreslin@umich.edu * Handles a response (cache line fill/write ack) from the bus. 2462982Sstever@eecs.umich.edu * @param pkt The request being responded to. 2472810Srdreslin@umich.edu */ 2484626Sstever@eecs.umich.edu void handleResponse(PacketPtr pkt); 2492810Srdreslin@umich.edu 2502810Srdreslin@umich.edu /** 2512810Srdreslin@umich.edu * Snoops bus transactions to maintain coherence. 2522982Sstever@eecs.umich.edu * @param pkt The current bus transaction. 2532810Srdreslin@umich.edu */ 2544626Sstever@eecs.umich.edu void snoopTiming(PacketPtr pkt); 2552810Srdreslin@umich.edu 2564626Sstever@eecs.umich.edu /** 2574626Sstever@eecs.umich.edu * Snoop for the provided request in the cache and return the estimated 2584626Sstever@eecs.umich.edu * time of completion. 2594626Sstever@eecs.umich.edu * @param pkt The memory request to snoop 2604626Sstever@eecs.umich.edu * @return The estimated completion time. 2614626Sstever@eecs.umich.edu */ 2624626Sstever@eecs.umich.edu Tick snoopAtomic(PacketPtr pkt); 2632810Srdreslin@umich.edu 2642810Srdreslin@umich.edu /** 2652982Sstever@eecs.umich.edu * Squash all requests associated with specified thread. 2662810Srdreslin@umich.edu * intended for use by I-cache. 2672982Sstever@eecs.umich.edu * @param threadNum The thread to squash. 2682810Srdreslin@umich.edu */ 2694626Sstever@eecs.umich.edu void squash(int threadNum); 2704626Sstever@eecs.umich.edu 2714626Sstever@eecs.umich.edu /** 2725365Sstever@gmail.com * Generate an appropriate downstream bus request packet for the 2735365Sstever@gmail.com * given parameters. 2745365Sstever@gmail.com * @param cpu_pkt The upstream request that needs to be satisfied. 2755365Sstever@gmail.com * @param blk The block currently in the cache corresponding to 2765365Sstever@gmail.com * cpu_pkt (NULL if none). 2775365Sstever@gmail.com * @param needsExclusive Indicates that an exclusive copy is required 2785365Sstever@gmail.com * even if the request in cpu_pkt doesn't indicate that. 2795365Sstever@gmail.com * @return A new Packet containing the request, or NULL if the 2805365Sstever@gmail.com * current request in cpu_pkt should just be forwarded on. 2814626Sstever@eecs.umich.edu */ 2824628Sstever@eecs.umich.edu PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk, 2834628Sstever@eecs.umich.edu bool needsExclusive); 2845365Sstever@gmail.com 2855365Sstever@gmail.com /** 2865365Sstever@gmail.com * Return the next MSHR to service, either a pending miss from the 2875365Sstever@gmail.com * mshrQueue, a buffered write from the write buffer, or something 2885365Sstever@gmail.com * from the prefetcher. This function is responsible for 2895365Sstever@gmail.com * prioritizing among those sources on the fly. 2905365Sstever@gmail.com */ 2914626Sstever@eecs.umich.edu MSHR *getNextMSHR(); 2925365Sstever@gmail.com 2935365Sstever@gmail.com /** 2945365Sstever@gmail.com * Selects an outstanding request to service. Called when the 2955365Sstever@gmail.com * cache gets granted the downstream bus in timing mode. 2965365Sstever@gmail.com * @return The request to service, NULL if none found. 2975365Sstever@gmail.com */ 2984628Sstever@eecs.umich.edu PacketPtr getTimingPacket(); 2994626Sstever@eecs.umich.edu 3004626Sstever@eecs.umich.edu /** 3014626Sstever@eecs.umich.edu * Marks a request as in service (sent on the bus). This can have side 3024626Sstever@eecs.umich.edu * effect since storage for no response commands is deallocated once they 3034626Sstever@eecs.umich.edu * are successfully sent. 3044626Sstever@eecs.umich.edu * @param pkt The request that was sent on the bus. 3054626Sstever@eecs.umich.edu */ 3067667Ssteve.reinhardt@amd.com void markInService(MSHR *mshr, PacketPtr pkt = 0); 3074626Sstever@eecs.umich.edu 3084626Sstever@eecs.umich.edu /** 3094626Sstever@eecs.umich.edu * Perform the given writeback request. 3104626Sstever@eecs.umich.edu * @param pkt The writeback request. 3114626Sstever@eecs.umich.edu */ 3124626Sstever@eecs.umich.edu void doWriteback(PacketPtr pkt); 3134626Sstever@eecs.umich.edu 3144626Sstever@eecs.umich.edu /** 3154626Sstever@eecs.umich.edu * Return whether there are any outstanding misses. 3164626Sstever@eecs.umich.edu */ 3174626Sstever@eecs.umich.edu bool outstandingMisses() const 3182810Srdreslin@umich.edu { 3194626Sstever@eecs.umich.edu return mshrQueue.allocated != 0; 3202810Srdreslin@umich.edu } 3212810Srdreslin@umich.edu 3224626Sstever@eecs.umich.edu CacheBlk *findBlock(Addr addr) { 3234626Sstever@eecs.umich.edu return tags->findBlock(addr); 3242810Srdreslin@umich.edu } 3252810Srdreslin@umich.edu 3263861Sstever@eecs.umich.edu bool inCache(Addr addr) { 3273861Sstever@eecs.umich.edu return (tags->findBlock(addr) != 0); 3283861Sstever@eecs.umich.edu } 3293861Sstever@eecs.umich.edu 3303861Sstever@eecs.umich.edu bool inMissQueue(Addr addr) { 3314626Sstever@eecs.umich.edu return (mshrQueue.findMatch(addr) != 0); 3323861Sstever@eecs.umich.edu } 3335875Ssteve.reinhardt@amd.com 3345875Ssteve.reinhardt@amd.com /** 3355875Ssteve.reinhardt@amd.com * Find next request ready time from among possible sources. 3365875Ssteve.reinhardt@amd.com */ 3375875Ssteve.reinhardt@amd.com Tick nextMSHRReadyTime(); 3382810Srdreslin@umich.edu}; 3392810Srdreslin@umich.edu 3402810Srdreslin@umich.edu#endif // __CACHE_HH__ 341