cache.hh revision 7667
12810Srdreslin@umich.edu/* 22810Srdreslin@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 32810Srdreslin@umich.edu * All rights reserved. 42810Srdreslin@umich.edu * 52810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 62810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 72810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 82810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 92810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 102810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 112810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 122810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 132810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 142810Srdreslin@umich.edu * this software without specific prior written permission. 152810Srdreslin@umich.edu * 162810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * Authors: Erik Hallnor 292810Srdreslin@umich.edu * Dave Greene 302810Srdreslin@umich.edu * Steve Reinhardt 314458Sstever@eecs.umich.edu * Ron Dreslinski 322810Srdreslin@umich.edu */ 332810Srdreslin@umich.edu 342810Srdreslin@umich.edu/** 352810Srdreslin@umich.edu * @file 362810Srdreslin@umich.edu * Describes a cache based on template policies. 372810Srdreslin@umich.edu */ 382810Srdreslin@umich.edu 392810Srdreslin@umich.edu#ifndef __CACHE_HH__ 402810Srdreslin@umich.edu#define __CACHE_HH__ 412810Srdreslin@umich.edu 422810Srdreslin@umich.edu#include "base/misc.hh" // fatal, panic, and warn 432810Srdreslin@umich.edu 445338Sstever@gmail.com#include "mem/cache/base.hh" 455338Sstever@gmail.com#include "mem/cache/blk.hh" 465338Sstever@gmail.com#include "mem/cache/mshr.hh" 472810Srdreslin@umich.edu 484458Sstever@eecs.umich.edu#include "sim/eventq.hh" 494458Sstever@eecs.umich.edu 502813Srdreslin@umich.edu//Forward decleration 513861Sstever@eecs.umich.educlass BasePrefetcher; 522810Srdreslin@umich.edu 532810Srdreslin@umich.edu/** 542810Srdreslin@umich.edu * A template-policy based cache. The behavior of the cache can be altered by 552810Srdreslin@umich.edu * supplying different template policies. TagStore handles all tag and data 564672Sstever@eecs.umich.edu * storage @sa TagStore. 572810Srdreslin@umich.edu */ 584672Sstever@eecs.umich.edutemplate <class TagStore> 592810Srdreslin@umich.educlass Cache : public BaseCache 602810Srdreslin@umich.edu{ 612810Srdreslin@umich.edu public: 622810Srdreslin@umich.edu /** Define the type of cache block to use. */ 632810Srdreslin@umich.edu typedef typename TagStore::BlkType BlkType; 643860Sstever@eecs.umich.edu /** A typedef for a list of BlkType pointers. */ 653860Sstever@eecs.umich.edu typedef typename TagStore::BlkList BlkList; 662810Srdreslin@umich.edu 672810Srdreslin@umich.edu protected: 682810Srdreslin@umich.edu 693738Sstever@eecs.umich.edu class CpuSidePort : public CachePort 703738Sstever@eecs.umich.edu { 713738Sstever@eecs.umich.edu public: 723738Sstever@eecs.umich.edu CpuSidePort(const std::string &_name, 734965Ssaidi@eecs.umich.edu Cache<TagStore> *_cache, 746122SSteve.Reinhardt@amd.com const std::string &_label); 753738Sstever@eecs.umich.edu 763738Sstever@eecs.umich.edu // BaseCache::CachePort just has a BaseCache *; this function 773738Sstever@eecs.umich.edu // lets us get back the type info we lost when we stored the 783738Sstever@eecs.umich.edu // cache pointer there. 794672Sstever@eecs.umich.edu Cache<TagStore> *myCache() { 804672Sstever@eecs.umich.edu return static_cast<Cache<TagStore> *>(cache); 813738Sstever@eecs.umich.edu } 823738Sstever@eecs.umich.edu 834478Sstever@eecs.umich.edu virtual void getDeviceAddressRanges(AddrRangeList &resp, 844478Sstever@eecs.umich.edu bool &snoop); 854478Sstever@eecs.umich.edu 863738Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 873738Sstever@eecs.umich.edu 883738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 893738Sstever@eecs.umich.edu 903738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 913738Sstever@eecs.umich.edu }; 923738Sstever@eecs.umich.edu 933738Sstever@eecs.umich.edu class MemSidePort : public CachePort 943738Sstever@eecs.umich.edu { 953738Sstever@eecs.umich.edu public: 963738Sstever@eecs.umich.edu MemSidePort(const std::string &_name, 974965Ssaidi@eecs.umich.edu Cache<TagStore> *_cache, 986122SSteve.Reinhardt@amd.com const std::string &_label); 993738Sstever@eecs.umich.edu 1003738Sstever@eecs.umich.edu // BaseCache::CachePort just has a BaseCache *; this function 1013738Sstever@eecs.umich.edu // lets us get back the type info we lost when we stored the 1023738Sstever@eecs.umich.edu // cache pointer there. 1034672Sstever@eecs.umich.edu Cache<TagStore> *myCache() { 1044672Sstever@eecs.umich.edu return static_cast<Cache<TagStore> *>(cache); 1053738Sstever@eecs.umich.edu } 1063738Sstever@eecs.umich.edu 1074626Sstever@eecs.umich.edu void sendPacket(); 1084626Sstever@eecs.umich.edu 1094626Sstever@eecs.umich.edu void processSendEvent(); 1104458Sstever@eecs.umich.edu 1114478Sstever@eecs.umich.edu virtual void getDeviceAddressRanges(AddrRangeList &resp, 1124478Sstever@eecs.umich.edu bool &snoop); 1134478Sstever@eecs.umich.edu 1143738Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 1153738Sstever@eecs.umich.edu 1164458Sstever@eecs.umich.edu virtual void recvRetry(); 1174458Sstever@eecs.umich.edu 1183738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 1193738Sstever@eecs.umich.edu 1203738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 1214458Sstever@eecs.umich.edu 1224626Sstever@eecs.umich.edu typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent> 1234626Sstever@eecs.umich.edu SendEvent; 1243738Sstever@eecs.umich.edu }; 1253738Sstever@eecs.umich.edu 1262810Srdreslin@umich.edu /** Tag and data Storage */ 1272810Srdreslin@umich.edu TagStore *tags; 1284626Sstever@eecs.umich.edu 1292810Srdreslin@umich.edu /** Prefetcher */ 1303861Sstever@eecs.umich.edu BasePrefetcher *prefetcher; 1312810Srdreslin@umich.edu 1324671Sstever@eecs.umich.edu /** Temporary cache block for occasional transitory use */ 1334671Sstever@eecs.umich.edu BlkType *tempBlock; 1344671Sstever@eecs.umich.edu 1352810Srdreslin@umich.edu /** 1365707Shsul@eecs.umich.edu * This cache should allocate a block on a line-sized write miss. 1373860Sstever@eecs.umich.edu */ 1383860Sstever@eecs.umich.edu const bool doFastWrites; 1393860Sstever@eecs.umich.edu 1405875Ssteve.reinhardt@amd.com /** 1415875Ssteve.reinhardt@amd.com * Notify the prefetcher on every access, not just misses. 1425875Ssteve.reinhardt@amd.com */ 1435875Ssteve.reinhardt@amd.com const bool prefetchOnAccess; 1443860Sstever@eecs.umich.edu 1453860Sstever@eecs.umich.edu /** 1463860Sstever@eecs.umich.edu * Does all the processing necessary to perform the provided request. 1473860Sstever@eecs.umich.edu * @param pkt The memory request to perform. 1483860Sstever@eecs.umich.edu * @param lat The latency of the access. 1493860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 1503860Sstever@eecs.umich.edu * @param update True if the replacement data should be updated. 1515707Shsul@eecs.umich.edu * @return Boolean indicating whether the request was satisfied. 1523860Sstever@eecs.umich.edu */ 1535388Sstever@gmail.com bool access(PacketPtr pkt, BlkType *&blk, 1545388Sstever@gmail.com int &lat, PacketList &writebacks); 1554219Srdreslin@umich.edu 1564219Srdreslin@umich.edu /** 1574219Srdreslin@umich.edu *Handle doing the Compare and Swap function for SPARC. 1584219Srdreslin@umich.edu */ 1594626Sstever@eecs.umich.edu void cmpAndSwap(BlkType *blk, PacketPtr pkt); 1603860Sstever@eecs.umich.edu 1613860Sstever@eecs.umich.edu /** 1625350Sstever@gmail.com * Find a block frame for new block at address addr, assuming that 1635350Sstever@gmail.com * the block is not currently in the cache. Append writebacks if 1645350Sstever@gmail.com * any to provided packet list. Return free block frame. May 1655350Sstever@gmail.com * return NULL if there are no replaceable blocks at the moment. 1665350Sstever@gmail.com */ 1675350Sstever@gmail.com BlkType *allocateBlock(Addr addr, PacketList &writebacks); 1685350Sstever@gmail.com 1695350Sstever@gmail.com /** 1703860Sstever@eecs.umich.edu * Populates a cache block and handles all outstanding requests for the 1713860Sstever@eecs.umich.edu * satisfied fill request. This version takes two memory requests. One 1723860Sstever@eecs.umich.edu * contains the fill data, the other is an optional target to satisfy. 1734626Sstever@eecs.umich.edu * @param pkt The memory request with the fill data. 1743860Sstever@eecs.umich.edu * @param blk The cache block if it already exists. 1753860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 1763860Sstever@eecs.umich.edu * @return Pointer to the new cache block. 1773860Sstever@eecs.umich.edu */ 1784626Sstever@eecs.umich.edu BlkType *handleFill(PacketPtr pkt, BlkType *blk, 1794626Sstever@eecs.umich.edu PacketList &writebacks); 1803860Sstever@eecs.umich.edu 1817667Ssteve.reinhardt@amd.com void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk, 1827667Ssteve.reinhardt@amd.com bool deferred_response = false, 1837667Ssteve.reinhardt@amd.com bool pending_downgrade = false); 1844628Sstever@eecs.umich.edu bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk); 1854626Sstever@eecs.umich.edu 1864670Sstever@eecs.umich.edu void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data, 1875319Sstever@gmail.com bool already_copied, bool pending_inval); 1883860Sstever@eecs.umich.edu 1893860Sstever@eecs.umich.edu /** 1903860Sstever@eecs.umich.edu * Sets the blk to the new state. 1913860Sstever@eecs.umich.edu * @param blk The cache block being snooped. 1923860Sstever@eecs.umich.edu * @param new_state The new coherence state for the block. 1933860Sstever@eecs.umich.edu */ 1944670Sstever@eecs.umich.edu void handleSnoop(PacketPtr ptk, BlkType *blk, 1955319Sstever@gmail.com bool is_timing, bool is_deferred, bool pending_inval); 1963860Sstever@eecs.umich.edu 1973860Sstever@eecs.umich.edu /** 1983860Sstever@eecs.umich.edu * Create a writeback request for the given block. 1993860Sstever@eecs.umich.edu * @param blk The block to writeback. 2003860Sstever@eecs.umich.edu * @return The writeback request for the block. 2013860Sstever@eecs.umich.edu */ 2023860Sstever@eecs.umich.edu PacketPtr writebackBlk(BlkType *blk); 2033860Sstever@eecs.umich.edu 2042810Srdreslin@umich.edu public: 2052810Srdreslin@umich.edu /** Instantiates a basic cache object. */ 2065034Smilesck@eecs.umich.edu Cache(const Params *p, TagStore *tags, BasePrefetcher *prefetcher); 2072810Srdreslin@umich.edu 2083738Sstever@eecs.umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 2095494Sstever@gmail.com virtual void deletePortRefs(Port *p); 2102813Srdreslin@umich.edu 2112810Srdreslin@umich.edu void regStats(); 2122810Srdreslin@umich.edu 2132810Srdreslin@umich.edu /** 2142810Srdreslin@umich.edu * Performs the access specified by the request. 2152982Sstever@eecs.umich.edu * @param pkt The request to perform. 2162810Srdreslin@umich.edu * @return The result of the access. 2172810Srdreslin@umich.edu */ 2184626Sstever@eecs.umich.edu bool timingAccess(PacketPtr pkt); 2192810Srdreslin@umich.edu 2202810Srdreslin@umich.edu /** 2214626Sstever@eecs.umich.edu * Performs the access specified by the request. 2224626Sstever@eecs.umich.edu * @param pkt The request to perform. 2234626Sstever@eecs.umich.edu * @return The result of the access. 2242810Srdreslin@umich.edu */ 2254626Sstever@eecs.umich.edu Tick atomicAccess(PacketPtr pkt); 2262810Srdreslin@umich.edu 2272810Srdreslin@umich.edu /** 2284626Sstever@eecs.umich.edu * Performs the access specified by the request. 2294626Sstever@eecs.umich.edu * @param pkt The request to perform. 2304626Sstever@eecs.umich.edu * @return The result of the access. 2312810Srdreslin@umich.edu */ 2325314Sstever@gmail.com void functionalAccess(PacketPtr pkt, CachePort *incomingPort, 2335314Sstever@gmail.com CachePort *otherSidePort); 2343293Srdreslin@umich.edu 2353293Srdreslin@umich.edu /** 2362810Srdreslin@umich.edu * Handles a response (cache line fill/write ack) from the bus. 2372982Sstever@eecs.umich.edu * @param pkt The request being responded to. 2382810Srdreslin@umich.edu */ 2394626Sstever@eecs.umich.edu void handleResponse(PacketPtr pkt); 2402810Srdreslin@umich.edu 2412810Srdreslin@umich.edu /** 2422810Srdreslin@umich.edu * Snoops bus transactions to maintain coherence. 2432982Sstever@eecs.umich.edu * @param pkt The current bus transaction. 2442810Srdreslin@umich.edu */ 2454626Sstever@eecs.umich.edu void snoopTiming(PacketPtr pkt); 2462810Srdreslin@umich.edu 2474626Sstever@eecs.umich.edu /** 2484626Sstever@eecs.umich.edu * Snoop for the provided request in the cache and return the estimated 2494626Sstever@eecs.umich.edu * time of completion. 2504626Sstever@eecs.umich.edu * @param pkt The memory request to snoop 2514626Sstever@eecs.umich.edu * @return The estimated completion time. 2524626Sstever@eecs.umich.edu */ 2534626Sstever@eecs.umich.edu Tick snoopAtomic(PacketPtr pkt); 2542810Srdreslin@umich.edu 2552810Srdreslin@umich.edu /** 2562982Sstever@eecs.umich.edu * Squash all requests associated with specified thread. 2572810Srdreslin@umich.edu * intended for use by I-cache. 2582982Sstever@eecs.umich.edu * @param threadNum The thread to squash. 2592810Srdreslin@umich.edu */ 2604626Sstever@eecs.umich.edu void squash(int threadNum); 2614626Sstever@eecs.umich.edu 2624626Sstever@eecs.umich.edu /** 2635365Sstever@gmail.com * Generate an appropriate downstream bus request packet for the 2645365Sstever@gmail.com * given parameters. 2655365Sstever@gmail.com * @param cpu_pkt The upstream request that needs to be satisfied. 2665365Sstever@gmail.com * @param blk The block currently in the cache corresponding to 2675365Sstever@gmail.com * cpu_pkt (NULL if none). 2685365Sstever@gmail.com * @param needsExclusive Indicates that an exclusive copy is required 2695365Sstever@gmail.com * even if the request in cpu_pkt doesn't indicate that. 2705365Sstever@gmail.com * @return A new Packet containing the request, or NULL if the 2715365Sstever@gmail.com * current request in cpu_pkt should just be forwarded on. 2724626Sstever@eecs.umich.edu */ 2734628Sstever@eecs.umich.edu PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk, 2744628Sstever@eecs.umich.edu bool needsExclusive); 2755365Sstever@gmail.com 2765365Sstever@gmail.com /** 2775365Sstever@gmail.com * Return the next MSHR to service, either a pending miss from the 2785365Sstever@gmail.com * mshrQueue, a buffered write from the write buffer, or something 2795365Sstever@gmail.com * from the prefetcher. This function is responsible for 2805365Sstever@gmail.com * prioritizing among those sources on the fly. 2815365Sstever@gmail.com */ 2824626Sstever@eecs.umich.edu MSHR *getNextMSHR(); 2835365Sstever@gmail.com 2845365Sstever@gmail.com /** 2855365Sstever@gmail.com * Selects an outstanding request to service. Called when the 2865365Sstever@gmail.com * cache gets granted the downstream bus in timing mode. 2875365Sstever@gmail.com * @return The request to service, NULL if none found. 2885365Sstever@gmail.com */ 2894628Sstever@eecs.umich.edu PacketPtr getTimingPacket(); 2904626Sstever@eecs.umich.edu 2914626Sstever@eecs.umich.edu /** 2924626Sstever@eecs.umich.edu * Marks a request as in service (sent on the bus). This can have side 2934626Sstever@eecs.umich.edu * effect since storage for no response commands is deallocated once they 2944626Sstever@eecs.umich.edu * are successfully sent. 2954626Sstever@eecs.umich.edu * @param pkt The request that was sent on the bus. 2964626Sstever@eecs.umich.edu */ 2977667Ssteve.reinhardt@amd.com void markInService(MSHR *mshr, PacketPtr pkt = 0); 2984626Sstever@eecs.umich.edu 2994626Sstever@eecs.umich.edu /** 3004626Sstever@eecs.umich.edu * Perform the given writeback request. 3014626Sstever@eecs.umich.edu * @param pkt The writeback request. 3024626Sstever@eecs.umich.edu */ 3034626Sstever@eecs.umich.edu void doWriteback(PacketPtr pkt); 3044626Sstever@eecs.umich.edu 3054626Sstever@eecs.umich.edu /** 3064626Sstever@eecs.umich.edu * Return whether there are any outstanding misses. 3074626Sstever@eecs.umich.edu */ 3084626Sstever@eecs.umich.edu bool outstandingMisses() const 3092810Srdreslin@umich.edu { 3104626Sstever@eecs.umich.edu return mshrQueue.allocated != 0; 3112810Srdreslin@umich.edu } 3122810Srdreslin@umich.edu 3134626Sstever@eecs.umich.edu CacheBlk *findBlock(Addr addr) { 3144626Sstever@eecs.umich.edu return tags->findBlock(addr); 3152810Srdreslin@umich.edu } 3162810Srdreslin@umich.edu 3173861Sstever@eecs.umich.edu bool inCache(Addr addr) { 3183861Sstever@eecs.umich.edu return (tags->findBlock(addr) != 0); 3193861Sstever@eecs.umich.edu } 3203861Sstever@eecs.umich.edu 3213861Sstever@eecs.umich.edu bool inMissQueue(Addr addr) { 3224626Sstever@eecs.umich.edu return (mshrQueue.findMatch(addr) != 0); 3233861Sstever@eecs.umich.edu } 3245875Ssteve.reinhardt@amd.com 3255875Ssteve.reinhardt@amd.com /** 3265875Ssteve.reinhardt@amd.com * Find next request ready time from among possible sources. 3275875Ssteve.reinhardt@amd.com */ 3285875Ssteve.reinhardt@amd.com Tick nextMSHRReadyTime(); 3292810Srdreslin@umich.edu}; 3302810Srdreslin@umich.edu 3312810Srdreslin@umich.edu#endif // __CACHE_HH__ 332