cache.hh revision 4478
12810Srdreslin@umich.edu/* 22810Srdreslin@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 32810Srdreslin@umich.edu * All rights reserved. 42810Srdreslin@umich.edu * 52810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 62810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 72810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 82810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 92810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 102810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 112810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 122810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 132810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 142810Srdreslin@umich.edu * this software without specific prior written permission. 152810Srdreslin@umich.edu * 162810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * Authors: Erik Hallnor 292810Srdreslin@umich.edu * Dave Greene 302810Srdreslin@umich.edu * Steve Reinhardt 314458Sstever@eecs.umich.edu * Ron Dreslinski 322810Srdreslin@umich.edu */ 332810Srdreslin@umich.edu 342810Srdreslin@umich.edu/** 352810Srdreslin@umich.edu * @file 362810Srdreslin@umich.edu * Describes a cache based on template policies. 372810Srdreslin@umich.edu */ 382810Srdreslin@umich.edu 392810Srdreslin@umich.edu#ifndef __CACHE_HH__ 402810Srdreslin@umich.edu#define __CACHE_HH__ 412810Srdreslin@umich.edu 423860Sstever@eecs.umich.edu#include "base/compression/base.hh" 432810Srdreslin@umich.edu#include "base/misc.hh" // fatal, panic, and warn 442810Srdreslin@umich.edu#include "cpu/smt.hh" // SMT_MAX_THREADS 452810Srdreslin@umich.edu 462810Srdreslin@umich.edu#include "mem/cache/base_cache.hh" 473860Sstever@eecs.umich.edu#include "mem/cache/cache_blk.hh" 483719Sstever@eecs.umich.edu#include "mem/cache/miss/miss_buffer.hh" 492810Srdreslin@umich.edu 504458Sstever@eecs.umich.edu#include "sim/eventq.hh" 514458Sstever@eecs.umich.edu 522813Srdreslin@umich.edu//Forward decleration 532813Srdreslin@umich.educlass MSHR; 543861Sstever@eecs.umich.educlass BasePrefetcher; 552810Srdreslin@umich.edu 562810Srdreslin@umich.edu/** 572810Srdreslin@umich.edu * A template-policy based cache. The behavior of the cache can be altered by 582810Srdreslin@umich.edu * supplying different template policies. TagStore handles all tag and data 592810Srdreslin@umich.edu * storage @sa TagStore. Buffering handles all misses and writes/writebacks 602810Srdreslin@umich.edu * @sa MissQueue. Coherence handles all coherence policy details @sa 612810Srdreslin@umich.edu * UniCoherence, SimpleMultiCoherence. 622810Srdreslin@umich.edu */ 633719Sstever@eecs.umich.edutemplate <class TagStore, class Coherence> 642810Srdreslin@umich.educlass Cache : public BaseCache 652810Srdreslin@umich.edu{ 662810Srdreslin@umich.edu public: 672810Srdreslin@umich.edu /** Define the type of cache block to use. */ 682810Srdreslin@umich.edu typedef typename TagStore::BlkType BlkType; 693860Sstever@eecs.umich.edu /** A typedef for a list of BlkType pointers. */ 703860Sstever@eecs.umich.edu typedef typename TagStore::BlkList BlkList; 712810Srdreslin@umich.edu 722810Srdreslin@umich.edu bool prefetchAccess; 733738Sstever@eecs.umich.edu 742810Srdreslin@umich.edu protected: 752810Srdreslin@umich.edu 763738Sstever@eecs.umich.edu class CpuSidePort : public CachePort 773738Sstever@eecs.umich.edu { 783738Sstever@eecs.umich.edu public: 793738Sstever@eecs.umich.edu CpuSidePort(const std::string &_name, 803738Sstever@eecs.umich.edu Cache<TagStore,Coherence> *_cache); 813738Sstever@eecs.umich.edu 823738Sstever@eecs.umich.edu // BaseCache::CachePort just has a BaseCache *; this function 833738Sstever@eecs.umich.edu // lets us get back the type info we lost when we stored the 843738Sstever@eecs.umich.edu // cache pointer there. 853738Sstever@eecs.umich.edu Cache<TagStore,Coherence> *myCache() { 863738Sstever@eecs.umich.edu return static_cast<Cache<TagStore,Coherence> *>(cache); 873738Sstever@eecs.umich.edu } 883738Sstever@eecs.umich.edu 894458Sstever@eecs.umich.edu void processRequestEvent(); 904458Sstever@eecs.umich.edu void processResponseEvent(); 914458Sstever@eecs.umich.edu 924478Sstever@eecs.umich.edu virtual void getDeviceAddressRanges(AddrRangeList &resp, 934478Sstever@eecs.umich.edu bool &snoop); 944478Sstever@eecs.umich.edu 953738Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 963738Sstever@eecs.umich.edu 974458Sstever@eecs.umich.edu virtual void recvRetry(); 984458Sstever@eecs.umich.edu 993738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 1003738Sstever@eecs.umich.edu 1013738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 1024458Sstever@eecs.umich.edu 1034458Sstever@eecs.umich.edu typedef EventWrapper<CpuSidePort, &CpuSidePort::processResponseEvent> 1044458Sstever@eecs.umich.edu ResponseEvent; 1054458Sstever@eecs.umich.edu 1064458Sstever@eecs.umich.edu typedef EventWrapper<CpuSidePort, &CpuSidePort::processRequestEvent> 1074458Sstever@eecs.umich.edu RequestEvent; 1084458Sstever@eecs.umich.edu 1094458Sstever@eecs.umich.edu virtual void scheduleRequestEvent(Tick t) { 1104458Sstever@eecs.umich.edu new RequestEvent(this, t); 1114458Sstever@eecs.umich.edu } 1123738Sstever@eecs.umich.edu }; 1133738Sstever@eecs.umich.edu 1143738Sstever@eecs.umich.edu class MemSidePort : public CachePort 1153738Sstever@eecs.umich.edu { 1163738Sstever@eecs.umich.edu public: 1173738Sstever@eecs.umich.edu MemSidePort(const std::string &_name, 1183738Sstever@eecs.umich.edu Cache<TagStore,Coherence> *_cache); 1193738Sstever@eecs.umich.edu 1203738Sstever@eecs.umich.edu // BaseCache::CachePort just has a BaseCache *; this function 1213738Sstever@eecs.umich.edu // lets us get back the type info we lost when we stored the 1223738Sstever@eecs.umich.edu // cache pointer there. 1233738Sstever@eecs.umich.edu Cache<TagStore,Coherence> *myCache() { 1243738Sstever@eecs.umich.edu return static_cast<Cache<TagStore,Coherence> *>(cache); 1253738Sstever@eecs.umich.edu } 1263738Sstever@eecs.umich.edu 1274458Sstever@eecs.umich.edu void processRequestEvent(); 1284458Sstever@eecs.umich.edu void processResponseEvent(); 1294458Sstever@eecs.umich.edu 1304478Sstever@eecs.umich.edu virtual void getDeviceAddressRanges(AddrRangeList &resp, 1314478Sstever@eecs.umich.edu bool &snoop); 1324478Sstever@eecs.umich.edu 1333738Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 1343738Sstever@eecs.umich.edu 1354458Sstever@eecs.umich.edu virtual void recvRetry(); 1364458Sstever@eecs.umich.edu 1373738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 1383738Sstever@eecs.umich.edu 1393738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 1404458Sstever@eecs.umich.edu 1414458Sstever@eecs.umich.edu typedef EventWrapper<MemSidePort, &MemSidePort::processResponseEvent> 1424458Sstever@eecs.umich.edu ResponseEvent; 1434458Sstever@eecs.umich.edu 1444458Sstever@eecs.umich.edu typedef EventWrapper<MemSidePort, &MemSidePort::processRequestEvent> 1454458Sstever@eecs.umich.edu RequestEvent; 1464458Sstever@eecs.umich.edu 1474458Sstever@eecs.umich.edu virtual void scheduleRequestEvent(Tick t) { 1484458Sstever@eecs.umich.edu new RequestEvent(this, t); 1494458Sstever@eecs.umich.edu } 1503738Sstever@eecs.umich.edu }; 1513738Sstever@eecs.umich.edu 1522810Srdreslin@umich.edu /** Tag and data Storage */ 1532810Srdreslin@umich.edu TagStore *tags; 1542810Srdreslin@umich.edu /** Miss and Writeback handler */ 1553719Sstever@eecs.umich.edu MissBuffer *missQueue; 1562810Srdreslin@umich.edu /** Coherence protocol. */ 1572810Srdreslin@umich.edu Coherence *coherence; 1582810Srdreslin@umich.edu 1592810Srdreslin@umich.edu /** Prefetcher */ 1603861Sstever@eecs.umich.edu BasePrefetcher *prefetcher; 1612810Srdreslin@umich.edu 1622810Srdreslin@umich.edu /** 1632810Srdreslin@umich.edu * The clock ratio of the outgoing bus. 1642810Srdreslin@umich.edu * Used for calculating critical word first. 1652810Srdreslin@umich.edu */ 1662810Srdreslin@umich.edu int busRatio; 1672810Srdreslin@umich.edu 1682810Srdreslin@umich.edu /** 1692810Srdreslin@umich.edu * The bus width in bytes of the outgoing bus. 1702810Srdreslin@umich.edu * Used for calculating critical word first. 1712810Srdreslin@umich.edu */ 1722810Srdreslin@umich.edu int busWidth; 1732810Srdreslin@umich.edu 1742813Srdreslin@umich.edu /** 1752813Srdreslin@umich.edu * The latency of a hit in this device. 1762813Srdreslin@umich.edu */ 1772813Srdreslin@umich.edu int hitLatency; 1782813Srdreslin@umich.edu 1792810Srdreslin@umich.edu /** 1802810Srdreslin@umich.edu * A permanent mem req to always be used to cause invalidations. 1812810Srdreslin@umich.edu * Used to append to target list, to cause an invalidation. 1822810Srdreslin@umich.edu */ 1833349Sbinkertn@umich.edu PacketPtr invalidatePkt; 1843208Srdreslin@umich.edu Request *invalidateReq; 1852810Srdreslin@umich.edu 1863860Sstever@eecs.umich.edu /** 1873860Sstever@eecs.umich.edu * Policy class for performing compression. 1883860Sstever@eecs.umich.edu */ 1893860Sstever@eecs.umich.edu CompressionAlgorithm *compressionAlg; 1903860Sstever@eecs.umich.edu 1913860Sstever@eecs.umich.edu /** 1923860Sstever@eecs.umich.edu * The block size of this cache. Set to value in the Tags object. 1933860Sstever@eecs.umich.edu */ 1943860Sstever@eecs.umich.edu const int16_t blkSize; 1953860Sstever@eecs.umich.edu 1963860Sstever@eecs.umich.edu /** 1973860Sstever@eecs.umich.edu * Can this cache should allocate a block on a line-sized write miss. 1983860Sstever@eecs.umich.edu */ 1993860Sstever@eecs.umich.edu const bool doFastWrites; 2003860Sstever@eecs.umich.edu 2013860Sstever@eecs.umich.edu const bool prefetchMiss; 2023860Sstever@eecs.umich.edu 2033860Sstever@eecs.umich.edu /** 2043860Sstever@eecs.umich.edu * Can the data can be stored in a compressed form. 2053860Sstever@eecs.umich.edu */ 2063860Sstever@eecs.umich.edu const bool storeCompressed; 2073860Sstever@eecs.umich.edu 2083860Sstever@eecs.umich.edu /** 2093860Sstever@eecs.umich.edu * Do we need to compress blocks on writebacks (i.e. because 2103860Sstever@eecs.umich.edu * writeback bus is compressed but storage is not)? 2113860Sstever@eecs.umich.edu */ 2123860Sstever@eecs.umich.edu const bool compressOnWriteback; 2133860Sstever@eecs.umich.edu 2143860Sstever@eecs.umich.edu /** 2153860Sstever@eecs.umich.edu * The latency of a compression operation. 2163860Sstever@eecs.umich.edu */ 2173860Sstever@eecs.umich.edu const int16_t compLatency; 2183860Sstever@eecs.umich.edu 2193860Sstever@eecs.umich.edu /** 2203860Sstever@eecs.umich.edu * Should we use an adaptive compression scheme. 2213860Sstever@eecs.umich.edu */ 2223860Sstever@eecs.umich.edu const bool adaptiveCompression; 2233860Sstever@eecs.umich.edu 2243860Sstever@eecs.umich.edu /** 2253860Sstever@eecs.umich.edu * Do writebacks need to be compressed (i.e. because writeback bus 2263860Sstever@eecs.umich.edu * is compressed), whether or not they're already compressed for 2273860Sstever@eecs.umich.edu * storage. 2283860Sstever@eecs.umich.edu */ 2293860Sstever@eecs.umich.edu const bool writebackCompressed; 2303860Sstever@eecs.umich.edu 2313860Sstever@eecs.umich.edu /** 2323860Sstever@eecs.umich.edu * Compare the internal block data to the fast access block data. 2333860Sstever@eecs.umich.edu * @param blk The cache block to check. 2343860Sstever@eecs.umich.edu * @return True if the data is the same. 2353860Sstever@eecs.umich.edu */ 2363860Sstever@eecs.umich.edu bool verifyData(BlkType *blk); 2373860Sstever@eecs.umich.edu 2383860Sstever@eecs.umich.edu /** 2393860Sstever@eecs.umich.edu * Update the internal data of the block. The data to write is assumed to 2403860Sstever@eecs.umich.edu * be in the fast access data. 2413860Sstever@eecs.umich.edu * @param blk The block with the data to update. 2423860Sstever@eecs.umich.edu * @param writebacks A list to store any generated writebacks. 2433860Sstever@eecs.umich.edu * @param compress_block True if we should compress this block 2443860Sstever@eecs.umich.edu */ 2453860Sstever@eecs.umich.edu void updateData(BlkType *blk, PacketList &writebacks, bool compress_block); 2463860Sstever@eecs.umich.edu 2473860Sstever@eecs.umich.edu /** 2483860Sstever@eecs.umich.edu * Handle a replacement for the given request. 2493860Sstever@eecs.umich.edu * @param blk A pointer to the block, usually NULL 2503860Sstever@eecs.umich.edu * @param pkt The memory request to satisfy. 2513860Sstever@eecs.umich.edu * @param new_state The new state of the block. 2523860Sstever@eecs.umich.edu * @param writebacks A list to store any generated writebacks. 2533860Sstever@eecs.umich.edu */ 2543860Sstever@eecs.umich.edu BlkType* doReplacement(BlkType *blk, PacketPtr &pkt, 2553860Sstever@eecs.umich.edu CacheBlk::State new_state, PacketList &writebacks); 2563860Sstever@eecs.umich.edu 2573860Sstever@eecs.umich.edu /** 2583860Sstever@eecs.umich.edu * Does all the processing necessary to perform the provided request. 2593860Sstever@eecs.umich.edu * @param pkt The memory request to perform. 2603860Sstever@eecs.umich.edu * @param lat The latency of the access. 2613860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 2623860Sstever@eecs.umich.edu * @param update True if the replacement data should be updated. 2633860Sstever@eecs.umich.edu * @return Pointer to the cache block touched by the request. NULL if it 2643860Sstever@eecs.umich.edu * was a miss. 2653860Sstever@eecs.umich.edu */ 2663860Sstever@eecs.umich.edu BlkType* handleAccess(PacketPtr &pkt, int & lat, 2673860Sstever@eecs.umich.edu PacketList & writebacks, bool update = true); 2683860Sstever@eecs.umich.edu 2694219Srdreslin@umich.edu 2704219Srdreslin@umich.edu /** 2714219Srdreslin@umich.edu *Handle doing the Compare and Swap function for SPARC. 2724219Srdreslin@umich.edu */ 2734219Srdreslin@umich.edu void cmpAndSwap(BlkType *blk, PacketPtr &pkt); 2744219Srdreslin@umich.edu 2753860Sstever@eecs.umich.edu /** 2763860Sstever@eecs.umich.edu * Populates a cache block and handles all outstanding requests for the 2773860Sstever@eecs.umich.edu * satisfied fill request. This version takes an MSHR pointer and uses its 2783860Sstever@eecs.umich.edu * request to fill the cache block, while repsonding to its targets. 2793860Sstever@eecs.umich.edu * @param blk The cache block if it already exists. 2803860Sstever@eecs.umich.edu * @param mshr The MSHR that contains the fill data and targets to satisfy. 2813860Sstever@eecs.umich.edu * @param new_state The state of the new cache block. 2823860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 2833860Sstever@eecs.umich.edu * @return Pointer to the new cache block. 2843860Sstever@eecs.umich.edu */ 2853860Sstever@eecs.umich.edu BlkType* handleFill(BlkType *blk, MSHR * mshr, CacheBlk::State new_state, 2863860Sstever@eecs.umich.edu PacketList & writebacks, PacketPtr pkt); 2873860Sstever@eecs.umich.edu 2883860Sstever@eecs.umich.edu /** 2893860Sstever@eecs.umich.edu * Populates a cache block and handles all outstanding requests for the 2903860Sstever@eecs.umich.edu * satisfied fill request. This version takes two memory requests. One 2913860Sstever@eecs.umich.edu * contains the fill data, the other is an optional target to satisfy. 2923860Sstever@eecs.umich.edu * Used for Cache::probe. 2933860Sstever@eecs.umich.edu * @param blk The cache block if it already exists. 2943860Sstever@eecs.umich.edu * @param pkt The memory request with the fill data. 2953860Sstever@eecs.umich.edu * @param new_state The state of the new cache block. 2963860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 2973860Sstever@eecs.umich.edu * @param target The memory request to perform after the fill. 2983860Sstever@eecs.umich.edu * @return Pointer to the new cache block. 2993860Sstever@eecs.umich.edu */ 3003860Sstever@eecs.umich.edu BlkType* handleFill(BlkType *blk, PacketPtr &pkt, 3013860Sstever@eecs.umich.edu CacheBlk::State new_state, 3023860Sstever@eecs.umich.edu PacketList & writebacks, PacketPtr target = NULL); 3033860Sstever@eecs.umich.edu 3043860Sstever@eecs.umich.edu /** 3053860Sstever@eecs.umich.edu * Sets the blk to the new state and handles the given request. 3063860Sstever@eecs.umich.edu * @param blk The cache block being snooped. 3073860Sstever@eecs.umich.edu * @param new_state The new coherence state for the block. 3083860Sstever@eecs.umich.edu * @param pkt The request to satisfy 3093860Sstever@eecs.umich.edu */ 3103860Sstever@eecs.umich.edu void handleSnoop(BlkType *blk, CacheBlk::State new_state, 3113860Sstever@eecs.umich.edu PacketPtr &pkt); 3123860Sstever@eecs.umich.edu 3133860Sstever@eecs.umich.edu /** 3143860Sstever@eecs.umich.edu * Sets the blk to the new state. 3153860Sstever@eecs.umich.edu * @param blk The cache block being snooped. 3163860Sstever@eecs.umich.edu * @param new_state The new coherence state for the block. 3173860Sstever@eecs.umich.edu */ 3183860Sstever@eecs.umich.edu void handleSnoop(BlkType *blk, CacheBlk::State new_state); 3193860Sstever@eecs.umich.edu 3203860Sstever@eecs.umich.edu /** 3213860Sstever@eecs.umich.edu * Create a writeback request for the given block. 3223860Sstever@eecs.umich.edu * @param blk The block to writeback. 3233860Sstever@eecs.umich.edu * @return The writeback request for the block. 3243860Sstever@eecs.umich.edu */ 3253860Sstever@eecs.umich.edu PacketPtr writebackBlk(BlkType *blk); 3263860Sstever@eecs.umich.edu 3272810Srdreslin@umich.edu public: 3282810Srdreslin@umich.edu 3292810Srdreslin@umich.edu class Params 3302810Srdreslin@umich.edu { 3312810Srdreslin@umich.edu public: 3322810Srdreslin@umich.edu TagStore *tags; 3333719Sstever@eecs.umich.edu MissBuffer *missQueue; 3342810Srdreslin@umich.edu Coherence *coherence; 3352810Srdreslin@umich.edu BaseCache::Params baseParams; 3363861Sstever@eecs.umich.edu BasePrefetcher*prefetcher; 3372810Srdreslin@umich.edu bool prefetchAccess; 3382813Srdreslin@umich.edu int hitLatency; 3393860Sstever@eecs.umich.edu CompressionAlgorithm *compressionAlg; 3403860Sstever@eecs.umich.edu const int16_t blkSize; 3413860Sstever@eecs.umich.edu const bool doFastWrites; 3423860Sstever@eecs.umich.edu const bool prefetchMiss; 3433860Sstever@eecs.umich.edu const bool storeCompressed; 3443860Sstever@eecs.umich.edu const bool compressOnWriteback; 3453860Sstever@eecs.umich.edu const int16_t compLatency; 3463860Sstever@eecs.umich.edu const bool adaptiveCompression; 3473860Sstever@eecs.umich.edu const bool writebackCompressed; 3482810Srdreslin@umich.edu 3493719Sstever@eecs.umich.edu Params(TagStore *_tags, MissBuffer *mq, Coherence *coh, 3503315Sstever@eecs.umich.edu BaseCache::Params params, 3513861Sstever@eecs.umich.edu BasePrefetcher *_prefetcher, 3523860Sstever@eecs.umich.edu bool prefetch_access, int hit_latency, 3533860Sstever@eecs.umich.edu bool do_fast_writes, 3543860Sstever@eecs.umich.edu bool store_compressed, bool adaptive_compression, 3553860Sstever@eecs.umich.edu bool writeback_compressed, 3563860Sstever@eecs.umich.edu CompressionAlgorithm *_compressionAlg, int comp_latency, 3573860Sstever@eecs.umich.edu bool prefetch_miss) 3583315Sstever@eecs.umich.edu : tags(_tags), missQueue(mq), coherence(coh), 3593315Sstever@eecs.umich.edu baseParams(params), 3602813Srdreslin@umich.edu prefetcher(_prefetcher), prefetchAccess(prefetch_access), 3613860Sstever@eecs.umich.edu hitLatency(hit_latency), 3623860Sstever@eecs.umich.edu compressionAlg(_compressionAlg), 3633860Sstever@eecs.umich.edu blkSize(_tags->getBlockSize()), 3643860Sstever@eecs.umich.edu doFastWrites(do_fast_writes), 3653860Sstever@eecs.umich.edu prefetchMiss(prefetch_miss), 3663860Sstever@eecs.umich.edu storeCompressed(store_compressed), 3673860Sstever@eecs.umich.edu compressOnWriteback(!store_compressed && writeback_compressed), 3683860Sstever@eecs.umich.edu compLatency(comp_latency), 3693860Sstever@eecs.umich.edu adaptiveCompression(adaptive_compression), 3703860Sstever@eecs.umich.edu writebackCompressed(writeback_compressed) 3712810Srdreslin@umich.edu { 3722810Srdreslin@umich.edu } 3732810Srdreslin@umich.edu }; 3742810Srdreslin@umich.edu 3752810Srdreslin@umich.edu /** Instantiates a basic cache object. */ 3762812Srdreslin@umich.edu Cache(const std::string &_name, Params ¶ms); 3772810Srdreslin@umich.edu 3783738Sstever@eecs.umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 3794190Ssaidi@eecs.umich.edu virtual void deletePortRefs(Port *p); 3802813Srdreslin@umich.edu 3812810Srdreslin@umich.edu void regStats(); 3822810Srdreslin@umich.edu 3832810Srdreslin@umich.edu /** 3842810Srdreslin@umich.edu * Performs the access specified by the request. 3852982Sstever@eecs.umich.edu * @param pkt The request to perform. 3862810Srdreslin@umich.edu * @return The result of the access. 3872810Srdreslin@umich.edu */ 3883349Sbinkertn@umich.edu bool access(PacketPtr &pkt); 3892810Srdreslin@umich.edu 3902810Srdreslin@umich.edu /** 3912810Srdreslin@umich.edu * Selects a request to send on the bus. 3922810Srdreslin@umich.edu * @return The memory request to service. 3932810Srdreslin@umich.edu */ 3944458Sstever@eecs.umich.edu PacketPtr getPacket(); 3952810Srdreslin@umich.edu 3962810Srdreslin@umich.edu /** 3972810Srdreslin@umich.edu * Was the request was sent successfully? 3982982Sstever@eecs.umich.edu * @param pkt The request. 3992810Srdreslin@umich.edu * @param success True if the request was sent successfully. 4002810Srdreslin@umich.edu */ 4014458Sstever@eecs.umich.edu void sendResult(PacketPtr &pkt, MSHR* mshr, bool success); 4023293Srdreslin@umich.edu 4033293Srdreslin@umich.edu /** 4042810Srdreslin@umich.edu * Handles a response (cache line fill/write ack) from the bus. 4052982Sstever@eecs.umich.edu * @param pkt The request being responded to. 4062810Srdreslin@umich.edu */ 4073349Sbinkertn@umich.edu void handleResponse(PacketPtr &pkt); 4082810Srdreslin@umich.edu 4092810Srdreslin@umich.edu /** 4102810Srdreslin@umich.edu * Snoops bus transactions to maintain coherence. 4112982Sstever@eecs.umich.edu * @param pkt The current bus transaction. 4122810Srdreslin@umich.edu */ 4133349Sbinkertn@umich.edu void snoop(PacketPtr &pkt); 4142810Srdreslin@umich.edu 4153349Sbinkertn@umich.edu void snoopResponse(PacketPtr &pkt); 4162810Srdreslin@umich.edu 4172810Srdreslin@umich.edu /** 4182982Sstever@eecs.umich.edu * Squash all requests associated with specified thread. 4192810Srdreslin@umich.edu * intended for use by I-cache. 4202982Sstever@eecs.umich.edu * @param threadNum The thread to squash. 4212810Srdreslin@umich.edu */ 4222811Srdreslin@umich.edu void squash(int threadNum) 4232810Srdreslin@umich.edu { 4242811Srdreslin@umich.edu missQueue->squash(threadNum); 4252810Srdreslin@umich.edu } 4262810Srdreslin@umich.edu 4272810Srdreslin@umich.edu /** 4282810Srdreslin@umich.edu * Return the number of outstanding misses in a Cache. 4292810Srdreslin@umich.edu * Default returns 0. 4302810Srdreslin@umich.edu * 4312810Srdreslin@umich.edu * @retval unsigned The number of missing still outstanding. 4322810Srdreslin@umich.edu */ 4332810Srdreslin@umich.edu unsigned outstandingMisses() const 4342810Srdreslin@umich.edu { 4352810Srdreslin@umich.edu return missQueue->getMisses(); 4362810Srdreslin@umich.edu } 4372810Srdreslin@umich.edu 4382810Srdreslin@umich.edu /** 4392810Srdreslin@umich.edu * Perform the access specified in the request and return the estimated 4402810Srdreslin@umich.edu * time of completion. This function can either update the hierarchy state 4412810Srdreslin@umich.edu * or just perform the access wherever the data is found depending on the 4422810Srdreslin@umich.edu * state of the update flag. 4432982Sstever@eecs.umich.edu * @param pkt The memory request to satisfy 4442810Srdreslin@umich.edu * @param update If true, update the hierarchy, otherwise just perform the 4452810Srdreslin@umich.edu * request. 4462810Srdreslin@umich.edu * @return The estimated completion time. 4472810Srdreslin@umich.edu */ 4483349Sbinkertn@umich.edu Tick probe(PacketPtr &pkt, bool update, CachePort * otherSidePort); 4492810Srdreslin@umich.edu 4502810Srdreslin@umich.edu /** 4512810Srdreslin@umich.edu * Snoop for the provided request in the cache and return the estimated 4522810Srdreslin@umich.edu * time of completion. 4532810Srdreslin@umich.edu * @todo Can a snoop probe not change state? 4542982Sstever@eecs.umich.edu * @param pkt The memory request to satisfy 4552810Srdreslin@umich.edu * @param update If true, update the hierarchy, otherwise just perform the 4562810Srdreslin@umich.edu * request. 4572810Srdreslin@umich.edu * @return The estimated completion time. 4582810Srdreslin@umich.edu */ 4593349Sbinkertn@umich.edu Tick snoopProbe(PacketPtr &pkt); 4603861Sstever@eecs.umich.edu 4613861Sstever@eecs.umich.edu bool inCache(Addr addr) { 4623861Sstever@eecs.umich.edu return (tags->findBlock(addr) != 0); 4633861Sstever@eecs.umich.edu } 4643861Sstever@eecs.umich.edu 4653861Sstever@eecs.umich.edu bool inMissQueue(Addr addr) { 4663861Sstever@eecs.umich.edu return (missQueue->findMSHR(addr) != 0); 4673861Sstever@eecs.umich.edu } 4682810Srdreslin@umich.edu}; 4692810Srdreslin@umich.edu 4702810Srdreslin@umich.edu#endif // __CACHE_HH__ 471