cache.hh revision 4458
12810Srdreslin@umich.edu/* 22810Srdreslin@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 32810Srdreslin@umich.edu * All rights reserved. 42810Srdreslin@umich.edu * 52810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 62810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 72810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 82810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 92810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 102810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 112810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 122810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 132810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 142810Srdreslin@umich.edu * this software without specific prior written permission. 152810Srdreslin@umich.edu * 162810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * Authors: Erik Hallnor 292810Srdreslin@umich.edu * Dave Greene 302810Srdreslin@umich.edu * Steve Reinhardt 314458Sstever@eecs.umich.edu * Ron Dreslinski 322810Srdreslin@umich.edu */ 332810Srdreslin@umich.edu 342810Srdreslin@umich.edu/** 352810Srdreslin@umich.edu * @file 362810Srdreslin@umich.edu * Describes a cache based on template policies. 372810Srdreslin@umich.edu */ 382810Srdreslin@umich.edu 392810Srdreslin@umich.edu#ifndef __CACHE_HH__ 402810Srdreslin@umich.edu#define __CACHE_HH__ 412810Srdreslin@umich.edu 423860Sstever@eecs.umich.edu#include "base/compression/base.hh" 432810Srdreslin@umich.edu#include "base/misc.hh" // fatal, panic, and warn 442810Srdreslin@umich.edu#include "cpu/smt.hh" // SMT_MAX_THREADS 452810Srdreslin@umich.edu 462810Srdreslin@umich.edu#include "mem/cache/base_cache.hh" 473860Sstever@eecs.umich.edu#include "mem/cache/cache_blk.hh" 483719Sstever@eecs.umich.edu#include "mem/cache/miss/miss_buffer.hh" 492810Srdreslin@umich.edu 504458Sstever@eecs.umich.edu#include "sim/eventq.hh" 514458Sstever@eecs.umich.edu 522813Srdreslin@umich.edu//Forward decleration 532813Srdreslin@umich.educlass MSHR; 543861Sstever@eecs.umich.educlass BasePrefetcher; 552810Srdreslin@umich.edu 562810Srdreslin@umich.edu/** 572810Srdreslin@umich.edu * A template-policy based cache. The behavior of the cache can be altered by 582810Srdreslin@umich.edu * supplying different template policies. TagStore handles all tag and data 592810Srdreslin@umich.edu * storage @sa TagStore. Buffering handles all misses and writes/writebacks 602810Srdreslin@umich.edu * @sa MissQueue. Coherence handles all coherence policy details @sa 612810Srdreslin@umich.edu * UniCoherence, SimpleMultiCoherence. 622810Srdreslin@umich.edu */ 633719Sstever@eecs.umich.edutemplate <class TagStore, class Coherence> 642810Srdreslin@umich.educlass Cache : public BaseCache 652810Srdreslin@umich.edu{ 662810Srdreslin@umich.edu public: 672810Srdreslin@umich.edu /** Define the type of cache block to use. */ 682810Srdreslin@umich.edu typedef typename TagStore::BlkType BlkType; 693860Sstever@eecs.umich.edu /** A typedef for a list of BlkType pointers. */ 703860Sstever@eecs.umich.edu typedef typename TagStore::BlkList BlkList; 712810Srdreslin@umich.edu 722810Srdreslin@umich.edu bool prefetchAccess; 733738Sstever@eecs.umich.edu 742810Srdreslin@umich.edu protected: 752810Srdreslin@umich.edu 763738Sstever@eecs.umich.edu class CpuSidePort : public CachePort 773738Sstever@eecs.umich.edu { 783738Sstever@eecs.umich.edu public: 793738Sstever@eecs.umich.edu CpuSidePort(const std::string &_name, 803738Sstever@eecs.umich.edu Cache<TagStore,Coherence> *_cache); 813738Sstever@eecs.umich.edu 823738Sstever@eecs.umich.edu // BaseCache::CachePort just has a BaseCache *; this function 833738Sstever@eecs.umich.edu // lets us get back the type info we lost when we stored the 843738Sstever@eecs.umich.edu // cache pointer there. 853738Sstever@eecs.umich.edu Cache<TagStore,Coherence> *myCache() { 863738Sstever@eecs.umich.edu return static_cast<Cache<TagStore,Coherence> *>(cache); 873738Sstever@eecs.umich.edu } 883738Sstever@eecs.umich.edu 894458Sstever@eecs.umich.edu void processRequestEvent(); 904458Sstever@eecs.umich.edu void processResponseEvent(); 914458Sstever@eecs.umich.edu 923738Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 933738Sstever@eecs.umich.edu 944458Sstever@eecs.umich.edu virtual void recvRetry(); 954458Sstever@eecs.umich.edu 963738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 973738Sstever@eecs.umich.edu 983738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 994458Sstever@eecs.umich.edu 1004458Sstever@eecs.umich.edu typedef EventWrapper<CpuSidePort, &CpuSidePort::processResponseEvent> 1014458Sstever@eecs.umich.edu ResponseEvent; 1024458Sstever@eecs.umich.edu 1034458Sstever@eecs.umich.edu typedef EventWrapper<CpuSidePort, &CpuSidePort::processRequestEvent> 1044458Sstever@eecs.umich.edu RequestEvent; 1054458Sstever@eecs.umich.edu 1064458Sstever@eecs.umich.edu virtual void scheduleRequestEvent(Tick t) { 1074458Sstever@eecs.umich.edu new RequestEvent(this, t); 1084458Sstever@eecs.umich.edu } 1093738Sstever@eecs.umich.edu }; 1103738Sstever@eecs.umich.edu 1113738Sstever@eecs.umich.edu class MemSidePort : public CachePort 1123738Sstever@eecs.umich.edu { 1133738Sstever@eecs.umich.edu public: 1143738Sstever@eecs.umich.edu MemSidePort(const std::string &_name, 1153738Sstever@eecs.umich.edu Cache<TagStore,Coherence> *_cache); 1163738Sstever@eecs.umich.edu 1173738Sstever@eecs.umich.edu // BaseCache::CachePort just has a BaseCache *; this function 1183738Sstever@eecs.umich.edu // lets us get back the type info we lost when we stored the 1193738Sstever@eecs.umich.edu // cache pointer there. 1203738Sstever@eecs.umich.edu Cache<TagStore,Coherence> *myCache() { 1213738Sstever@eecs.umich.edu return static_cast<Cache<TagStore,Coherence> *>(cache); 1223738Sstever@eecs.umich.edu } 1233738Sstever@eecs.umich.edu 1244458Sstever@eecs.umich.edu void processRequestEvent(); 1254458Sstever@eecs.umich.edu void processResponseEvent(); 1264458Sstever@eecs.umich.edu 1273738Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 1283738Sstever@eecs.umich.edu 1294458Sstever@eecs.umich.edu virtual void recvRetry(); 1304458Sstever@eecs.umich.edu 1313738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 1323738Sstever@eecs.umich.edu 1333738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 1344458Sstever@eecs.umich.edu 1354458Sstever@eecs.umich.edu typedef EventWrapper<MemSidePort, &MemSidePort::processResponseEvent> 1364458Sstever@eecs.umich.edu ResponseEvent; 1374458Sstever@eecs.umich.edu 1384458Sstever@eecs.umich.edu typedef EventWrapper<MemSidePort, &MemSidePort::processRequestEvent> 1394458Sstever@eecs.umich.edu RequestEvent; 1404458Sstever@eecs.umich.edu 1414458Sstever@eecs.umich.edu virtual void scheduleRequestEvent(Tick t) { 1424458Sstever@eecs.umich.edu new RequestEvent(this, t); 1434458Sstever@eecs.umich.edu } 1443738Sstever@eecs.umich.edu }; 1453738Sstever@eecs.umich.edu 1462810Srdreslin@umich.edu /** Tag and data Storage */ 1472810Srdreslin@umich.edu TagStore *tags; 1482810Srdreslin@umich.edu /** Miss and Writeback handler */ 1493719Sstever@eecs.umich.edu MissBuffer *missQueue; 1502810Srdreslin@umich.edu /** Coherence protocol. */ 1512810Srdreslin@umich.edu Coherence *coherence; 1522810Srdreslin@umich.edu 1532810Srdreslin@umich.edu /** Prefetcher */ 1543861Sstever@eecs.umich.edu BasePrefetcher *prefetcher; 1552810Srdreslin@umich.edu 1562810Srdreslin@umich.edu /** 1572810Srdreslin@umich.edu * The clock ratio of the outgoing bus. 1582810Srdreslin@umich.edu * Used for calculating critical word first. 1592810Srdreslin@umich.edu */ 1602810Srdreslin@umich.edu int busRatio; 1612810Srdreslin@umich.edu 1622810Srdreslin@umich.edu /** 1632810Srdreslin@umich.edu * The bus width in bytes of the outgoing bus. 1642810Srdreslin@umich.edu * Used for calculating critical word first. 1652810Srdreslin@umich.edu */ 1662810Srdreslin@umich.edu int busWidth; 1672810Srdreslin@umich.edu 1682813Srdreslin@umich.edu /** 1692813Srdreslin@umich.edu * The latency of a hit in this device. 1702813Srdreslin@umich.edu */ 1712813Srdreslin@umich.edu int hitLatency; 1722813Srdreslin@umich.edu 1732810Srdreslin@umich.edu /** 1742810Srdreslin@umich.edu * A permanent mem req to always be used to cause invalidations. 1752810Srdreslin@umich.edu * Used to append to target list, to cause an invalidation. 1762810Srdreslin@umich.edu */ 1773349Sbinkertn@umich.edu PacketPtr invalidatePkt; 1783208Srdreslin@umich.edu Request *invalidateReq; 1792810Srdreslin@umich.edu 1803860Sstever@eecs.umich.edu /** 1813860Sstever@eecs.umich.edu * Policy class for performing compression. 1823860Sstever@eecs.umich.edu */ 1833860Sstever@eecs.umich.edu CompressionAlgorithm *compressionAlg; 1843860Sstever@eecs.umich.edu 1853860Sstever@eecs.umich.edu /** 1863860Sstever@eecs.umich.edu * The block size of this cache. Set to value in the Tags object. 1873860Sstever@eecs.umich.edu */ 1883860Sstever@eecs.umich.edu const int16_t blkSize; 1893860Sstever@eecs.umich.edu 1903860Sstever@eecs.umich.edu /** 1913860Sstever@eecs.umich.edu * Can this cache should allocate a block on a line-sized write miss. 1923860Sstever@eecs.umich.edu */ 1933860Sstever@eecs.umich.edu const bool doFastWrites; 1943860Sstever@eecs.umich.edu 1953860Sstever@eecs.umich.edu const bool prefetchMiss; 1963860Sstever@eecs.umich.edu 1973860Sstever@eecs.umich.edu /** 1983860Sstever@eecs.umich.edu * Can the data can be stored in a compressed form. 1993860Sstever@eecs.umich.edu */ 2003860Sstever@eecs.umich.edu const bool storeCompressed; 2013860Sstever@eecs.umich.edu 2023860Sstever@eecs.umich.edu /** 2033860Sstever@eecs.umich.edu * Do we need to compress blocks on writebacks (i.e. because 2043860Sstever@eecs.umich.edu * writeback bus is compressed but storage is not)? 2053860Sstever@eecs.umich.edu */ 2063860Sstever@eecs.umich.edu const bool compressOnWriteback; 2073860Sstever@eecs.umich.edu 2083860Sstever@eecs.umich.edu /** 2093860Sstever@eecs.umich.edu * The latency of a compression operation. 2103860Sstever@eecs.umich.edu */ 2113860Sstever@eecs.umich.edu const int16_t compLatency; 2123860Sstever@eecs.umich.edu 2133860Sstever@eecs.umich.edu /** 2143860Sstever@eecs.umich.edu * Should we use an adaptive compression scheme. 2153860Sstever@eecs.umich.edu */ 2163860Sstever@eecs.umich.edu const bool adaptiveCompression; 2173860Sstever@eecs.umich.edu 2183860Sstever@eecs.umich.edu /** 2193860Sstever@eecs.umich.edu * Do writebacks need to be compressed (i.e. because writeback bus 2203860Sstever@eecs.umich.edu * is compressed), whether or not they're already compressed for 2213860Sstever@eecs.umich.edu * storage. 2223860Sstever@eecs.umich.edu */ 2233860Sstever@eecs.umich.edu const bool writebackCompressed; 2243860Sstever@eecs.umich.edu 2253860Sstever@eecs.umich.edu /** 2263860Sstever@eecs.umich.edu * Compare the internal block data to the fast access block data. 2273860Sstever@eecs.umich.edu * @param blk The cache block to check. 2283860Sstever@eecs.umich.edu * @return True if the data is the same. 2293860Sstever@eecs.umich.edu */ 2303860Sstever@eecs.umich.edu bool verifyData(BlkType *blk); 2313860Sstever@eecs.umich.edu 2323860Sstever@eecs.umich.edu /** 2333860Sstever@eecs.umich.edu * Update the internal data of the block. The data to write is assumed to 2343860Sstever@eecs.umich.edu * be in the fast access data. 2353860Sstever@eecs.umich.edu * @param blk The block with the data to update. 2363860Sstever@eecs.umich.edu * @param writebacks A list to store any generated writebacks. 2373860Sstever@eecs.umich.edu * @param compress_block True if we should compress this block 2383860Sstever@eecs.umich.edu */ 2393860Sstever@eecs.umich.edu void updateData(BlkType *blk, PacketList &writebacks, bool compress_block); 2403860Sstever@eecs.umich.edu 2413860Sstever@eecs.umich.edu /** 2423860Sstever@eecs.umich.edu * Handle a replacement for the given request. 2433860Sstever@eecs.umich.edu * @param blk A pointer to the block, usually NULL 2443860Sstever@eecs.umich.edu * @param pkt The memory request to satisfy. 2453860Sstever@eecs.umich.edu * @param new_state The new state of the block. 2463860Sstever@eecs.umich.edu * @param writebacks A list to store any generated writebacks. 2473860Sstever@eecs.umich.edu */ 2483860Sstever@eecs.umich.edu BlkType* doReplacement(BlkType *blk, PacketPtr &pkt, 2493860Sstever@eecs.umich.edu CacheBlk::State new_state, PacketList &writebacks); 2503860Sstever@eecs.umich.edu 2513860Sstever@eecs.umich.edu /** 2523860Sstever@eecs.umich.edu * Does all the processing necessary to perform the provided request. 2533860Sstever@eecs.umich.edu * @param pkt The memory request to perform. 2543860Sstever@eecs.umich.edu * @param lat The latency of the access. 2553860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 2563860Sstever@eecs.umich.edu * @param update True if the replacement data should be updated. 2573860Sstever@eecs.umich.edu * @return Pointer to the cache block touched by the request. NULL if it 2583860Sstever@eecs.umich.edu * was a miss. 2593860Sstever@eecs.umich.edu */ 2603860Sstever@eecs.umich.edu BlkType* handleAccess(PacketPtr &pkt, int & lat, 2613860Sstever@eecs.umich.edu PacketList & writebacks, bool update = true); 2623860Sstever@eecs.umich.edu 2634219Srdreslin@umich.edu 2644219Srdreslin@umich.edu /** 2654219Srdreslin@umich.edu *Handle doing the Compare and Swap function for SPARC. 2664219Srdreslin@umich.edu */ 2674219Srdreslin@umich.edu void cmpAndSwap(BlkType *blk, PacketPtr &pkt); 2684219Srdreslin@umich.edu 2693860Sstever@eecs.umich.edu /** 2703860Sstever@eecs.umich.edu * Populates a cache block and handles all outstanding requests for the 2713860Sstever@eecs.umich.edu * satisfied fill request. This version takes an MSHR pointer and uses its 2723860Sstever@eecs.umich.edu * request to fill the cache block, while repsonding to its targets. 2733860Sstever@eecs.umich.edu * @param blk The cache block if it already exists. 2743860Sstever@eecs.umich.edu * @param mshr The MSHR that contains the fill data and targets to satisfy. 2753860Sstever@eecs.umich.edu * @param new_state The state of the new cache block. 2763860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 2773860Sstever@eecs.umich.edu * @return Pointer to the new cache block. 2783860Sstever@eecs.umich.edu */ 2793860Sstever@eecs.umich.edu BlkType* handleFill(BlkType *blk, MSHR * mshr, CacheBlk::State new_state, 2803860Sstever@eecs.umich.edu PacketList & writebacks, PacketPtr pkt); 2813860Sstever@eecs.umich.edu 2823860Sstever@eecs.umich.edu /** 2833860Sstever@eecs.umich.edu * Populates a cache block and handles all outstanding requests for the 2843860Sstever@eecs.umich.edu * satisfied fill request. This version takes two memory requests. One 2853860Sstever@eecs.umich.edu * contains the fill data, the other is an optional target to satisfy. 2863860Sstever@eecs.umich.edu * Used for Cache::probe. 2873860Sstever@eecs.umich.edu * @param blk The cache block if it already exists. 2883860Sstever@eecs.umich.edu * @param pkt The memory request with the fill data. 2893860Sstever@eecs.umich.edu * @param new_state The state of the new cache block. 2903860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 2913860Sstever@eecs.umich.edu * @param target The memory request to perform after the fill. 2923860Sstever@eecs.umich.edu * @return Pointer to the new cache block. 2933860Sstever@eecs.umich.edu */ 2943860Sstever@eecs.umich.edu BlkType* handleFill(BlkType *blk, PacketPtr &pkt, 2953860Sstever@eecs.umich.edu CacheBlk::State new_state, 2963860Sstever@eecs.umich.edu PacketList & writebacks, PacketPtr target = NULL); 2973860Sstever@eecs.umich.edu 2983860Sstever@eecs.umich.edu /** 2993860Sstever@eecs.umich.edu * Sets the blk to the new state and handles the given request. 3003860Sstever@eecs.umich.edu * @param blk The cache block being snooped. 3013860Sstever@eecs.umich.edu * @param new_state The new coherence state for the block. 3023860Sstever@eecs.umich.edu * @param pkt The request to satisfy 3033860Sstever@eecs.umich.edu */ 3043860Sstever@eecs.umich.edu void handleSnoop(BlkType *blk, CacheBlk::State new_state, 3053860Sstever@eecs.umich.edu PacketPtr &pkt); 3063860Sstever@eecs.umich.edu 3073860Sstever@eecs.umich.edu /** 3083860Sstever@eecs.umich.edu * Sets the blk to the new state. 3093860Sstever@eecs.umich.edu * @param blk The cache block being snooped. 3103860Sstever@eecs.umich.edu * @param new_state The new coherence state for the block. 3113860Sstever@eecs.umich.edu */ 3123860Sstever@eecs.umich.edu void handleSnoop(BlkType *blk, CacheBlk::State new_state); 3133860Sstever@eecs.umich.edu 3143860Sstever@eecs.umich.edu /** 3153860Sstever@eecs.umich.edu * Create a writeback request for the given block. 3163860Sstever@eecs.umich.edu * @param blk The block to writeback. 3173860Sstever@eecs.umich.edu * @return The writeback request for the block. 3183860Sstever@eecs.umich.edu */ 3193860Sstever@eecs.umich.edu PacketPtr writebackBlk(BlkType *blk); 3203860Sstever@eecs.umich.edu 3212810Srdreslin@umich.edu public: 3222810Srdreslin@umich.edu 3232810Srdreslin@umich.edu class Params 3242810Srdreslin@umich.edu { 3252810Srdreslin@umich.edu public: 3262810Srdreslin@umich.edu TagStore *tags; 3273719Sstever@eecs.umich.edu MissBuffer *missQueue; 3282810Srdreslin@umich.edu Coherence *coherence; 3292810Srdreslin@umich.edu BaseCache::Params baseParams; 3303861Sstever@eecs.umich.edu BasePrefetcher*prefetcher; 3312810Srdreslin@umich.edu bool prefetchAccess; 3322813Srdreslin@umich.edu int hitLatency; 3333860Sstever@eecs.umich.edu CompressionAlgorithm *compressionAlg; 3343860Sstever@eecs.umich.edu const int16_t blkSize; 3353860Sstever@eecs.umich.edu const bool doFastWrites; 3363860Sstever@eecs.umich.edu const bool prefetchMiss; 3373860Sstever@eecs.umich.edu const bool storeCompressed; 3383860Sstever@eecs.umich.edu const bool compressOnWriteback; 3393860Sstever@eecs.umich.edu const int16_t compLatency; 3403860Sstever@eecs.umich.edu const bool adaptiveCompression; 3413860Sstever@eecs.umich.edu const bool writebackCompressed; 3422810Srdreslin@umich.edu 3433719Sstever@eecs.umich.edu Params(TagStore *_tags, MissBuffer *mq, Coherence *coh, 3443315Sstever@eecs.umich.edu BaseCache::Params params, 3453861Sstever@eecs.umich.edu BasePrefetcher *_prefetcher, 3463860Sstever@eecs.umich.edu bool prefetch_access, int hit_latency, 3473860Sstever@eecs.umich.edu bool do_fast_writes, 3483860Sstever@eecs.umich.edu bool store_compressed, bool adaptive_compression, 3493860Sstever@eecs.umich.edu bool writeback_compressed, 3503860Sstever@eecs.umich.edu CompressionAlgorithm *_compressionAlg, int comp_latency, 3513860Sstever@eecs.umich.edu bool prefetch_miss) 3523315Sstever@eecs.umich.edu : tags(_tags), missQueue(mq), coherence(coh), 3533315Sstever@eecs.umich.edu baseParams(params), 3542813Srdreslin@umich.edu prefetcher(_prefetcher), prefetchAccess(prefetch_access), 3553860Sstever@eecs.umich.edu hitLatency(hit_latency), 3563860Sstever@eecs.umich.edu compressionAlg(_compressionAlg), 3573860Sstever@eecs.umich.edu blkSize(_tags->getBlockSize()), 3583860Sstever@eecs.umich.edu doFastWrites(do_fast_writes), 3593860Sstever@eecs.umich.edu prefetchMiss(prefetch_miss), 3603860Sstever@eecs.umich.edu storeCompressed(store_compressed), 3613860Sstever@eecs.umich.edu compressOnWriteback(!store_compressed && writeback_compressed), 3623860Sstever@eecs.umich.edu compLatency(comp_latency), 3633860Sstever@eecs.umich.edu adaptiveCompression(adaptive_compression), 3643860Sstever@eecs.umich.edu writebackCompressed(writeback_compressed) 3652810Srdreslin@umich.edu { 3662810Srdreslin@umich.edu } 3672810Srdreslin@umich.edu }; 3682810Srdreslin@umich.edu 3692810Srdreslin@umich.edu /** Instantiates a basic cache object. */ 3702812Srdreslin@umich.edu Cache(const std::string &_name, Params ¶ms); 3712810Srdreslin@umich.edu 3723738Sstever@eecs.umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 3734190Ssaidi@eecs.umich.edu virtual void deletePortRefs(Port *p); 3742813Srdreslin@umich.edu 3752810Srdreslin@umich.edu void regStats(); 3762810Srdreslin@umich.edu 3772810Srdreslin@umich.edu /** 3782810Srdreslin@umich.edu * Performs the access specified by the request. 3792982Sstever@eecs.umich.edu * @param pkt The request to perform. 3802810Srdreslin@umich.edu * @return The result of the access. 3812810Srdreslin@umich.edu */ 3823349Sbinkertn@umich.edu bool access(PacketPtr &pkt); 3832810Srdreslin@umich.edu 3842810Srdreslin@umich.edu /** 3852810Srdreslin@umich.edu * Selects a request to send on the bus. 3862810Srdreslin@umich.edu * @return The memory request to service. 3872810Srdreslin@umich.edu */ 3884458Sstever@eecs.umich.edu PacketPtr getPacket(); 3892810Srdreslin@umich.edu 3902810Srdreslin@umich.edu /** 3912810Srdreslin@umich.edu * Was the request was sent successfully? 3922982Sstever@eecs.umich.edu * @param pkt The request. 3932810Srdreslin@umich.edu * @param success True if the request was sent successfully. 3942810Srdreslin@umich.edu */ 3954458Sstever@eecs.umich.edu void sendResult(PacketPtr &pkt, MSHR* mshr, bool success); 3963293Srdreslin@umich.edu 3973293Srdreslin@umich.edu /** 3982810Srdreslin@umich.edu * Handles a response (cache line fill/write ack) from the bus. 3992982Sstever@eecs.umich.edu * @param pkt The request being responded to. 4002810Srdreslin@umich.edu */ 4013349Sbinkertn@umich.edu void handleResponse(PacketPtr &pkt); 4022810Srdreslin@umich.edu 4032810Srdreslin@umich.edu /** 4042810Srdreslin@umich.edu * Snoops bus transactions to maintain coherence. 4052982Sstever@eecs.umich.edu * @param pkt The current bus transaction. 4062810Srdreslin@umich.edu */ 4073349Sbinkertn@umich.edu void snoop(PacketPtr &pkt); 4082810Srdreslin@umich.edu 4093349Sbinkertn@umich.edu void snoopResponse(PacketPtr &pkt); 4102810Srdreslin@umich.edu 4112810Srdreslin@umich.edu /** 4122982Sstever@eecs.umich.edu * Squash all requests associated with specified thread. 4132810Srdreslin@umich.edu * intended for use by I-cache. 4142982Sstever@eecs.umich.edu * @param threadNum The thread to squash. 4152810Srdreslin@umich.edu */ 4162811Srdreslin@umich.edu void squash(int threadNum) 4172810Srdreslin@umich.edu { 4182811Srdreslin@umich.edu missQueue->squash(threadNum); 4192810Srdreslin@umich.edu } 4202810Srdreslin@umich.edu 4212810Srdreslin@umich.edu /** 4222810Srdreslin@umich.edu * Return the number of outstanding misses in a Cache. 4232810Srdreslin@umich.edu * Default returns 0. 4242810Srdreslin@umich.edu * 4252810Srdreslin@umich.edu * @retval unsigned The number of missing still outstanding. 4262810Srdreslin@umich.edu */ 4272810Srdreslin@umich.edu unsigned outstandingMisses() const 4282810Srdreslin@umich.edu { 4292810Srdreslin@umich.edu return missQueue->getMisses(); 4302810Srdreslin@umich.edu } 4312810Srdreslin@umich.edu 4322810Srdreslin@umich.edu /** 4332810Srdreslin@umich.edu * Perform the access specified in the request and return the estimated 4342810Srdreslin@umich.edu * time of completion. This function can either update the hierarchy state 4352810Srdreslin@umich.edu * or just perform the access wherever the data is found depending on the 4362810Srdreslin@umich.edu * state of the update flag. 4372982Sstever@eecs.umich.edu * @param pkt The memory request to satisfy 4382810Srdreslin@umich.edu * @param update If true, update the hierarchy, otherwise just perform the 4392810Srdreslin@umich.edu * request. 4402810Srdreslin@umich.edu * @return The estimated completion time. 4412810Srdreslin@umich.edu */ 4423349Sbinkertn@umich.edu Tick probe(PacketPtr &pkt, bool update, CachePort * otherSidePort); 4432810Srdreslin@umich.edu 4442810Srdreslin@umich.edu /** 4452810Srdreslin@umich.edu * Snoop for the provided request in the cache and return the estimated 4462810Srdreslin@umich.edu * time of completion. 4472810Srdreslin@umich.edu * @todo Can a snoop probe not change state? 4482982Sstever@eecs.umich.edu * @param pkt The memory request to satisfy 4492810Srdreslin@umich.edu * @param update If true, update the hierarchy, otherwise just perform the 4502810Srdreslin@umich.edu * request. 4512810Srdreslin@umich.edu * @return The estimated completion time. 4522810Srdreslin@umich.edu */ 4533349Sbinkertn@umich.edu Tick snoopProbe(PacketPtr &pkt); 4543861Sstever@eecs.umich.edu 4553861Sstever@eecs.umich.edu bool inCache(Addr addr) { 4563861Sstever@eecs.umich.edu return (tags->findBlock(addr) != 0); 4573861Sstever@eecs.umich.edu } 4583861Sstever@eecs.umich.edu 4593861Sstever@eecs.umich.edu bool inMissQueue(Addr addr) { 4603861Sstever@eecs.umich.edu return (missQueue->findMSHR(addr) != 0); 4613861Sstever@eecs.umich.edu } 4622810Srdreslin@umich.edu}; 4632810Srdreslin@umich.edu 4642810Srdreslin@umich.edu#endif // __CACHE_HH__ 465