cache.hh revision 3738
12810Srdreslin@umich.edu/* 22810Srdreslin@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 32810Srdreslin@umich.edu * All rights reserved. 42810Srdreslin@umich.edu * 52810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 62810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 72810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 82810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 92810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 102810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 112810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 122810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 132810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 142810Srdreslin@umich.edu * this software without specific prior written permission. 152810Srdreslin@umich.edu * 162810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * Authors: Erik Hallnor 292810Srdreslin@umich.edu * Dave Greene 302810Srdreslin@umich.edu * Steve Reinhardt 312810Srdreslin@umich.edu */ 322810Srdreslin@umich.edu 332810Srdreslin@umich.edu/** 342810Srdreslin@umich.edu * @file 352810Srdreslin@umich.edu * Describes a cache based on template policies. 362810Srdreslin@umich.edu */ 372810Srdreslin@umich.edu 382810Srdreslin@umich.edu#ifndef __CACHE_HH__ 392810Srdreslin@umich.edu#define __CACHE_HH__ 402810Srdreslin@umich.edu 412810Srdreslin@umich.edu#include "base/misc.hh" // fatal, panic, and warn 422810Srdreslin@umich.edu#include "cpu/smt.hh" // SMT_MAX_THREADS 432810Srdreslin@umich.edu 442810Srdreslin@umich.edu#include "mem/cache/base_cache.hh" 453719Sstever@eecs.umich.edu#include "mem/cache/miss/miss_buffer.hh" 462810Srdreslin@umich.edu#include "mem/cache/prefetch/prefetcher.hh" 472810Srdreslin@umich.edu 482813Srdreslin@umich.edu//Forward decleration 492813Srdreslin@umich.educlass MSHR; 502813Srdreslin@umich.edu 512810Srdreslin@umich.edu 522810Srdreslin@umich.edu/** 532810Srdreslin@umich.edu * A template-policy based cache. The behavior of the cache can be altered by 542810Srdreslin@umich.edu * supplying different template policies. TagStore handles all tag and data 552810Srdreslin@umich.edu * storage @sa TagStore. Buffering handles all misses and writes/writebacks 562810Srdreslin@umich.edu * @sa MissQueue. Coherence handles all coherence policy details @sa 572810Srdreslin@umich.edu * UniCoherence, SimpleMultiCoherence. 582810Srdreslin@umich.edu */ 593719Sstever@eecs.umich.edutemplate <class TagStore, class Coherence> 602810Srdreslin@umich.educlass Cache : public BaseCache 612810Srdreslin@umich.edu{ 622810Srdreslin@umich.edu public: 632810Srdreslin@umich.edu /** Define the type of cache block to use. */ 642810Srdreslin@umich.edu typedef typename TagStore::BlkType BlkType; 652810Srdreslin@umich.edu 662810Srdreslin@umich.edu bool prefetchAccess; 673738Sstever@eecs.umich.edu 682810Srdreslin@umich.edu protected: 692810Srdreslin@umich.edu 703738Sstever@eecs.umich.edu class CpuSidePort : public CachePort 713738Sstever@eecs.umich.edu { 723738Sstever@eecs.umich.edu public: 733738Sstever@eecs.umich.edu CpuSidePort(const std::string &_name, 743738Sstever@eecs.umich.edu Cache<TagStore,Coherence> *_cache); 753738Sstever@eecs.umich.edu 763738Sstever@eecs.umich.edu // BaseCache::CachePort just has a BaseCache *; this function 773738Sstever@eecs.umich.edu // lets us get back the type info we lost when we stored the 783738Sstever@eecs.umich.edu // cache pointer there. 793738Sstever@eecs.umich.edu Cache<TagStore,Coherence> *myCache() { 803738Sstever@eecs.umich.edu return static_cast<Cache<TagStore,Coherence> *>(cache); 813738Sstever@eecs.umich.edu } 823738Sstever@eecs.umich.edu 833738Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 843738Sstever@eecs.umich.edu 853738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 863738Sstever@eecs.umich.edu 873738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 883738Sstever@eecs.umich.edu }; 893738Sstever@eecs.umich.edu 903738Sstever@eecs.umich.edu class MemSidePort : public CachePort 913738Sstever@eecs.umich.edu { 923738Sstever@eecs.umich.edu public: 933738Sstever@eecs.umich.edu MemSidePort(const std::string &_name, 943738Sstever@eecs.umich.edu Cache<TagStore,Coherence> *_cache); 953738Sstever@eecs.umich.edu 963738Sstever@eecs.umich.edu // BaseCache::CachePort just has a BaseCache *; this function 973738Sstever@eecs.umich.edu // lets us get back the type info we lost when we stored the 983738Sstever@eecs.umich.edu // cache pointer there. 993738Sstever@eecs.umich.edu Cache<TagStore,Coherence> *myCache() { 1003738Sstever@eecs.umich.edu return static_cast<Cache<TagStore,Coherence> *>(cache); 1013738Sstever@eecs.umich.edu } 1023738Sstever@eecs.umich.edu 1033738Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 1043738Sstever@eecs.umich.edu 1053738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 1063738Sstever@eecs.umich.edu 1073738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 1083738Sstever@eecs.umich.edu }; 1093738Sstever@eecs.umich.edu 1102810Srdreslin@umich.edu /** Tag and data Storage */ 1112810Srdreslin@umich.edu TagStore *tags; 1122810Srdreslin@umich.edu /** Miss and Writeback handler */ 1133719Sstever@eecs.umich.edu MissBuffer *missQueue; 1142810Srdreslin@umich.edu /** Coherence protocol. */ 1152810Srdreslin@umich.edu Coherence *coherence; 1162810Srdreslin@umich.edu 1172810Srdreslin@umich.edu /** Prefetcher */ 1183719Sstever@eecs.umich.edu Prefetcher<TagStore> *prefetcher; 1192810Srdreslin@umich.edu 1202810Srdreslin@umich.edu /** 1212810Srdreslin@umich.edu * The clock ratio of the outgoing bus. 1222810Srdreslin@umich.edu * Used for calculating critical word first. 1232810Srdreslin@umich.edu */ 1242810Srdreslin@umich.edu int busRatio; 1252810Srdreslin@umich.edu 1262810Srdreslin@umich.edu /** 1272810Srdreslin@umich.edu * The bus width in bytes of the outgoing bus. 1282810Srdreslin@umich.edu * Used for calculating critical word first. 1292810Srdreslin@umich.edu */ 1302810Srdreslin@umich.edu int busWidth; 1312810Srdreslin@umich.edu 1322813Srdreslin@umich.edu /** 1332813Srdreslin@umich.edu * The latency of a hit in this device. 1342813Srdreslin@umich.edu */ 1352813Srdreslin@umich.edu int hitLatency; 1362813Srdreslin@umich.edu 1372810Srdreslin@umich.edu /** 1382810Srdreslin@umich.edu * A permanent mem req to always be used to cause invalidations. 1392810Srdreslin@umich.edu * Used to append to target list, to cause an invalidation. 1402810Srdreslin@umich.edu */ 1413349Sbinkertn@umich.edu PacketPtr invalidatePkt; 1423208Srdreslin@umich.edu Request *invalidateReq; 1432810Srdreslin@umich.edu 1442810Srdreslin@umich.edu public: 1452810Srdreslin@umich.edu 1462810Srdreslin@umich.edu class Params 1472810Srdreslin@umich.edu { 1482810Srdreslin@umich.edu public: 1492810Srdreslin@umich.edu TagStore *tags; 1503719Sstever@eecs.umich.edu MissBuffer *missQueue; 1512810Srdreslin@umich.edu Coherence *coherence; 1522810Srdreslin@umich.edu BaseCache::Params baseParams; 1533719Sstever@eecs.umich.edu Prefetcher<TagStore> *prefetcher; 1542810Srdreslin@umich.edu bool prefetchAccess; 1552813Srdreslin@umich.edu int hitLatency; 1562810Srdreslin@umich.edu 1573719Sstever@eecs.umich.edu Params(TagStore *_tags, MissBuffer *mq, Coherence *coh, 1583315Sstever@eecs.umich.edu BaseCache::Params params, 1593719Sstever@eecs.umich.edu Prefetcher<TagStore> *_prefetcher, 1602813Srdreslin@umich.edu bool prefetch_access, int hit_latency) 1613315Sstever@eecs.umich.edu : tags(_tags), missQueue(mq), coherence(coh), 1623315Sstever@eecs.umich.edu baseParams(params), 1632813Srdreslin@umich.edu prefetcher(_prefetcher), prefetchAccess(prefetch_access), 1642813Srdreslin@umich.edu hitLatency(hit_latency) 1652810Srdreslin@umich.edu { 1662810Srdreslin@umich.edu } 1672810Srdreslin@umich.edu }; 1682810Srdreslin@umich.edu 1692810Srdreslin@umich.edu /** Instantiates a basic cache object. */ 1702812Srdreslin@umich.edu Cache(const std::string &_name, Params ¶ms); 1712810Srdreslin@umich.edu 1723738Sstever@eecs.umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 1732813Srdreslin@umich.edu 1742825Srdreslin@umich.edu virtual void recvStatusChange(Port::Status status, bool isCpuSide); 1752813Srdreslin@umich.edu 1762810Srdreslin@umich.edu void regStats(); 1772810Srdreslin@umich.edu 1782810Srdreslin@umich.edu /** 1792810Srdreslin@umich.edu * Performs the access specified by the request. 1802982Sstever@eecs.umich.edu * @param pkt The request to perform. 1812810Srdreslin@umich.edu * @return The result of the access. 1822810Srdreslin@umich.edu */ 1833349Sbinkertn@umich.edu bool access(PacketPtr &pkt); 1842810Srdreslin@umich.edu 1852810Srdreslin@umich.edu /** 1862810Srdreslin@umich.edu * Selects a request to send on the bus. 1872810Srdreslin@umich.edu * @return The memory request to service. 1882810Srdreslin@umich.edu */ 1893349Sbinkertn@umich.edu virtual PacketPtr getPacket(); 1902810Srdreslin@umich.edu 1912810Srdreslin@umich.edu /** 1922810Srdreslin@umich.edu * Was the request was sent successfully? 1932982Sstever@eecs.umich.edu * @param pkt The request. 1942810Srdreslin@umich.edu * @param success True if the request was sent successfully. 1952810Srdreslin@umich.edu */ 1963349Sbinkertn@umich.edu virtual void sendResult(PacketPtr &pkt, MSHR* mshr, bool success); 1972810Srdreslin@umich.edu 1982810Srdreslin@umich.edu /** 1993293Srdreslin@umich.edu * Was the CSHR request was sent successfully? 2003293Srdreslin@umich.edu * @param pkt The request. 2013293Srdreslin@umich.edu * @param success True if the request was sent successfully. 2023293Srdreslin@umich.edu */ 2033349Sbinkertn@umich.edu virtual void sendCoherenceResult(PacketPtr &pkt, MSHR* cshr, bool success); 2043293Srdreslin@umich.edu 2053293Srdreslin@umich.edu /** 2062810Srdreslin@umich.edu * Handles a response (cache line fill/write ack) from the bus. 2072982Sstever@eecs.umich.edu * @param pkt The request being responded to. 2082810Srdreslin@umich.edu */ 2093349Sbinkertn@umich.edu void handleResponse(PacketPtr &pkt); 2102810Srdreslin@umich.edu 2112810Srdreslin@umich.edu /** 2122810Srdreslin@umich.edu * Selects a coherence message to forward to lower levels of the hierarchy. 2132810Srdreslin@umich.edu * @return The coherence message to forward. 2142810Srdreslin@umich.edu */ 2153349Sbinkertn@umich.edu virtual PacketPtr getCoherencePacket(); 2162810Srdreslin@umich.edu 2172810Srdreslin@umich.edu /** 2182810Srdreslin@umich.edu * Snoops bus transactions to maintain coherence. 2192982Sstever@eecs.umich.edu * @param pkt The current bus transaction. 2202810Srdreslin@umich.edu */ 2213349Sbinkertn@umich.edu void snoop(PacketPtr &pkt); 2222810Srdreslin@umich.edu 2233349Sbinkertn@umich.edu void snoopResponse(PacketPtr &pkt); 2242810Srdreslin@umich.edu 2252810Srdreslin@umich.edu /** 2262810Srdreslin@umich.edu * Invalidates the block containing address if found. 2272810Srdreslin@umich.edu * @param addr The address to look for. 2282810Srdreslin@umich.edu * @param asid The address space ID of the address. 2292810Srdreslin@umich.edu * @todo Is this function necessary? 2302810Srdreslin@umich.edu */ 2312991Srdreslin@umich.edu void invalidateBlk(Addr addr); 2322810Srdreslin@umich.edu 2332810Srdreslin@umich.edu /** 2342982Sstever@eecs.umich.edu * Squash all requests associated with specified thread. 2352810Srdreslin@umich.edu * intended for use by I-cache. 2362982Sstever@eecs.umich.edu * @param threadNum The thread to squash. 2372810Srdreslin@umich.edu */ 2382811Srdreslin@umich.edu void squash(int threadNum) 2392810Srdreslin@umich.edu { 2402811Srdreslin@umich.edu missQueue->squash(threadNum); 2412810Srdreslin@umich.edu } 2422810Srdreslin@umich.edu 2432810Srdreslin@umich.edu /** 2442810Srdreslin@umich.edu * Return the number of outstanding misses in a Cache. 2452810Srdreslin@umich.edu * Default returns 0. 2462810Srdreslin@umich.edu * 2472810Srdreslin@umich.edu * @retval unsigned The number of missing still outstanding. 2482810Srdreslin@umich.edu */ 2492810Srdreslin@umich.edu unsigned outstandingMisses() const 2502810Srdreslin@umich.edu { 2512810Srdreslin@umich.edu return missQueue->getMisses(); 2522810Srdreslin@umich.edu } 2532810Srdreslin@umich.edu 2542810Srdreslin@umich.edu /** 2552810Srdreslin@umich.edu * Perform the access specified in the request and return the estimated 2562810Srdreslin@umich.edu * time of completion. This function can either update the hierarchy state 2572810Srdreslin@umich.edu * or just perform the access wherever the data is found depending on the 2582810Srdreslin@umich.edu * state of the update flag. 2592982Sstever@eecs.umich.edu * @param pkt The memory request to satisfy 2602810Srdreslin@umich.edu * @param update If true, update the hierarchy, otherwise just perform the 2612810Srdreslin@umich.edu * request. 2622810Srdreslin@umich.edu * @return The estimated completion time. 2632810Srdreslin@umich.edu */ 2643349Sbinkertn@umich.edu Tick probe(PacketPtr &pkt, bool update, CachePort * otherSidePort); 2652810Srdreslin@umich.edu 2662810Srdreslin@umich.edu /** 2672810Srdreslin@umich.edu * Snoop for the provided request in the cache and return the estimated 2682810Srdreslin@umich.edu * time of completion. 2692810Srdreslin@umich.edu * @todo Can a snoop probe not change state? 2702982Sstever@eecs.umich.edu * @param pkt The memory request to satisfy 2712810Srdreslin@umich.edu * @param update If true, update the hierarchy, otherwise just perform the 2722810Srdreslin@umich.edu * request. 2732810Srdreslin@umich.edu * @return The estimated completion time. 2742810Srdreslin@umich.edu */ 2753349Sbinkertn@umich.edu Tick snoopProbe(PacketPtr &pkt); 2762810Srdreslin@umich.edu}; 2772810Srdreslin@umich.edu 2782810Srdreslin@umich.edu#endif // __CACHE_HH__ 279