cache.hh revision 3719
12810Srdreslin@umich.edu/* 22810Srdreslin@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 32810Srdreslin@umich.edu * All rights reserved. 42810Srdreslin@umich.edu * 52810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 62810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 72810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 82810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 92810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 102810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 112810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 122810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 132810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 142810Srdreslin@umich.edu * this software without specific prior written permission. 152810Srdreslin@umich.edu * 162810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * Authors: Erik Hallnor 292810Srdreslin@umich.edu * Dave Greene 302810Srdreslin@umich.edu * Steve Reinhardt 312810Srdreslin@umich.edu */ 322810Srdreslin@umich.edu 332810Srdreslin@umich.edu/** 342810Srdreslin@umich.edu * @file 352810Srdreslin@umich.edu * Describes a cache based on template policies. 362810Srdreslin@umich.edu */ 372810Srdreslin@umich.edu 382810Srdreslin@umich.edu#ifndef __CACHE_HH__ 392810Srdreslin@umich.edu#define __CACHE_HH__ 402810Srdreslin@umich.edu 412810Srdreslin@umich.edu#include "base/misc.hh" // fatal, panic, and warn 422810Srdreslin@umich.edu#include "cpu/smt.hh" // SMT_MAX_THREADS 432810Srdreslin@umich.edu 442810Srdreslin@umich.edu#include "mem/cache/base_cache.hh" 453719Sstever@eecs.umich.edu#include "mem/cache/miss/miss_buffer.hh" 462810Srdreslin@umich.edu#include "mem/cache/prefetch/prefetcher.hh" 472810Srdreslin@umich.edu 482813Srdreslin@umich.edu//Forward decleration 492813Srdreslin@umich.educlass MSHR; 502813Srdreslin@umich.edu 512810Srdreslin@umich.edu 522810Srdreslin@umich.edu/** 532810Srdreslin@umich.edu * A template-policy based cache. The behavior of the cache can be altered by 542810Srdreslin@umich.edu * supplying different template policies. TagStore handles all tag and data 552810Srdreslin@umich.edu * storage @sa TagStore. Buffering handles all misses and writes/writebacks 562810Srdreslin@umich.edu * @sa MissQueue. Coherence handles all coherence policy details @sa 572810Srdreslin@umich.edu * UniCoherence, SimpleMultiCoherence. 582810Srdreslin@umich.edu */ 593719Sstever@eecs.umich.edutemplate <class TagStore, class Coherence> 602810Srdreslin@umich.educlass Cache : public BaseCache 612810Srdreslin@umich.edu{ 622810Srdreslin@umich.edu public: 632810Srdreslin@umich.edu /** Define the type of cache block to use. */ 642810Srdreslin@umich.edu typedef typename TagStore::BlkType BlkType; 652810Srdreslin@umich.edu 662810Srdreslin@umich.edu bool prefetchAccess; 672810Srdreslin@umich.edu protected: 682810Srdreslin@umich.edu 692810Srdreslin@umich.edu /** Tag and data Storage */ 702810Srdreslin@umich.edu TagStore *tags; 712810Srdreslin@umich.edu /** Miss and Writeback handler */ 723719Sstever@eecs.umich.edu MissBuffer *missQueue; 732810Srdreslin@umich.edu /** Coherence protocol. */ 742810Srdreslin@umich.edu Coherence *coherence; 752810Srdreslin@umich.edu 762810Srdreslin@umich.edu /** Prefetcher */ 773719Sstever@eecs.umich.edu Prefetcher<TagStore> *prefetcher; 782810Srdreslin@umich.edu 792810Srdreslin@umich.edu /** 802810Srdreslin@umich.edu * The clock ratio of the outgoing bus. 812810Srdreslin@umich.edu * Used for calculating critical word first. 822810Srdreslin@umich.edu */ 832810Srdreslin@umich.edu int busRatio; 842810Srdreslin@umich.edu 852810Srdreslin@umich.edu /** 862810Srdreslin@umich.edu * The bus width in bytes of the outgoing bus. 872810Srdreslin@umich.edu * Used for calculating critical word first. 882810Srdreslin@umich.edu */ 892810Srdreslin@umich.edu int busWidth; 902810Srdreslin@umich.edu 912813Srdreslin@umich.edu /** 922813Srdreslin@umich.edu * The latency of a hit in this device. 932813Srdreslin@umich.edu */ 942813Srdreslin@umich.edu int hitLatency; 952813Srdreslin@umich.edu 962810Srdreslin@umich.edu /** 972810Srdreslin@umich.edu * A permanent mem req to always be used to cause invalidations. 982810Srdreslin@umich.edu * Used to append to target list, to cause an invalidation. 992810Srdreslin@umich.edu */ 1003349Sbinkertn@umich.edu PacketPtr invalidatePkt; 1013208Srdreslin@umich.edu Request *invalidateReq; 1022810Srdreslin@umich.edu 1032810Srdreslin@umich.edu public: 1042810Srdreslin@umich.edu 1052810Srdreslin@umich.edu class Params 1062810Srdreslin@umich.edu { 1072810Srdreslin@umich.edu public: 1082810Srdreslin@umich.edu TagStore *tags; 1093719Sstever@eecs.umich.edu MissBuffer *missQueue; 1102810Srdreslin@umich.edu Coherence *coherence; 1112810Srdreslin@umich.edu BaseCache::Params baseParams; 1123719Sstever@eecs.umich.edu Prefetcher<TagStore> *prefetcher; 1132810Srdreslin@umich.edu bool prefetchAccess; 1142813Srdreslin@umich.edu int hitLatency; 1152810Srdreslin@umich.edu 1163719Sstever@eecs.umich.edu Params(TagStore *_tags, MissBuffer *mq, Coherence *coh, 1173315Sstever@eecs.umich.edu BaseCache::Params params, 1183719Sstever@eecs.umich.edu Prefetcher<TagStore> *_prefetcher, 1192813Srdreslin@umich.edu bool prefetch_access, int hit_latency) 1203315Sstever@eecs.umich.edu : tags(_tags), missQueue(mq), coherence(coh), 1213315Sstever@eecs.umich.edu baseParams(params), 1222813Srdreslin@umich.edu prefetcher(_prefetcher), prefetchAccess(prefetch_access), 1232813Srdreslin@umich.edu hitLatency(hit_latency) 1242810Srdreslin@umich.edu { 1252810Srdreslin@umich.edu } 1262810Srdreslin@umich.edu }; 1272810Srdreslin@umich.edu 1282810Srdreslin@umich.edu /** Instantiates a basic cache object. */ 1292812Srdreslin@umich.edu Cache(const std::string &_name, Params ¶ms); 1302810Srdreslin@umich.edu 1313349Sbinkertn@umich.edu virtual bool doTimingAccess(PacketPtr pkt, CachePort *cachePort, 1322813Srdreslin@umich.edu bool isCpuSide); 1332813Srdreslin@umich.edu 1343349Sbinkertn@umich.edu virtual Tick doAtomicAccess(PacketPtr pkt, bool isCpuSide); 1352813Srdreslin@umich.edu 1363349Sbinkertn@umich.edu virtual void doFunctionalAccess(PacketPtr pkt, bool isCpuSide); 1372813Srdreslin@umich.edu 1382825Srdreslin@umich.edu virtual void recvStatusChange(Port::Status status, bool isCpuSide); 1392813Srdreslin@umich.edu 1402810Srdreslin@umich.edu void regStats(); 1412810Srdreslin@umich.edu 1422810Srdreslin@umich.edu /** 1432810Srdreslin@umich.edu * Performs the access specified by the request. 1442982Sstever@eecs.umich.edu * @param pkt The request to perform. 1452810Srdreslin@umich.edu * @return The result of the access. 1462810Srdreslin@umich.edu */ 1473349Sbinkertn@umich.edu bool access(PacketPtr &pkt); 1482810Srdreslin@umich.edu 1492810Srdreslin@umich.edu /** 1502810Srdreslin@umich.edu * Selects a request to send on the bus. 1512810Srdreslin@umich.edu * @return The memory request to service. 1522810Srdreslin@umich.edu */ 1533349Sbinkertn@umich.edu virtual PacketPtr getPacket(); 1542810Srdreslin@umich.edu 1552810Srdreslin@umich.edu /** 1562810Srdreslin@umich.edu * Was the request was sent successfully? 1572982Sstever@eecs.umich.edu * @param pkt The request. 1582810Srdreslin@umich.edu * @param success True if the request was sent successfully. 1592810Srdreslin@umich.edu */ 1603349Sbinkertn@umich.edu virtual void sendResult(PacketPtr &pkt, MSHR* mshr, bool success); 1612810Srdreslin@umich.edu 1622810Srdreslin@umich.edu /** 1633293Srdreslin@umich.edu * Was the CSHR request was sent successfully? 1643293Srdreslin@umich.edu * @param pkt The request. 1653293Srdreslin@umich.edu * @param success True if the request was sent successfully. 1663293Srdreslin@umich.edu */ 1673349Sbinkertn@umich.edu virtual void sendCoherenceResult(PacketPtr &pkt, MSHR* cshr, bool success); 1683293Srdreslin@umich.edu 1693293Srdreslin@umich.edu /** 1702810Srdreslin@umich.edu * Handles a response (cache line fill/write ack) from the bus. 1712982Sstever@eecs.umich.edu * @param pkt The request being responded to. 1722810Srdreslin@umich.edu */ 1733349Sbinkertn@umich.edu void handleResponse(PacketPtr &pkt); 1742810Srdreslin@umich.edu 1752810Srdreslin@umich.edu /** 1762810Srdreslin@umich.edu * Selects a coherence message to forward to lower levels of the hierarchy. 1772810Srdreslin@umich.edu * @return The coherence message to forward. 1782810Srdreslin@umich.edu */ 1793349Sbinkertn@umich.edu virtual PacketPtr getCoherencePacket(); 1802810Srdreslin@umich.edu 1812810Srdreslin@umich.edu /** 1822810Srdreslin@umich.edu * Snoops bus transactions to maintain coherence. 1832982Sstever@eecs.umich.edu * @param pkt The current bus transaction. 1842810Srdreslin@umich.edu */ 1853349Sbinkertn@umich.edu void snoop(PacketPtr &pkt); 1862810Srdreslin@umich.edu 1873349Sbinkertn@umich.edu void snoopResponse(PacketPtr &pkt); 1882810Srdreslin@umich.edu 1892810Srdreslin@umich.edu /** 1902810Srdreslin@umich.edu * Invalidates the block containing address if found. 1912810Srdreslin@umich.edu * @param addr The address to look for. 1922810Srdreslin@umich.edu * @param asid The address space ID of the address. 1932810Srdreslin@umich.edu * @todo Is this function necessary? 1942810Srdreslin@umich.edu */ 1952991Srdreslin@umich.edu void invalidateBlk(Addr addr); 1962810Srdreslin@umich.edu 1972810Srdreslin@umich.edu /** 1982982Sstever@eecs.umich.edu * Squash all requests associated with specified thread. 1992810Srdreslin@umich.edu * intended for use by I-cache. 2002982Sstever@eecs.umich.edu * @param threadNum The thread to squash. 2012810Srdreslin@umich.edu */ 2022811Srdreslin@umich.edu void squash(int threadNum) 2032810Srdreslin@umich.edu { 2042811Srdreslin@umich.edu missQueue->squash(threadNum); 2052810Srdreslin@umich.edu } 2062810Srdreslin@umich.edu 2072810Srdreslin@umich.edu /** 2082810Srdreslin@umich.edu * Return the number of outstanding misses in a Cache. 2092810Srdreslin@umich.edu * Default returns 0. 2102810Srdreslin@umich.edu * 2112810Srdreslin@umich.edu * @retval unsigned The number of missing still outstanding. 2122810Srdreslin@umich.edu */ 2132810Srdreslin@umich.edu unsigned outstandingMisses() const 2142810Srdreslin@umich.edu { 2152810Srdreslin@umich.edu return missQueue->getMisses(); 2162810Srdreslin@umich.edu } 2172810Srdreslin@umich.edu 2182810Srdreslin@umich.edu /** 2192810Srdreslin@umich.edu * Perform the access specified in the request and return the estimated 2202810Srdreslin@umich.edu * time of completion. This function can either update the hierarchy state 2212810Srdreslin@umich.edu * or just perform the access wherever the data is found depending on the 2222810Srdreslin@umich.edu * state of the update flag. 2232982Sstever@eecs.umich.edu * @param pkt The memory request to satisfy 2242810Srdreslin@umich.edu * @param update If true, update the hierarchy, otherwise just perform the 2252810Srdreslin@umich.edu * request. 2262810Srdreslin@umich.edu * @return The estimated completion time. 2272810Srdreslin@umich.edu */ 2283349Sbinkertn@umich.edu Tick probe(PacketPtr &pkt, bool update, CachePort * otherSidePort); 2292810Srdreslin@umich.edu 2302810Srdreslin@umich.edu /** 2312810Srdreslin@umich.edu * Snoop for the provided request in the cache and return the estimated 2322810Srdreslin@umich.edu * time of completion. 2332810Srdreslin@umich.edu * @todo Can a snoop probe not change state? 2342982Sstever@eecs.umich.edu * @param pkt The memory request to satisfy 2352810Srdreslin@umich.edu * @param update If true, update the hierarchy, otherwise just perform the 2362810Srdreslin@umich.edu * request. 2372810Srdreslin@umich.edu * @return The estimated completion time. 2382810Srdreslin@umich.edu */ 2393349Sbinkertn@umich.edu Tick snoopProbe(PacketPtr &pkt); 2402810Srdreslin@umich.edu}; 2412810Srdreslin@umich.edu 2422810Srdreslin@umich.edu#endif // __CACHE_HH__ 243