cache.hh revision 12724
12810Srdreslin@umich.edu/* 212719Snikos.nikoleris@arm.com * Copyright (c) 2012-2018 ARM Limited 38702Sandreas.hansson@arm.com * All rights reserved. 48702Sandreas.hansson@arm.com * 58702Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68702Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78702Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88702Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98702Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108702Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118702Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128702Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138702Sandreas.hansson@arm.com * 142810Srdreslin@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 152810Srdreslin@umich.edu * All rights reserved. 162810Srdreslin@umich.edu * 172810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 182810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 192810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 202810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 212810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 222810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 232810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 242810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 252810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 262810Srdreslin@umich.edu * this software without specific prior written permission. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810Srdreslin@umich.edu * 402810Srdreslin@umich.edu * Authors: Erik Hallnor 412810Srdreslin@umich.edu * Dave Greene 422810Srdreslin@umich.edu * Steve Reinhardt 434458Sstever@eecs.umich.edu * Ron Dreslinski 448856Sandreas.hansson@arm.com * Andreas Hansson 452810Srdreslin@umich.edu */ 462810Srdreslin@umich.edu 472810Srdreslin@umich.edu/** 482810Srdreslin@umich.edu * @file 4912724Snikos.nikoleris@arm.com * Describes a cache 502810Srdreslin@umich.edu */ 512810Srdreslin@umich.edu 5211051Sandreas.hansson@arm.com#ifndef __MEM_CACHE_CACHE_HH__ 5311051Sandreas.hansson@arm.com#define __MEM_CACHE_CACHE_HH__ 542810Srdreslin@umich.edu 5512724Snikos.nikoleris@arm.com#include <cstdint> 5611859Sandreas.hansson@arm.com#include <unordered_set> 5711859Sandreas.hansson@arm.com 5812724Snikos.nikoleris@arm.com#include "base/types.hh" 595338Sstever@gmail.com#include "mem/cache/base.hh" 6012724Snikos.nikoleris@arm.com#include "mem/packet.hh" 614458Sstever@eecs.umich.edu 6212724Snikos.nikoleris@arm.comclass CacheBlk; 6312724Snikos.nikoleris@arm.comstruct CacheParams; 6412724Snikos.nikoleris@arm.comclass MSHR; 652810Srdreslin@umich.edu 662810Srdreslin@umich.edu/** 6712724Snikos.nikoleris@arm.com * A coherent cache that can be arranged in flexible topologies. 682810Srdreslin@umich.edu */ 692810Srdreslin@umich.educlass Cache : public BaseCache 702810Srdreslin@umich.edu{ 712810Srdreslin@umich.edu protected: 722810Srdreslin@umich.edu /** 735707Shsul@eecs.umich.edu * This cache should allocate a block on a line-sized write miss. 743860Sstever@eecs.umich.edu */ 753860Sstever@eecs.umich.edu const bool doFastWrites; 763860Sstever@eecs.umich.edu 775875Ssteve.reinhardt@amd.com /** 7811276Sandreas.hansson@arm.com * Store the outstanding requests that we are expecting snoop 7911276Sandreas.hansson@arm.com * responses from so we can determine which snoop responses we 8011276Sandreas.hansson@arm.com * generated and which ones were merely forwarded. 8111276Sandreas.hansson@arm.com */ 8211276Sandreas.hansson@arm.com std::unordered_set<RequestPtr> outstandingSnoop; 8311276Sandreas.hansson@arm.com 8412724Snikos.nikoleris@arm.com protected: 8511276Sandreas.hansson@arm.com /** 8612724Snikos.nikoleris@arm.com * Turn line-sized writes into WriteInvalidate transactions. 873860Sstever@eecs.umich.edu */ 8812724Snikos.nikoleris@arm.com void promoteWholeLineWrites(PacketPtr pkt); 894219Srdreslin@umich.edu 9012724Snikos.nikoleris@arm.com bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 9112724Snikos.nikoleris@arm.com PacketList &writebacks) override; 923860Sstever@eecs.umich.edu 9312724Snikos.nikoleris@arm.com void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, 9412724Snikos.nikoleris@arm.com Tick request_time) override; 955350Sstever@gmail.com 9612724Snikos.nikoleris@arm.com void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, 9712724Snikos.nikoleris@arm.com Tick forward_time, 9812724Snikos.nikoleris@arm.com Tick request_time) override; 9911197Sandreas.hansson@arm.com 10012724Snikos.nikoleris@arm.com void recvTimingReq(PacketPtr pkt) override; 10111601Sandreas.hansson@arm.com 10212724Snikos.nikoleris@arm.com void doWritebacks(PacketList& writebacks, Tick forward_time) override; 1033860Sstever@eecs.umich.edu 10412724Snikos.nikoleris@arm.com void doWritebacksAtomic(PacketList& writebacks) override; 1059548Sandreas.hansson@arm.com 10612724Snikos.nikoleris@arm.com void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk, 10712724Snikos.nikoleris@arm.com PacketList& writebacks) override; 10812720Snikos.nikoleris@arm.com 10912724Snikos.nikoleris@arm.com void recvTimingSnoopReq(PacketPtr pkt) override; 11012720Snikos.nikoleris@arm.com 11112724Snikos.nikoleris@arm.com void recvTimingSnoopResp(PacketPtr pkt) override; 1129548Sandreas.hansson@arm.com 11312724Snikos.nikoleris@arm.com Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk, 11412724Snikos.nikoleris@arm.com PacketList &writebacks) override; 11510883Sali.jafri@arm.com 11612724Snikos.nikoleris@arm.com Tick recvAtomic(PacketPtr pkt) override; 11711130Sali.jafri@arm.com 11812724Snikos.nikoleris@arm.com Tick recvAtomicSnoop(PacketPtr pkt) override; 11911375Sandreas.hansson@arm.com 12011601Sandreas.hansson@arm.com void satisfyRequest(PacketPtr pkt, CacheBlk *blk, 12111601Sandreas.hansson@arm.com bool deferred_response = false, 12212724Snikos.nikoleris@arm.com bool pending_downgrade = false) override; 1234626Sstever@eecs.umich.edu 12410563Sandreas.hansson@arm.com void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 1255319Sstever@gmail.com bool already_copied, bool pending_inval); 1263860Sstever@eecs.umich.edu 1273860Sstever@eecs.umich.edu /** 12811127Sandreas.hansson@arm.com * Perform an upward snoop if needed, and update the block state 12911127Sandreas.hansson@arm.com * (possibly invalidating the block). Also create a response if required. 13011127Sandreas.hansson@arm.com * 13111127Sandreas.hansson@arm.com * @param pkt Snoop packet 13211127Sandreas.hansson@arm.com * @param blk Cache block being snooped 13311127Sandreas.hansson@arm.com * @param is_timing Timing or atomic for the response 13411127Sandreas.hansson@arm.com * @param is_deferred Is this a deferred snoop or not? 13511127Sandreas.hansson@arm.com * @param pending_inval Do we have a pending invalidation? 13611127Sandreas.hansson@arm.com * 13711127Sandreas.hansson@arm.com * @return The snoop delay incurred by the upwards snoop 1383860Sstever@eecs.umich.edu */ 13911127Sandreas.hansson@arm.com uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk, 14011127Sandreas.hansson@arm.com bool is_timing, bool is_deferred, bool pending_inval); 1413860Sstever@eecs.umich.edu 14212724Snikos.nikoleris@arm.com M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override; 14312723Snikos.nikoleris@arm.com 14412724Snikos.nikoleris@arm.com void evictBlock(CacheBlk *blk, PacketList &writebacks) override; 14512345Snikos.nikoleris@arm.com 14612345Snikos.nikoleris@arm.com /** 14710883Sali.jafri@arm.com * Create a CleanEvict request for the given block. 14812724Snikos.nikoleris@arm.com * 14910883Sali.jafri@arm.com * @param blk The block to evict. 15010883Sali.jafri@arm.com * @return The CleanEvict request for the block. 15110883Sali.jafri@arm.com */ 15210883Sali.jafri@arm.com PacketPtr cleanEvictBlk(CacheBlk *blk); 15310883Sali.jafri@arm.com 15411452Sandreas.hansson@arm.com PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 15512724Snikos.nikoleris@arm.com bool needsWritable) const override; 1565365Sstever@gmail.com 1575365Sstever@gmail.com /** 15810883Sali.jafri@arm.com * Send up a snoop request and find cached copies. If cached copies are 15910883Sali.jafri@arm.com * found, set the BLOCK_CACHED flag in pkt. 16010883Sali.jafri@arm.com */ 16112724Snikos.nikoleris@arm.com bool isCachedAbove(PacketPtr pkt, bool is_timing = true); 1629529Sandreas.hansson@arm.com 1639529Sandreas.hansson@arm.com public: 1649529Sandreas.hansson@arm.com /** Instantiates a basic cache object. */ 16511053Sandreas.hansson@arm.com Cache(const CacheParams *p); 1669529Sandreas.hansson@arm.com 16711375Sandreas.hansson@arm.com /** 16811375Sandreas.hansson@arm.com * Take an MSHR, turn it into a suitable downstream packet, and 16911375Sandreas.hansson@arm.com * send it out. This construct allows a queue entry to choose a suitable 17011375Sandreas.hansson@arm.com * approach based on its type. 17111375Sandreas.hansson@arm.com * 17211375Sandreas.hansson@arm.com * @param mshr The MSHR to turn into a packet and send 17311375Sandreas.hansson@arm.com * @return True if the port is waiting for a retry 17411375Sandreas.hansson@arm.com */ 17512724Snikos.nikoleris@arm.com bool sendMSHRQueuePacket(MSHR* mshr) override; 17610815Sdavid.guillen@arm.com}; 17710815Sdavid.guillen@arm.com 17811051Sandreas.hansson@arm.com#endif // __MEM_CACHE_CACHE_HH__ 179