cache.hh revision 12334
12810Srdreslin@umich.edu/* 211375Sandreas.hansson@arm.com * Copyright (c) 2012-2016 ARM Limited 38702Sandreas.hansson@arm.com * All rights reserved. 48702Sandreas.hansson@arm.com * 58702Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68702Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78702Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88702Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98702Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108702Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118702Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128702Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138702Sandreas.hansson@arm.com * 142810Srdreslin@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 152810Srdreslin@umich.edu * All rights reserved. 162810Srdreslin@umich.edu * 172810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 182810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 192810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 202810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 212810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 222810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 232810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 242810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 252810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 262810Srdreslin@umich.edu * this software without specific prior written permission. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810Srdreslin@umich.edu * 402810Srdreslin@umich.edu * Authors: Erik Hallnor 412810Srdreslin@umich.edu * Dave Greene 422810Srdreslin@umich.edu * Steve Reinhardt 434458Sstever@eecs.umich.edu * Ron Dreslinski 448856Sandreas.hansson@arm.com * Andreas Hansson 452810Srdreslin@umich.edu */ 462810Srdreslin@umich.edu 472810Srdreslin@umich.edu/** 482810Srdreslin@umich.edu * @file 492810Srdreslin@umich.edu * Describes a cache based on template policies. 502810Srdreslin@umich.edu */ 512810Srdreslin@umich.edu 5211051Sandreas.hansson@arm.com#ifndef __MEM_CACHE_CACHE_HH__ 5311051Sandreas.hansson@arm.com#define __MEM_CACHE_CACHE_HH__ 542810Srdreslin@umich.edu 5511859Sandreas.hansson@arm.com#include <unordered_set> 5611859Sandreas.hansson@arm.com 5712334Sgabeblack@google.com#include "base/logging.hh" // fatal, panic, and warn 5811197Sandreas.hansson@arm.com#include "enums/Clusivity.hh" 595338Sstever@gmail.com#include "mem/cache/base.hh" 605338Sstever@gmail.com#include "mem/cache/blk.hh" 615338Sstever@gmail.com#include "mem/cache/mshr.hh" 6210815Sdavid.guillen@arm.com#include "mem/cache/tags/base.hh" 6311053Sandreas.hansson@arm.com#include "params/Cache.hh" 644458Sstever@eecs.umich.edu#include "sim/eventq.hh" 654458Sstever@eecs.umich.edu 662813Srdreslin@umich.edu//Forward decleration 673861Sstever@eecs.umich.educlass BasePrefetcher; 682810Srdreslin@umich.edu 692810Srdreslin@umich.edu/** 702810Srdreslin@umich.edu * A template-policy based cache. The behavior of the cache can be altered by 712810Srdreslin@umich.edu * supplying different template policies. TagStore handles all tag and data 729264Sdjordje.kovacevic@arm.com * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System" 732810Srdreslin@umich.edu */ 742810Srdreslin@umich.educlass Cache : public BaseCache 752810Srdreslin@umich.edu{ 762810Srdreslin@umich.edu protected: 772810Srdreslin@umich.edu 788856Sandreas.hansson@arm.com /** 798856Sandreas.hansson@arm.com * The CPU-side port extends the base cache slave port with access 808856Sandreas.hansson@arm.com * functions for functional, atomic and timing requests. 818856Sandreas.hansson@arm.com */ 828856Sandreas.hansson@arm.com class CpuSidePort : public CacheSlavePort 833738Sstever@eecs.umich.edu { 848856Sandreas.hansson@arm.com private: 853738Sstever@eecs.umich.edu 868856Sandreas.hansson@arm.com // a pointer to our specific cache implementation 8710815Sdavid.guillen@arm.com Cache *cache; 883738Sstever@eecs.umich.edu 898856Sandreas.hansson@arm.com protected: 904478Sstever@eecs.umich.edu 918975Sandreas.hansson@arm.com virtual bool recvTimingSnoopResp(PacketPtr pkt); 928948Sandreas.hansson@arm.com 938975Sandreas.hansson@arm.com virtual bool recvTimingReq(PacketPtr pkt); 943738Sstever@eecs.umich.edu 953738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 963738Sstever@eecs.umich.edu 973738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 988856Sandreas.hansson@arm.com 999090Sandreas.hansson@arm.com virtual AddrRangeList getAddrRanges() const; 1008856Sandreas.hansson@arm.com 1018856Sandreas.hansson@arm.com public: 1028856Sandreas.hansson@arm.com 10310815Sdavid.guillen@arm.com CpuSidePort(const std::string &_name, Cache *_cache, 1048856Sandreas.hansson@arm.com const std::string &_label); 1058856Sandreas.hansson@arm.com 1063738Sstever@eecs.umich.edu }; 1073738Sstever@eecs.umich.edu 1088856Sandreas.hansson@arm.com /** 1098914Sandreas.hansson@arm.com * Override the default behaviour of sendDeferredPacket to enable 1108914Sandreas.hansson@arm.com * the memory-side cache port to also send requests based on the 1118914Sandreas.hansson@arm.com * current MSHR status. This queue has a pointer to our specific 1128914Sandreas.hansson@arm.com * cache implementation and is used by the MemSidePort. 1138914Sandreas.hansson@arm.com */ 11410713Sandreas.hansson@arm.com class CacheReqPacketQueue : public ReqPacketQueue 1158914Sandreas.hansson@arm.com { 1168914Sandreas.hansson@arm.com 1178914Sandreas.hansson@arm.com protected: 1188914Sandreas.hansson@arm.com 11910815Sdavid.guillen@arm.com Cache &cache; 12010713Sandreas.hansson@arm.com SnoopRespPacketQueue &snoopRespQueue; 1218914Sandreas.hansson@arm.com 1228914Sandreas.hansson@arm.com public: 1238914Sandreas.hansson@arm.com 12410815Sdavid.guillen@arm.com CacheReqPacketQueue(Cache &cache, MasterPort &port, 12510713Sandreas.hansson@arm.com SnoopRespPacketQueue &snoop_resp_queue, 12610713Sandreas.hansson@arm.com const std::string &label) : 12710713Sandreas.hansson@arm.com ReqPacketQueue(cache, port, label), cache(cache), 12810713Sandreas.hansson@arm.com snoopRespQueue(snoop_resp_queue) { } 1298914Sandreas.hansson@arm.com 1308914Sandreas.hansson@arm.com /** 1318914Sandreas.hansson@arm.com * Override the normal sendDeferredPacket and do not only 1328914Sandreas.hansson@arm.com * consider the transmit list (used for responses), but also 1338914Sandreas.hansson@arm.com * requests. 1348914Sandreas.hansson@arm.com */ 1358914Sandreas.hansson@arm.com virtual void sendDeferredPacket(); 1368914Sandreas.hansson@arm.com 13711375Sandreas.hansson@arm.com /** 13811375Sandreas.hansson@arm.com * Check if there is a conflicting snoop response about to be 13911375Sandreas.hansson@arm.com * send out, and if so simply stall any requests, and schedule 14011375Sandreas.hansson@arm.com * a send event at the same time as the next snoop response is 14111375Sandreas.hansson@arm.com * being sent out. 14211375Sandreas.hansson@arm.com */ 14311375Sandreas.hansson@arm.com bool checkConflictingSnoop(Addr addr) 14411375Sandreas.hansson@arm.com { 14511375Sandreas.hansson@arm.com if (snoopRespQueue.hasAddr(addr)) { 14611375Sandreas.hansson@arm.com DPRINTF(CachePort, "Waiting for snoop response to be " 14711375Sandreas.hansson@arm.com "sent\n"); 14811375Sandreas.hansson@arm.com Tick when = snoopRespQueue.deferredPacketReadyTime(); 14911375Sandreas.hansson@arm.com schedSendEvent(when); 15011375Sandreas.hansson@arm.com return true; 15111375Sandreas.hansson@arm.com } 15211375Sandreas.hansson@arm.com return false; 15311375Sandreas.hansson@arm.com } 1548914Sandreas.hansson@arm.com }; 1558914Sandreas.hansson@arm.com 1568914Sandreas.hansson@arm.com /** 1578856Sandreas.hansson@arm.com * The memory-side port extends the base cache master port with 1588856Sandreas.hansson@arm.com * access functions for functional, atomic and timing snoops. 1598856Sandreas.hansson@arm.com */ 1608856Sandreas.hansson@arm.com class MemSidePort : public CacheMasterPort 1613738Sstever@eecs.umich.edu { 1628856Sandreas.hansson@arm.com private: 1633738Sstever@eecs.umich.edu 1648914Sandreas.hansson@arm.com /** The cache-specific queue. */ 16510713Sandreas.hansson@arm.com CacheReqPacketQueue _reqQueue; 16610713Sandreas.hansson@arm.com 16710713Sandreas.hansson@arm.com SnoopRespPacketQueue _snoopRespQueue; 1688914Sandreas.hansson@arm.com 1698856Sandreas.hansson@arm.com // a pointer to our specific cache implementation 17010815Sdavid.guillen@arm.com Cache *cache; 1713738Sstever@eecs.umich.edu 1728856Sandreas.hansson@arm.com protected: 1734478Sstever@eecs.umich.edu 1748975Sandreas.hansson@arm.com virtual void recvTimingSnoopReq(PacketPtr pkt); 1758948Sandreas.hansson@arm.com 1768975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 1773738Sstever@eecs.umich.edu 1788948Sandreas.hansson@arm.com virtual Tick recvAtomicSnoop(PacketPtr pkt); 1793738Sstever@eecs.umich.edu 1808948Sandreas.hansson@arm.com virtual void recvFunctionalSnoop(PacketPtr pkt); 1814458Sstever@eecs.umich.edu 1828856Sandreas.hansson@arm.com public: 1838856Sandreas.hansson@arm.com 18410815Sdavid.guillen@arm.com MemSidePort(const std::string &_name, Cache *_cache, 1858856Sandreas.hansson@arm.com const std::string &_label); 1863738Sstever@eecs.umich.edu }; 1873738Sstever@eecs.umich.edu 1882810Srdreslin@umich.edu /** Tag and data Storage */ 18910815Sdavid.guillen@arm.com BaseTags *tags; 1904626Sstever@eecs.umich.edu 1912810Srdreslin@umich.edu /** Prefetcher */ 1923861Sstever@eecs.umich.edu BasePrefetcher *prefetcher; 1932810Srdreslin@umich.edu 1944671Sstever@eecs.umich.edu /** Temporary cache block for occasional transitory use */ 19510815Sdavid.guillen@arm.com CacheBlk *tempBlock; 1964671Sstever@eecs.umich.edu 1972810Srdreslin@umich.edu /** 1985707Shsul@eecs.umich.edu * This cache should allocate a block on a line-sized write miss. 1993860Sstever@eecs.umich.edu */ 2003860Sstever@eecs.umich.edu const bool doFastWrites; 2013860Sstever@eecs.umich.edu 2025875Ssteve.reinhardt@amd.com /** 20310345SCurtis.Dunham@arm.com * Turn line-sized writes into WriteInvalidate transactions. 20410345SCurtis.Dunham@arm.com */ 20510345SCurtis.Dunham@arm.com void promoteWholeLineWrites(PacketPtr pkt); 20610345SCurtis.Dunham@arm.com 20710345SCurtis.Dunham@arm.com /** 2085875Ssteve.reinhardt@amd.com * Notify the prefetcher on every access, not just misses. 2095875Ssteve.reinhardt@amd.com */ 2105875Ssteve.reinhardt@amd.com const bool prefetchOnAccess; 2113860Sstever@eecs.umich.edu 21211197Sandreas.hansson@arm.com /** 21311197Sandreas.hansson@arm.com * Clusivity with respect to the upstream cache, determining if we 21411197Sandreas.hansson@arm.com * fill into both this cache and the cache above on a miss. Note 21511197Sandreas.hansson@arm.com * that we currently do not support strict clusivity policies. 21611197Sandreas.hansson@arm.com */ 21711197Sandreas.hansson@arm.com const Enums::Clusivity clusivity; 21811197Sandreas.hansson@arm.com 21911199Sandreas.hansson@arm.com /** 22011199Sandreas.hansson@arm.com * Determine if clean lines should be written back or not. In 22111199Sandreas.hansson@arm.com * cases where a downstream cache is mostly inclusive we likely 22211199Sandreas.hansson@arm.com * want it to act as a victim cache also for lines that have not 22311199Sandreas.hansson@arm.com * been modified. Hence, we cannot simply drop the line (or send a 22411199Sandreas.hansson@arm.com * clean evict), but rather need to send the actual data. 22511199Sandreas.hansson@arm.com */ 22611199Sandreas.hansson@arm.com const bool writebackClean; 22711199Sandreas.hansson@arm.com 2283860Sstever@eecs.umich.edu /** 22911190Sandreas.hansson@arm.com * Upstream caches need this packet until true is returned, so 23011190Sandreas.hansson@arm.com * hold it for deletion until a subsequent call 2319063SAli.Saidi@ARM.com */ 23211190Sandreas.hansson@arm.com std::unique_ptr<Packet> pendingDelete; 2339063SAli.Saidi@ARM.com 2349063SAli.Saidi@ARM.com /** 23511197Sandreas.hansson@arm.com * Writebacks from the tempBlock, resulting on the response path 23611197Sandreas.hansson@arm.com * in atomic mode, must happen after the call to recvAtomic has 23711197Sandreas.hansson@arm.com * finished (for the right ordering of the packets). We therefore 23811197Sandreas.hansson@arm.com * need to hold on to the packets, and have a method and an event 23911197Sandreas.hansson@arm.com * to send them. 24011197Sandreas.hansson@arm.com */ 24111197Sandreas.hansson@arm.com PacketPtr tempBlockWriteback; 24211197Sandreas.hansson@arm.com 24311197Sandreas.hansson@arm.com /** 24411197Sandreas.hansson@arm.com * Send the outstanding tempBlock writeback. To be called after 24511197Sandreas.hansson@arm.com * recvAtomic finishes in cases where the block we filled is in 24611197Sandreas.hansson@arm.com * fact the tempBlock, and now needs to be written back. 24711197Sandreas.hansson@arm.com */ 24811197Sandreas.hansson@arm.com void writebackTempBlockAtomic() { 24911197Sandreas.hansson@arm.com assert(tempBlockWriteback != nullptr); 25011197Sandreas.hansson@arm.com PacketList writebacks{tempBlockWriteback}; 25111197Sandreas.hansson@arm.com doWritebacksAtomic(writebacks); 25211197Sandreas.hansson@arm.com tempBlockWriteback = nullptr; 25311197Sandreas.hansson@arm.com } 25411197Sandreas.hansson@arm.com 25511197Sandreas.hansson@arm.com /** 25611197Sandreas.hansson@arm.com * An event to writeback the tempBlock after recvAtomic 25711197Sandreas.hansson@arm.com * finishes. To avoid other calls to recvAtomic getting in 25811197Sandreas.hansson@arm.com * between, we create this event with a higher priority. 25911197Sandreas.hansson@arm.com */ 26012084Sspwilson2@wisc.edu EventFunctionWrapper writebackTempBlockAtomicEvent; 26111197Sandreas.hansson@arm.com 26211197Sandreas.hansson@arm.com /** 26311276Sandreas.hansson@arm.com * Store the outstanding requests that we are expecting snoop 26411276Sandreas.hansson@arm.com * responses from so we can determine which snoop responses we 26511276Sandreas.hansson@arm.com * generated and which ones were merely forwarded. 26611276Sandreas.hansson@arm.com */ 26711276Sandreas.hansson@arm.com std::unordered_set<RequestPtr> outstandingSnoop; 26811276Sandreas.hansson@arm.com 26911276Sandreas.hansson@arm.com /** 2703860Sstever@eecs.umich.edu * Does all the processing necessary to perform the provided request. 2713860Sstever@eecs.umich.edu * @param pkt The memory request to perform. 27210048Saminfar@gmail.com * @param blk The cache block to be updated. 2733860Sstever@eecs.umich.edu * @param lat The latency of the access. 2743860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 2755707Shsul@eecs.umich.edu * @return Boolean indicating whether the request was satisfied. 2763860Sstever@eecs.umich.edu */ 27710815Sdavid.guillen@arm.com bool access(PacketPtr pkt, CacheBlk *&blk, 2789288Sandreas.hansson@arm.com Cycles &lat, PacketList &writebacks); 2794219Srdreslin@umich.edu 2804219Srdreslin@umich.edu /** 2814219Srdreslin@umich.edu *Handle doing the Compare and Swap function for SPARC. 2824219Srdreslin@umich.edu */ 28310815Sdavid.guillen@arm.com void cmpAndSwap(CacheBlk *blk, PacketPtr pkt); 2843860Sstever@eecs.umich.edu 2853860Sstever@eecs.umich.edu /** 28610028SGiacomo.Gabrielli@arm.com * Find a block frame for new block at address addr targeting the 28710028SGiacomo.Gabrielli@arm.com * given security space, assuming that the block is not currently 28810028SGiacomo.Gabrielli@arm.com * in the cache. Append writebacks if any to provided packet 28911484Snikos.nikoleris@arm.com * list. Return free block frame. May return nullptr if there are 29010028SGiacomo.Gabrielli@arm.com * no replaceable blocks at the moment. 2915350Sstever@gmail.com */ 29210815Sdavid.guillen@arm.com CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks); 2935350Sstever@gmail.com 2945350Sstever@gmail.com /** 29511197Sandreas.hansson@arm.com * Invalidate a cache block. 29611197Sandreas.hansson@arm.com * 29711197Sandreas.hansson@arm.com * @param blk Block to invalidate 29811197Sandreas.hansson@arm.com */ 29911197Sandreas.hansson@arm.com void invalidateBlock(CacheBlk *blk); 30011197Sandreas.hansson@arm.com 30111197Sandreas.hansson@arm.com /** 30211601Sandreas.hansson@arm.com * Maintain the clusivity of this cache by potentially 30311601Sandreas.hansson@arm.com * invalidating a block. This method works in conjunction with 30411601Sandreas.hansson@arm.com * satisfyRequest, but is separate to allow us to handle all MSHR 30511601Sandreas.hansson@arm.com * targets before potentially dropping a block. 30611601Sandreas.hansson@arm.com * 30711601Sandreas.hansson@arm.com * @param from_cache Whether we have dealt with a packet from a cache 30811601Sandreas.hansson@arm.com * @param blk The block that should potentially be dropped 30911601Sandreas.hansson@arm.com */ 31011601Sandreas.hansson@arm.com void maintainClusivity(bool from_cache, CacheBlk *blk); 31111601Sandreas.hansson@arm.com 31211601Sandreas.hansson@arm.com /** 3133860Sstever@eecs.umich.edu * Populates a cache block and handles all outstanding requests for the 3143860Sstever@eecs.umich.edu * satisfied fill request. This version takes two memory requests. One 3153860Sstever@eecs.umich.edu * contains the fill data, the other is an optional target to satisfy. 3164626Sstever@eecs.umich.edu * @param pkt The memory request with the fill data. 3173860Sstever@eecs.umich.edu * @param blk The cache block if it already exists. 3183860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 31911197Sandreas.hansson@arm.com * @param allocate Whether to allocate a block or use the temp block 3203860Sstever@eecs.umich.edu * @return Pointer to the new cache block. 3213860Sstever@eecs.umich.edu */ 32210815Sdavid.guillen@arm.com CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk, 32311197Sandreas.hansson@arm.com PacketList &writebacks, bool allocate); 3243860Sstever@eecs.umich.edu 32511197Sandreas.hansson@arm.com /** 32611197Sandreas.hansson@arm.com * Determine whether we should allocate on a fill or not. If this 32711197Sandreas.hansson@arm.com * cache is mostly inclusive with regards to the upstream cache(s) 32811197Sandreas.hansson@arm.com * we always allocate (for any non-forwarded and cacheable 32911197Sandreas.hansson@arm.com * requests). In the case of a mostly exclusive cache, we allocate 33011197Sandreas.hansson@arm.com * on fill if the packet did not come from a cache, thus if we: 33111197Sandreas.hansson@arm.com * are dealing with a whole-line write (the latter behaves much 33211197Sandreas.hansson@arm.com * like a writeback), the original target packet came from a 33311197Sandreas.hansson@arm.com * non-caching source, or if we are performing a prefetch or LLSC. 33411197Sandreas.hansson@arm.com * 33511197Sandreas.hansson@arm.com * @param cmd Command of the incoming requesting packet 33611197Sandreas.hansson@arm.com * @return Whether we should allocate on the fill 33711197Sandreas.hansson@arm.com */ 33811211Sandreas.sandberg@arm.com inline bool allocOnFill(MemCmd cmd) const override 33911197Sandreas.hansson@arm.com { 34011197Sandreas.hansson@arm.com return clusivity == Enums::mostly_incl || 34111197Sandreas.hansson@arm.com cmd == MemCmd::WriteLineReq || 34211197Sandreas.hansson@arm.com cmd == MemCmd::ReadReq || 34311197Sandreas.hansson@arm.com cmd == MemCmd::WriteReq || 34411197Sandreas.hansson@arm.com cmd.isPrefetch() || 34511197Sandreas.hansson@arm.com cmd.isLLSC(); 34611197Sandreas.hansson@arm.com } 3479548Sandreas.hansson@arm.com 3489548Sandreas.hansson@arm.com /** 3499548Sandreas.hansson@arm.com * Performs the access specified by the request. 3509548Sandreas.hansson@arm.com * @param pkt The request to perform. 3519548Sandreas.hansson@arm.com * @return The result of the access. 3529548Sandreas.hansson@arm.com */ 3539548Sandreas.hansson@arm.com bool recvTimingReq(PacketPtr pkt); 3549548Sandreas.hansson@arm.com 3559548Sandreas.hansson@arm.com /** 35610883Sali.jafri@arm.com * Insert writebacks into the write buffer 35710883Sali.jafri@arm.com */ 35810883Sali.jafri@arm.com void doWritebacks(PacketList& writebacks, Tick forward_time); 35910883Sali.jafri@arm.com 36010883Sali.jafri@arm.com /** 36111130Sali.jafri@arm.com * Send writebacks down the memory hierarchy in atomic mode 36211130Sali.jafri@arm.com */ 36311130Sali.jafri@arm.com void doWritebacksAtomic(PacketList& writebacks); 36411130Sali.jafri@arm.com 36511130Sali.jafri@arm.com /** 36611375Sandreas.hansson@arm.com * Handling the special case of uncacheable write responses to 36711375Sandreas.hansson@arm.com * make recvTimingResp less cluttered. 36811375Sandreas.hansson@arm.com */ 36911375Sandreas.hansson@arm.com void handleUncacheableWriteResp(PacketPtr pkt); 37011375Sandreas.hansson@arm.com 37111375Sandreas.hansson@arm.com /** 3729548Sandreas.hansson@arm.com * Handles a response (cache line fill/write ack) from the bus. 3739548Sandreas.hansson@arm.com * @param pkt The response packet 3749548Sandreas.hansson@arm.com */ 3759548Sandreas.hansson@arm.com void recvTimingResp(PacketPtr pkt); 3769548Sandreas.hansson@arm.com 3779548Sandreas.hansson@arm.com /** 3789548Sandreas.hansson@arm.com * Snoops bus transactions to maintain coherence. 3799548Sandreas.hansson@arm.com * @param pkt The current bus transaction. 3809548Sandreas.hansson@arm.com */ 3819548Sandreas.hansson@arm.com void recvTimingSnoopReq(PacketPtr pkt); 3829548Sandreas.hansson@arm.com 3839548Sandreas.hansson@arm.com /** 3849548Sandreas.hansson@arm.com * Handle a snoop response. 3859548Sandreas.hansson@arm.com * @param pkt Snoop response packet 3869548Sandreas.hansson@arm.com */ 3879548Sandreas.hansson@arm.com void recvTimingSnoopResp(PacketPtr pkt); 3889548Sandreas.hansson@arm.com 3899548Sandreas.hansson@arm.com /** 3909548Sandreas.hansson@arm.com * Performs the access specified by the request. 3919548Sandreas.hansson@arm.com * @param pkt The request to perform. 3929782Sandreas.hansson@arm.com * @return The number of ticks required for the access. 3939548Sandreas.hansson@arm.com */ 3949782Sandreas.hansson@arm.com Tick recvAtomic(PacketPtr pkt); 3959548Sandreas.hansson@arm.com 3969548Sandreas.hansson@arm.com /** 3979548Sandreas.hansson@arm.com * Snoop for the provided request in the cache and return the estimated 3989782Sandreas.hansson@arm.com * time taken. 3999548Sandreas.hansson@arm.com * @param pkt The memory request to snoop 4009782Sandreas.hansson@arm.com * @return The number of ticks required for the snoop. 4019548Sandreas.hansson@arm.com */ 4029782Sandreas.hansson@arm.com Tick recvAtomicSnoop(PacketPtr pkt); 4039548Sandreas.hansson@arm.com 4049548Sandreas.hansson@arm.com /** 4059548Sandreas.hansson@arm.com * Performs the access specified by the request. 4069548Sandreas.hansson@arm.com * @param pkt The request to perform. 4079548Sandreas.hansson@arm.com * @param fromCpuSide from the CPU side port or the memory side port 4089548Sandreas.hansson@arm.com */ 4099548Sandreas.hansson@arm.com void functionalAccess(PacketPtr pkt, bool fromCpuSide); 4109548Sandreas.hansson@arm.com 41111601Sandreas.hansson@arm.com /** 41211601Sandreas.hansson@arm.com * Perform any necessary updates to the block and perform any data 41311601Sandreas.hansson@arm.com * exchange between the packet and the block. The flags of the 41411601Sandreas.hansson@arm.com * packet are also set accordingly. 41511601Sandreas.hansson@arm.com * 41611601Sandreas.hansson@arm.com * @param pkt Request packet from upstream that hit a block 41711601Sandreas.hansson@arm.com * @param blk Cache block that the packet hit 41811601Sandreas.hansson@arm.com * @param deferred_response Whether this hit is to block that 41911601Sandreas.hansson@arm.com * originally missed 42011601Sandreas.hansson@arm.com * @param pending_downgrade Whether the writable flag is to be removed 42111601Sandreas.hansson@arm.com * 42211601Sandreas.hansson@arm.com * @return True if the block is to be invalidated 42311601Sandreas.hansson@arm.com */ 42411601Sandreas.hansson@arm.com void satisfyRequest(PacketPtr pkt, CacheBlk *blk, 42511601Sandreas.hansson@arm.com bool deferred_response = false, 42611601Sandreas.hansson@arm.com bool pending_downgrade = false); 4274626Sstever@eecs.umich.edu 42810563Sandreas.hansson@arm.com void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 4295319Sstever@gmail.com bool already_copied, bool pending_inval); 4303860Sstever@eecs.umich.edu 4313860Sstever@eecs.umich.edu /** 43211127Sandreas.hansson@arm.com * Perform an upward snoop if needed, and update the block state 43311127Sandreas.hansson@arm.com * (possibly invalidating the block). Also create a response if required. 43411127Sandreas.hansson@arm.com * 43511127Sandreas.hansson@arm.com * @param pkt Snoop packet 43611127Sandreas.hansson@arm.com * @param blk Cache block being snooped 43711127Sandreas.hansson@arm.com * @param is_timing Timing or atomic for the response 43811127Sandreas.hansson@arm.com * @param is_deferred Is this a deferred snoop or not? 43911127Sandreas.hansson@arm.com * @param pending_inval Do we have a pending invalidation? 44011127Sandreas.hansson@arm.com * 44111127Sandreas.hansson@arm.com * @return The snoop delay incurred by the upwards snoop 4423860Sstever@eecs.umich.edu */ 44311127Sandreas.hansson@arm.com uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk, 44411127Sandreas.hansson@arm.com bool is_timing, bool is_deferred, bool pending_inval); 4453860Sstever@eecs.umich.edu 4463860Sstever@eecs.umich.edu /** 4473860Sstever@eecs.umich.edu * Create a writeback request for the given block. 4483860Sstever@eecs.umich.edu * @param blk The block to writeback. 4493860Sstever@eecs.umich.edu * @return The writeback request for the block. 4503860Sstever@eecs.umich.edu */ 45110815Sdavid.guillen@arm.com PacketPtr writebackBlk(CacheBlk *blk); 4523860Sstever@eecs.umich.edu 45310883Sali.jafri@arm.com /** 45410883Sali.jafri@arm.com * Create a CleanEvict request for the given block. 45510883Sali.jafri@arm.com * @param blk The block to evict. 45610883Sali.jafri@arm.com * @return The CleanEvict request for the block. 45710883Sali.jafri@arm.com */ 45810883Sali.jafri@arm.com PacketPtr cleanEvictBlk(CacheBlk *blk); 45910883Sali.jafri@arm.com 4609347SAndreas.Sandberg@arm.com 46111169Sandreas.hansson@arm.com void memWriteback() override; 46211169Sandreas.hansson@arm.com void memInvalidate() override; 46311169Sandreas.hansson@arm.com bool isDirty() const override; 4649347SAndreas.Sandberg@arm.com 4659347SAndreas.Sandberg@arm.com /** 4669347SAndreas.Sandberg@arm.com * Cache block visitor that writes back dirty cache blocks using 4679347SAndreas.Sandberg@arm.com * functional writes. 4689347SAndreas.Sandberg@arm.com * 4699347SAndreas.Sandberg@arm.com * \return Always returns true. 4709347SAndreas.Sandberg@arm.com */ 47110815Sdavid.guillen@arm.com bool writebackVisitor(CacheBlk &blk); 4729347SAndreas.Sandberg@arm.com /** 4739347SAndreas.Sandberg@arm.com * Cache block visitor that invalidates all blocks in the cache. 4749347SAndreas.Sandberg@arm.com * 4759347SAndreas.Sandberg@arm.com * @warn Dirty cache lines will not be written back to memory. 4769347SAndreas.Sandberg@arm.com * 4779347SAndreas.Sandberg@arm.com * \return Always returns true. 4789347SAndreas.Sandberg@arm.com */ 47910815Sdavid.guillen@arm.com bool invalidateVisitor(CacheBlk &blk); 4809347SAndreas.Sandberg@arm.com 4819445SAndreas.Sandberg@ARM.com /** 48211452Sandreas.hansson@arm.com * Create an appropriate downstream bus request packet for the 4835365Sstever@gmail.com * given parameters. 48411452Sandreas.hansson@arm.com * @param cpu_pkt The miss that needs to be satisfied. 4855365Sstever@gmail.com * @param blk The block currently in the cache corresponding to 48611484Snikos.nikoleris@arm.com * cpu_pkt (nullptr if none). 48711452Sandreas.hansson@arm.com * @param needsWritable Indicates that the block must be writable 4885365Sstever@gmail.com * even if the request in cpu_pkt doesn't indicate that. 48911484Snikos.nikoleris@arm.com * @return A new Packet containing the request, or nullptr if the 4905365Sstever@gmail.com * current request in cpu_pkt should just be forwarded on. 4914626Sstever@eecs.umich.edu */ 49211452Sandreas.hansson@arm.com PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 49311452Sandreas.hansson@arm.com bool needsWritable) const; 4945365Sstever@gmail.com 4955365Sstever@gmail.com /** 49611375Sandreas.hansson@arm.com * Return the next queue entry to service, either a pending miss 49711375Sandreas.hansson@arm.com * from the MSHR queue, a buffered write from the write buffer, or 49811375Sandreas.hansson@arm.com * something from the prefetcher. This function is responsible 49911375Sandreas.hansson@arm.com * for prioritizing among those sources on the fly. 5005365Sstever@gmail.com */ 50111375Sandreas.hansson@arm.com QueueEntry* getNextQueueEntry(); 5025365Sstever@gmail.com 5035365Sstever@gmail.com /** 50410883Sali.jafri@arm.com * Send up a snoop request and find cached copies. If cached copies are 50510883Sali.jafri@arm.com * found, set the BLOCK_CACHED flag in pkt. 50610883Sali.jafri@arm.com */ 50711130Sali.jafri@arm.com bool isCachedAbove(PacketPtr pkt, bool is_timing = true) const; 50810883Sali.jafri@arm.com 50910883Sali.jafri@arm.com /** 5104626Sstever@eecs.umich.edu * Return whether there are any outstanding misses. 5114626Sstever@eecs.umich.edu */ 5124626Sstever@eecs.umich.edu bool outstandingMisses() const 5132810Srdreslin@umich.edu { 51411375Sandreas.hansson@arm.com return !mshrQueue.isEmpty(); 5152810Srdreslin@umich.edu } 5162810Srdreslin@umich.edu 51710028SGiacomo.Gabrielli@arm.com CacheBlk *findBlock(Addr addr, bool is_secure) const { 51810028SGiacomo.Gabrielli@arm.com return tags->findBlock(addr, is_secure); 5192810Srdreslin@umich.edu } 5202810Srdreslin@umich.edu 52111169Sandreas.hansson@arm.com bool inCache(Addr addr, bool is_secure) const override { 52210028SGiacomo.Gabrielli@arm.com return (tags->findBlock(addr, is_secure) != 0); 5233861Sstever@eecs.umich.edu } 5243861Sstever@eecs.umich.edu 52511169Sandreas.hansson@arm.com bool inMissQueue(Addr addr, bool is_secure) const override { 52610028SGiacomo.Gabrielli@arm.com return (mshrQueue.findMatch(addr, is_secure) != 0); 5273861Sstever@eecs.umich.edu } 5285875Ssteve.reinhardt@amd.com 5295875Ssteve.reinhardt@amd.com /** 5305875Ssteve.reinhardt@amd.com * Find next request ready time from among possible sources. 5315875Ssteve.reinhardt@amd.com */ 53211375Sandreas.hansson@arm.com Tick nextQueueReadyTime() const; 5339529Sandreas.hansson@arm.com 5349529Sandreas.hansson@arm.com public: 5359529Sandreas.hansson@arm.com /** Instantiates a basic cache object. */ 53611053Sandreas.hansson@arm.com Cache(const CacheParams *p); 5379529Sandreas.hansson@arm.com 5389813Srioshering@gmail.com /** Non-default destructor is needed to deallocate memory. */ 5399813Srioshering@gmail.com virtual ~Cache(); 5409813Srioshering@gmail.com 54111169Sandreas.hansson@arm.com void regStats() override; 5428985SAli.Saidi@ARM.com 54311375Sandreas.hansson@arm.com /** 54411375Sandreas.hansson@arm.com * Take an MSHR, turn it into a suitable downstream packet, and 54511375Sandreas.hansson@arm.com * send it out. This construct allows a queue entry to choose a suitable 54611375Sandreas.hansson@arm.com * approach based on its type. 54711375Sandreas.hansson@arm.com * 54811375Sandreas.hansson@arm.com * @param mshr The MSHR to turn into a packet and send 54911375Sandreas.hansson@arm.com * @return True if the port is waiting for a retry 55011375Sandreas.hansson@arm.com */ 55111375Sandreas.hansson@arm.com bool sendMSHRQueuePacket(MSHR* mshr); 55211375Sandreas.hansson@arm.com 55311375Sandreas.hansson@arm.com /** 55411375Sandreas.hansson@arm.com * Similar to sendMSHR, but for a write-queue entry 55511375Sandreas.hansson@arm.com * instead. Create the packet, and send it, and if successful also 55611375Sandreas.hansson@arm.com * mark the entry in service. 55711375Sandreas.hansson@arm.com * 55811375Sandreas.hansson@arm.com * @param wq_entry The write-queue entry to turn into a packet and send 55911375Sandreas.hansson@arm.com * @return True if the port is waiting for a retry 56011375Sandreas.hansson@arm.com */ 56111375Sandreas.hansson@arm.com bool sendWriteQueuePacket(WriteQueueEntry* wq_entry); 56211375Sandreas.hansson@arm.com 5638985SAli.Saidi@ARM.com /** serialize the state of the caches 5648985SAli.Saidi@ARM.com * We currently don't support checkpointing cache state, so this panics. 5658985SAli.Saidi@ARM.com */ 56611168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 56711168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 5682810Srdreslin@umich.edu}; 5692810Srdreslin@umich.edu 57010815Sdavid.guillen@arm.com/** 57110815Sdavid.guillen@arm.com * Wrap a method and present it as a cache block visitor. 57210815Sdavid.guillen@arm.com * 57310815Sdavid.guillen@arm.com * For example the forEachBlk method in the tag arrays expects a 57410815Sdavid.guillen@arm.com * callable object/function as their parameter. This class wraps a 57510815Sdavid.guillen@arm.com * method in an object and presents callable object that adheres to 57610815Sdavid.guillen@arm.com * the cache block visitor protocol. 57710815Sdavid.guillen@arm.com */ 57810815Sdavid.guillen@arm.comclass CacheBlkVisitorWrapper : public CacheBlkVisitor 57910815Sdavid.guillen@arm.com{ 58010815Sdavid.guillen@arm.com public: 58110815Sdavid.guillen@arm.com typedef bool (Cache::*VisitorPtr)(CacheBlk &blk); 58210815Sdavid.guillen@arm.com 58310815Sdavid.guillen@arm.com CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor) 58410815Sdavid.guillen@arm.com : cache(_cache), visitor(_visitor) {} 58510815Sdavid.guillen@arm.com 58611168Sandreas.hansson@arm.com bool operator()(CacheBlk &blk) override { 58710815Sdavid.guillen@arm.com return (cache.*visitor)(blk); 58810815Sdavid.guillen@arm.com } 58910815Sdavid.guillen@arm.com 59010815Sdavid.guillen@arm.com private: 59110815Sdavid.guillen@arm.com Cache &cache; 59210815Sdavid.guillen@arm.com VisitorPtr visitor; 59310815Sdavid.guillen@arm.com}; 59410815Sdavid.guillen@arm.com 59510815Sdavid.guillen@arm.com/** 59610815Sdavid.guillen@arm.com * Cache block visitor that determines if there are dirty blocks in a 59710815Sdavid.guillen@arm.com * cache. 59810815Sdavid.guillen@arm.com * 59910815Sdavid.guillen@arm.com * Use with the forEachBlk method in the tag array to determine if the 60010815Sdavid.guillen@arm.com * array contains dirty blocks. 60110815Sdavid.guillen@arm.com */ 60210815Sdavid.guillen@arm.comclass CacheBlkIsDirtyVisitor : public CacheBlkVisitor 60310815Sdavid.guillen@arm.com{ 60410815Sdavid.guillen@arm.com public: 60510815Sdavid.guillen@arm.com CacheBlkIsDirtyVisitor() 60610815Sdavid.guillen@arm.com : _isDirty(false) {} 60710815Sdavid.guillen@arm.com 60811168Sandreas.hansson@arm.com bool operator()(CacheBlk &blk) override { 60910815Sdavid.guillen@arm.com if (blk.isDirty()) { 61010815Sdavid.guillen@arm.com _isDirty = true; 61110815Sdavid.guillen@arm.com return false; 61210815Sdavid.guillen@arm.com } else { 61310815Sdavid.guillen@arm.com return true; 61410815Sdavid.guillen@arm.com } 61510815Sdavid.guillen@arm.com } 61610815Sdavid.guillen@arm.com 61710815Sdavid.guillen@arm.com /** 61810815Sdavid.guillen@arm.com * Does the array contain a dirty line? 61910815Sdavid.guillen@arm.com * 62010815Sdavid.guillen@arm.com * \return true if yes, false otherwise. 62110815Sdavid.guillen@arm.com */ 62210815Sdavid.guillen@arm.com bool isDirty() const { return _isDirty; }; 62310815Sdavid.guillen@arm.com 62410815Sdavid.guillen@arm.com private: 62510815Sdavid.guillen@arm.com bool _isDirty; 62610815Sdavid.guillen@arm.com}; 62710815Sdavid.guillen@arm.com 62811051Sandreas.hansson@arm.com#endif // __MEM_CACHE_CACHE_HH__ 629