cache.hh revision 11197
12810Srdreslin@umich.edu/* 211197Sandreas.hansson@arm.com * Copyright (c) 2012-2015 ARM Limited 38702Sandreas.hansson@arm.com * All rights reserved. 48702Sandreas.hansson@arm.com * 58702Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68702Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78702Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88702Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98702Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108702Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118702Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128702Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138702Sandreas.hansson@arm.com * 142810Srdreslin@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 152810Srdreslin@umich.edu * All rights reserved. 162810Srdreslin@umich.edu * 172810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 182810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 192810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 202810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 212810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 222810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 232810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 242810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 252810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 262810Srdreslin@umich.edu * this software without specific prior written permission. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810Srdreslin@umich.edu * 402810Srdreslin@umich.edu * Authors: Erik Hallnor 412810Srdreslin@umich.edu * Dave Greene 422810Srdreslin@umich.edu * Steve Reinhardt 434458Sstever@eecs.umich.edu * Ron Dreslinski 448856Sandreas.hansson@arm.com * Andreas Hansson 452810Srdreslin@umich.edu */ 462810Srdreslin@umich.edu 472810Srdreslin@umich.edu/** 482810Srdreslin@umich.edu * @file 492810Srdreslin@umich.edu * Describes a cache based on template policies. 502810Srdreslin@umich.edu */ 512810Srdreslin@umich.edu 5211051Sandreas.hansson@arm.com#ifndef __MEM_CACHE_CACHE_HH__ 5311051Sandreas.hansson@arm.com#define __MEM_CACHE_CACHE_HH__ 542810Srdreslin@umich.edu 552810Srdreslin@umich.edu#include "base/misc.hh" // fatal, panic, and warn 5611197Sandreas.hansson@arm.com#include "enums/Clusivity.hh" 575338Sstever@gmail.com#include "mem/cache/base.hh" 585338Sstever@gmail.com#include "mem/cache/blk.hh" 595338Sstever@gmail.com#include "mem/cache/mshr.hh" 6010815Sdavid.guillen@arm.com#include "mem/cache/tags/base.hh" 6111053Sandreas.hansson@arm.com#include "params/Cache.hh" 624458Sstever@eecs.umich.edu#include "sim/eventq.hh" 634458Sstever@eecs.umich.edu 642813Srdreslin@umich.edu//Forward decleration 653861Sstever@eecs.umich.educlass BasePrefetcher; 662810Srdreslin@umich.edu 672810Srdreslin@umich.edu/** 682810Srdreslin@umich.edu * A template-policy based cache. The behavior of the cache can be altered by 692810Srdreslin@umich.edu * supplying different template policies. TagStore handles all tag and data 709264Sdjordje.kovacevic@arm.com * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System" 712810Srdreslin@umich.edu */ 722810Srdreslin@umich.educlass Cache : public BaseCache 732810Srdreslin@umich.edu{ 742810Srdreslin@umich.edu public: 7510815Sdavid.guillen@arm.com 7610815Sdavid.guillen@arm.com /** A typedef for a list of CacheBlk pointers. */ 7710815Sdavid.guillen@arm.com typedef std::list<CacheBlk*> BlkList; 782810Srdreslin@umich.edu 792810Srdreslin@umich.edu protected: 802810Srdreslin@umich.edu 818856Sandreas.hansson@arm.com /** 828856Sandreas.hansson@arm.com * The CPU-side port extends the base cache slave port with access 838856Sandreas.hansson@arm.com * functions for functional, atomic and timing requests. 848856Sandreas.hansson@arm.com */ 858856Sandreas.hansson@arm.com class CpuSidePort : public CacheSlavePort 863738Sstever@eecs.umich.edu { 878856Sandreas.hansson@arm.com private: 883738Sstever@eecs.umich.edu 898856Sandreas.hansson@arm.com // a pointer to our specific cache implementation 9010815Sdavid.guillen@arm.com Cache *cache; 913738Sstever@eecs.umich.edu 928856Sandreas.hansson@arm.com protected: 934478Sstever@eecs.umich.edu 948975Sandreas.hansson@arm.com virtual bool recvTimingSnoopResp(PacketPtr pkt); 958948Sandreas.hansson@arm.com 968975Sandreas.hansson@arm.com virtual bool recvTimingReq(PacketPtr pkt); 973738Sstever@eecs.umich.edu 983738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 993738Sstever@eecs.umich.edu 1003738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 1018856Sandreas.hansson@arm.com 1029090Sandreas.hansson@arm.com virtual AddrRangeList getAddrRanges() const; 1038856Sandreas.hansson@arm.com 1048856Sandreas.hansson@arm.com public: 1058856Sandreas.hansson@arm.com 10610815Sdavid.guillen@arm.com CpuSidePort(const std::string &_name, Cache *_cache, 1078856Sandreas.hansson@arm.com const std::string &_label); 1088856Sandreas.hansson@arm.com 1093738Sstever@eecs.umich.edu }; 1103738Sstever@eecs.umich.edu 1118856Sandreas.hansson@arm.com /** 1128914Sandreas.hansson@arm.com * Override the default behaviour of sendDeferredPacket to enable 1138914Sandreas.hansson@arm.com * the memory-side cache port to also send requests based on the 1148914Sandreas.hansson@arm.com * current MSHR status. This queue has a pointer to our specific 1158914Sandreas.hansson@arm.com * cache implementation and is used by the MemSidePort. 1168914Sandreas.hansson@arm.com */ 11710713Sandreas.hansson@arm.com class CacheReqPacketQueue : public ReqPacketQueue 1188914Sandreas.hansson@arm.com { 1198914Sandreas.hansson@arm.com 1208914Sandreas.hansson@arm.com protected: 1218914Sandreas.hansson@arm.com 12210815Sdavid.guillen@arm.com Cache &cache; 12310713Sandreas.hansson@arm.com SnoopRespPacketQueue &snoopRespQueue; 1248914Sandreas.hansson@arm.com 1258914Sandreas.hansson@arm.com public: 1268914Sandreas.hansson@arm.com 12710815Sdavid.guillen@arm.com CacheReqPacketQueue(Cache &cache, MasterPort &port, 12810713Sandreas.hansson@arm.com SnoopRespPacketQueue &snoop_resp_queue, 12910713Sandreas.hansson@arm.com const std::string &label) : 13010713Sandreas.hansson@arm.com ReqPacketQueue(cache, port, label), cache(cache), 13110713Sandreas.hansson@arm.com snoopRespQueue(snoop_resp_queue) { } 1328914Sandreas.hansson@arm.com 1338914Sandreas.hansson@arm.com /** 1348914Sandreas.hansson@arm.com * Override the normal sendDeferredPacket and do not only 1358914Sandreas.hansson@arm.com * consider the transmit list (used for responses), but also 1368914Sandreas.hansson@arm.com * requests. 1378914Sandreas.hansson@arm.com */ 1388914Sandreas.hansson@arm.com virtual void sendDeferredPacket(); 1398914Sandreas.hansson@arm.com 1408914Sandreas.hansson@arm.com }; 1418914Sandreas.hansson@arm.com 1428914Sandreas.hansson@arm.com /** 1438856Sandreas.hansson@arm.com * The memory-side port extends the base cache master port with 1448856Sandreas.hansson@arm.com * access functions for functional, atomic and timing snoops. 1458856Sandreas.hansson@arm.com */ 1468856Sandreas.hansson@arm.com class MemSidePort : public CacheMasterPort 1473738Sstever@eecs.umich.edu { 1488856Sandreas.hansson@arm.com private: 1493738Sstever@eecs.umich.edu 1508914Sandreas.hansson@arm.com /** The cache-specific queue. */ 15110713Sandreas.hansson@arm.com CacheReqPacketQueue _reqQueue; 15210713Sandreas.hansson@arm.com 15310713Sandreas.hansson@arm.com SnoopRespPacketQueue _snoopRespQueue; 1548914Sandreas.hansson@arm.com 1558856Sandreas.hansson@arm.com // a pointer to our specific cache implementation 15610815Sdavid.guillen@arm.com Cache *cache; 1573738Sstever@eecs.umich.edu 1588856Sandreas.hansson@arm.com protected: 1594478Sstever@eecs.umich.edu 1608975Sandreas.hansson@arm.com virtual void recvTimingSnoopReq(PacketPtr pkt); 1618948Sandreas.hansson@arm.com 1628975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 1633738Sstever@eecs.umich.edu 1648948Sandreas.hansson@arm.com virtual Tick recvAtomicSnoop(PacketPtr pkt); 1653738Sstever@eecs.umich.edu 1668948Sandreas.hansson@arm.com virtual void recvFunctionalSnoop(PacketPtr pkt); 1674458Sstever@eecs.umich.edu 1688856Sandreas.hansson@arm.com public: 1698856Sandreas.hansson@arm.com 17010815Sdavid.guillen@arm.com MemSidePort(const std::string &_name, Cache *_cache, 1718856Sandreas.hansson@arm.com const std::string &_label); 1723738Sstever@eecs.umich.edu }; 1733738Sstever@eecs.umich.edu 1742810Srdreslin@umich.edu /** Tag and data Storage */ 17510815Sdavid.guillen@arm.com BaseTags *tags; 1764626Sstever@eecs.umich.edu 1772810Srdreslin@umich.edu /** Prefetcher */ 1783861Sstever@eecs.umich.edu BasePrefetcher *prefetcher; 1792810Srdreslin@umich.edu 1804671Sstever@eecs.umich.edu /** Temporary cache block for occasional transitory use */ 18110815Sdavid.guillen@arm.com CacheBlk *tempBlock; 1824671Sstever@eecs.umich.edu 1832810Srdreslin@umich.edu /** 1845707Shsul@eecs.umich.edu * This cache should allocate a block on a line-sized write miss. 1853860Sstever@eecs.umich.edu */ 1863860Sstever@eecs.umich.edu const bool doFastWrites; 1873860Sstever@eecs.umich.edu 1885875Ssteve.reinhardt@amd.com /** 18910345SCurtis.Dunham@arm.com * Turn line-sized writes into WriteInvalidate transactions. 19010345SCurtis.Dunham@arm.com */ 19110345SCurtis.Dunham@arm.com void promoteWholeLineWrites(PacketPtr pkt); 19210345SCurtis.Dunham@arm.com 19310345SCurtis.Dunham@arm.com /** 1945875Ssteve.reinhardt@amd.com * Notify the prefetcher on every access, not just misses. 1955875Ssteve.reinhardt@amd.com */ 1965875Ssteve.reinhardt@amd.com const bool prefetchOnAccess; 1973860Sstever@eecs.umich.edu 19811197Sandreas.hansson@arm.com /** 19911197Sandreas.hansson@arm.com * Clusivity with respect to the upstream cache, determining if we 20011197Sandreas.hansson@arm.com * fill into both this cache and the cache above on a miss. Note 20111197Sandreas.hansson@arm.com * that we currently do not support strict clusivity policies. 20211197Sandreas.hansson@arm.com */ 20311197Sandreas.hansson@arm.com const Enums::Clusivity clusivity; 20411197Sandreas.hansson@arm.com 2053860Sstever@eecs.umich.edu /** 20611190Sandreas.hansson@arm.com * Upstream caches need this packet until true is returned, so 20711190Sandreas.hansson@arm.com * hold it for deletion until a subsequent call 2089063SAli.Saidi@ARM.com */ 20911190Sandreas.hansson@arm.com std::unique_ptr<Packet> pendingDelete; 2109063SAli.Saidi@ARM.com 2119063SAli.Saidi@ARM.com /** 21211197Sandreas.hansson@arm.com * Writebacks from the tempBlock, resulting on the response path 21311197Sandreas.hansson@arm.com * in atomic mode, must happen after the call to recvAtomic has 21411197Sandreas.hansson@arm.com * finished (for the right ordering of the packets). We therefore 21511197Sandreas.hansson@arm.com * need to hold on to the packets, and have a method and an event 21611197Sandreas.hansson@arm.com * to send them. 21711197Sandreas.hansson@arm.com */ 21811197Sandreas.hansson@arm.com PacketPtr tempBlockWriteback; 21911197Sandreas.hansson@arm.com 22011197Sandreas.hansson@arm.com /** 22111197Sandreas.hansson@arm.com * Send the outstanding tempBlock writeback. To be called after 22211197Sandreas.hansson@arm.com * recvAtomic finishes in cases where the block we filled is in 22311197Sandreas.hansson@arm.com * fact the tempBlock, and now needs to be written back. 22411197Sandreas.hansson@arm.com */ 22511197Sandreas.hansson@arm.com void writebackTempBlockAtomic() { 22611197Sandreas.hansson@arm.com assert(tempBlockWriteback != nullptr); 22711197Sandreas.hansson@arm.com PacketList writebacks{tempBlockWriteback}; 22811197Sandreas.hansson@arm.com doWritebacksAtomic(writebacks); 22911197Sandreas.hansson@arm.com tempBlockWriteback = nullptr; 23011197Sandreas.hansson@arm.com } 23111197Sandreas.hansson@arm.com 23211197Sandreas.hansson@arm.com /** 23311197Sandreas.hansson@arm.com * An event to writeback the tempBlock after recvAtomic 23411197Sandreas.hansson@arm.com * finishes. To avoid other calls to recvAtomic getting in 23511197Sandreas.hansson@arm.com * between, we create this event with a higher priority. 23611197Sandreas.hansson@arm.com */ 23711197Sandreas.hansson@arm.com EventWrapper<Cache, &Cache::writebackTempBlockAtomic> \ 23811197Sandreas.hansson@arm.com writebackTempBlockAtomicEvent; 23911197Sandreas.hansson@arm.com 24011197Sandreas.hansson@arm.com /** 2413860Sstever@eecs.umich.edu * Does all the processing necessary to perform the provided request. 2423860Sstever@eecs.umich.edu * @param pkt The memory request to perform. 24310048Saminfar@gmail.com * @param blk The cache block to be updated. 2443860Sstever@eecs.umich.edu * @param lat The latency of the access. 2453860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 2465707Shsul@eecs.umich.edu * @return Boolean indicating whether the request was satisfied. 2473860Sstever@eecs.umich.edu */ 24810815Sdavid.guillen@arm.com bool access(PacketPtr pkt, CacheBlk *&blk, 2499288Sandreas.hansson@arm.com Cycles &lat, PacketList &writebacks); 2504219Srdreslin@umich.edu 2514219Srdreslin@umich.edu /** 2524219Srdreslin@umich.edu *Handle doing the Compare and Swap function for SPARC. 2534219Srdreslin@umich.edu */ 25410815Sdavid.guillen@arm.com void cmpAndSwap(CacheBlk *blk, PacketPtr pkt); 2553860Sstever@eecs.umich.edu 2563860Sstever@eecs.umich.edu /** 25710028SGiacomo.Gabrielli@arm.com * Find a block frame for new block at address addr targeting the 25810028SGiacomo.Gabrielli@arm.com * given security space, assuming that the block is not currently 25910028SGiacomo.Gabrielli@arm.com * in the cache. Append writebacks if any to provided packet 26010028SGiacomo.Gabrielli@arm.com * list. Return free block frame. May return NULL if there are 26110028SGiacomo.Gabrielli@arm.com * no replaceable blocks at the moment. 2625350Sstever@gmail.com */ 26310815Sdavid.guillen@arm.com CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks); 2645350Sstever@gmail.com 2655350Sstever@gmail.com /** 26611197Sandreas.hansson@arm.com * Invalidate a cache block. 26711197Sandreas.hansson@arm.com * 26811197Sandreas.hansson@arm.com * @param blk Block to invalidate 26911197Sandreas.hansson@arm.com */ 27011197Sandreas.hansson@arm.com void invalidateBlock(CacheBlk *blk); 27111197Sandreas.hansson@arm.com 27211197Sandreas.hansson@arm.com /** 2733860Sstever@eecs.umich.edu * Populates a cache block and handles all outstanding requests for the 2743860Sstever@eecs.umich.edu * satisfied fill request. This version takes two memory requests. One 2753860Sstever@eecs.umich.edu * contains the fill data, the other is an optional target to satisfy. 2764626Sstever@eecs.umich.edu * @param pkt The memory request with the fill data. 2773860Sstever@eecs.umich.edu * @param blk The cache block if it already exists. 2783860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 27911197Sandreas.hansson@arm.com * @param allocate Whether to allocate a block or use the temp block 2803860Sstever@eecs.umich.edu * @return Pointer to the new cache block. 2813860Sstever@eecs.umich.edu */ 28210815Sdavid.guillen@arm.com CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk, 28311197Sandreas.hansson@arm.com PacketList &writebacks, bool allocate); 2843860Sstever@eecs.umich.edu 28511197Sandreas.hansson@arm.com /** 28611197Sandreas.hansson@arm.com * Determine whether we should allocate on a fill or not. If this 28711197Sandreas.hansson@arm.com * cache is mostly inclusive with regards to the upstream cache(s) 28811197Sandreas.hansson@arm.com * we always allocate (for any non-forwarded and cacheable 28911197Sandreas.hansson@arm.com * requests). In the case of a mostly exclusive cache, we allocate 29011197Sandreas.hansson@arm.com * on fill if the packet did not come from a cache, thus if we: 29111197Sandreas.hansson@arm.com * are dealing with a whole-line write (the latter behaves much 29211197Sandreas.hansson@arm.com * like a writeback), the original target packet came from a 29311197Sandreas.hansson@arm.com * non-caching source, or if we are performing a prefetch or LLSC. 29411197Sandreas.hansson@arm.com * 29511197Sandreas.hansson@arm.com * @param cmd Command of the incoming requesting packet 29611197Sandreas.hansson@arm.com * @return Whether we should allocate on the fill 29711197Sandreas.hansson@arm.com */ 29811197Sandreas.hansson@arm.com inline bool allocOnFill(MemCmd cmd) const 29911197Sandreas.hansson@arm.com { 30011197Sandreas.hansson@arm.com return clusivity == Enums::mostly_incl || 30111197Sandreas.hansson@arm.com cmd == MemCmd::WriteLineReq || 30211197Sandreas.hansson@arm.com cmd == MemCmd::ReadReq || 30311197Sandreas.hansson@arm.com cmd == MemCmd::WriteReq || 30411197Sandreas.hansson@arm.com cmd.isPrefetch() || 30511197Sandreas.hansson@arm.com cmd.isLLSC(); 30611197Sandreas.hansson@arm.com } 3079548Sandreas.hansson@arm.com 3089548Sandreas.hansson@arm.com /** 3099548Sandreas.hansson@arm.com * Performs the access specified by the request. 3109548Sandreas.hansson@arm.com * @param pkt The request to perform. 3119548Sandreas.hansson@arm.com * @return The result of the access. 3129548Sandreas.hansson@arm.com */ 3139548Sandreas.hansson@arm.com bool recvTimingReq(PacketPtr pkt); 3149548Sandreas.hansson@arm.com 3159548Sandreas.hansson@arm.com /** 31610883Sali.jafri@arm.com * Insert writebacks into the write buffer 31710883Sali.jafri@arm.com */ 31810883Sali.jafri@arm.com void doWritebacks(PacketList& writebacks, Tick forward_time); 31910883Sali.jafri@arm.com 32010883Sali.jafri@arm.com /** 32111130Sali.jafri@arm.com * Send writebacks down the memory hierarchy in atomic mode 32211130Sali.jafri@arm.com */ 32311130Sali.jafri@arm.com void doWritebacksAtomic(PacketList& writebacks); 32411130Sali.jafri@arm.com 32511130Sali.jafri@arm.com /** 3269548Sandreas.hansson@arm.com * Handles a response (cache line fill/write ack) from the bus. 3279548Sandreas.hansson@arm.com * @param pkt The response packet 3289548Sandreas.hansson@arm.com */ 3299548Sandreas.hansson@arm.com void recvTimingResp(PacketPtr pkt); 3309548Sandreas.hansson@arm.com 3319548Sandreas.hansson@arm.com /** 3329548Sandreas.hansson@arm.com * Snoops bus transactions to maintain coherence. 3339548Sandreas.hansson@arm.com * @param pkt The current bus transaction. 3349548Sandreas.hansson@arm.com */ 3359548Sandreas.hansson@arm.com void recvTimingSnoopReq(PacketPtr pkt); 3369548Sandreas.hansson@arm.com 3379548Sandreas.hansson@arm.com /** 3389548Sandreas.hansson@arm.com * Handle a snoop response. 3399548Sandreas.hansson@arm.com * @param pkt Snoop response packet 3409548Sandreas.hansson@arm.com */ 3419548Sandreas.hansson@arm.com void recvTimingSnoopResp(PacketPtr pkt); 3429548Sandreas.hansson@arm.com 3439548Sandreas.hansson@arm.com /** 3449548Sandreas.hansson@arm.com * Performs the access specified by the request. 3459548Sandreas.hansson@arm.com * @param pkt The request to perform. 3469782Sandreas.hansson@arm.com * @return The number of ticks required for the access. 3479548Sandreas.hansson@arm.com */ 3489782Sandreas.hansson@arm.com Tick recvAtomic(PacketPtr pkt); 3499548Sandreas.hansson@arm.com 3509548Sandreas.hansson@arm.com /** 3519548Sandreas.hansson@arm.com * Snoop for the provided request in the cache and return the estimated 3529782Sandreas.hansson@arm.com * time taken. 3539548Sandreas.hansson@arm.com * @param pkt The memory request to snoop 3549782Sandreas.hansson@arm.com * @return The number of ticks required for the snoop. 3559548Sandreas.hansson@arm.com */ 3569782Sandreas.hansson@arm.com Tick recvAtomicSnoop(PacketPtr pkt); 3579548Sandreas.hansson@arm.com 3589548Sandreas.hansson@arm.com /** 3599548Sandreas.hansson@arm.com * Performs the access specified by the request. 3609548Sandreas.hansson@arm.com * @param pkt The request to perform. 3619548Sandreas.hansson@arm.com * @param fromCpuSide from the CPU side port or the memory side port 3629548Sandreas.hansson@arm.com */ 3639548Sandreas.hansson@arm.com void functionalAccess(PacketPtr pkt, bool fromCpuSide); 3649548Sandreas.hansson@arm.com 36510815Sdavid.guillen@arm.com void satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk, 3667667Ssteve.reinhardt@amd.com bool deferred_response = false, 3677667Ssteve.reinhardt@amd.com bool pending_downgrade = false); 36810815Sdavid.guillen@arm.com bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, CacheBlk *blk); 3694626Sstever@eecs.umich.edu 37010563Sandreas.hansson@arm.com void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 3715319Sstever@gmail.com bool already_copied, bool pending_inval); 3723860Sstever@eecs.umich.edu 3733860Sstever@eecs.umich.edu /** 37411127Sandreas.hansson@arm.com * Perform an upward snoop if needed, and update the block state 37511127Sandreas.hansson@arm.com * (possibly invalidating the block). Also create a response if required. 37611127Sandreas.hansson@arm.com * 37711127Sandreas.hansson@arm.com * @param pkt Snoop packet 37811127Sandreas.hansson@arm.com * @param blk Cache block being snooped 37911127Sandreas.hansson@arm.com * @param is_timing Timing or atomic for the response 38011127Sandreas.hansson@arm.com * @param is_deferred Is this a deferred snoop or not? 38111127Sandreas.hansson@arm.com * @param pending_inval Do we have a pending invalidation? 38211127Sandreas.hansson@arm.com * 38311127Sandreas.hansson@arm.com * @return The snoop delay incurred by the upwards snoop 3843860Sstever@eecs.umich.edu */ 38511127Sandreas.hansson@arm.com uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk, 38611127Sandreas.hansson@arm.com bool is_timing, bool is_deferred, bool pending_inval); 3873860Sstever@eecs.umich.edu 3883860Sstever@eecs.umich.edu /** 3893860Sstever@eecs.umich.edu * Create a writeback request for the given block. 3903860Sstever@eecs.umich.edu * @param blk The block to writeback. 3913860Sstever@eecs.umich.edu * @return The writeback request for the block. 3923860Sstever@eecs.umich.edu */ 39310815Sdavid.guillen@arm.com PacketPtr writebackBlk(CacheBlk *blk); 3943860Sstever@eecs.umich.edu 39510883Sali.jafri@arm.com /** 39610883Sali.jafri@arm.com * Create a CleanEvict request for the given block. 39710883Sali.jafri@arm.com * @param blk The block to evict. 39810883Sali.jafri@arm.com * @return The CleanEvict request for the block. 39910883Sali.jafri@arm.com */ 40010883Sali.jafri@arm.com PacketPtr cleanEvictBlk(CacheBlk *blk); 40110883Sali.jafri@arm.com 4029347SAndreas.Sandberg@arm.com 40311169Sandreas.hansson@arm.com void memWriteback() override; 40411169Sandreas.hansson@arm.com void memInvalidate() override; 40511169Sandreas.hansson@arm.com bool isDirty() const override; 4069347SAndreas.Sandberg@arm.com 4079347SAndreas.Sandberg@arm.com /** 4089347SAndreas.Sandberg@arm.com * Cache block visitor that writes back dirty cache blocks using 4099347SAndreas.Sandberg@arm.com * functional writes. 4109347SAndreas.Sandberg@arm.com * 4119347SAndreas.Sandberg@arm.com * \return Always returns true. 4129347SAndreas.Sandberg@arm.com */ 41310815Sdavid.guillen@arm.com bool writebackVisitor(CacheBlk &blk); 4149347SAndreas.Sandberg@arm.com /** 4159347SAndreas.Sandberg@arm.com * Cache block visitor that invalidates all blocks in the cache. 4169347SAndreas.Sandberg@arm.com * 4179347SAndreas.Sandberg@arm.com * @warn Dirty cache lines will not be written back to memory. 4189347SAndreas.Sandberg@arm.com * 4199347SAndreas.Sandberg@arm.com * \return Always returns true. 4209347SAndreas.Sandberg@arm.com */ 42110815Sdavid.guillen@arm.com bool invalidateVisitor(CacheBlk &blk); 4229347SAndreas.Sandberg@arm.com 4239445SAndreas.Sandberg@ARM.com /** 4245365Sstever@gmail.com * Generate an appropriate downstream bus request packet for the 4255365Sstever@gmail.com * given parameters. 4265365Sstever@gmail.com * @param cpu_pkt The upstream request that needs to be satisfied. 4275365Sstever@gmail.com * @param blk The block currently in the cache corresponding to 4285365Sstever@gmail.com * cpu_pkt (NULL if none). 4295365Sstever@gmail.com * @param needsExclusive Indicates that an exclusive copy is required 4305365Sstever@gmail.com * even if the request in cpu_pkt doesn't indicate that. 4315365Sstever@gmail.com * @return A new Packet containing the request, or NULL if the 4325365Sstever@gmail.com * current request in cpu_pkt should just be forwarded on. 4334626Sstever@eecs.umich.edu */ 43410815Sdavid.guillen@arm.com PacketPtr getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk, 4359529Sandreas.hansson@arm.com bool needsExclusive) const; 4365365Sstever@gmail.com 4375365Sstever@gmail.com /** 4385365Sstever@gmail.com * Return the next MSHR to service, either a pending miss from the 4395365Sstever@gmail.com * mshrQueue, a buffered write from the write buffer, or something 4405365Sstever@gmail.com * from the prefetcher. This function is responsible for 4415365Sstever@gmail.com * prioritizing among those sources on the fly. 4425365Sstever@gmail.com */ 4434626Sstever@eecs.umich.edu MSHR *getNextMSHR(); 4445365Sstever@gmail.com 4455365Sstever@gmail.com /** 44610883Sali.jafri@arm.com * Send up a snoop request and find cached copies. If cached copies are 44710883Sali.jafri@arm.com * found, set the BLOCK_CACHED flag in pkt. 44810883Sali.jafri@arm.com */ 44911130Sali.jafri@arm.com bool isCachedAbove(PacketPtr pkt, bool is_timing = true) const; 45010883Sali.jafri@arm.com 45110883Sali.jafri@arm.com /** 4525365Sstever@gmail.com * Selects an outstanding request to service. Called when the 4535365Sstever@gmail.com * cache gets granted the downstream bus in timing mode. 4545365Sstever@gmail.com * @return The request to service, NULL if none found. 4555365Sstever@gmail.com */ 4564628Sstever@eecs.umich.edu PacketPtr getTimingPacket(); 4574626Sstever@eecs.umich.edu 4584626Sstever@eecs.umich.edu /** 45910679Sandreas.hansson@arm.com * Marks a request as in service (sent on the bus). This can have 46010679Sandreas.hansson@arm.com * side effect since storage for no response commands is 46110679Sandreas.hansson@arm.com * deallocated once they are successfully sent. Also remember if 46210679Sandreas.hansson@arm.com * we are expecting a dirty response from another cache, 46310679Sandreas.hansson@arm.com * effectively making this MSHR the ordering point. 4644626Sstever@eecs.umich.edu */ 46510679Sandreas.hansson@arm.com void markInService(MSHR *mshr, bool pending_dirty_resp); 4664626Sstever@eecs.umich.edu 4674626Sstever@eecs.umich.edu /** 4684626Sstever@eecs.umich.edu * Return whether there are any outstanding misses. 4694626Sstever@eecs.umich.edu */ 4704626Sstever@eecs.umich.edu bool outstandingMisses() const 4712810Srdreslin@umich.edu { 4724626Sstever@eecs.umich.edu return mshrQueue.allocated != 0; 4732810Srdreslin@umich.edu } 4742810Srdreslin@umich.edu 47510028SGiacomo.Gabrielli@arm.com CacheBlk *findBlock(Addr addr, bool is_secure) const { 47610028SGiacomo.Gabrielli@arm.com return tags->findBlock(addr, is_secure); 4772810Srdreslin@umich.edu } 4782810Srdreslin@umich.edu 47911169Sandreas.hansson@arm.com bool inCache(Addr addr, bool is_secure) const override { 48010028SGiacomo.Gabrielli@arm.com return (tags->findBlock(addr, is_secure) != 0); 4813861Sstever@eecs.umich.edu } 4823861Sstever@eecs.umich.edu 48311169Sandreas.hansson@arm.com bool inMissQueue(Addr addr, bool is_secure) const override { 48410028SGiacomo.Gabrielli@arm.com return (mshrQueue.findMatch(addr, is_secure) != 0); 4853861Sstever@eecs.umich.edu } 4865875Ssteve.reinhardt@amd.com 4875875Ssteve.reinhardt@amd.com /** 4885875Ssteve.reinhardt@amd.com * Find next request ready time from among possible sources. 4895875Ssteve.reinhardt@amd.com */ 4909529Sandreas.hansson@arm.com Tick nextMSHRReadyTime() const; 4919529Sandreas.hansson@arm.com 4929529Sandreas.hansson@arm.com public: 4939529Sandreas.hansson@arm.com /** Instantiates a basic cache object. */ 49411053Sandreas.hansson@arm.com Cache(const CacheParams *p); 4959529Sandreas.hansson@arm.com 4969813Srioshering@gmail.com /** Non-default destructor is needed to deallocate memory. */ 4979813Srioshering@gmail.com virtual ~Cache(); 4989813Srioshering@gmail.com 49911169Sandreas.hansson@arm.com void regStats() override; 5008985SAli.Saidi@ARM.com 5018985SAli.Saidi@ARM.com /** serialize the state of the caches 5028985SAli.Saidi@ARM.com * We currently don't support checkpointing cache state, so this panics. 5038985SAli.Saidi@ARM.com */ 50411168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 50511168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 5062810Srdreslin@umich.edu}; 5072810Srdreslin@umich.edu 50810815Sdavid.guillen@arm.com/** 50910815Sdavid.guillen@arm.com * Wrap a method and present it as a cache block visitor. 51010815Sdavid.guillen@arm.com * 51110815Sdavid.guillen@arm.com * For example the forEachBlk method in the tag arrays expects a 51210815Sdavid.guillen@arm.com * callable object/function as their parameter. This class wraps a 51310815Sdavid.guillen@arm.com * method in an object and presents callable object that adheres to 51410815Sdavid.guillen@arm.com * the cache block visitor protocol. 51510815Sdavid.guillen@arm.com */ 51610815Sdavid.guillen@arm.comclass CacheBlkVisitorWrapper : public CacheBlkVisitor 51710815Sdavid.guillen@arm.com{ 51810815Sdavid.guillen@arm.com public: 51910815Sdavid.guillen@arm.com typedef bool (Cache::*VisitorPtr)(CacheBlk &blk); 52010815Sdavid.guillen@arm.com 52110815Sdavid.guillen@arm.com CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor) 52210815Sdavid.guillen@arm.com : cache(_cache), visitor(_visitor) {} 52310815Sdavid.guillen@arm.com 52411168Sandreas.hansson@arm.com bool operator()(CacheBlk &blk) override { 52510815Sdavid.guillen@arm.com return (cache.*visitor)(blk); 52610815Sdavid.guillen@arm.com } 52710815Sdavid.guillen@arm.com 52810815Sdavid.guillen@arm.com private: 52910815Sdavid.guillen@arm.com Cache &cache; 53010815Sdavid.guillen@arm.com VisitorPtr visitor; 53110815Sdavid.guillen@arm.com}; 53210815Sdavid.guillen@arm.com 53310815Sdavid.guillen@arm.com/** 53410815Sdavid.guillen@arm.com * Cache block visitor that determines if there are dirty blocks in a 53510815Sdavid.guillen@arm.com * cache. 53610815Sdavid.guillen@arm.com * 53710815Sdavid.guillen@arm.com * Use with the forEachBlk method in the tag array to determine if the 53810815Sdavid.guillen@arm.com * array contains dirty blocks. 53910815Sdavid.guillen@arm.com */ 54010815Sdavid.guillen@arm.comclass CacheBlkIsDirtyVisitor : public CacheBlkVisitor 54110815Sdavid.guillen@arm.com{ 54210815Sdavid.guillen@arm.com public: 54310815Sdavid.guillen@arm.com CacheBlkIsDirtyVisitor() 54410815Sdavid.guillen@arm.com : _isDirty(false) {} 54510815Sdavid.guillen@arm.com 54611168Sandreas.hansson@arm.com bool operator()(CacheBlk &blk) override { 54710815Sdavid.guillen@arm.com if (blk.isDirty()) { 54810815Sdavid.guillen@arm.com _isDirty = true; 54910815Sdavid.guillen@arm.com return false; 55010815Sdavid.guillen@arm.com } else { 55110815Sdavid.guillen@arm.com return true; 55210815Sdavid.guillen@arm.com } 55310815Sdavid.guillen@arm.com } 55410815Sdavid.guillen@arm.com 55510815Sdavid.guillen@arm.com /** 55610815Sdavid.guillen@arm.com * Does the array contain a dirty line? 55710815Sdavid.guillen@arm.com * 55810815Sdavid.guillen@arm.com * \return true if yes, false otherwise. 55910815Sdavid.guillen@arm.com */ 56010815Sdavid.guillen@arm.com bool isDirty() const { return _isDirty; }; 56110815Sdavid.guillen@arm.com 56210815Sdavid.guillen@arm.com private: 56310815Sdavid.guillen@arm.com bool _isDirty; 56410815Sdavid.guillen@arm.com}; 56510815Sdavid.guillen@arm.com 56611051Sandreas.hansson@arm.com#endif // __MEM_CACHE_CACHE_HH__ 567