cache.hh revision 11053
12810Srdreslin@umich.edu/* 210343SCurtis.Dunham@arm.com * Copyright (c) 2012-2014 ARM Limited 38702Sandreas.hansson@arm.com * All rights reserved. 48702Sandreas.hansson@arm.com * 58702Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68702Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78702Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88702Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98702Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108702Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118702Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128702Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138702Sandreas.hansson@arm.com * 142810Srdreslin@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 152810Srdreslin@umich.edu * All rights reserved. 162810Srdreslin@umich.edu * 172810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 182810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 192810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 202810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 212810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 222810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 232810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 242810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 252810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 262810Srdreslin@umich.edu * this software without specific prior written permission. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810Srdreslin@umich.edu * 402810Srdreslin@umich.edu * Authors: Erik Hallnor 412810Srdreslin@umich.edu * Dave Greene 422810Srdreslin@umich.edu * Steve Reinhardt 434458Sstever@eecs.umich.edu * Ron Dreslinski 448856Sandreas.hansson@arm.com * Andreas Hansson 452810Srdreslin@umich.edu */ 462810Srdreslin@umich.edu 472810Srdreslin@umich.edu/** 482810Srdreslin@umich.edu * @file 492810Srdreslin@umich.edu * Describes a cache based on template policies. 502810Srdreslin@umich.edu */ 512810Srdreslin@umich.edu 5211051Sandreas.hansson@arm.com#ifndef __MEM_CACHE_CACHE_HH__ 5311051Sandreas.hansson@arm.com#define __MEM_CACHE_CACHE_HH__ 542810Srdreslin@umich.edu 552810Srdreslin@umich.edu#include "base/misc.hh" // fatal, panic, and warn 565338Sstever@gmail.com#include "mem/cache/base.hh" 575338Sstever@gmail.com#include "mem/cache/blk.hh" 585338Sstever@gmail.com#include "mem/cache/mshr.hh" 5910815Sdavid.guillen@arm.com#include "mem/cache/tags/base.hh" 6011053Sandreas.hansson@arm.com#include "params/Cache.hh" 614458Sstever@eecs.umich.edu#include "sim/eventq.hh" 624458Sstever@eecs.umich.edu 632813Srdreslin@umich.edu//Forward decleration 643861Sstever@eecs.umich.educlass BasePrefetcher; 652810Srdreslin@umich.edu 662810Srdreslin@umich.edu/** 672810Srdreslin@umich.edu * A template-policy based cache. The behavior of the cache can be altered by 682810Srdreslin@umich.edu * supplying different template policies. TagStore handles all tag and data 699264Sdjordje.kovacevic@arm.com * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System" 702810Srdreslin@umich.edu */ 712810Srdreslin@umich.educlass Cache : public BaseCache 722810Srdreslin@umich.edu{ 732810Srdreslin@umich.edu public: 7410815Sdavid.guillen@arm.com 7510815Sdavid.guillen@arm.com /** A typedef for a list of CacheBlk pointers. */ 7610815Sdavid.guillen@arm.com typedef std::list<CacheBlk*> BlkList; 772810Srdreslin@umich.edu 782810Srdreslin@umich.edu protected: 792810Srdreslin@umich.edu 808856Sandreas.hansson@arm.com /** 818856Sandreas.hansson@arm.com * The CPU-side port extends the base cache slave port with access 828856Sandreas.hansson@arm.com * functions for functional, atomic and timing requests. 838856Sandreas.hansson@arm.com */ 848856Sandreas.hansson@arm.com class CpuSidePort : public CacheSlavePort 853738Sstever@eecs.umich.edu { 868856Sandreas.hansson@arm.com private: 873738Sstever@eecs.umich.edu 888856Sandreas.hansson@arm.com // a pointer to our specific cache implementation 8910815Sdavid.guillen@arm.com Cache *cache; 903738Sstever@eecs.umich.edu 918856Sandreas.hansson@arm.com protected: 924478Sstever@eecs.umich.edu 938975Sandreas.hansson@arm.com virtual bool recvTimingSnoopResp(PacketPtr pkt); 948948Sandreas.hansson@arm.com 958975Sandreas.hansson@arm.com virtual bool recvTimingReq(PacketPtr pkt); 963738Sstever@eecs.umich.edu 973738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 983738Sstever@eecs.umich.edu 993738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 1008856Sandreas.hansson@arm.com 1019090Sandreas.hansson@arm.com virtual AddrRangeList getAddrRanges() const; 1028856Sandreas.hansson@arm.com 1038856Sandreas.hansson@arm.com public: 1048856Sandreas.hansson@arm.com 10510815Sdavid.guillen@arm.com CpuSidePort(const std::string &_name, Cache *_cache, 1068856Sandreas.hansson@arm.com const std::string &_label); 1078856Sandreas.hansson@arm.com 1083738Sstever@eecs.umich.edu }; 1093738Sstever@eecs.umich.edu 1108856Sandreas.hansson@arm.com /** 1118914Sandreas.hansson@arm.com * Override the default behaviour of sendDeferredPacket to enable 1128914Sandreas.hansson@arm.com * the memory-side cache port to also send requests based on the 1138914Sandreas.hansson@arm.com * current MSHR status. This queue has a pointer to our specific 1148914Sandreas.hansson@arm.com * cache implementation and is used by the MemSidePort. 1158914Sandreas.hansson@arm.com */ 11610713Sandreas.hansson@arm.com class CacheReqPacketQueue : public ReqPacketQueue 1178914Sandreas.hansson@arm.com { 1188914Sandreas.hansson@arm.com 1198914Sandreas.hansson@arm.com protected: 1208914Sandreas.hansson@arm.com 12110815Sdavid.guillen@arm.com Cache &cache; 12210713Sandreas.hansson@arm.com SnoopRespPacketQueue &snoopRespQueue; 1238914Sandreas.hansson@arm.com 1248914Sandreas.hansson@arm.com public: 1258914Sandreas.hansson@arm.com 12610815Sdavid.guillen@arm.com CacheReqPacketQueue(Cache &cache, MasterPort &port, 12710713Sandreas.hansson@arm.com SnoopRespPacketQueue &snoop_resp_queue, 12810713Sandreas.hansson@arm.com const std::string &label) : 12910713Sandreas.hansson@arm.com ReqPacketQueue(cache, port, label), cache(cache), 13010713Sandreas.hansson@arm.com snoopRespQueue(snoop_resp_queue) { } 1318914Sandreas.hansson@arm.com 1328914Sandreas.hansson@arm.com /** 1338914Sandreas.hansson@arm.com * Override the normal sendDeferredPacket and do not only 1348914Sandreas.hansson@arm.com * consider the transmit list (used for responses), but also 1358914Sandreas.hansson@arm.com * requests. 1368914Sandreas.hansson@arm.com */ 1378914Sandreas.hansson@arm.com virtual void sendDeferredPacket(); 1388914Sandreas.hansson@arm.com 1398914Sandreas.hansson@arm.com }; 1408914Sandreas.hansson@arm.com 1418914Sandreas.hansson@arm.com /** 1428856Sandreas.hansson@arm.com * The memory-side port extends the base cache master port with 1438856Sandreas.hansson@arm.com * access functions for functional, atomic and timing snoops. 1448856Sandreas.hansson@arm.com */ 1458856Sandreas.hansson@arm.com class MemSidePort : public CacheMasterPort 1463738Sstever@eecs.umich.edu { 1478856Sandreas.hansson@arm.com private: 1483738Sstever@eecs.umich.edu 1498914Sandreas.hansson@arm.com /** The cache-specific queue. */ 15010713Sandreas.hansson@arm.com CacheReqPacketQueue _reqQueue; 15110713Sandreas.hansson@arm.com 15210713Sandreas.hansson@arm.com SnoopRespPacketQueue _snoopRespQueue; 1538914Sandreas.hansson@arm.com 1548856Sandreas.hansson@arm.com // a pointer to our specific cache implementation 15510815Sdavid.guillen@arm.com Cache *cache; 1563738Sstever@eecs.umich.edu 1578856Sandreas.hansson@arm.com protected: 1584478Sstever@eecs.umich.edu 1598975Sandreas.hansson@arm.com virtual void recvTimingSnoopReq(PacketPtr pkt); 1608948Sandreas.hansson@arm.com 1618975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 1623738Sstever@eecs.umich.edu 1638948Sandreas.hansson@arm.com virtual Tick recvAtomicSnoop(PacketPtr pkt); 1643738Sstever@eecs.umich.edu 1658948Sandreas.hansson@arm.com virtual void recvFunctionalSnoop(PacketPtr pkt); 1664458Sstever@eecs.umich.edu 1678856Sandreas.hansson@arm.com public: 1688856Sandreas.hansson@arm.com 16910815Sdavid.guillen@arm.com MemSidePort(const std::string &_name, Cache *_cache, 1708856Sandreas.hansson@arm.com const std::string &_label); 1713738Sstever@eecs.umich.edu }; 1723738Sstever@eecs.umich.edu 1732810Srdreslin@umich.edu /** Tag and data Storage */ 17410815Sdavid.guillen@arm.com BaseTags *tags; 1754626Sstever@eecs.umich.edu 1762810Srdreslin@umich.edu /** Prefetcher */ 1773861Sstever@eecs.umich.edu BasePrefetcher *prefetcher; 1782810Srdreslin@umich.edu 1794671Sstever@eecs.umich.edu /** Temporary cache block for occasional transitory use */ 18010815Sdavid.guillen@arm.com CacheBlk *tempBlock; 1814671Sstever@eecs.umich.edu 1822810Srdreslin@umich.edu /** 1835707Shsul@eecs.umich.edu * This cache should allocate a block on a line-sized write miss. 1843860Sstever@eecs.umich.edu */ 1853860Sstever@eecs.umich.edu const bool doFastWrites; 1863860Sstever@eecs.umich.edu 1875875Ssteve.reinhardt@amd.com /** 18810345SCurtis.Dunham@arm.com * Turn line-sized writes into WriteInvalidate transactions. 18910345SCurtis.Dunham@arm.com */ 19010345SCurtis.Dunham@arm.com void promoteWholeLineWrites(PacketPtr pkt); 19110345SCurtis.Dunham@arm.com 19210345SCurtis.Dunham@arm.com /** 1935875Ssteve.reinhardt@amd.com * Notify the prefetcher on every access, not just misses. 1945875Ssteve.reinhardt@amd.com */ 1955875Ssteve.reinhardt@amd.com const bool prefetchOnAccess; 1963860Sstever@eecs.umich.edu 1973860Sstever@eecs.umich.edu /** 1989063SAli.Saidi@ARM.com * @todo this is a temporary workaround until the 4-phase code is committed. 1999063SAli.Saidi@ARM.com * upstream caches need this packet until true is returned, so hold it for 2009063SAli.Saidi@ARM.com * deletion until a subsequent call 2019063SAli.Saidi@ARM.com */ 2029063SAli.Saidi@ARM.com std::vector<PacketPtr> pendingDelete; 2039063SAli.Saidi@ARM.com 2049063SAli.Saidi@ARM.com /** 2053860Sstever@eecs.umich.edu * Does all the processing necessary to perform the provided request. 2063860Sstever@eecs.umich.edu * @param pkt The memory request to perform. 20710048Saminfar@gmail.com * @param blk The cache block to be updated. 2083860Sstever@eecs.umich.edu * @param lat The latency of the access. 2093860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 2105707Shsul@eecs.umich.edu * @return Boolean indicating whether the request was satisfied. 2113860Sstever@eecs.umich.edu */ 21210815Sdavid.guillen@arm.com bool access(PacketPtr pkt, CacheBlk *&blk, 2139288Sandreas.hansson@arm.com Cycles &lat, PacketList &writebacks); 2144219Srdreslin@umich.edu 2154219Srdreslin@umich.edu /** 2164219Srdreslin@umich.edu *Handle doing the Compare and Swap function for SPARC. 2174219Srdreslin@umich.edu */ 21810815Sdavid.guillen@arm.com void cmpAndSwap(CacheBlk *blk, PacketPtr pkt); 2193860Sstever@eecs.umich.edu 2203860Sstever@eecs.umich.edu /** 22110028SGiacomo.Gabrielli@arm.com * Find a block frame for new block at address addr targeting the 22210028SGiacomo.Gabrielli@arm.com * given security space, assuming that the block is not currently 22310028SGiacomo.Gabrielli@arm.com * in the cache. Append writebacks if any to provided packet 22410028SGiacomo.Gabrielli@arm.com * list. Return free block frame. May return NULL if there are 22510028SGiacomo.Gabrielli@arm.com * no replaceable blocks at the moment. 2265350Sstever@gmail.com */ 22710815Sdavid.guillen@arm.com CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks); 2285350Sstever@gmail.com 2295350Sstever@gmail.com /** 2303860Sstever@eecs.umich.edu * Populates a cache block and handles all outstanding requests for the 2313860Sstever@eecs.umich.edu * satisfied fill request. This version takes two memory requests. One 2323860Sstever@eecs.umich.edu * contains the fill data, the other is an optional target to satisfy. 2334626Sstever@eecs.umich.edu * @param pkt The memory request with the fill data. 2343860Sstever@eecs.umich.edu * @param blk The cache block if it already exists. 2353860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 2363860Sstever@eecs.umich.edu * @return Pointer to the new cache block. 2373860Sstever@eecs.umich.edu */ 23810815Sdavid.guillen@arm.com CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk, 2394626Sstever@eecs.umich.edu PacketList &writebacks); 2403860Sstever@eecs.umich.edu 2419548Sandreas.hansson@arm.com 2429548Sandreas.hansson@arm.com /** 2439548Sandreas.hansson@arm.com * Performs the access specified by the request. 2449548Sandreas.hansson@arm.com * @param pkt The request to perform. 2459548Sandreas.hansson@arm.com * @return The result of the access. 2469548Sandreas.hansson@arm.com */ 2479548Sandreas.hansson@arm.com bool recvTimingReq(PacketPtr pkt); 2489548Sandreas.hansson@arm.com 2499548Sandreas.hansson@arm.com /** 25010883Sali.jafri@arm.com * Insert writebacks into the write buffer 25110883Sali.jafri@arm.com */ 25210883Sali.jafri@arm.com void doWritebacks(PacketList& writebacks, Tick forward_time); 25310883Sali.jafri@arm.com 25410883Sali.jafri@arm.com /** 2559548Sandreas.hansson@arm.com * Handles a response (cache line fill/write ack) from the bus. 2569548Sandreas.hansson@arm.com * @param pkt The response packet 2579548Sandreas.hansson@arm.com */ 2589548Sandreas.hansson@arm.com void recvTimingResp(PacketPtr pkt); 2599548Sandreas.hansson@arm.com 2609548Sandreas.hansson@arm.com /** 2619548Sandreas.hansson@arm.com * Snoops bus transactions to maintain coherence. 2629548Sandreas.hansson@arm.com * @param pkt The current bus transaction. 2639548Sandreas.hansson@arm.com */ 2649548Sandreas.hansson@arm.com void recvTimingSnoopReq(PacketPtr pkt); 2659548Sandreas.hansson@arm.com 2669548Sandreas.hansson@arm.com /** 2679548Sandreas.hansson@arm.com * Handle a snoop response. 2689548Sandreas.hansson@arm.com * @param pkt Snoop response packet 2699548Sandreas.hansson@arm.com */ 2709548Sandreas.hansson@arm.com void recvTimingSnoopResp(PacketPtr pkt); 2719548Sandreas.hansson@arm.com 2729548Sandreas.hansson@arm.com /** 2739548Sandreas.hansson@arm.com * Performs the access specified by the request. 2749548Sandreas.hansson@arm.com * @param pkt The request to perform. 2759782Sandreas.hansson@arm.com * @return The number of ticks required for the access. 2769548Sandreas.hansson@arm.com */ 2779782Sandreas.hansson@arm.com Tick recvAtomic(PacketPtr pkt); 2789548Sandreas.hansson@arm.com 2799548Sandreas.hansson@arm.com /** 2809548Sandreas.hansson@arm.com * Snoop for the provided request in the cache and return the estimated 2819782Sandreas.hansson@arm.com * time taken. 2829548Sandreas.hansson@arm.com * @param pkt The memory request to snoop 2839782Sandreas.hansson@arm.com * @return The number of ticks required for the snoop. 2849548Sandreas.hansson@arm.com */ 2859782Sandreas.hansson@arm.com Tick recvAtomicSnoop(PacketPtr pkt); 2869548Sandreas.hansson@arm.com 2879548Sandreas.hansson@arm.com /** 2889548Sandreas.hansson@arm.com * Performs the access specified by the request. 2899548Sandreas.hansson@arm.com * @param pkt The request to perform. 2909548Sandreas.hansson@arm.com * @param fromCpuSide from the CPU side port or the memory side port 2919548Sandreas.hansson@arm.com */ 2929548Sandreas.hansson@arm.com void functionalAccess(PacketPtr pkt, bool fromCpuSide); 2939548Sandreas.hansson@arm.com 29410815Sdavid.guillen@arm.com void satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk, 2957667Ssteve.reinhardt@amd.com bool deferred_response = false, 2967667Ssteve.reinhardt@amd.com bool pending_downgrade = false); 29710815Sdavid.guillen@arm.com bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, CacheBlk *blk); 2984626Sstever@eecs.umich.edu 29910563Sandreas.hansson@arm.com void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 3005319Sstever@gmail.com bool already_copied, bool pending_inval); 3013860Sstever@eecs.umich.edu 3023860Sstever@eecs.umich.edu /** 3033860Sstever@eecs.umich.edu * Sets the blk to the new state. 3043860Sstever@eecs.umich.edu * @param blk The cache block being snooped. 3053860Sstever@eecs.umich.edu * @param new_state The new coherence state for the block. 3063860Sstever@eecs.umich.edu */ 30710815Sdavid.guillen@arm.com void handleSnoop(PacketPtr ptk, CacheBlk *blk, 3085319Sstever@gmail.com bool is_timing, bool is_deferred, bool pending_inval); 3093860Sstever@eecs.umich.edu 3103860Sstever@eecs.umich.edu /** 3113860Sstever@eecs.umich.edu * Create a writeback request for the given block. 3123860Sstever@eecs.umich.edu * @param blk The block to writeback. 3133860Sstever@eecs.umich.edu * @return The writeback request for the block. 3143860Sstever@eecs.umich.edu */ 31510815Sdavid.guillen@arm.com PacketPtr writebackBlk(CacheBlk *blk); 3163860Sstever@eecs.umich.edu 31710883Sali.jafri@arm.com /** 31810883Sali.jafri@arm.com * Create a CleanEvict request for the given block. 31910883Sali.jafri@arm.com * @param blk The block to evict. 32010883Sali.jafri@arm.com * @return The CleanEvict request for the block. 32110883Sali.jafri@arm.com */ 32210883Sali.jafri@arm.com PacketPtr cleanEvictBlk(CacheBlk *blk); 32310883Sali.jafri@arm.com 3249347SAndreas.Sandberg@arm.com 3259347SAndreas.Sandberg@arm.com void memWriteback(); 3269347SAndreas.Sandberg@arm.com void memInvalidate(); 3279347SAndreas.Sandberg@arm.com bool isDirty() const; 3289347SAndreas.Sandberg@arm.com 3299347SAndreas.Sandberg@arm.com /** 3309347SAndreas.Sandberg@arm.com * Cache block visitor that writes back dirty cache blocks using 3319347SAndreas.Sandberg@arm.com * functional writes. 3329347SAndreas.Sandberg@arm.com * 3339347SAndreas.Sandberg@arm.com * \return Always returns true. 3349347SAndreas.Sandberg@arm.com */ 33510815Sdavid.guillen@arm.com bool writebackVisitor(CacheBlk &blk); 3369347SAndreas.Sandberg@arm.com /** 3379347SAndreas.Sandberg@arm.com * Cache block visitor that invalidates all blocks in the cache. 3389347SAndreas.Sandberg@arm.com * 3399347SAndreas.Sandberg@arm.com * @warn Dirty cache lines will not be written back to memory. 3409347SAndreas.Sandberg@arm.com * 3419347SAndreas.Sandberg@arm.com * \return Always returns true. 3429347SAndreas.Sandberg@arm.com */ 34310815Sdavid.guillen@arm.com bool invalidateVisitor(CacheBlk &blk); 3449347SAndreas.Sandberg@arm.com 3459445SAndreas.Sandberg@ARM.com /** 3462982Sstever@eecs.umich.edu * Squash all requests associated with specified thread. 3472810Srdreslin@umich.edu * intended for use by I-cache. 3482982Sstever@eecs.umich.edu * @param threadNum The thread to squash. 3492810Srdreslin@umich.edu */ 3504626Sstever@eecs.umich.edu void squash(int threadNum); 3514626Sstever@eecs.umich.edu 3524626Sstever@eecs.umich.edu /** 3535365Sstever@gmail.com * Generate an appropriate downstream bus request packet for the 3545365Sstever@gmail.com * given parameters. 3555365Sstever@gmail.com * @param cpu_pkt The upstream request that needs to be satisfied. 3565365Sstever@gmail.com * @param blk The block currently in the cache corresponding to 3575365Sstever@gmail.com * cpu_pkt (NULL if none). 3585365Sstever@gmail.com * @param needsExclusive Indicates that an exclusive copy is required 3595365Sstever@gmail.com * even if the request in cpu_pkt doesn't indicate that. 3605365Sstever@gmail.com * @return A new Packet containing the request, or NULL if the 3615365Sstever@gmail.com * current request in cpu_pkt should just be forwarded on. 3624626Sstever@eecs.umich.edu */ 36310815Sdavid.guillen@arm.com PacketPtr getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk, 3649529Sandreas.hansson@arm.com bool needsExclusive) const; 3655365Sstever@gmail.com 3665365Sstever@gmail.com /** 3675365Sstever@gmail.com * Return the next MSHR to service, either a pending miss from the 3685365Sstever@gmail.com * mshrQueue, a buffered write from the write buffer, or something 3695365Sstever@gmail.com * from the prefetcher. This function is responsible for 3705365Sstever@gmail.com * prioritizing among those sources on the fly. 3715365Sstever@gmail.com */ 3724626Sstever@eecs.umich.edu MSHR *getNextMSHR(); 3735365Sstever@gmail.com 3745365Sstever@gmail.com /** 37510883Sali.jafri@arm.com * Send up a snoop request and find cached copies. If cached copies are 37610883Sali.jafri@arm.com * found, set the BLOCK_CACHED flag in pkt. 37710883Sali.jafri@arm.com */ 37810883Sali.jafri@arm.com bool isCachedAbove(const PacketPtr pkt) const; 37910883Sali.jafri@arm.com 38010883Sali.jafri@arm.com /** 3815365Sstever@gmail.com * Selects an outstanding request to service. Called when the 3825365Sstever@gmail.com * cache gets granted the downstream bus in timing mode. 3835365Sstever@gmail.com * @return The request to service, NULL if none found. 3845365Sstever@gmail.com */ 3854628Sstever@eecs.umich.edu PacketPtr getTimingPacket(); 3864626Sstever@eecs.umich.edu 3874626Sstever@eecs.umich.edu /** 38810679Sandreas.hansson@arm.com * Marks a request as in service (sent on the bus). This can have 38910679Sandreas.hansson@arm.com * side effect since storage for no response commands is 39010679Sandreas.hansson@arm.com * deallocated once they are successfully sent. Also remember if 39110679Sandreas.hansson@arm.com * we are expecting a dirty response from another cache, 39210679Sandreas.hansson@arm.com * effectively making this MSHR the ordering point. 3934626Sstever@eecs.umich.edu */ 39410679Sandreas.hansson@arm.com void markInService(MSHR *mshr, bool pending_dirty_resp); 3954626Sstever@eecs.umich.edu 3964626Sstever@eecs.umich.edu /** 3974626Sstever@eecs.umich.edu * Return whether there are any outstanding misses. 3984626Sstever@eecs.umich.edu */ 3994626Sstever@eecs.umich.edu bool outstandingMisses() const 4002810Srdreslin@umich.edu { 4014626Sstever@eecs.umich.edu return mshrQueue.allocated != 0; 4022810Srdreslin@umich.edu } 4032810Srdreslin@umich.edu 40410028SGiacomo.Gabrielli@arm.com CacheBlk *findBlock(Addr addr, bool is_secure) const { 40510028SGiacomo.Gabrielli@arm.com return tags->findBlock(addr, is_secure); 4062810Srdreslin@umich.edu } 4072810Srdreslin@umich.edu 40810028SGiacomo.Gabrielli@arm.com bool inCache(Addr addr, bool is_secure) const { 40910028SGiacomo.Gabrielli@arm.com return (tags->findBlock(addr, is_secure) != 0); 4103861Sstever@eecs.umich.edu } 4113861Sstever@eecs.umich.edu 41210028SGiacomo.Gabrielli@arm.com bool inMissQueue(Addr addr, bool is_secure) const { 41310028SGiacomo.Gabrielli@arm.com return (mshrQueue.findMatch(addr, is_secure) != 0); 4143861Sstever@eecs.umich.edu } 4155875Ssteve.reinhardt@amd.com 4165875Ssteve.reinhardt@amd.com /** 4175875Ssteve.reinhardt@amd.com * Find next request ready time from among possible sources. 4185875Ssteve.reinhardt@amd.com */ 4199529Sandreas.hansson@arm.com Tick nextMSHRReadyTime() const; 4209529Sandreas.hansson@arm.com 4219529Sandreas.hansson@arm.com public: 4229529Sandreas.hansson@arm.com /** Instantiates a basic cache object. */ 42311053Sandreas.hansson@arm.com Cache(const CacheParams *p); 4249529Sandreas.hansson@arm.com 4259813Srioshering@gmail.com /** Non-default destructor is needed to deallocate memory. */ 4269813Srioshering@gmail.com virtual ~Cache(); 4279813Srioshering@gmail.com 4289529Sandreas.hansson@arm.com void regStats(); 4298985SAli.Saidi@ARM.com 4308985SAli.Saidi@ARM.com /** serialize the state of the caches 4318985SAli.Saidi@ARM.com * We currently don't support checkpointing cache state, so this panics. 4328985SAli.Saidi@ARM.com */ 43310905Sandreas.sandberg@arm.com void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 43410905Sandreas.sandberg@arm.com void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; 4352810Srdreslin@umich.edu}; 4362810Srdreslin@umich.edu 43710815Sdavid.guillen@arm.com/** 43810815Sdavid.guillen@arm.com * Wrap a method and present it as a cache block visitor. 43910815Sdavid.guillen@arm.com * 44010815Sdavid.guillen@arm.com * For example the forEachBlk method in the tag arrays expects a 44110815Sdavid.guillen@arm.com * callable object/function as their parameter. This class wraps a 44210815Sdavid.guillen@arm.com * method in an object and presents callable object that adheres to 44310815Sdavid.guillen@arm.com * the cache block visitor protocol. 44410815Sdavid.guillen@arm.com */ 44510815Sdavid.guillen@arm.comclass CacheBlkVisitorWrapper : public CacheBlkVisitor 44610815Sdavid.guillen@arm.com{ 44710815Sdavid.guillen@arm.com public: 44810815Sdavid.guillen@arm.com typedef bool (Cache::*VisitorPtr)(CacheBlk &blk); 44910815Sdavid.guillen@arm.com 45010815Sdavid.guillen@arm.com CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor) 45110815Sdavid.guillen@arm.com : cache(_cache), visitor(_visitor) {} 45210815Sdavid.guillen@arm.com 45310815Sdavid.guillen@arm.com bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE { 45410815Sdavid.guillen@arm.com return (cache.*visitor)(blk); 45510815Sdavid.guillen@arm.com } 45610815Sdavid.guillen@arm.com 45710815Sdavid.guillen@arm.com private: 45810815Sdavid.guillen@arm.com Cache &cache; 45910815Sdavid.guillen@arm.com VisitorPtr visitor; 46010815Sdavid.guillen@arm.com}; 46110815Sdavid.guillen@arm.com 46210815Sdavid.guillen@arm.com/** 46310815Sdavid.guillen@arm.com * Cache block visitor that determines if there are dirty blocks in a 46410815Sdavid.guillen@arm.com * cache. 46510815Sdavid.guillen@arm.com * 46610815Sdavid.guillen@arm.com * Use with the forEachBlk method in the tag array to determine if the 46710815Sdavid.guillen@arm.com * array contains dirty blocks. 46810815Sdavid.guillen@arm.com */ 46910815Sdavid.guillen@arm.comclass CacheBlkIsDirtyVisitor : public CacheBlkVisitor 47010815Sdavid.guillen@arm.com{ 47110815Sdavid.guillen@arm.com public: 47210815Sdavid.guillen@arm.com CacheBlkIsDirtyVisitor() 47310815Sdavid.guillen@arm.com : _isDirty(false) {} 47410815Sdavid.guillen@arm.com 47510815Sdavid.guillen@arm.com bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE { 47610815Sdavid.guillen@arm.com if (blk.isDirty()) { 47710815Sdavid.guillen@arm.com _isDirty = true; 47810815Sdavid.guillen@arm.com return false; 47910815Sdavid.guillen@arm.com } else { 48010815Sdavid.guillen@arm.com return true; 48110815Sdavid.guillen@arm.com } 48210815Sdavid.guillen@arm.com } 48310815Sdavid.guillen@arm.com 48410815Sdavid.guillen@arm.com /** 48510815Sdavid.guillen@arm.com * Does the array contain a dirty line? 48610815Sdavid.guillen@arm.com * 48710815Sdavid.guillen@arm.com * \return true if yes, false otherwise. 48810815Sdavid.guillen@arm.com */ 48910815Sdavid.guillen@arm.com bool isDirty() const { return _isDirty; }; 49010815Sdavid.guillen@arm.com 49110815Sdavid.guillen@arm.com private: 49210815Sdavid.guillen@arm.com bool _isDirty; 49310815Sdavid.guillen@arm.com}; 49410815Sdavid.guillen@arm.com 49511051Sandreas.hansson@arm.com#endif // __MEM_CACHE_CACHE_HH__ 496