cache.hh revision 10883
12623SN/A/* 28948Sandreas.hansson@arm.com * Copyright (c) 2012-2014 ARM Limited 37725SAli.Saidi@ARM.com * All rights reserved. 47725SAli.Saidi@ARM.com * 57725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137725SAli.Saidi@ARM.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Erik Hallnor 412623SN/A * Dave Greene 422623SN/A * Steve Reinhardt 433170Sstever@eecs.umich.edu * Ron Dreslinski 448105Sgblack@eecs.umich.edu * Andreas Hansson 452623SN/A */ 464040Ssaidi@eecs.umich.edu 476658Snate@binkert.org/** 488229Snate@binkert.org * @file 492623SN/A * Describes a cache based on template policies. 508232Snate@binkert.org */ 519152Satgutier@umich.edu 528232Snate@binkert.org#ifndef __CACHE_HH__ 538232Snate@binkert.org#define __CACHE_HH__ 543348Sbinkertn@umich.edu 553348Sbinkertn@umich.edu#include "base/misc.hh" // fatal, panic, and warn 564762Snate@binkert.org#include "mem/cache/base.hh" 577678Sgblack@eecs.umich.edu#include "mem/cache/blk.hh" 588779Sgblack@eecs.umich.edu#include "mem/cache/mshr.hh" 592901Ssaidi@eecs.umich.edu#include "mem/cache/tags/base.hh" 602623SN/A#include "sim/eventq.hh" 612623SN/A 622623SN/A//Forward decleration 632623SN/Aclass BasePrefetcher; 642623SN/A 652623SN/A/** 662623SN/A * A template-policy based cache. The behavior of the cache can be altered by 672623SN/A * supplying different template policies. TagStore handles all tag and data 688921Sandreas.hansson@arm.com * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System" 698921Sandreas.hansson@arm.com */ 708921Sandreas.hansson@arm.comclass Cache : public BaseCache 718921Sandreas.hansson@arm.com{ 729058Satgutier@umich.edu public: 738779Sgblack@eecs.umich.edu 748779Sgblack@eecs.umich.edu /** A typedef for a list of CacheBlk pointers. */ 758779Sgblack@eecs.umich.edu typedef std::list<CacheBlk*> BlkList; 768779Sgblack@eecs.umich.edu 778779Sgblack@eecs.umich.edu protected: 782623SN/A 792623SN/A /** 802623SN/A * The CPU-side port extends the base cache slave port with access 812623SN/A * functions for functional, atomic and timing requests. 828707Sandreas.hansson@arm.com */ 832948Ssaidi@eecs.umich.edu class CpuSidePort : public CacheSlavePort 842948Ssaidi@eecs.umich.edu { 855606Snate@binkert.org private: 862948Ssaidi@eecs.umich.edu 872948Ssaidi@eecs.umich.edu // a pointer to our specific cache implementation 885529Snate@binkert.org Cache *cache; 898707Sandreas.hansson@arm.com 909179Sandreas.hansson@arm.com protected: 919179Sandreas.hansson@arm.com 922623SN/A virtual bool recvTimingSnoopResp(PacketPtr pkt); 932623SN/A 943647Srdreslin@umich.edu virtual bool recvTimingReq(PacketPtr pkt); 952901Ssaidi@eecs.umich.edu 967897Shestness@cs.utexas.edu virtual Tick recvAtomic(PacketPtr pkt); 972623SN/A 982623SN/A virtual void recvFunctional(PacketPtr pkt); 992623SN/A 1002623SN/A virtual AddrRangeList getAddrRanges() const; 1012623SN/A 1022623SN/A public: 1032623SN/A 1042623SN/A CpuSidePort(const std::string &_name, Cache *_cache, 1052623SN/A const std::string &_label); 1062623SN/A 1072915Sktlim@umich.edu }; 1082915Sktlim@umich.edu 1092623SN/A /** 1102623SN/A * Override the default behaviour of sendDeferredPacket to enable 1112623SN/A * the memory-side cache port to also send requests based on the 1122623SN/A * current MSHR status. This queue has a pointer to our specific 1132623SN/A * cache implementation and is used by the MemSidePort. 1142623SN/A */ 1152915Sktlim@umich.edu class CacheReqPacketQueue : public ReqPacketQueue 1162915Sktlim@umich.edu { 1172623SN/A 1182798Sktlim@umich.edu protected: 1192798Sktlim@umich.edu 1202901Ssaidi@eecs.umich.edu Cache &cache; 1212839Sktlim@umich.edu SnoopRespPacketQueue &snoopRespQueue; 1222798Sktlim@umich.edu 1232839Sktlim@umich.edu public: 1242798Sktlim@umich.edu 1255496Ssaidi@eecs.umich.edu CacheReqPacketQueue(Cache &cache, MasterPort &port, 1262901Ssaidi@eecs.umich.edu SnoopRespPacketQueue &snoop_resp_queue, 1272901Ssaidi@eecs.umich.edu const std::string &label) : 1282798Sktlim@umich.edu ReqPacketQueue(cache, port, label), cache(cache), 1292839Sktlim@umich.edu snoopRespQueue(snoop_resp_queue) { } 1302839Sktlim@umich.edu 1319152Satgutier@umich.edu /** 1322901Ssaidi@eecs.umich.edu * Override the normal sendDeferredPacket and do not only 1332798Sktlim@umich.edu * consider the transmit list (used for responses), but also 1342623SN/A * requests. 1352623SN/A */ 1362623SN/A virtual void sendDeferredPacket(); 1372798Sktlim@umich.edu 1382623SN/A }; 1395221Ssaidi@eecs.umich.edu 1402798Sktlim@umich.edu /** 1414762Snate@binkert.org * The memory-side port extends the base cache master port with 1423201Shsul@eecs.umich.edu * access functions for functional, atomic and timing snoops. 1435710Scws3k@cs.virginia.edu */ 1445710Scws3k@cs.virginia.edu class MemSidePort : public CacheMasterPort 1452915Sktlim@umich.edu { 1465710Scws3k@cs.virginia.edu private: 1472623SN/A 1482798Sktlim@umich.edu /** The cache-specific queue. */ 1492901Ssaidi@eecs.umich.edu CacheReqPacketQueue _reqQueue; 1502798Sktlim@umich.edu 1512798Sktlim@umich.edu SnoopRespPacketQueue _snoopRespQueue; 1522798Sktlim@umich.edu 1532798Sktlim@umich.edu // a pointer to our specific cache implementation 1542798Sktlim@umich.edu Cache *cache; 1555496Ssaidi@eecs.umich.edu 1562798Sktlim@umich.edu protected: 1579179Sandreas.hansson@arm.com 1582867Sktlim@umich.edu virtual void recvTimingSnoopReq(PacketPtr pkt); 1592867Sktlim@umich.edu 1602867Sktlim@umich.edu virtual bool recvTimingResp(PacketPtr pkt); 1615710Scws3k@cs.virginia.edu 1625606Snate@binkert.org virtual Tick recvAtomicSnoop(PacketPtr pkt); 1632623SN/A 1642623SN/A virtual void recvFunctionalSnoop(PacketPtr pkt); 1652623SN/A 1662623SN/A public: 1672623SN/A 1682623SN/A MemSidePort(const std::string &_name, Cache *_cache, 1698737Skoansin.tan@gmail.com const std::string &_label); 1702623SN/A }; 1712680Sktlim@umich.edu 1722623SN/A /** Tag and data Storage */ 1732680Sktlim@umich.edu BaseTags *tags; 1742680Sktlim@umich.edu 1752680Sktlim@umich.edu /** Prefetcher */ 1762623SN/A BasePrefetcher *prefetcher; 1772623SN/A 1782623SN/A /** Temporary cache block for occasional transitory use */ 1792623SN/A CacheBlk *tempBlock; 1803201Shsul@eecs.umich.edu 1813201Shsul@eecs.umich.edu /** 1823201Shsul@eecs.umich.edu * This cache should allocate a block on a line-sized write miss. 1833201Shsul@eecs.umich.edu */ 1845169Ssaidi@eecs.umich.edu const bool doFastWrites; 1859179Sandreas.hansson@arm.com 1862623SN/A /** 1872623SN/A * Turn line-sized writes into WriteInvalidate transactions. 1882623SN/A */ 1892623SN/A void promoteWholeLineWrites(PacketPtr pkt); 1909180Sandreas.hansson@arm.com 1912623SN/A /** 1925221Ssaidi@eecs.umich.edu * Notify the prefetcher on every access, not just misses. 1935221Ssaidi@eecs.umich.edu */ 1942623SN/A const bool prefetchOnAccess; 1952683Sktlim@umich.edu 1962623SN/A /** 1972623SN/A * @todo this is a temporary workaround until the 4-phase code is committed. 1982623SN/A * upstream caches need this packet until true is returned, so hold it for 1992623SN/A * deletion until a subsequent call 2002623SN/A */ 2013686Sktlim@umich.edu std::vector<PacketPtr> pendingDelete; 2022623SN/A 2039179Sandreas.hansson@arm.com /** 2042623SN/A * Does all the processing necessary to perform the provided request. 2052623SN/A * @param pkt The memory request to perform. 2062623SN/A * @param blk The cache block to be updated. 2072623SN/A * @param lat The latency of the access. 2088737Skoansin.tan@gmail.com * @param writebacks List for any writebacks that need to be performed. 2092623SN/A * @return Boolean indicating whether the request was satisfied. 2105221Ssaidi@eecs.umich.edu */ 2115221Ssaidi@eecs.umich.edu bool access(PacketPtr pkt, CacheBlk *&blk, 2122623SN/A Cycles &lat, PacketList &writebacks); 2132683Sktlim@umich.edu 2142623SN/A /** 2156043Sgblack@eecs.umich.edu *Handle doing the Compare and Swap function for SPARC. 2166043Sgblack@eecs.umich.edu */ 2176043Sgblack@eecs.umich.edu void cmpAndSwap(CacheBlk *blk, PacketPtr pkt); 2182644Sstever@eecs.umich.edu 2192623SN/A /** 2202644Sstever@eecs.umich.edu * Find a block frame for new block at address addr targeting the 2212644Sstever@eecs.umich.edu * given security space, assuming that the block is not currently 2222623SN/A * in the cache. Append writebacks if any to provided packet 2232623SN/A * list. Return free block frame. May return NULL if there are 2242623SN/A * no replaceable blocks at the moment. 2252623SN/A */ 2262623SN/A CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks); 2275728Sgblack@eecs.umich.edu 2285728Sgblack@eecs.umich.edu /** 2295728Sgblack@eecs.umich.edu * Populates a cache block and handles all outstanding requests for the 2305728Sgblack@eecs.umich.edu * satisfied fill request. This version takes two memory requests. One 2318105Sgblack@eecs.umich.edu * contains the fill data, the other is an optional target to satisfy. 2329180Sandreas.hansson@arm.com * @param pkt The memory request with the fill data. 2339179Sandreas.hansson@arm.com * @param blk The cache block if it already exists. 2345728Sgblack@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 2355728Sgblack@eecs.umich.edu * @return Pointer to the new cache block. 2368975Sandreas.hansson@arm.com */ 2375728Sgblack@eecs.umich.edu CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk, 2385728Sgblack@eecs.umich.edu PacketList &writebacks); 2395728Sgblack@eecs.umich.edu 2405728Sgblack@eecs.umich.edu 2415728Sgblack@eecs.umich.edu /** 2425728Sgblack@eecs.umich.edu * Performs the access specified by the request. 2435728Sgblack@eecs.umich.edu * @param pkt The request to perform. 2445728Sgblack@eecs.umich.edu * @return The result of the access. 2455728Sgblack@eecs.umich.edu */ 2462623SN/A bool recvTimingReq(PacketPtr pkt); 2475894Sgblack@eecs.umich.edu 2486973Stjones1@inf.ed.ac.uk /** 2496973Stjones1@inf.ed.ac.uk * Insert writebacks into the write buffer 2505744Sgblack@eecs.umich.edu */ 2515894Sgblack@eecs.umich.edu void doWritebacks(PacketList& writebacks, Tick forward_time); 2525894Sgblack@eecs.umich.edu 2537691SAli.Saidi@ARM.com /** 2545894Sgblack@eecs.umich.edu * Handles a response (cache line fill/write ack) from the bus. 2555894Sgblack@eecs.umich.edu * @param pkt The response packet 2565894Sgblack@eecs.umich.edu */ 2575894Sgblack@eecs.umich.edu void recvTimingResp(PacketPtr pkt); 2585894Sgblack@eecs.umich.edu 2595894Sgblack@eecs.umich.edu /** 2605894Sgblack@eecs.umich.edu * Snoops bus transactions to maintain coherence. 2615894Sgblack@eecs.umich.edu * @param pkt The current bus transaction. 2625894Sgblack@eecs.umich.edu */ 2636102Sgblack@eecs.umich.edu void recvTimingSnoopReq(PacketPtr pkt); 2645894Sgblack@eecs.umich.edu 2655894Sgblack@eecs.umich.edu /** 2665894Sgblack@eecs.umich.edu * Handle a snoop response. 2675894Sgblack@eecs.umich.edu * @param pkt Snoop response packet 2685894Sgblack@eecs.umich.edu */ 2695894Sgblack@eecs.umich.edu void recvTimingSnoopResp(PacketPtr pkt); 2705894Sgblack@eecs.umich.edu 2715894Sgblack@eecs.umich.edu /** 2725894Sgblack@eecs.umich.edu * Performs the access specified by the request. 2735894Sgblack@eecs.umich.edu * @param pkt The request to perform. 2745894Sgblack@eecs.umich.edu * @return The number of ticks required for the access. 2755894Sgblack@eecs.umich.edu */ 2765894Sgblack@eecs.umich.edu Tick recvAtomic(PacketPtr pkt); 2775894Sgblack@eecs.umich.edu 2785894Sgblack@eecs.umich.edu /** 2795894Sgblack@eecs.umich.edu * Snoop for the provided request in the cache and return the estimated 2805894Sgblack@eecs.umich.edu * time taken. 2816973Stjones1@inf.ed.ac.uk * @param pkt The memory request to snoop 2826973Stjones1@inf.ed.ac.uk * @return The number of ticks required for the snoop. 2835894Sgblack@eecs.umich.edu */ 2845894Sgblack@eecs.umich.edu Tick recvAtomicSnoop(PacketPtr pkt); 2855894Sgblack@eecs.umich.edu 2865894Sgblack@eecs.umich.edu /** 2875894Sgblack@eecs.umich.edu * Performs the access specified by the request. 2885894Sgblack@eecs.umich.edu * @param pkt The request to perform. 2895894Sgblack@eecs.umich.edu * @param fromCpuSide from the CPU side port or the memory side port 2905894Sgblack@eecs.umich.edu */ 2917911Shestness@cs.utexas.edu void functionalAccess(PacketPtr pkt, bool fromCpuSide); 2927911Shestness@cs.utexas.edu 2935894Sgblack@eecs.umich.edu void satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk, 2945894Sgblack@eecs.umich.edu bool deferred_response = false, 2957911Shestness@cs.utexas.edu bool pending_downgrade = false); 2967911Shestness@cs.utexas.edu bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, CacheBlk *blk); 2975894Sgblack@eecs.umich.edu 2985894Sgblack@eecs.umich.edu void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 2995894Sgblack@eecs.umich.edu bool already_copied, bool pending_inval); 3005894Sgblack@eecs.umich.edu 3015894Sgblack@eecs.umich.edu /** 3025894Sgblack@eecs.umich.edu * Sets the blk to the new state. 3037911Shestness@cs.utexas.edu * @param blk The cache block being snooped. 3047911Shestness@cs.utexas.edu * @param new_state The new coherence state for the block. 3055894Sgblack@eecs.umich.edu */ 3065894Sgblack@eecs.umich.edu void handleSnoop(PacketPtr ptk, CacheBlk *blk, 3075894Sgblack@eecs.umich.edu bool is_timing, bool is_deferred, bool pending_inval); 3087911Shestness@cs.utexas.edu 3097911Shestness@cs.utexas.edu /** 3105894Sgblack@eecs.umich.edu * Create a writeback request for the given block. 3115894Sgblack@eecs.umich.edu * @param blk The block to writeback. 3125894Sgblack@eecs.umich.edu * @return The writeback request for the block. 3135894Sgblack@eecs.umich.edu */ 3145894Sgblack@eecs.umich.edu PacketPtr writebackBlk(CacheBlk *blk); 3155894Sgblack@eecs.umich.edu 3165894Sgblack@eecs.umich.edu /** 3175894Sgblack@eecs.umich.edu * Create a CleanEvict request for the given block. 3185894Sgblack@eecs.umich.edu * @param blk The block to evict. 3195894Sgblack@eecs.umich.edu * @return The CleanEvict request for the block. 3206739Sgblack@eecs.umich.edu */ 3216739Sgblack@eecs.umich.edu PacketPtr cleanEvictBlk(CacheBlk *blk); 3229179Sandreas.hansson@arm.com 3239179Sandreas.hansson@arm.com 3245894Sgblack@eecs.umich.edu void memWriteback(); 3255894Sgblack@eecs.umich.edu void memInvalidate(); 3265894Sgblack@eecs.umich.edu bool isDirty() const; 3275894Sgblack@eecs.umich.edu 3285894Sgblack@eecs.umich.edu /** 3295744Sgblack@eecs.umich.edu * Cache block visitor that writes back dirty cache blocks using 3305744Sgblack@eecs.umich.edu * functional writes. 3315894Sgblack@eecs.umich.edu * 3325894Sgblack@eecs.umich.edu * \return Always returns true. 3335894Sgblack@eecs.umich.edu */ 3345894Sgblack@eecs.umich.edu bool writebackVisitor(CacheBlk &blk); 3355894Sgblack@eecs.umich.edu /** 3365894Sgblack@eecs.umich.edu * Cache block visitor that invalidates all blocks in the cache. 3375894Sgblack@eecs.umich.edu * 3385894Sgblack@eecs.umich.edu * @warn Dirty cache lines will not be written back to memory. 3395894Sgblack@eecs.umich.edu * 3405894Sgblack@eecs.umich.edu * \return Always returns true. 3415894Sgblack@eecs.umich.edu */ 3425894Sgblack@eecs.umich.edu bool invalidateVisitor(CacheBlk &blk); 3435894Sgblack@eecs.umich.edu 3445894Sgblack@eecs.umich.edu /** 3455894Sgblack@eecs.umich.edu * Squash all requests associated with specified thread. 3465894Sgblack@eecs.umich.edu * intended for use by I-cache. 3476102Sgblack@eecs.umich.edu * @param threadNum The thread to squash. 3485894Sgblack@eecs.umich.edu */ 3495894Sgblack@eecs.umich.edu void squash(int threadNum); 3505894Sgblack@eecs.umich.edu 3516102Sgblack@eecs.umich.edu /** 3525894Sgblack@eecs.umich.edu * Generate an appropriate downstream bus request packet for the 3535894Sgblack@eecs.umich.edu * given parameters. 3545894Sgblack@eecs.umich.edu * @param cpu_pkt The upstream request that needs to be satisfied. 3555894Sgblack@eecs.umich.edu * @param blk The block currently in the cache corresponding to 3565894Sgblack@eecs.umich.edu * cpu_pkt (NULL if none). 3578949Sandreas.hansson@arm.com * @param needsExclusive Indicates that an exclusive copy is required 3585894Sgblack@eecs.umich.edu * even if the request in cpu_pkt doesn't indicate that. 3595894Sgblack@eecs.umich.edu * @return A new Packet containing the request, or NULL if the 3605894Sgblack@eecs.umich.edu * current request in cpu_pkt should just be forwarded on. 3615894Sgblack@eecs.umich.edu */ 3625894Sgblack@eecs.umich.edu PacketPtr getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk, 3635894Sgblack@eecs.umich.edu bool needsExclusive) const; 3645894Sgblack@eecs.umich.edu 3655894Sgblack@eecs.umich.edu /** 3665894Sgblack@eecs.umich.edu * Return the next MSHR to service, either a pending miss from the 3678105Sgblack@eecs.umich.edu * mshrQueue, a buffered write from the write buffer, or something 3685744Sgblack@eecs.umich.edu * from the prefetcher. This function is responsible for 3695894Sgblack@eecs.umich.edu * prioritizing among those sources on the fly. 3705894Sgblack@eecs.umich.edu */ 3715894Sgblack@eecs.umich.edu MSHR *getNextMSHR(); 3725894Sgblack@eecs.umich.edu 3735894Sgblack@eecs.umich.edu /** 3745894Sgblack@eecs.umich.edu * Send up a snoop request and find cached copies. If cached copies are 3755894Sgblack@eecs.umich.edu * found, set the BLOCK_CACHED flag in pkt. 3765894Sgblack@eecs.umich.edu */ 3778832SAli.Saidi@ARM.com bool isCachedAbove(const PacketPtr pkt) const; 3788949Sandreas.hansson@arm.com 3795744Sgblack@eecs.umich.edu /** 3807691SAli.Saidi@ARM.com * Selects an outstanding request to service. Called when the 3815744Sgblack@eecs.umich.edu * cache gets granted the downstream bus in timing mode. 3825744Sgblack@eecs.umich.edu * @return The request to service, NULL if none found. 3835744Sgblack@eecs.umich.edu */ 3845744Sgblack@eecs.umich.edu PacketPtr getTimingPacket(); 3855744Sgblack@eecs.umich.edu 3865744Sgblack@eecs.umich.edu /** 3875744Sgblack@eecs.umich.edu * Marks a request as in service (sent on the bus). This can have 3885744Sgblack@eecs.umich.edu * side effect since storage for no response commands is 3895744Sgblack@eecs.umich.edu * deallocated once they are successfully sent. Also remember if 3905744Sgblack@eecs.umich.edu * we are expecting a dirty response from another cache, 3915744Sgblack@eecs.umich.edu * effectively making this MSHR the ordering point. 3925744Sgblack@eecs.umich.edu */ 3932623SN/A void markInService(MSHR *mshr, bool pending_dirty_resp); 3948444Sgblack@eecs.umich.edu 3958444Sgblack@eecs.umich.edu /** 3962623SN/A * Return whether there are any outstanding misses. 3975728Sgblack@eecs.umich.edu */ 3985728Sgblack@eecs.umich.edu bool outstandingMisses() const 3996221Snate@binkert.org { 4007720Sgblack@eecs.umich.edu return mshrQueue.allocated != 0; 4016227Snate@binkert.org } 4026973Stjones1@inf.ed.ac.uk 4032623SN/A CacheBlk *findBlock(Addr addr, bool is_secure) const { 4047045Ssteve.reinhardt@amd.com return tags->findBlock(addr, is_secure); 4057045Ssteve.reinhardt@amd.com } 4067045Ssteve.reinhardt@amd.com 4077045Ssteve.reinhardt@amd.com bool inCache(Addr addr, bool is_secure) const { 4087520Sgblack@eecs.umich.edu return (tags->findBlock(addr, is_secure) != 0); 4098832SAli.Saidi@ARM.com } 4105728Sgblack@eecs.umich.edu 4117520Sgblack@eecs.umich.edu bool inMissQueue(Addr addr, bool is_secure) const { 4125744Sgblack@eecs.umich.edu return (mshrQueue.findMatch(addr, is_secure) != 0); 4135728Sgblack@eecs.umich.edu } 4145894Sgblack@eecs.umich.edu 4155744Sgblack@eecs.umich.edu /** 4165894Sgblack@eecs.umich.edu * Find next request ready time from among possible sources. 4176102Sgblack@eecs.umich.edu */ 4185894Sgblack@eecs.umich.edu Tick nextMSHRReadyTime() const; 4195894Sgblack@eecs.umich.edu 4206973Stjones1@inf.ed.ac.uk public: 4217520Sgblack@eecs.umich.edu /** Instantiates a basic cache object. */ 4226973Stjones1@inf.ed.ac.uk Cache(const Params *p); 4238486Sgblack@eecs.umich.edu 4248486Sgblack@eecs.umich.edu /** Non-default destructor is needed to deallocate memory. */ 4258486Sgblack@eecs.umich.edu virtual ~Cache(); 4268486Sgblack@eecs.umich.edu 4276973Stjones1@inf.ed.ac.uk void regStats(); 4286973Stjones1@inf.ed.ac.uk 4296973Stjones1@inf.ed.ac.uk /** serialize the state of the caches 4305744Sgblack@eecs.umich.edu * We currently don't support checkpointing cache state, so this panics. 4316973Stjones1@inf.ed.ac.uk */ 4327520Sgblack@eecs.umich.edu virtual void serialize(std::ostream &os); 4338486Sgblack@eecs.umich.edu void unserialize(Checkpoint *cp, const std::string §ion); 4348486Sgblack@eecs.umich.edu}; 4356973Stjones1@inf.ed.ac.uk 4362623SN/A/** 4372623SN/A * Wrap a method and present it as a cache block visitor. 4385728Sgblack@eecs.umich.edu * 4392623SN/A * For example the forEachBlk method in the tag arrays expects a 4402623SN/A * callable object/function as their parameter. This class wraps a 4415728Sgblack@eecs.umich.edu * method in an object and presents callable object that adheres to 4425728Sgblack@eecs.umich.edu * the cache block visitor protocol. 4435728Sgblack@eecs.umich.edu */ 4445728Sgblack@eecs.umich.educlass CacheBlkVisitorWrapper : public CacheBlkVisitor 4458105Sgblack@eecs.umich.edu{ 4469180Sandreas.hansson@arm.com public: 4479179Sandreas.hansson@arm.com typedef bool (Cache::*VisitorPtr)(CacheBlk &blk); 4485728Sgblack@eecs.umich.edu 4495728Sgblack@eecs.umich.edu CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor) 4508975Sandreas.hansson@arm.com : cache(_cache), visitor(_visitor) {} 4515728Sgblack@eecs.umich.edu 4525728Sgblack@eecs.umich.edu bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE { 4535728Sgblack@eecs.umich.edu return (cache.*visitor)(blk); 4545728Sgblack@eecs.umich.edu } 4555728Sgblack@eecs.umich.edu 4565728Sgblack@eecs.umich.edu private: 4575728Sgblack@eecs.umich.edu Cache &cache; 4585728Sgblack@eecs.umich.edu VisitorPtr visitor; 4592623SN/A}; 4602623SN/A 4618444Sgblack@eecs.umich.edu/** 4628444Sgblack@eecs.umich.edu * Cache block visitor that determines if there are dirty blocks in a 4632623SN/A * cache. 4648443Sgblack@eecs.umich.edu * 4658443Sgblack@eecs.umich.edu * Use with the forEachBlk method in the tag array to determine if the 4668443Sgblack@eecs.umich.edu * array contains dirty blocks. 4675728Sgblack@eecs.umich.edu */ 4686221Snate@binkert.orgclass CacheBlkIsDirtyVisitor : public CacheBlkVisitor 4697720Sgblack@eecs.umich.edu{ 4706227Snate@binkert.org public: 4716973Stjones1@inf.ed.ac.uk CacheBlkIsDirtyVisitor() 4723169Sstever@eecs.umich.edu : _isDirty(false) {} 4737045Ssteve.reinhardt@amd.com 4747045Ssteve.reinhardt@amd.com bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE { 4757045Ssteve.reinhardt@amd.com if (blk.isDirty()) { 4767045Ssteve.reinhardt@amd.com _isDirty = true; 4777520Sgblack@eecs.umich.edu return false; 4788832SAli.Saidi@ARM.com } else { 4795728Sgblack@eecs.umich.edu return true; 4807520Sgblack@eecs.umich.edu } 4815744Sgblack@eecs.umich.edu } 4825728Sgblack@eecs.umich.edu 4835894Sgblack@eecs.umich.edu /** 4845744Sgblack@eecs.umich.edu * Does the array contain a dirty line? 4855894Sgblack@eecs.umich.edu * 4866102Sgblack@eecs.umich.edu * \return true if yes, false otherwise. 4875894Sgblack@eecs.umich.edu */ 4885894Sgblack@eecs.umich.edu bool isDirty() const { return _isDirty; }; 4896973Stjones1@inf.ed.ac.uk 4908443Sgblack@eecs.umich.edu private: 4918486Sgblack@eecs.umich.edu bool _isDirty; 4928486Sgblack@eecs.umich.edu}; 4938486Sgblack@eecs.umich.edu 4948486Sgblack@eecs.umich.edu#endif // __CACHE_HH__ 4956973Stjones1@inf.ed.ac.uk