cache.cc revision 12724
12810Srdreslin@umich.edu/*
212500Snikos.nikoleris@arm.com * Copyright (c) 2010-2018 ARM Limited
311051Sandreas.hansson@arm.com * All rights reserved.
411051Sandreas.hansson@arm.com *
511051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall
611051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual
711051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating
811051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software
911051Sandreas.hansson@arm.com * licensed hereunder.  You may use the software subject to the license
1011051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated
1111051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software,
1211051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form.
1311051Sandreas.hansson@arm.com *
1411051Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan
1511051Sandreas.hansson@arm.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc.
162810Srdreslin@umich.edu * All rights reserved.
172810Srdreslin@umich.edu *
182810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without
192810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are
202810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright
212810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer;
222810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright
232810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the
242810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution;
252810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its
262810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from
272810Srdreslin@umich.edu * this software without specific prior written permission.
282810Srdreslin@umich.edu *
292810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
302810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
312810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
322810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
332810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
342810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
352810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
362810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
372810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
382810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
392810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
402810Srdreslin@umich.edu *
412810Srdreslin@umich.edu * Authors: Erik Hallnor
4211051Sandreas.hansson@arm.com *          Dave Greene
4311051Sandreas.hansson@arm.com *          Nathan Binkert
442810Srdreslin@umich.edu *          Steve Reinhardt
4511051Sandreas.hansson@arm.com *          Ron Dreslinski
4611051Sandreas.hansson@arm.com *          Andreas Sandberg
4712349Snikos.nikoleris@arm.com *          Nikos Nikoleris
482810Srdreslin@umich.edu */
492810Srdreslin@umich.edu
502810Srdreslin@umich.edu/**
512810Srdreslin@umich.edu * @file
5211051Sandreas.hansson@arm.com * Cache definitions.
532810Srdreslin@umich.edu */
542810Srdreslin@umich.edu
5511051Sandreas.hansson@arm.com#include "mem/cache/cache.hh"
562810Srdreslin@umich.edu
5712334Sgabeblack@google.com#include <cassert>
5811051Sandreas.hansson@arm.com
5911051Sandreas.hansson@arm.com#include "base/compiler.hh"
6011051Sandreas.hansson@arm.com#include "base/logging.hh"
6111051Sandreas.hansson@arm.com#include "base/trace.hh"
6211288Ssteve.reinhardt@amd.com#include "base/types.hh"
6311051Sandreas.hansson@arm.com#include "debug/Cache.hh"
6411051Sandreas.hansson@arm.com#include "debug/CacheTags.hh"
6511051Sandreas.hansson@arm.com#include "debug/CacheVerbose.hh"
6611051Sandreas.hansson@arm.com#include "enums/Clusivity.hh"
6711051Sandreas.hansson@arm.com#include "mem/cache/blk.hh"
6811053Sandreas.hansson@arm.com#include "mem/cache/mshr.hh"
6911053Sandreas.hansson@arm.com#include "mem/cache/tags/base.hh"
7011051Sandreas.hansson@arm.com#include "mem/cache/write_queue_entry.hh"
7111051Sandreas.hansson@arm.com#include "mem/request.hh"
7211051Sandreas.hansson@arm.com#include "params/Cache.hh"
7311197Sandreas.hansson@arm.com
7411197Sandreas.hansson@arm.comCache::Cache(const CacheParams *p)
7511199Sandreas.hansson@arm.com    : BaseCache(p, p->system->cacheLineSize()),
7611197Sandreas.hansson@arm.com      doFastWrites(true)
7712084Sspwilson2@wisc.edu{
7812084Sspwilson2@wisc.edu}
7911197Sandreas.hansson@arm.com
8011051Sandreas.hansson@arm.comvoid
8111051Sandreas.hansson@arm.comCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk,
8211051Sandreas.hansson@arm.com                      bool deferred_response, bool pending_downgrade)
8311051Sandreas.hansson@arm.com{
8411051Sandreas.hansson@arm.com    BaseCache::satisfyRequest(pkt, blk);
8511051Sandreas.hansson@arm.com
8611051Sandreas.hansson@arm.com    if (pkt->isRead()) {
8711051Sandreas.hansson@arm.com        // determine if this read is from a (coherent) cache or not
8811051Sandreas.hansson@arm.com        if (pkt->fromCache()) {
8911051Sandreas.hansson@arm.com            assert(pkt->getSize() == blkSize);
9011051Sandreas.hansson@arm.com            // special handling for coherent block requests from
9111051Sandreas.hansson@arm.com            // upper-level caches
9211051Sandreas.hansson@arm.com            if (pkt->needsWritable()) {
9311051Sandreas.hansson@arm.com                // sanity check
9411051Sandreas.hansson@arm.com                assert(pkt->cmd == MemCmd::ReadExReq ||
9511051Sandreas.hansson@arm.com                       pkt->cmd == MemCmd::SCUpgradeFailReq);
9611051Sandreas.hansson@arm.com                assert(!pkt->hasSharers());
9711051Sandreas.hansson@arm.com
9811051Sandreas.hansson@arm.com                // if we have a dirty copy, make sure the recipient
9911051Sandreas.hansson@arm.com                // keeps it marked dirty (in the modified state)
10011051Sandreas.hansson@arm.com                if (blk->isDirty()) {
10111051Sandreas.hansson@arm.com                    pkt->setCacheResponding();
10211051Sandreas.hansson@arm.com                    blk->status &= ~BlkDirty;
10311051Sandreas.hansson@arm.com                }
10411051Sandreas.hansson@arm.com            } else if (blk->isWritable() && !pending_downgrade &&
10511051Sandreas.hansson@arm.com                       !pkt->hasSharers() &&
10611051Sandreas.hansson@arm.com                       pkt->cmd != MemCmd::ReadCleanReq) {
10711051Sandreas.hansson@arm.com                // we can give the requester a writable copy on a read
10811051Sandreas.hansson@arm.com                // request if:
10911051Sandreas.hansson@arm.com                // - we have a writable copy at this level (& below)
11011051Sandreas.hansson@arm.com                // - we don't have a pending snoop from below
11111051Sandreas.hansson@arm.com                //   signaling another read request
11211051Sandreas.hansson@arm.com                // - no other cache above has a copy (otherwise it
11311051Sandreas.hansson@arm.com                //   would have set hasSharers flag when
11411051Sandreas.hansson@arm.com                //   snooping the packet)
11511051Sandreas.hansson@arm.com                // - the read has explicitly asked for a clean
11611051Sandreas.hansson@arm.com                //   copy of the line
11711051Sandreas.hansson@arm.com                if (blk->isDirty()) {
11811051Sandreas.hansson@arm.com                    // special considerations if we're owner:
11911051Sandreas.hansson@arm.com                    if (!deferred_response) {
12011051Sandreas.hansson@arm.com                        // respond with the line in Modified state
12111051Sandreas.hansson@arm.com                        // (cacheResponding set, hasSharers not set)
12211051Sandreas.hansson@arm.com                        pkt->setCacheResponding();
12311051Sandreas.hansson@arm.com
12411051Sandreas.hansson@arm.com                        // if this cache is mostly inclusive, we
12511051Sandreas.hansson@arm.com                        // keep the block in the Exclusive state,
12611051Sandreas.hansson@arm.com                        // and pass it upwards as Modified
12711051Sandreas.hansson@arm.com                        // (writable and dirty), hence we have
12811051Sandreas.hansson@arm.com                        // multiple caches, all on the same path
12911051Sandreas.hansson@arm.com                        // towards memory, all considering the
13011051Sandreas.hansson@arm.com                        // same block writable, but only one
13111051Sandreas.hansson@arm.com                        // considering it Modified
13211051Sandreas.hansson@arm.com
13311051Sandreas.hansson@arm.com                        // we get away with multiple caches (on
13411051Sandreas.hansson@arm.com                        // the same path to memory) considering
13511051Sandreas.hansson@arm.com                        // the block writeable as we always enter
13611051Sandreas.hansson@arm.com                        // the cache hierarchy through a cache,
13711051Sandreas.hansson@arm.com                        // and first snoop upwards in all other
13811051Sandreas.hansson@arm.com                        // branches
13911051Sandreas.hansson@arm.com                        blk->status &= ~BlkDirty;
14011051Sandreas.hansson@arm.com                    } else {
14111051Sandreas.hansson@arm.com                        // if we're responding after our own miss,
14211051Sandreas.hansson@arm.com                        // there's a window where the recipient didn't
14311051Sandreas.hansson@arm.com                        // know it was getting ownership and may not
14411051Sandreas.hansson@arm.com                        // have responded to snoops correctly, so we
14511051Sandreas.hansson@arm.com                        // have to respond with a shared line
14611051Sandreas.hansson@arm.com                        pkt->setHasSharers();
14711051Sandreas.hansson@arm.com                    }
14811051Sandreas.hansson@arm.com                }
14911051Sandreas.hansson@arm.com            } else {
15011051Sandreas.hansson@arm.com                // otherwise only respond with a shared copy
15111601Sandreas.hansson@arm.com                pkt->setHasSharers();
15211601Sandreas.hansson@arm.com            }
15311051Sandreas.hansson@arm.com        }
15411051Sandreas.hansson@arm.com    }
15511051Sandreas.hansson@arm.com}
15611051Sandreas.hansson@arm.com
15711051Sandreas.hansson@arm.com/////////////////////////////////////////////////////
15811051Sandreas.hansson@arm.com//
15911051Sandreas.hansson@arm.com// Access path: requests coming in from the CPU side
16011051Sandreas.hansson@arm.com//
16111051Sandreas.hansson@arm.com/////////////////////////////////////////////////////
16211051Sandreas.hansson@arm.com
16311284Sandreas.hansson@arm.combool
16411051Sandreas.hansson@arm.comCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
16511051Sandreas.hansson@arm.com              PacketList &writebacks)
16611051Sandreas.hansson@arm.com{
16711051Sandreas.hansson@arm.com
16811051Sandreas.hansson@arm.com    if (pkt->req->isUncacheable()) {
16911051Sandreas.hansson@arm.com        assert(pkt->isRequest());
17011051Sandreas.hansson@arm.com
17111284Sandreas.hansson@arm.com        chatty_assert(!(isReadOnly && pkt->isWrite()),
17211284Sandreas.hansson@arm.com                      "Should never see a write in a read-only cache %s\n",
17311284Sandreas.hansson@arm.com                      name());
17411284Sandreas.hansson@arm.com
17511051Sandreas.hansson@arm.com        DPRINTF(Cache, "%s for %s\n", __func__, pkt->print());
17611284Sandreas.hansson@arm.com
17711051Sandreas.hansson@arm.com        // flush and invalidate any existing block
17811051Sandreas.hansson@arm.com        CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure()));
17911051Sandreas.hansson@arm.com        if (old_blk && old_blk->isValid()) {
18011284Sandreas.hansson@arm.com            evictBlock(old_blk, writebacks);
18111284Sandreas.hansson@arm.com        }
18211284Sandreas.hansson@arm.com
18311284Sandreas.hansson@arm.com        blk = nullptr;
18411051Sandreas.hansson@arm.com        // lookupLatency is the latency in case the request is uncacheable.
18511744Snikos.nikoleris@arm.com        lat = lookupLatency;
18611051Sandreas.hansson@arm.com        return false;
18711051Sandreas.hansson@arm.com    }
18811051Sandreas.hansson@arm.com
18911051Sandreas.hansson@arm.com    return BaseCache::access(pkt, blk, lat, writebacks);
19011286Sandreas.hansson@arm.com}
19111286Sandreas.hansson@arm.com
19211286Sandreas.hansson@arm.comvoid
19311051Sandreas.hansson@arm.comCache::doWritebacks(PacketList& writebacks, Tick forward_time)
19411286Sandreas.hansson@arm.com{
19511600Sandreas.hansson@arm.com    while (!writebacks.empty()) {
19611600Sandreas.hansson@arm.com        PacketPtr wbPkt = writebacks.front();
19711051Sandreas.hansson@arm.com        // We use forwardLatency here because we are copying writebacks to
19811051Sandreas.hansson@arm.com        // write buffer.
19911051Sandreas.hansson@arm.com
20011284Sandreas.hansson@arm.com        // Call isCachedAbove for Writebacks, CleanEvicts and
20111051Sandreas.hansson@arm.com        // WriteCleans to discover if the block is cached above.
20211051Sandreas.hansson@arm.com        if (isCachedAbove(wbPkt)) {
20311051Sandreas.hansson@arm.com            if (wbPkt->cmd == MemCmd::CleanEvict) {
20411602Sandreas.hansson@arm.com                // Delete CleanEvict because cached copies exist above. The
20511051Sandreas.hansson@arm.com                // packet destructor will delete the request object because
20611051Sandreas.hansson@arm.com                // this is a non-snoop request packet which does not require a
20711284Sandreas.hansson@arm.com                // response.
20811051Sandreas.hansson@arm.com                delete wbPkt;
20911284Sandreas.hansson@arm.com            } else if (wbPkt->cmd == MemCmd::WritebackClean) {
21011602Sandreas.hansson@arm.com                // clean writeback, do not send since the block is
21111051Sandreas.hansson@arm.com                // still cached above
21211051Sandreas.hansson@arm.com                assert(writebackClean);
21311284Sandreas.hansson@arm.com                delete wbPkt;
21411051Sandreas.hansson@arm.com            } else {
21511284Sandreas.hansson@arm.com                assert(wbPkt->cmd == MemCmd::WritebackDirty ||
21611284Sandreas.hansson@arm.com                       wbPkt->cmd == MemCmd::WriteClean);
21711284Sandreas.hansson@arm.com                // Set BLOCK_CACHED flag in Writeback and send below, so that
21811051Sandreas.hansson@arm.com                // the Writeback does not reset the bit corresponding to this
21911051Sandreas.hansson@arm.com                // address in the snoop filter below.
22011051Sandreas.hansson@arm.com                wbPkt->setBlockCached();
22111284Sandreas.hansson@arm.com                allocateWriteBuffer(wbPkt, forward_time);
22211284Sandreas.hansson@arm.com            }
22311284Sandreas.hansson@arm.com        } else {
22411284Sandreas.hansson@arm.com            // If the block is not cached above, send packet below. Both
22511051Sandreas.hansson@arm.com            // CleanEvict and Writeback with BLOCK_CACHED flag cleared will
22611051Sandreas.hansson@arm.com            // reset the bit corresponding to this address in the snoop filter
22711051Sandreas.hansson@arm.com            // below.
22811284Sandreas.hansson@arm.com            allocateWriteBuffer(wbPkt, forward_time);
22911284Sandreas.hansson@arm.com        }
23011284Sandreas.hansson@arm.com        writebacks.pop_front();
23111197Sandreas.hansson@arm.com    }
23211601Sandreas.hansson@arm.com}
23311601Sandreas.hansson@arm.com
23411601Sandreas.hansson@arm.comvoid
23511601Sandreas.hansson@arm.comCache::doWritebacksAtomic(PacketList& writebacks)
23611601Sandreas.hansson@arm.com{
23711601Sandreas.hansson@arm.com    while (!writebacks.empty()) {
23811601Sandreas.hansson@arm.com        PacketPtr wbPkt = writebacks.front();
23911601Sandreas.hansson@arm.com        // Call isCachedAbove for both Writebacks and CleanEvicts. If
24011197Sandreas.hansson@arm.com        // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks
24111601Sandreas.hansson@arm.com        // and discard CleanEvicts.
24211601Sandreas.hansson@arm.com        if (isCachedAbove(wbPkt, false)) {
24311601Sandreas.hansson@arm.com            if (wbPkt->cmd == MemCmd::WritebackDirty ||
24411601Sandreas.hansson@arm.com                wbPkt->cmd == MemCmd::WriteClean) {
24511601Sandreas.hansson@arm.com                // Set BLOCK_CACHED flag in Writeback and send below,
24611601Sandreas.hansson@arm.com                // so that the Writeback does not reset the bit
24711601Sandreas.hansson@arm.com                // corresponding to this address in the snoop filter
24811051Sandreas.hansson@arm.com                // below. We can discard CleanEvicts because cached
24911051Sandreas.hansson@arm.com                // copies exist above. Atomic mode isCachedAbove
25011051Sandreas.hansson@arm.com                // modifies packet to set BLOCK_CACHED flag
25111051Sandreas.hansson@arm.com                memSidePort.sendAtomic(wbPkt);
25211051Sandreas.hansson@arm.com            }
25311284Sandreas.hansson@arm.com        } else {
25411284Sandreas.hansson@arm.com            // If the block is not cached above, send packet below. Both
25511051Sandreas.hansson@arm.com            // CleanEvict and Writeback with BLOCK_CACHED flag cleared will
25611051Sandreas.hansson@arm.com            // reset the bit corresponding to this address in the snoop filter
25711051Sandreas.hansson@arm.com            // below.
25811051Sandreas.hansson@arm.com            memSidePort.sendAtomic(wbPkt);
25911284Sandreas.hansson@arm.com        }
26011051Sandreas.hansson@arm.com        writebacks.pop_front();
26111051Sandreas.hansson@arm.com        // In case of CleanEvicts, the packet destructor will delete the
26211602Sandreas.hansson@arm.com        // request object because this is a non-snoop request packet which
26311602Sandreas.hansson@arm.com        // does not require a response.
26411602Sandreas.hansson@arm.com        delete wbPkt;
26511602Sandreas.hansson@arm.com    }
26611602Sandreas.hansson@arm.com}
26711602Sandreas.hansson@arm.com
26811602Sandreas.hansson@arm.com
26911602Sandreas.hansson@arm.comvoid
27011602Sandreas.hansson@arm.comCache::recvTimingSnoopResp(PacketPtr pkt)
27111602Sandreas.hansson@arm.com{
27211602Sandreas.hansson@arm.com    DPRINTF(Cache, "%s for %s\n", __func__, pkt->print());
27311051Sandreas.hansson@arm.com
27411602Sandreas.hansson@arm.com    assert(pkt->isResponse());
27511197Sandreas.hansson@arm.com    assert(!system->bypassCaches());
27611744Snikos.nikoleris@arm.com
27711744Snikos.nikoleris@arm.com    // determine if the response is from a snoop request we created
27811051Sandreas.hansson@arm.com    // (in which case it should be in the outstandingSnoop), or if we
27911051Sandreas.hansson@arm.com    // merely forwarded someone else's snoop request
28011051Sandreas.hansson@arm.com    const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) ==
28111051Sandreas.hansson@arm.com        outstandingSnoop.end();
28211051Sandreas.hansson@arm.com
28311051Sandreas.hansson@arm.com    if (!forwardAsSnoop) {
28411051Sandreas.hansson@arm.com        // the packet came from this cache, so sink it here and do not
28511051Sandreas.hansson@arm.com        // forward it
28611051Sandreas.hansson@arm.com        assert(pkt->cmd == MemCmd::HardPFResp);
28711051Sandreas.hansson@arm.com
28811051Sandreas.hansson@arm.com        outstandingSnoop.erase(pkt->req);
28911051Sandreas.hansson@arm.com
29011051Sandreas.hansson@arm.com        DPRINTF(Cache, "Got prefetch response from above for addr "
29111051Sandreas.hansson@arm.com                "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns");
29211051Sandreas.hansson@arm.com        recvTimingResp(pkt);
29311051Sandreas.hansson@arm.com        return;
29411051Sandreas.hansson@arm.com    }
29511051Sandreas.hansson@arm.com
29611051Sandreas.hansson@arm.com    // forwardLatency is set here because there is a response from an
29711051Sandreas.hansson@arm.com    // upper level cache.
29811744Snikos.nikoleris@arm.com    // To pay the delay that occurs if the packet comes from the bus,
29911051Sandreas.hansson@arm.com    // we charge also headerDelay.
30011051Sandreas.hansson@arm.com    Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay;
30111744Snikos.nikoleris@arm.com    // Reset the timing of the packet.
30211051Sandreas.hansson@arm.com    pkt->headerDelay = pkt->payloadDelay = 0;
30311051Sandreas.hansson@arm.com    memSidePort.schedTimingSnoopResp(pkt, snoop_resp_time);
30411051Sandreas.hansson@arm.com}
30511051Sandreas.hansson@arm.com
30611199Sandreas.hansson@arm.comvoid
30711051Sandreas.hansson@arm.comCache::promoteWholeLineWrites(PacketPtr pkt)
30811051Sandreas.hansson@arm.com{
30911051Sandreas.hansson@arm.com    // Cache line clearing instructions
31011867Snikos.nikoleris@arm.com    if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) &&
31111051Sandreas.hansson@arm.com        (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) {
31211051Sandreas.hansson@arm.com        pkt->cmd = MemCmd::WriteLineReq;
31311484Snikos.nikoleris@arm.com        DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n");
31411051Sandreas.hansson@arm.com    }
31511051Sandreas.hansson@arm.com}
31611051Sandreas.hansson@arm.com
31711051Sandreas.hansson@arm.comvoid
31811051Sandreas.hansson@arm.comCache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time)
31911051Sandreas.hansson@arm.com{
32011051Sandreas.hansson@arm.com    // should never be satisfying an uncacheable access as we
32111870Snikos.nikoleris@arm.com    // flush and invalidate any existing block as part of the
32211051Sandreas.hansson@arm.com    // lookup
32311744Snikos.nikoleris@arm.com    assert(!pkt->req->isUncacheable());
32411051Sandreas.hansson@arm.com
32511051Sandreas.hansson@arm.com    BaseCache::handleTimingReqHit(pkt, blk, request_time);
32612349Snikos.nikoleris@arm.com}
32712349Snikos.nikoleris@arm.com
32812349Snikos.nikoleris@arm.comvoid
32912349Snikos.nikoleris@arm.comCache::handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, Tick forward_time,
33012349Snikos.nikoleris@arm.com                           Tick request_time)
33112349Snikos.nikoleris@arm.com{
33212349Snikos.nikoleris@arm.com    if (pkt->req->isUncacheable()) {
33312349Snikos.nikoleris@arm.com        // ignore any existing MSHR if we are dealing with an
33412349Snikos.nikoleris@arm.com        // uncacheable request
33511051Sandreas.hansson@arm.com
33611199Sandreas.hansson@arm.com        // should have flushed and have no valid block
33711051Sandreas.hansson@arm.com        assert(!blk || !blk->isValid());
33811051Sandreas.hansson@arm.com
33911051Sandreas.hansson@arm.com        mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++;
34011051Sandreas.hansson@arm.com
34111051Sandreas.hansson@arm.com        if (pkt->isWrite()) {
34211051Sandreas.hansson@arm.com            allocateWriteBuffer(pkt, forward_time);
34311051Sandreas.hansson@arm.com        } else {
34411051Sandreas.hansson@arm.com            assert(pkt->isRead());
34511375Sandreas.hansson@arm.com
34611375Sandreas.hansson@arm.com            // uncacheable accesses always allocate a new MSHR
34711375Sandreas.hansson@arm.com
34811199Sandreas.hansson@arm.com            // Here we are using forward_time, modelling the latency of
34911199Sandreas.hansson@arm.com            // a miss (outbound) just as forwardLatency, neglecting the
35011199Sandreas.hansson@arm.com            // lookupLatency component.
35111199Sandreas.hansson@arm.com            allocateMissBuffer(pkt, forward_time);
35211199Sandreas.hansson@arm.com        }
35311199Sandreas.hansson@arm.com
35411199Sandreas.hansson@arm.com        return;
35511199Sandreas.hansson@arm.com    }
35611199Sandreas.hansson@arm.com
35711199Sandreas.hansson@arm.com    Addr blk_addr = pkt->getBlockAddr(blkSize);
35811199Sandreas.hansson@arm.com
35911199Sandreas.hansson@arm.com    MSHR *mshr = mshrQueue.findMatch(blk_addr, pkt->isSecure());
36011199Sandreas.hansson@arm.com
36111199Sandreas.hansson@arm.com    // Software prefetch handling:
36211199Sandreas.hansson@arm.com    // To keep the core from waiting on data it won't look at
36311199Sandreas.hansson@arm.com    // anyway, send back a response with dummy data. Miss handling
36411199Sandreas.hansson@arm.com    // will continue asynchronously. Unfortunately, the core will
36511199Sandreas.hansson@arm.com    // insist upon freeing original Packet/Request, so we have to
36611199Sandreas.hansson@arm.com    // create a new pair with a different lifecycle. Note that this
36711199Sandreas.hansson@arm.com    // processing happens before any MSHR munging on the behalf of
36811375Sandreas.hansson@arm.com    // this request because this new Request will be the one stored
36911199Sandreas.hansson@arm.com    // into the MSHRs, not the original.
37011199Sandreas.hansson@arm.com    if (pkt->cmd.isSWPrefetch()) {
37111051Sandreas.hansson@arm.com        assert(pkt->needsResponse());
37211051Sandreas.hansson@arm.com        assert(pkt->req->hasPaddr());
37311051Sandreas.hansson@arm.com        assert(!pkt->req->isUncacheable());
37411051Sandreas.hansson@arm.com
37511051Sandreas.hansson@arm.com        // There's no reason to add a prefetch as an additional target
37611199Sandreas.hansson@arm.com        // to an existing MSHR. If an outstanding request is already
37711051Sandreas.hansson@arm.com        // in progress, there is nothing for the prefetch to do.
37811199Sandreas.hansson@arm.com        // If this is the case, we don't even create a request at all.
37911199Sandreas.hansson@arm.com        PacketPtr pf = nullptr;
38011199Sandreas.hansson@arm.com
38111199Sandreas.hansson@arm.com        if (!mshr) {
38211199Sandreas.hansson@arm.com            // copy the request and create a new SoftPFReq packet
38311199Sandreas.hansson@arm.com            RequestPtr req = new Request(pkt->req->getPaddr(),
38411199Sandreas.hansson@arm.com                                         pkt->req->getSize(),
38511199Sandreas.hansson@arm.com                                         pkt->req->getFlags(),
38611199Sandreas.hansson@arm.com                                         pkt->req->masterId());
38711199Sandreas.hansson@arm.com            pf = new Packet(req, pkt->cmd);
38811199Sandreas.hansson@arm.com            pf->allocate();
38911199Sandreas.hansson@arm.com            assert(pf->getAddr() == pkt->getAddr());
39011484Snikos.nikoleris@arm.com            assert(pf->getSize() == pkt->getSize());
39111051Sandreas.hansson@arm.com        }
39211051Sandreas.hansson@arm.com
39311484Snikos.nikoleris@arm.com        pkt->makeTimingResponse();
39411051Sandreas.hansson@arm.com
39511051Sandreas.hansson@arm.com        // request_time is used here, taking into account lat and the delay
39611051Sandreas.hansson@arm.com        // charged if the packet comes from the xbar.
39711051Sandreas.hansson@arm.com        cpuSidePort.schedTimingResp(pkt, request_time, true);
39811051Sandreas.hansson@arm.com
39911051Sandreas.hansson@arm.com        // If an outstanding request is in progress (we found an
40011051Sandreas.hansson@arm.com        // MSHR) this is set to null
40111051Sandreas.hansson@arm.com        pkt = pf;
40211051Sandreas.hansson@arm.com    }
40311051Sandreas.hansson@arm.com
40411051Sandreas.hansson@arm.com    BaseCache::handleTimingReqMiss(pkt, mshr, blk, forward_time, request_time);
40511199Sandreas.hansson@arm.com}
40611199Sandreas.hansson@arm.com
40711199Sandreas.hansson@arm.comvoid
40812500Snikos.nikoleris@arm.comCache::recvTimingReq(PacketPtr pkt)
40911199Sandreas.hansson@arm.com{
41011199Sandreas.hansson@arm.com    DPRINTF(CacheTags, "%s tags:\n%s\n", __func__, tags->print());
41111284Sandreas.hansson@arm.com
41211284Sandreas.hansson@arm.com    assert(pkt->isRequest());
41311284Sandreas.hansson@arm.com
41411284Sandreas.hansson@arm.com    // Just forward the packet if caches are disabled.
41511051Sandreas.hansson@arm.com    if (system->bypassCaches()) {
41611051Sandreas.hansson@arm.com        // @todo This should really enqueue the packet rather
41711051Sandreas.hansson@arm.com        bool M5_VAR_USED success = memSidePort.sendTimingReq(pkt);
41811051Sandreas.hansson@arm.com        assert(success);
41912633Sodanrc@yahoo.com.br        return;
42011051Sandreas.hansson@arm.com    }
42111051Sandreas.hansson@arm.com
42212556Snikos.nikoleris@arm.com    promoteWholeLineWrites(pkt);
42312556Snikos.nikoleris@arm.com
42412556Snikos.nikoleris@arm.com    if (pkt->cacheResponding()) {
42511051Sandreas.hansson@arm.com        // a cache above us (but not where the packet came from) is
42611051Sandreas.hansson@arm.com        // responding to the request, in other words it has the line
42711484Snikos.nikoleris@arm.com        // in Modified or Owned state
42811051Sandreas.hansson@arm.com        DPRINTF(Cache, "Cache above responding to %s: not responding\n",
42911051Sandreas.hansson@arm.com                pkt->print());
43011051Sandreas.hansson@arm.com
43111051Sandreas.hansson@arm.com        // if the packet needs the block to be writable, and the cache
43211051Sandreas.hansson@arm.com        // that has promised to respond (setting the cache responding
43311051Sandreas.hansson@arm.com        // flag) is not providing writable (it is in Owned rather than
43411051Sandreas.hansson@arm.com        // the Modified state), we know that there may be other Shared
43511051Sandreas.hansson@arm.com        // copies in the system; go out and invalidate them all
43611051Sandreas.hansson@arm.com        assert(pkt->needsWritable() && !pkt->responderHadWritable());
43711051Sandreas.hansson@arm.com
43811051Sandreas.hansson@arm.com        // an upstream cache that had the line in Owned state
43912345Snikos.nikoleris@arm.com        // (dirty, but not writable), is responding and thus
44012345Snikos.nikoleris@arm.com        // transferring the dirty line from one branch of the
44112345Snikos.nikoleris@arm.com        // cache hierarchy to another
44212345Snikos.nikoleris@arm.com
44312345Snikos.nikoleris@arm.com        // send out an express snoop and invalidate all other
44412345Snikos.nikoleris@arm.com        // copies (snooping a packet that needs writable is the
44512345Snikos.nikoleris@arm.com        // same as an invalidation), thus turning the Owned line
44612345Snikos.nikoleris@arm.com        // into a Modified line, note that we don't invalidate the
44712346Snikos.nikoleris@arm.com        // block in the current cache or any other cache on the
44812346Snikos.nikoleris@arm.com        // path to memory
44912346Snikos.nikoleris@arm.com
45012345Snikos.nikoleris@arm.com        // create a downstream express snoop with cleared packet
45112346Snikos.nikoleris@arm.com        // flags, there is no need to allocate any data as the
45212346Snikos.nikoleris@arm.com        // packet is merely used to co-ordinate state transitions
45312346Snikos.nikoleris@arm.com        Packet *snoop_pkt = new Packet(pkt, true, false);
45412346Snikos.nikoleris@arm.com
45512346Snikos.nikoleris@arm.com        // also reset the bus time that the original packet has
45612346Snikos.nikoleris@arm.com        // not yet paid for
45712346Snikos.nikoleris@arm.com        snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0;
45812346Snikos.nikoleris@arm.com
45912346Snikos.nikoleris@arm.com        // make this an instantaneous express snoop, and let the
46012346Snikos.nikoleris@arm.com        // other caches in the system know that the another cache
46112346Snikos.nikoleris@arm.com        // is responding, because we have found the authorative
46212346Snikos.nikoleris@arm.com        // copy (Modified or Owned) that will supply the right
46312346Snikos.nikoleris@arm.com        // data
46412346Snikos.nikoleris@arm.com        snoop_pkt->setExpressSnoop();
46512346Snikos.nikoleris@arm.com        snoop_pkt->setCacheResponding();
46612346Snikos.nikoleris@arm.com
46712345Snikos.nikoleris@arm.com        // this express snoop travels towards the memory, and at
46812345Snikos.nikoleris@arm.com        // every crossbar it is snooped upwards thus reaching
46912345Snikos.nikoleris@arm.com        // every cache in the system
47012345Snikos.nikoleris@arm.com        bool M5_VAR_USED success = memSidePort.sendTimingReq(snoop_pkt);
47112345Snikos.nikoleris@arm.com        // express snoops always succeed
47212345Snikos.nikoleris@arm.com        assert(success);
47312345Snikos.nikoleris@arm.com
47412500Snikos.nikoleris@arm.com        // main memory will delete the snoop packet
47512346Snikos.nikoleris@arm.com
47612346Snikos.nikoleris@arm.com        // queue for deletion, as opposed to immediate deletion, as
47712346Snikos.nikoleris@arm.com        // the sending cache is still relying on the packet
47812345Snikos.nikoleris@arm.com        pendingDelete.reset(pkt);
47912345Snikos.nikoleris@arm.com
48012633Sodanrc@yahoo.com.br        // no need to take any further action in this particular cache
48112345Snikos.nikoleris@arm.com        // as an upstram cache has already committed to responding,
48212345Snikos.nikoleris@arm.com        // and we have already sent out any express snoops in the
48312345Snikos.nikoleris@arm.com        // section above to ensure all other copies in the system are
48412345Snikos.nikoleris@arm.com        // invalidated
48512345Snikos.nikoleris@arm.com        return;
48612345Snikos.nikoleris@arm.com    }
48712346Snikos.nikoleris@arm.com
48812346Snikos.nikoleris@arm.com    BaseCache::recvTimingReq(pkt);
48912346Snikos.nikoleris@arm.com}
49011601Sandreas.hansson@arm.com
49111601Sandreas.hansson@arm.comPacketPtr
49211051Sandreas.hansson@arm.comCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
49311051Sandreas.hansson@arm.com                        bool needsWritable) const
49411601Sandreas.hansson@arm.com{
49511601Sandreas.hansson@arm.com    // should never see evictions here
49611601Sandreas.hansson@arm.com    assert(!cpu_pkt->isEviction());
49711051Sandreas.hansson@arm.com
49811051Sandreas.hansson@arm.com    bool blkValid = blk && blk->isValid();
49911051Sandreas.hansson@arm.com
50011484Snikos.nikoleris@arm.com    if (cpu_pkt->req->isUncacheable() ||
50111284Sandreas.hansson@arm.com        (!blkValid && cpu_pkt->isUpgrade()) ||
50211051Sandreas.hansson@arm.com        cpu_pkt->cmd == MemCmd::InvalidateReq || cpu_pkt->isClean()) {
50311051Sandreas.hansson@arm.com        // uncacheable requests and upgrades from upper-level caches
50411051Sandreas.hansson@arm.com        // that missed completely just go through as is
50511484Snikos.nikoleris@arm.com        return nullptr;
50611051Sandreas.hansson@arm.com    }
50711051Sandreas.hansson@arm.com
50811051Sandreas.hansson@arm.com    assert(cpu_pkt->needsResponse());
50911051Sandreas.hansson@arm.com
51011051Sandreas.hansson@arm.com    MemCmd cmd;
51111051Sandreas.hansson@arm.com    // @TODO make useUpgrades a parameter.
51211051Sandreas.hansson@arm.com    // Note that ownership protocols require upgrade, otherwise a
51311051Sandreas.hansson@arm.com    // write miss on a shared owned block will generate a ReadExcl,
51411051Sandreas.hansson@arm.com    // which will clobber the owned copy.
51511601Sandreas.hansson@arm.com    const bool useUpgrades = true;
51611601Sandreas.hansson@arm.com    if (cpu_pkt->cmd == MemCmd::WriteLineReq) {
51711601Sandreas.hansson@arm.com        assert(!blkValid || !blk->isWritable());
51811601Sandreas.hansson@arm.com        // forward as invalidate to all other caches, this gives us
51911601Sandreas.hansson@arm.com        // the line in Exclusive state, and invalidates all other
52011601Sandreas.hansson@arm.com        // copies
52111601Sandreas.hansson@arm.com        cmd = MemCmd::InvalidateReq;
52211601Sandreas.hansson@arm.com    } else if (blkValid && useUpgrades) {
52311601Sandreas.hansson@arm.com        // only reason to be here is that blk is read only and we need
52411601Sandreas.hansson@arm.com        // it to be writable
52511601Sandreas.hansson@arm.com        assert(needsWritable);
52611601Sandreas.hansson@arm.com        assert(!blk->isWritable());
52711051Sandreas.hansson@arm.com        cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq;
52811051Sandreas.hansson@arm.com    } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq ||
52911051Sandreas.hansson@arm.com               cpu_pkt->cmd == MemCmd::StoreCondFailReq) {
53011051Sandreas.hansson@arm.com        // Even though this SC will fail, we still need to send out the
53111051Sandreas.hansson@arm.com        // request and get the data to supply it to other snoopers in the case
53212345Snikos.nikoleris@arm.com        // where the determination the StoreCond fails is delayed due to
53312345Snikos.nikoleris@arm.com        // all caches not being on the same local bus.
53412345Snikos.nikoleris@arm.com        cmd = MemCmd::SCUpgradeFailReq;
53512345Snikos.nikoleris@arm.com    } else {
53611051Sandreas.hansson@arm.com        // block is invalid
53711051Sandreas.hansson@arm.com
53811051Sandreas.hansson@arm.com        // If the request does not need a writable there are two cases
53911051Sandreas.hansson@arm.com        // where we need to ensure the response will not fetch the
54011051Sandreas.hansson@arm.com        // block in dirty state:
54111051Sandreas.hansson@arm.com        // * this cache is read only and it does not perform
54211051Sandreas.hansson@arm.com        //   writebacks,
54311199Sandreas.hansson@arm.com        // * this cache is mostly exclusive and will not fill (since
54411199Sandreas.hansson@arm.com        //   it does not fill it will have to writeback the dirty data
54511199Sandreas.hansson@arm.com        //   immediately which generates uneccesary writebacks).
54611199Sandreas.hansson@arm.com        bool force_clean_rsp = isReadOnly || clusivity == Enums::mostly_excl;
54711199Sandreas.hansson@arm.com        cmd = needsWritable ? MemCmd::ReadExReq :
54811051Sandreas.hansson@arm.com            (force_clean_rsp ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq);
54912345Snikos.nikoleris@arm.com    }
55012345Snikos.nikoleris@arm.com    PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize);
55111051Sandreas.hansson@arm.com
55211051Sandreas.hansson@arm.com    // if there are upstream caches that have already marked the
55311051Sandreas.hansson@arm.com    // packet as having sharers (not passing writable), pass that info
55411051Sandreas.hansson@arm.com    // downstream
55511051Sandreas.hansson@arm.com    if (cpu_pkt->hasSharers() && !needsWritable) {
55611051Sandreas.hansson@arm.com        // note that cpu_pkt may have spent a considerable time in the
55711051Sandreas.hansson@arm.com        // MSHR queue and that the information could possibly be out
55811051Sandreas.hansson@arm.com        // of date, however, there is no harm in conservatively
55911051Sandreas.hansson@arm.com        // assuming the block has sharers
56011051Sandreas.hansson@arm.com        pkt->setHasSharers();
56111051Sandreas.hansson@arm.com        DPRINTF(Cache, "%s: passing hasSharers from %s to %s\n",
56211051Sandreas.hansson@arm.com                __func__, cpu_pkt->print(), pkt->print());
56311051Sandreas.hansson@arm.com    }
56411051Sandreas.hansson@arm.com
56511051Sandreas.hansson@arm.com    // the packet should be block aligned
56611051Sandreas.hansson@arm.com    assert(pkt->getAddr() == pkt->getBlockAddr(blkSize));
56711051Sandreas.hansson@arm.com
56811130Sali.jafri@arm.com    pkt->allocate();
56911130Sali.jafri@arm.com    DPRINTF(Cache, "%s: created %s from %s\n", __func__, pkt->print(),
57011130Sali.jafri@arm.com            cpu_pkt->print());
57111130Sali.jafri@arm.com    return pkt;
57211130Sali.jafri@arm.com}
57311130Sali.jafri@arm.com
57411130Sali.jafri@arm.com
57511130Sali.jafri@arm.comCycles
57611130Sali.jafri@arm.comCache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk,
57712345Snikos.nikoleris@arm.com                           PacketList &writebacks)
57812345Snikos.nikoleris@arm.com{
57911130Sali.jafri@arm.com    // deal with the packets that go through the write path of
58011130Sali.jafri@arm.com    // the cache, i.e. any evictions and writes
58111130Sali.jafri@arm.com    if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean ||
58211130Sali.jafri@arm.com        (pkt->req->isUncacheable() && pkt->isWrite())) {
58311130Sali.jafri@arm.com        Cycles latency = ticksToCycles(memSidePort.sendAtomic(pkt));
58411130Sali.jafri@arm.com
58511130Sali.jafri@arm.com        // at this point, if the request was an uncacheable write
58611130Sali.jafri@arm.com        // request, it has been satisfied by a memory below and the
58711130Sali.jafri@arm.com        // packet carries the response back
58811130Sali.jafri@arm.com        assert(!(pkt->req->isUncacheable() && pkt->isWrite()) ||
58911130Sali.jafri@arm.com               pkt->isResponse());
59011130Sali.jafri@arm.com
59111130Sali.jafri@arm.com        return latency;
59211130Sali.jafri@arm.com    }
59311130Sali.jafri@arm.com
59411130Sali.jafri@arm.com    // only misses left
59511130Sali.jafri@arm.com
59611130Sali.jafri@arm.com    PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable());
59711130Sali.jafri@arm.com
59811130Sali.jafri@arm.com    bool is_forward = (bus_pkt == nullptr);
59911130Sali.jafri@arm.com
60011130Sali.jafri@arm.com    if (is_forward) {
60111130Sali.jafri@arm.com        // just forwarding the same request to the next level
60211051Sandreas.hansson@arm.com        // no local cache operation involved
60311051Sandreas.hansson@arm.com        bus_pkt = pkt;
60411051Sandreas.hansson@arm.com    }
60511051Sandreas.hansson@arm.com
60611744Snikos.nikoleris@arm.com    DPRINTF(Cache, "%s: Sending an atomic %s\n", __func__,
60711051Sandreas.hansson@arm.com            bus_pkt->print());
60811051Sandreas.hansson@arm.com
60911051Sandreas.hansson@arm.com#if TRACING_ON
61011051Sandreas.hansson@arm.com    CacheBlk::State old_state = blk ? blk->status : 0;
61111276Sandreas.hansson@arm.com#endif
61211276Sandreas.hansson@arm.com
61311276Sandreas.hansson@arm.com    Cycles latency = ticksToCycles(memSidePort.sendAtomic(bus_pkt));
61411276Sandreas.hansson@arm.com
61511276Sandreas.hansson@arm.com    bool is_invalidate = bus_pkt->isInvalidate();
61611276Sandreas.hansson@arm.com
61711276Sandreas.hansson@arm.com    // We are now dealing with the response handling
61811276Sandreas.hansson@arm.com    DPRINTF(Cache, "%s: Receive response: %s in state %i\n", __func__,
61911276Sandreas.hansson@arm.com            bus_pkt->print(), old_state);
62011051Sandreas.hansson@arm.com
62111276Sandreas.hansson@arm.com    // If packet was a forward, the response (if any) is already
62211276Sandreas.hansson@arm.com    // in place in the bus_pkt == pkt structure, so we don't need
62311276Sandreas.hansson@arm.com    // to do anything.  Otherwise, use the separate bus_pkt to
62411276Sandreas.hansson@arm.com    // generate response to pkt and then delete it.
62511276Sandreas.hansson@arm.com    if (!is_forward) {
62611051Sandreas.hansson@arm.com        if (pkt->needsResponse()) {
62711051Sandreas.hansson@arm.com            assert(bus_pkt->isResponse());
62811051Sandreas.hansson@arm.com            if (bus_pkt->isError()) {
62911051Sandreas.hansson@arm.com                pkt->makeAtomicResponse();
63011051Sandreas.hansson@arm.com                pkt->copyError(bus_pkt);
63111051Sandreas.hansson@arm.com            } else if (pkt->cmd == MemCmd::WriteLineReq) {
63211051Sandreas.hansson@arm.com                // note the use of pkt, not bus_pkt here.
63311051Sandreas.hansson@arm.com
63411051Sandreas.hansson@arm.com                // write-line request to the cache that promoted
63511051Sandreas.hansson@arm.com                // the write to a whole line
63611051Sandreas.hansson@arm.com                blk = handleFill(pkt, blk, writebacks,
63711051Sandreas.hansson@arm.com                                 allocOnFill(pkt->cmd));
63811051Sandreas.hansson@arm.com                assert(blk != NULL);
63911051Sandreas.hansson@arm.com                is_invalidate = false;
64011051Sandreas.hansson@arm.com                satisfyRequest(pkt, blk);
64111051Sandreas.hansson@arm.com            } else if (bus_pkt->isRead() ||
64211051Sandreas.hansson@arm.com                       bus_pkt->cmd == MemCmd::UpgradeResp) {
64311051Sandreas.hansson@arm.com                // we're updating cache state to allow us to
64411051Sandreas.hansson@arm.com                // satisfy the upstream request from the cache
64511051Sandreas.hansson@arm.com                blk = handleFill(bus_pkt, blk, writebacks,
64611051Sandreas.hansson@arm.com                                 allocOnFill(pkt->cmd));
64711051Sandreas.hansson@arm.com                satisfyRequest(pkt, blk);
64811051Sandreas.hansson@arm.com                maintainClusivity(pkt->fromCache(), blk);
64911051Sandreas.hansson@arm.com            } else {
65011051Sandreas.hansson@arm.com                // we're satisfying the upstream request without
65112630Snikos.nikoleris@arm.com                // modifying cache state, e.g., a write-through
65211051Sandreas.hansson@arm.com                pkt->makeAtomicResponse();
65311051Sandreas.hansson@arm.com            }
65411830Sbaz21@cam.ac.uk        }
65511051Sandreas.hansson@arm.com        delete bus_pkt;
65611051Sandreas.hansson@arm.com    }
65711051Sandreas.hansson@arm.com
65811051Sandreas.hansson@arm.com    if (is_invalidate && blk && blk->isValid()) {
65911051Sandreas.hansson@arm.com        invalidateBlock(blk);
66011051Sandreas.hansson@arm.com    }
66111051Sandreas.hansson@arm.com
66211051Sandreas.hansson@arm.com    return latency;
66312630Snikos.nikoleris@arm.com}
66411051Sandreas.hansson@arm.com
66511051Sandreas.hansson@arm.comTick
66611051Sandreas.hansson@arm.comCache::recvAtomic(PacketPtr pkt)
66711051Sandreas.hansson@arm.com{
66812349Snikos.nikoleris@arm.com    // Forward the request if the system is in cache bypass mode.
66912349Snikos.nikoleris@arm.com    if (system->bypassCaches())
67012349Snikos.nikoleris@arm.com        return ticksToCycles(memSidePort.sendAtomic(pkt));
67112349Snikos.nikoleris@arm.com
67211284Sandreas.hansson@arm.com    promoteWholeLineWrites(pkt);
67311051Sandreas.hansson@arm.com
67411284Sandreas.hansson@arm.com    return BaseCache::recvAtomic(pkt);
67511284Sandreas.hansson@arm.com}
67611744Snikos.nikoleris@arm.com
67711744Snikos.nikoleris@arm.com
67811051Sandreas.hansson@arm.com/////////////////////////////////////////////////////
67911284Sandreas.hansson@arm.com//
68011284Sandreas.hansson@arm.com// Response handling: responses from the memory side
68111284Sandreas.hansson@arm.com//
68211284Sandreas.hansson@arm.com/////////////////////////////////////////////////////
68311284Sandreas.hansson@arm.com
68411334Sandreas.hansson@arm.com
68511284Sandreas.hansson@arm.comvoid
68611334Sandreas.hansson@arm.comCache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk,
68711334Sandreas.hansson@arm.com                          PacketList &writebacks)
68811334Sandreas.hansson@arm.com{
68911334Sandreas.hansson@arm.com    MSHR::Target *initial_tgt = mshr->getTarget();
69011284Sandreas.hansson@arm.com    // First offset for critical word first calculations
69111334Sandreas.hansson@arm.com    const int initial_offset = initial_tgt->pkt->getOffset(blkSize);
69211334Sandreas.hansson@arm.com
69311334Sandreas.hansson@arm.com    const bool is_error = pkt->isError();
69411334Sandreas.hansson@arm.com    bool is_fill = !mshr->isForward &&
69511334Sandreas.hansson@arm.com        (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp);
69611334Sandreas.hansson@arm.com    // allow invalidation responses originating from write-line
69711051Sandreas.hansson@arm.com    // requests to be discarded
69811334Sandreas.hansson@arm.com    bool is_invalidate = pkt->isInvalidate();
69911334Sandreas.hansson@arm.com
70011334Sandreas.hansson@arm.com    MSHR::TargetList targets = mshr->extractServiceableTargets(pkt);
70111334Sandreas.hansson@arm.com    for (auto &target: targets) {
70211051Sandreas.hansson@arm.com        Packet *tgt_pkt = target.pkt;
70311334Sandreas.hansson@arm.com        switch (target.source) {
70411334Sandreas.hansson@arm.com          case MSHR::Target::FromCPU:
70511334Sandreas.hansson@arm.com            Tick completion_time;
70611051Sandreas.hansson@arm.com            // Here we charge on completion_time the delay of the xbar if the
70711334Sandreas.hansson@arm.com            // packet comes from it, charged on headerDelay.
70811334Sandreas.hansson@arm.com            completion_time = pkt->headerDelay;
70911334Sandreas.hansson@arm.com
71011334Sandreas.hansson@arm.com            // Software prefetch handling for cache closest to core
71111334Sandreas.hansson@arm.com            if (tgt_pkt->cmd.isSWPrefetch()) {
71211334Sandreas.hansson@arm.com                // a software prefetch would have already been ack'd
71311334Sandreas.hansson@arm.com                // immediately with dummy data so the core would be able to
71411051Sandreas.hansson@arm.com                // retire it. This request completes right here, so we
71511334Sandreas.hansson@arm.com                // deallocate it.
71611334Sandreas.hansson@arm.com                delete tgt_pkt->req;
71711334Sandreas.hansson@arm.com                delete tgt_pkt;
71811334Sandreas.hansson@arm.com                break; // skip response
71911334Sandreas.hansson@arm.com            }
72011334Sandreas.hansson@arm.com
72111334Sandreas.hansson@arm.com            // unlike the other packet flows, where data is found in other
72211334Sandreas.hansson@arm.com            // caches or memory and brought back, write-line requests always
72311051Sandreas.hansson@arm.com            // have the data right away, so the above check for "is fill?"
72411284Sandreas.hansson@arm.com            // cannot actually be determined until examining the stored MSHR
72511284Sandreas.hansson@arm.com            // state. We "catch up" with that logic here, which is duplicated
72611190Sandreas.hansson@arm.com            // from above.
72711051Sandreas.hansson@arm.com            if (tgt_pkt->cmd == MemCmd::WriteLineReq) {
72811334Sandreas.hansson@arm.com                assert(!is_error);
72911334Sandreas.hansson@arm.com                // we got the block in a writable state, so promote
73011334Sandreas.hansson@arm.com                // any deferred targets if possible
73111334Sandreas.hansson@arm.com                mshr->promoteWritable();
73211334Sandreas.hansson@arm.com                // NB: we use the original packet here and not the response!
73312630Snikos.nikoleris@arm.com                blk = handleFill(tgt_pkt, blk, writebacks,
73411051Sandreas.hansson@arm.com                                 targets.allocOnFill);
73511051Sandreas.hansson@arm.com                assert(blk);
73611051Sandreas.hansson@arm.com
73711051Sandreas.hansson@arm.com                // treat as a fill, and discard the invalidation
73811051Sandreas.hansson@arm.com                // response
73911051Sandreas.hansson@arm.com                is_fill = true;
74011051Sandreas.hansson@arm.com                is_invalidate = false;
74111051Sandreas.hansson@arm.com            }
74211051Sandreas.hansson@arm.com
74311484Snikos.nikoleris@arm.com            if (is_fill) {
74411051Sandreas.hansson@arm.com                satisfyRequest(tgt_pkt, blk, true, mshr->hasPostDowngrade());
74511051Sandreas.hansson@arm.com
74611051Sandreas.hansson@arm.com                // How many bytes past the first request is this one
74711051Sandreas.hansson@arm.com                int transfer_offset =
74811051Sandreas.hansson@arm.com                    tgt_pkt->getOffset(blkSize) - initial_offset;
74911051Sandreas.hansson@arm.com                if (transfer_offset < 0) {
75011051Sandreas.hansson@arm.com                    transfer_offset += blkSize;
75111051Sandreas.hansson@arm.com                }
75211051Sandreas.hansson@arm.com
75311051Sandreas.hansson@arm.com                // If not critical word (offset) return payloadDelay.
75411051Sandreas.hansson@arm.com                // responseLatency is the latency of the return path
75511051Sandreas.hansson@arm.com                // from lower level caches/memory to an upper level cache or
75611051Sandreas.hansson@arm.com                // the core.
75711051Sandreas.hansson@arm.com                completion_time += clockEdge(responseLatency) +
75811051Sandreas.hansson@arm.com                    (transfer_offset ? pkt->payloadDelay : 0);
75911051Sandreas.hansson@arm.com
76011051Sandreas.hansson@arm.com                assert(!tgt_pkt->req->isUncacheable());
76111051Sandreas.hansson@arm.com
76211051Sandreas.hansson@arm.com                assert(tgt_pkt->req->masterId() < system->maxMasters());
76311051Sandreas.hansson@arm.com                missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] +=
76411051Sandreas.hansson@arm.com                    completion_time - target.recvTime;
76511051Sandreas.hansson@arm.com            } else if (pkt->cmd == MemCmd::UpgradeFailResp) {
76611051Sandreas.hansson@arm.com                // failed StoreCond upgrade
76711051Sandreas.hansson@arm.com                assert(tgt_pkt->cmd == MemCmd::StoreCondReq ||
76811051Sandreas.hansson@arm.com                       tgt_pkt->cmd == MemCmd::StoreCondFailReq ||
76911051Sandreas.hansson@arm.com                       tgt_pkt->cmd == MemCmd::SCUpgradeFailReq);
77011051Sandreas.hansson@arm.com                // responseLatency is the latency of the return path
77111051Sandreas.hansson@arm.com                // from lower level caches/memory to an upper level cache or
77211051Sandreas.hansson@arm.com                // the core.
77311051Sandreas.hansson@arm.com                completion_time += clockEdge(responseLatency) +
77411051Sandreas.hansson@arm.com                    pkt->payloadDelay;
77511051Sandreas.hansson@arm.com                tgt_pkt->req->setExtraData(0);
77611051Sandreas.hansson@arm.com            } else {
77711051Sandreas.hansson@arm.com                // We are about to send a response to a cache above
77811051Sandreas.hansson@arm.com                // that asked for an invalidation; we need to
77911483Snikos.nikoleris@arm.com                // invalidate our copy immediately as the most
78011483Snikos.nikoleris@arm.com                // up-to-date copy of the block will now be in the
78111051Sandreas.hansson@arm.com                // cache above. It will also prevent this cache from
78211051Sandreas.hansson@arm.com                // responding (if the block was previously dirty) to
78311051Sandreas.hansson@arm.com                // snoops as they should snoop the caches above where
78411051Sandreas.hansson@arm.com                // they will get the response from.
78512349Snikos.nikoleris@arm.com                if (is_invalidate && blk && blk->isValid()) {
78612349Snikos.nikoleris@arm.com                    invalidateBlock(blk);
78711051Sandreas.hansson@arm.com                }
78812349Snikos.nikoleris@arm.com                // not a cache fill, just forwarding response
78911051Sandreas.hansson@arm.com                // responseLatency is the latency of the return path
79011051Sandreas.hansson@arm.com                // from lower level cahces/memory to the core.
79111051Sandreas.hansson@arm.com                completion_time += clockEdge(responseLatency) +
79211051Sandreas.hansson@arm.com                    pkt->payloadDelay;
79311051Sandreas.hansson@arm.com                if (pkt->isRead() && !is_error) {
79411051Sandreas.hansson@arm.com                    // sanity check
79511051Sandreas.hansson@arm.com                    assert(pkt->getAddr() == tgt_pkt->getAddr());
79611051Sandreas.hansson@arm.com                    assert(pkt->getSize() >= tgt_pkt->getSize());
79711051Sandreas.hansson@arm.com
79811051Sandreas.hansson@arm.com                    tgt_pkt->setData(pkt->getConstPtr<uint8_t>());
79911051Sandreas.hansson@arm.com                }
80011051Sandreas.hansson@arm.com            }
80111194Sali.jafri@arm.com            tgt_pkt->makeTimingResponse();
80211051Sandreas.hansson@arm.com            // if this packet is an error copy that to the new packet
80311744Snikos.nikoleris@arm.com            if (is_error)
80411744Snikos.nikoleris@arm.com                tgt_pkt->copyError(pkt);
80511199Sandreas.hansson@arm.com            if (tgt_pkt->cmd == MemCmd::ReadResp &&
80611190Sandreas.hansson@arm.com                (is_invalidate || mshr->hasPostInvalidate())) {
80711190Sandreas.hansson@arm.com                // If intermediate cache got ReadRespWithInvalidate,
80811190Sandreas.hansson@arm.com                // propagate that.  Response should not have
80911190Sandreas.hansson@arm.com                // isInvalidate() set otherwise.
81011190Sandreas.hansson@arm.com                tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate;
81111051Sandreas.hansson@arm.com                DPRINTF(Cache, "%s: updated cmd to %s\n", __func__,
81211051Sandreas.hansson@arm.com                        tgt_pkt->print());
81311051Sandreas.hansson@arm.com            }
81411051Sandreas.hansson@arm.com            // Reset the bus additional time as it is now accounted for
81511892Snikos.nikoleris@arm.com            tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0;
81611051Sandreas.hansson@arm.com            cpuSidePort.schedTimingResp(tgt_pkt, completion_time, true);
81711051Sandreas.hansson@arm.com            break;
81811051Sandreas.hansson@arm.com
81911051Sandreas.hansson@arm.com          case MSHR::Target::FromPrefetcher:
82011051Sandreas.hansson@arm.com            assert(tgt_pkt->cmd == MemCmd::HardPFReq);
82111051Sandreas.hansson@arm.com            if (blk)
82211051Sandreas.hansson@arm.com                blk->status |= BlkHWPrefetched;
82311051Sandreas.hansson@arm.com            delete tgt_pkt->req;
82411051Sandreas.hansson@arm.com            delete tgt_pkt;
82511051Sandreas.hansson@arm.com            break;
82611051Sandreas.hansson@arm.com
82711051Sandreas.hansson@arm.com          case MSHR::Target::FromSnoop:
82811051Sandreas.hansson@arm.com            // I don't believe that a snoop can be in an error state
82911051Sandreas.hansson@arm.com            assert(!is_error);
83011051Sandreas.hansson@arm.com            // response to snoop request
83111051Sandreas.hansson@arm.com            DPRINTF(Cache, "processing deferred snoop...\n");
83211051Sandreas.hansson@arm.com            // If the response is invalidating, a snooping target can
83311051Sandreas.hansson@arm.com            // be satisfied if it is also invalidating. If the reponse is, not
83411051Sandreas.hansson@arm.com            // only invalidating, but more specifically an InvalidateResp and
83511051Sandreas.hansson@arm.com            // the MSHR was created due to an InvalidateReq then a cache above
83611051Sandreas.hansson@arm.com            // is waiting to satisfy a WriteLineReq. In this case even an
83711051Sandreas.hansson@arm.com            // non-invalidating snoop is added as a target here since this is
83811051Sandreas.hansson@arm.com            // the ordering point. When the InvalidateResp reaches this cache,
83911051Sandreas.hansson@arm.com            // the snooping target will snoop further the cache above with the
84011051Sandreas.hansson@arm.com            // WriteLineReq.
84111051Sandreas.hansson@arm.com            assert(!is_invalidate || pkt->cmd == MemCmd::InvalidateResp ||
84211051Sandreas.hansson@arm.com                   pkt->req->isCacheMaintenance() ||
84311051Sandreas.hansson@arm.com                   mshr->hasPostInvalidate());
84411051Sandreas.hansson@arm.com            handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate());
84511051Sandreas.hansson@arm.com            break;
84611051Sandreas.hansson@arm.com
84711051Sandreas.hansson@arm.com          default:
84811051Sandreas.hansson@arm.com            panic("Illegal target->source enum %d\n", target.source);
84911051Sandreas.hansson@arm.com        }
85011051Sandreas.hansson@arm.com    }
85111051Sandreas.hansson@arm.com
85211051Sandreas.hansson@arm.com    maintainClusivity(targets.hasFromCache, blk);
85311051Sandreas.hansson@arm.com
85411051Sandreas.hansson@arm.com    if (blk && blk->isValid()) {
85511286Sandreas.hansson@arm.com        // an invalidate response stemming from a write line request
85611051Sandreas.hansson@arm.com        // should not invalidate the block, so check if the
85711051Sandreas.hansson@arm.com        // invalidation should be discarded
85811194Sali.jafri@arm.com        if (is_invalidate || mshr->hasPostInvalidate()) {
85911051Sandreas.hansson@arm.com            invalidateBlock(blk);
86011051Sandreas.hansson@arm.com        } else if (mshr->hasPostDowngrade()) {
86111051Sandreas.hansson@arm.com            blk->status &= ~BlkWritable;
86211051Sandreas.hansson@arm.com        }
86311051Sandreas.hansson@arm.com    }
86411051Sandreas.hansson@arm.com}
86511051Sandreas.hansson@arm.com
86611051Sandreas.hansson@arm.comPacketPtr
86711051Sandreas.hansson@arm.comCache::evictBlock(CacheBlk *blk)
86811051Sandreas.hansson@arm.com{
86911051Sandreas.hansson@arm.com    PacketPtr pkt = (blk->isDirty() || writebackClean) ?
87011051Sandreas.hansson@arm.com        writebackBlk(blk) : cleanEvictBlk(blk);
87111051Sandreas.hansson@arm.com
87211051Sandreas.hansson@arm.com    invalidateBlock(blk);
87311051Sandreas.hansson@arm.com
87411199Sandreas.hansson@arm.com    return pkt;
87511199Sandreas.hansson@arm.com}
87611199Sandreas.hansson@arm.com
87711051Sandreas.hansson@arm.comvoid
87811190Sandreas.hansson@arm.comCache::evictBlock(CacheBlk *blk, PacketList &writebacks)
87912349Snikos.nikoleris@arm.com{
88012349Snikos.nikoleris@arm.com    PacketPtr pkt = evictBlock(blk);
88112349Snikos.nikoleris@arm.com    if (pkt) {
88212349Snikos.nikoleris@arm.com        writebacks.push_back(pkt);
88312349Snikos.nikoleris@arm.com    }
88412349Snikos.nikoleris@arm.com}
88512349Snikos.nikoleris@arm.com
88611051Sandreas.hansson@arm.comPacketPtr
88711744Snikos.nikoleris@arm.comCache::cleanEvictBlk(CacheBlk *blk)
88811744Snikos.nikoleris@arm.com{
88911051Sandreas.hansson@arm.com    assert(!writebackClean);
89011051Sandreas.hansson@arm.com    assert(blk && blk->isValid() && !blk->isDirty());
89111051Sandreas.hansson@arm.com    // Creating a zero sized write, a message to the snoop filter
89211051Sandreas.hansson@arm.com    Request *req =
89311051Sandreas.hansson@arm.com        new Request(tags->regenerateBlkAddr(blk), blkSize, 0,
89411051Sandreas.hansson@arm.com                    Request::wbMasterId);
89511051Sandreas.hansson@arm.com    if (blk->isSecure())
89611051Sandreas.hansson@arm.com        req->setFlags(Request::SECURE);
89711051Sandreas.hansson@arm.com
89811051Sandreas.hansson@arm.com    req->taskId(blk->task_id);
89911197Sandreas.hansson@arm.com
90011197Sandreas.hansson@arm.com    PacketPtr pkt = new Packet(req, MemCmd::CleanEvict);
90111051Sandreas.hansson@arm.com    pkt->allocate();
90211051Sandreas.hansson@arm.com    DPRINTF(Cache, "Create CleanEvict %s\n", pkt->print());
90311051Sandreas.hansson@arm.com
90411051Sandreas.hansson@arm.com    return pkt;
90511051Sandreas.hansson@arm.com}
90611051Sandreas.hansson@arm.com
90711051Sandreas.hansson@arm.com
90811051Sandreas.hansson@arm.com/////////////////////////////////////////////////////
90911051Sandreas.hansson@arm.com//
91011051Sandreas.hansson@arm.com// Snoop path: requests coming in from the memory side
91111483Snikos.nikoleris@arm.com//
91211483Snikos.nikoleris@arm.com/////////////////////////////////////////////////////
91311051Sandreas.hansson@arm.com
91411051Sandreas.hansson@arm.comvoid
91511483Snikos.nikoleris@arm.comCache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
91611483Snikos.nikoleris@arm.com                              bool already_copied, bool pending_inval)
91711051Sandreas.hansson@arm.com{
91811051Sandreas.hansson@arm.com    // sanity check
91912349Snikos.nikoleris@arm.com    assert(req_pkt->isRequest());
92012349Snikos.nikoleris@arm.com    assert(req_pkt->needsResponse());
92111051Sandreas.hansson@arm.com
92211051Sandreas.hansson@arm.com    DPRINTF(Cache, "%s: for %s\n", __func__, req_pkt->print());
92311051Sandreas.hansson@arm.com    // timing-mode snoop responses require a new packet, unless we
92411051Sandreas.hansson@arm.com    // already made a copy...
92511051Sandreas.hansson@arm.com    PacketPtr pkt = req_pkt;
92611051Sandreas.hansson@arm.com    if (!already_copied)
92711051Sandreas.hansson@arm.com        // do not clear flags, and allocate space for data if the
92811051Sandreas.hansson@arm.com        // packet needs it (the only packets that carry data are read
92911051Sandreas.hansson@arm.com        // responses)
93011051Sandreas.hansson@arm.com        pkt = new Packet(req_pkt, false, req_pkt->isRead());
93111051Sandreas.hansson@arm.com
93211051Sandreas.hansson@arm.com    assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() ||
93312345Snikos.nikoleris@arm.com           pkt->hasSharers());
93411051Sandreas.hansson@arm.com    pkt->makeTimingResponse();
93511051Sandreas.hansson@arm.com    if (pkt->isRead()) {
93611051Sandreas.hansson@arm.com        pkt->setDataFromBlock(blk_data, blkSize);
93711051Sandreas.hansson@arm.com    }
93811051Sandreas.hansson@arm.com    if (pkt->cmd == MemCmd::ReadResp && pending_inval) {
93911051Sandreas.hansson@arm.com        // Assume we defer a response to a read from a far-away cache
94011051Sandreas.hansson@arm.com        // A, then later defer a ReadExcl from a cache B on the same
94111051Sandreas.hansson@arm.com        // bus as us. We'll assert cacheResponding in both cases, but
94211051Sandreas.hansson@arm.com        // in the latter case cacheResponding will keep the
94311051Sandreas.hansson@arm.com        // invalidation from reaching cache A. This special response
94411051Sandreas.hansson@arm.com        // tells cache A that it gets the block to satisfy its read,
94511051Sandreas.hansson@arm.com        // but must immediately invalidate it.
94611051Sandreas.hansson@arm.com        pkt->cmd = MemCmd::ReadRespWithInvalidate;
94711051Sandreas.hansson@arm.com    }
94811051Sandreas.hansson@arm.com    // Here we consider forward_time, paying for just forward latency and
94911051Sandreas.hansson@arm.com    // also charging the delay provided by the xbar.
95011051Sandreas.hansson@arm.com    // forward_time is used as send_time in next allocateWriteBuffer().
95111051Sandreas.hansson@arm.com    Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
95211051Sandreas.hansson@arm.com    // Here we reset the timing of the packet.
95311051Sandreas.hansson@arm.com    pkt->headerDelay = pkt->payloadDelay = 0;
95411051Sandreas.hansson@arm.com    DPRINTF(CacheVerbose, "%s: created response: %s tick: %lu\n", __func__,
95511051Sandreas.hansson@arm.com            pkt->print(), forward_time);
95611051Sandreas.hansson@arm.com    memSidePort.schedTimingSnoopResp(pkt, forward_time, true);
95711051Sandreas.hansson@arm.com}
95812349Snikos.nikoleris@arm.com
95912349Snikos.nikoleris@arm.comuint32_t
96011051Sandreas.hansson@arm.comCache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing,
96111051Sandreas.hansson@arm.com                   bool is_deferred, bool pending_inval)
96211051Sandreas.hansson@arm.com{
96311051Sandreas.hansson@arm.com    DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print());
96411051Sandreas.hansson@arm.com    // deferred snoops can only happen in timing mode
96511051Sandreas.hansson@arm.com    assert(!(is_deferred && !is_timing));
96611051Sandreas.hansson@arm.com    // pending_inval only makes sense on deferred snoops
96711051Sandreas.hansson@arm.com    assert(!(pending_inval && !is_deferred));
96811051Sandreas.hansson@arm.com    assert(pkt->isRequest());
96911051Sandreas.hansson@arm.com
97012349Snikos.nikoleris@arm.com    // the packet may get modified if we or a forwarded snooper
97112349Snikos.nikoleris@arm.com    // responds in atomic mode, so remember a few things about the
97211051Sandreas.hansson@arm.com    // original packet up front
97311051Sandreas.hansson@arm.com    bool invalidate = pkt->isInvalidate();
97411051Sandreas.hansson@arm.com    bool M5_VAR_USED needs_writable = pkt->needsWritable();
97511051Sandreas.hansson@arm.com
97611051Sandreas.hansson@arm.com    // at the moment we could get an uncacheable write which does not
97711051Sandreas.hansson@arm.com    // have the invalidate flag, and we need a suitable way of dealing
97811051Sandreas.hansson@arm.com    // with this case
97911051Sandreas.hansson@arm.com    panic_if(invalidate && pkt->req->isUncacheable(),
98011051Sandreas.hansson@arm.com             "%s got an invalidating uncacheable snoop request %s",
98111051Sandreas.hansson@arm.com             name(), pkt->print());
98211452Sandreas.hansson@arm.com
98311452Sandreas.hansson@arm.com    uint32_t snoop_delay = 0;
98411051Sandreas.hansson@arm.com
98511452Sandreas.hansson@arm.com    if (forwardSnoops) {
98611452Sandreas.hansson@arm.com        // first propagate snoop upward to see if anyone above us wants to
98711452Sandreas.hansson@arm.com        // handle it.  save & restore packet src since it will get
98811051Sandreas.hansson@arm.com        // rewritten to be relative to cpu-side bus (if any)
98911051Sandreas.hansson@arm.com        bool alreadyResponded = pkt->cacheResponding();
99011452Sandreas.hansson@arm.com        if (is_timing) {
99111745Sandreas.hansson@arm.com            // copy the packet so that we can clear any flags before
99212349Snikos.nikoleris@arm.com            // forwarding it upwards, we also allocate data (passing
99311452Sandreas.hansson@arm.com            // the pointer along in case of static data), in case
99411452Sandreas.hansson@arm.com            // there is a snoop hit in upper levels
99511452Sandreas.hansson@arm.com            Packet snoopPkt(pkt, true, true);
99611051Sandreas.hansson@arm.com            snoopPkt.setExpressSnoop();
99711051Sandreas.hansson@arm.com            // the snoop packet does not need to wait any additional
99811051Sandreas.hansson@arm.com            // time
99911051Sandreas.hansson@arm.com            snoopPkt.headerDelay = snoopPkt.payloadDelay = 0;
100011051Sandreas.hansson@arm.com            cpuSidePort.sendTimingSnoopReq(&snoopPkt);
100111051Sandreas.hansson@arm.com
100211051Sandreas.hansson@arm.com            // add the header delay (including crossbar and snoop
100311051Sandreas.hansson@arm.com            // delays) of the upward snoop to the snoop delay for this
100411051Sandreas.hansson@arm.com            // cache
100511051Sandreas.hansson@arm.com            snoop_delay += snoopPkt.headerDelay;
100611747Snikos.nikoleris@arm.com
100711747Snikos.nikoleris@arm.com            if (snoopPkt.cacheResponding()) {
100811747Snikos.nikoleris@arm.com                // cache-to-cache response from some upper cache
100911747Snikos.nikoleris@arm.com                assert(!alreadyResponded);
101011747Snikos.nikoleris@arm.com                pkt->setCacheResponding();
101111747Snikos.nikoleris@arm.com            }
101211747Snikos.nikoleris@arm.com            // upstream cache has the block, or has an outstanding
101311284Sandreas.hansson@arm.com            // MSHR, pass the flag on
101411284Sandreas.hansson@arm.com            if (snoopPkt.hasSharers()) {
101511284Sandreas.hansson@arm.com                pkt->setHasSharers();
101611051Sandreas.hansson@arm.com            }
101711051Sandreas.hansson@arm.com            // If this request is a prefetch or clean evict and an upper level
101811051Sandreas.hansson@arm.com            // signals block present, make sure to propagate the block
101911051Sandreas.hansson@arm.com            // presence to the requester.
102011051Sandreas.hansson@arm.com            if (snoopPkt.isBlockCached()) {
102111051Sandreas.hansson@arm.com                pkt->setBlockCached();
102211051Sandreas.hansson@arm.com            }
102311051Sandreas.hansson@arm.com            // If the request was satisfied by snooping the cache
102411051Sandreas.hansson@arm.com            // above, mark the original packet as satisfied too.
102511051Sandreas.hansson@arm.com            if (snoopPkt.satisfied()) {
102611051Sandreas.hansson@arm.com                pkt->setSatisfied();
102712425Snikos.nikoleris@arm.com            }
102812425Snikos.nikoleris@arm.com        } else {
102912425Snikos.nikoleris@arm.com            cpuSidePort.sendAtomicSnoop(pkt);
103012425Snikos.nikoleris@arm.com            if (!alreadyResponded && pkt->cacheResponding()) {
103112425Snikos.nikoleris@arm.com                // cache-to-cache response from some upper cache:
103212425Snikos.nikoleris@arm.com                // forward response to original requester
103312425Snikos.nikoleris@arm.com                assert(pkt->isResponse());
103412425Snikos.nikoleris@arm.com            }
103512425Snikos.nikoleris@arm.com        }
103612425Snikos.nikoleris@arm.com    }
103711284Sandreas.hansson@arm.com
103812425Snikos.nikoleris@arm.com    bool respond = false;
103911051Sandreas.hansson@arm.com    bool blk_valid = blk && blk->isValid();
104011051Sandreas.hansson@arm.com    if (pkt->isClean()) {
104111051Sandreas.hansson@arm.com        if (blk_valid && blk->isDirty()) {
104211284Sandreas.hansson@arm.com            DPRINTF(CacheVerbose, "%s: packet (snoop) %s found block: %s\n",
104311284Sandreas.hansson@arm.com                    __func__, pkt->print(), blk->print());
104411284Sandreas.hansson@arm.com            PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id);
104511602Sandreas.hansson@arm.com            PacketList writebacks;
104611051Sandreas.hansson@arm.com            writebacks.push_back(wb_pkt);
104711051Sandreas.hansson@arm.com
104811051Sandreas.hansson@arm.com            if (is_timing) {
104911284Sandreas.hansson@arm.com                // anything that is merely forwarded pays for the forward
105011284Sandreas.hansson@arm.com                // latency and the delay provided by the crossbar
105111744Snikos.nikoleris@arm.com                Tick forward_time = clockEdge(forwardLatency) +
105211744Snikos.nikoleris@arm.com                    pkt->headerDelay;
105311051Sandreas.hansson@arm.com                doWritebacks(writebacks, forward_time);
105411051Sandreas.hansson@arm.com            } else {
105511051Sandreas.hansson@arm.com                doWritebacksAtomic(writebacks);
105611892Snikos.nikoleris@arm.com            }
105711051Sandreas.hansson@arm.com            pkt->setSatisfied();
105811051Sandreas.hansson@arm.com        }
105911744Snikos.nikoleris@arm.com    } else if (!blk_valid) {
106011744Snikos.nikoleris@arm.com        DPRINTF(CacheVerbose, "%s: snoop miss for %s\n", __func__,
106111051Sandreas.hansson@arm.com                pkt->print());
106211051Sandreas.hansson@arm.com        if (is_deferred) {
106311051Sandreas.hansson@arm.com            // we no longer have the block, and will not respond, but a
106411051Sandreas.hansson@arm.com            // packet was allocated in MSHR::handleSnoop and we have
106511051Sandreas.hansson@arm.com            // to delete it
106611051Sandreas.hansson@arm.com            assert(pkt->needsResponse());
106711051Sandreas.hansson@arm.com
106811051Sandreas.hansson@arm.com            // we have passed the block to a cache upstream, that
106911051Sandreas.hansson@arm.com            // cache should be responding
107011051Sandreas.hansson@arm.com            assert(pkt->cacheResponding());
107111051Sandreas.hansson@arm.com
107211051Sandreas.hansson@arm.com            delete pkt;
107311051Sandreas.hansson@arm.com        }
107411051Sandreas.hansson@arm.com        return snoop_delay;
107511051Sandreas.hansson@arm.com    } else {
107611051Sandreas.hansson@arm.com        DPRINTF(Cache, "%s: snoop hit for %s, old state is %s\n", __func__,
107711333Sandreas.hansson@arm.com                pkt->print(), blk->print());
107811333Sandreas.hansson@arm.com
107912349Snikos.nikoleris@arm.com        // We may end up modifying both the block state and the packet (if
108012349Snikos.nikoleris@arm.com        // we respond in atomic mode), so just figure out what to do now
108111744Snikos.nikoleris@arm.com        // and then do it later. We respond to all snoops that need
108211744Snikos.nikoleris@arm.com        // responses provided we have the block in dirty state. The
108311333Sandreas.hansson@arm.com        // invalidation itself is taken care of below. We don't respond to
108411333Sandreas.hansson@arm.com        // cache maintenance operations as this is done by the destination
108511333Sandreas.hansson@arm.com        // xbar.
108611333Sandreas.hansson@arm.com        respond = blk->isDirty() && pkt->needsResponse();
108711334Sandreas.hansson@arm.com
108811334Sandreas.hansson@arm.com        chatty_assert(!(isReadOnly && blk->isDirty()), "Should never have "
108911051Sandreas.hansson@arm.com                      "a dirty block in a read-only cache %s\n", name());
109011051Sandreas.hansson@arm.com    }
109111051Sandreas.hansson@arm.com
109211051Sandreas.hansson@arm.com    // Invalidate any prefetch's from below that would strip write permissions
109311051Sandreas.hansson@arm.com    // MemCmd::HardPFReq is only observed by upstream caches.  After missing
109411051Sandreas.hansson@arm.com    // above and in it's own cache, a new MemCmd::ReadReq is created that
109511051Sandreas.hansson@arm.com    // downstream caches observe.
109611051Sandreas.hansson@arm.com    if (pkt->mustCheckAbove()) {
109711484Snikos.nikoleris@arm.com        DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s "
109811051Sandreas.hansson@arm.com                "from lower cache\n", pkt->getAddr(), pkt->print());
109911051Sandreas.hansson@arm.com        pkt->setBlockCached();
110011051Sandreas.hansson@arm.com        return snoop_delay;
110112349Snikos.nikoleris@arm.com    }
110212349Snikos.nikoleris@arm.com
110312349Snikos.nikoleris@arm.com    if (pkt->isRead() && !invalidate) {
110412349Snikos.nikoleris@arm.com        // reading without requiring the line in a writable state
110512349Snikos.nikoleris@arm.com        assert(!needs_writable);
110612349Snikos.nikoleris@arm.com        pkt->setHasSharers();
110712349Snikos.nikoleris@arm.com
110812351Snikos.nikoleris@arm.com        // if the requesting packet is uncacheable, retain the line in
110912349Snikos.nikoleris@arm.com        // the current state, otherwhise unset the writable flag,
111012349Snikos.nikoleris@arm.com        // which means we go from Modified to Owned (and will respond
111112349Snikos.nikoleris@arm.com        // below), remain in Owned (and will respond below), from
111212349Snikos.nikoleris@arm.com        // Exclusive to Shared, or remain in Shared
111311051Sandreas.hansson@arm.com        if (!pkt->req->isUncacheable())
111411051Sandreas.hansson@arm.com            blk->status &= ~BlkWritable;
111511130Sali.jafri@arm.com        DPRINTF(Cache, "new state is %s\n", blk->print());
111611051Sandreas.hansson@arm.com    }
111711051Sandreas.hansson@arm.com
111811051Sandreas.hansson@arm.com    if (respond) {
111911051Sandreas.hansson@arm.com        // prevent anyone else from responding, cache as well as
112011452Sandreas.hansson@arm.com        // memory, and also prevent any memory from even seeing the
112112345Snikos.nikoleris@arm.com        // request
112212345Snikos.nikoleris@arm.com        pkt->setCacheResponding();
112311452Sandreas.hansson@arm.com        if (!pkt->isClean() && blk->isWritable()) {
112411452Sandreas.hansson@arm.com            // inform the cache hierarchy that this cache had the line
112511452Sandreas.hansson@arm.com            // in the Modified state so that we avoid unnecessary
112611452Sandreas.hansson@arm.com            // invalidations (see Packet::setResponderHadWritable)
112711452Sandreas.hansson@arm.com            pkt->setResponderHadWritable();
112811452Sandreas.hansson@arm.com
112911452Sandreas.hansson@arm.com            // in the case of an uncacheable request there is no point
113011051Sandreas.hansson@arm.com            // in setting the responderHadWritable flag, but since the
113111484Snikos.nikoleris@arm.com            // recipient does not care there is no harm in doing so
113211051Sandreas.hansson@arm.com        } else {
113311051Sandreas.hansson@arm.com            // if the packet has needsWritable set we invalidate our
113411051Sandreas.hansson@arm.com            // copy below and all other copies will be invalidates
113511051Sandreas.hansson@arm.com            // through express snoops, and if needsWritable is not set
113611051Sandreas.hansson@arm.com            // we already called setHasSharers above
113711051Sandreas.hansson@arm.com        }
113811051Sandreas.hansson@arm.com
113911744Snikos.nikoleris@arm.com        // if we are returning a writable and dirty (Modified) line,
114011744Snikos.nikoleris@arm.com        // we should be invalidating the line
114111051Sandreas.hansson@arm.com        panic_if(!invalidate && !pkt->hasSharers(),
114211051Sandreas.hansson@arm.com                 "%s is passing a Modified line through %s, "
114311051Sandreas.hansson@arm.com                 "but keeping the block", name(), pkt->print());
114411051Sandreas.hansson@arm.com
114511051Sandreas.hansson@arm.com        if (is_timing) {
114611051Sandreas.hansson@arm.com            doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval);
114711051Sandreas.hansson@arm.com        } else {
114811452Sandreas.hansson@arm.com            pkt->makeAtomicResponse();
114911452Sandreas.hansson@arm.com            // packets such as upgrades do not actually have any data
115011051Sandreas.hansson@arm.com            // payload
115111744Snikos.nikoleris@arm.com            if (pkt->hasData())
115211744Snikos.nikoleris@arm.com                pkt->setDataFromBlock(blk->data, blkSize);
115311051Sandreas.hansson@arm.com        }
115411051Sandreas.hansson@arm.com    }
115511051Sandreas.hansson@arm.com
115611051Sandreas.hansson@arm.com    if (!respond && is_deferred) {
115711051Sandreas.hansson@arm.com        assert(pkt->needsResponse());
115811051Sandreas.hansson@arm.com
115911051Sandreas.hansson@arm.com        // if we copied the deferred packet with the intention to
116011051Sandreas.hansson@arm.com        // respond, but are not responding, then a cache above us must
116111051Sandreas.hansson@arm.com        // be, and we can use this as the indication of whether this
116211051Sandreas.hansson@arm.com        // is a packet where we created a copy of the request or not
116311051Sandreas.hansson@arm.com        if (!pkt->cacheResponding()) {
116411051Sandreas.hansson@arm.com            delete pkt->req;
116511051Sandreas.hansson@arm.com        }
116611051Sandreas.hansson@arm.com
116711051Sandreas.hansson@arm.com        delete pkt;
116811051Sandreas.hansson@arm.com    }
116911197Sandreas.hansson@arm.com
117011197Sandreas.hansson@arm.com    // Do this last in case it deallocates block data or something
117111452Sandreas.hansson@arm.com    // like that
117211452Sandreas.hansson@arm.com    if (blk_valid && invalidate) {
117311601Sandreas.hansson@arm.com        invalidateBlock(blk);
117411051Sandreas.hansson@arm.com        DPRINTF(Cache, "new state is %s\n", blk->print());
117511051Sandreas.hansson@arm.com    }
117611051Sandreas.hansson@arm.com
117711051Sandreas.hansson@arm.com    return snoop_delay;
117811197Sandreas.hansson@arm.com}
117911197Sandreas.hansson@arm.com
118011601Sandreas.hansson@arm.com
118111601Sandreas.hansson@arm.comvoid
118211051Sandreas.hansson@arm.comCache::recvTimingSnoopReq(PacketPtr pkt)
118311051Sandreas.hansson@arm.com{
118411051Sandreas.hansson@arm.com    DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print());
118511051Sandreas.hansson@arm.com
118611051Sandreas.hansson@arm.com    // Snoops shouldn't happen when bypassing caches
118711051Sandreas.hansson@arm.com    assert(!system->bypassCaches());
118811051Sandreas.hansson@arm.com
118911051Sandreas.hansson@arm.com    // no need to snoop requests that are not in range
119011452Sandreas.hansson@arm.com    if (!inRange(pkt->getAddr())) {
119111452Sandreas.hansson@arm.com        return;
119211452Sandreas.hansson@arm.com    }
119311452Sandreas.hansson@arm.com
119411051Sandreas.hansson@arm.com    bool is_secure = pkt->isSecure();
119511051Sandreas.hansson@arm.com    CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure);
119611051Sandreas.hansson@arm.com
119711051Sandreas.hansson@arm.com    Addr blk_addr = pkt->getBlockAddr(blkSize);
119811051Sandreas.hansson@arm.com    MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure);
119911051Sandreas.hansson@arm.com
120011051Sandreas.hansson@arm.com    // Update the latency cost of the snoop so that the crossbar can
120111051Sandreas.hansson@arm.com    // account for it. Do not overwrite what other neighbouring caches
120211051Sandreas.hansson@arm.com    // have already done, rather take the maximum. The update is
120311051Sandreas.hansson@arm.com    // tentative, for cases where we return before an upward snoop
120411051Sandreas.hansson@arm.com    // happens below.
120511051Sandreas.hansson@arm.com    pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay,
120611051Sandreas.hansson@arm.com                                         lookupLatency * clockPeriod());
120711197Sandreas.hansson@arm.com
120811130Sali.jafri@arm.com    // Inform request(Prefetch, CleanEvict or Writeback) from below of
120911051Sandreas.hansson@arm.com    // MSHR hit, set setBlockCached.
121011197Sandreas.hansson@arm.com    if (mshr && pkt->mustCheckAbove()) {
121111197Sandreas.hansson@arm.com        DPRINTF(Cache, "Setting block cached for %s from lower cache on "
121211197Sandreas.hansson@arm.com                "mshr hit\n", pkt->print());
121311197Sandreas.hansson@arm.com        pkt->setBlockCached();
121411197Sandreas.hansson@arm.com        return;
121511197Sandreas.hansson@arm.com    }
121611197Sandreas.hansson@arm.com
121711197Sandreas.hansson@arm.com    // Bypass any existing cache maintenance requests if the request
121811197Sandreas.hansson@arm.com    // has been satisfied already (i.e., the dirty block has been
121911197Sandreas.hansson@arm.com    // found).
122011197Sandreas.hansson@arm.com    if (mshr && pkt->req->isCacheMaintenance() && pkt->satisfied()) {
122111197Sandreas.hansson@arm.com        return;
122211197Sandreas.hansson@arm.com    }
122311197Sandreas.hansson@arm.com
122411197Sandreas.hansson@arm.com    // Let the MSHR itself track the snoop and decide whether we want
122511197Sandreas.hansson@arm.com    // to go ahead and do the regular cache snoop
122611197Sandreas.hansson@arm.com    if (mshr && mshr->handleSnoop(pkt, order++)) {
122711197Sandreas.hansson@arm.com        DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)."
122811197Sandreas.hansson@arm.com                "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns",
122911197Sandreas.hansson@arm.com                mshr->print());
123011199Sandreas.hansson@arm.com
123111199Sandreas.hansson@arm.com        if (mshr->getNumTargets() > numTarget)
123211867Snikos.nikoleris@arm.com            warn("allocating bonus target for snoop"); //handle later
123311197Sandreas.hansson@arm.com        return;
123411197Sandreas.hansson@arm.com    }
123511051Sandreas.hansson@arm.com
123611051Sandreas.hansson@arm.com    //We also need to check the writeback buffers and handle those
123711051Sandreas.hansson@arm.com    WriteQueueEntry *wb_entry = writeBuffer.findMatch(blk_addr, is_secure);
123811051Sandreas.hansson@arm.com    if (wb_entry) {
123911051Sandreas.hansson@arm.com        DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n",
124011051Sandreas.hansson@arm.com                pkt->getAddr(), is_secure ? "s" : "ns");
124111051Sandreas.hansson@arm.com        // Expect to see only Writebacks and/or CleanEvicts here, both of
124211051Sandreas.hansson@arm.com        // which should not be generated for uncacheable data.
124311051Sandreas.hansson@arm.com        assert(!wb_entry->isUncacheable());
124411051Sandreas.hansson@arm.com        // There should only be a single request responsible for generating
124511051Sandreas.hansson@arm.com        // Writebacks/CleanEvicts.
124611051Sandreas.hansson@arm.com        assert(wb_entry->getNumTargets() == 1);
124711051Sandreas.hansson@arm.com        PacketPtr wb_pkt = wb_entry->getTarget()->pkt;
124811051Sandreas.hansson@arm.com        assert(wb_pkt->isEviction() || wb_pkt->cmd == MemCmd::WriteClean);
124911051Sandreas.hansson@arm.com
125011051Sandreas.hansson@arm.com        if (pkt->isEviction()) {
125111051Sandreas.hansson@arm.com            // if the block is found in the write queue, set the BLOCK_CACHED
125211051Sandreas.hansson@arm.com            // flag for Writeback/CleanEvict snoop. On return the snoop will
125311051Sandreas.hansson@arm.com            // propagate the BLOCK_CACHED flag in Writeback packets and prevent
125411051Sandreas.hansson@arm.com            // any CleanEvicts from travelling down the memory hierarchy.
125511051Sandreas.hansson@arm.com            pkt->setBlockCached();
125611051Sandreas.hansson@arm.com            DPRINTF(Cache, "%s: Squashing %s from lower cache on writequeue "
125711892Snikos.nikoleris@arm.com                    "hit\n", __func__, pkt->print());
125811051Sandreas.hansson@arm.com            return;
125911051Sandreas.hansson@arm.com        }
126011051Sandreas.hansson@arm.com
126111051Sandreas.hansson@arm.com        // conceptually writebacks are no different to other blocks in
126211051Sandreas.hansson@arm.com        // this cache, so the behaviour is modelled after handleSnoop,
126311051Sandreas.hansson@arm.com        // the difference being that instead of querying the block
126411051Sandreas.hansson@arm.com        // state to determine if it is dirty and writable, we use the
126511051Sandreas.hansson@arm.com        // command and fields of the writeback packet
126611051Sandreas.hansson@arm.com        bool respond = wb_pkt->cmd == MemCmd::WritebackDirty &&
126711051Sandreas.hansson@arm.com            pkt->needsResponse();
126811051Sandreas.hansson@arm.com        bool have_writable = !wb_pkt->hasSharers();
126911051Sandreas.hansson@arm.com        bool invalidate = pkt->isInvalidate();
127011051Sandreas.hansson@arm.com
127111051Sandreas.hansson@arm.com        if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) {
127211051Sandreas.hansson@arm.com            assert(!pkt->needsWritable());
127311051Sandreas.hansson@arm.com            pkt->setHasSharers();
127411051Sandreas.hansson@arm.com            wb_pkt->setHasSharers();
127511051Sandreas.hansson@arm.com        }
127611284Sandreas.hansson@arm.com
127711284Sandreas.hansson@arm.com        if (respond) {
127811051Sandreas.hansson@arm.com            pkt->setCacheResponding();
127911051Sandreas.hansson@arm.com
128011284Sandreas.hansson@arm.com            if (have_writable) {
128111051Sandreas.hansson@arm.com                pkt->setResponderHadWritable();
128211051Sandreas.hansson@arm.com            }
128311051Sandreas.hansson@arm.com
128411051Sandreas.hansson@arm.com            doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(),
128511051Sandreas.hansson@arm.com                                   false, false);
128611051Sandreas.hansson@arm.com        }
128711051Sandreas.hansson@arm.com
128811744Snikos.nikoleris@arm.com        if (invalidate && wb_pkt->cmd != MemCmd::WriteClean) {
128911051Sandreas.hansson@arm.com            // Invalidation trumps our writeback... discard here
129011051Sandreas.hansson@arm.com            // Note: markInService will remove entry from writeback buffer.
129111051Sandreas.hansson@arm.com            markInService(wb_entry);
129211051Sandreas.hansson@arm.com            delete wb_pkt;
129311051Sandreas.hansson@arm.com        }
129411051Sandreas.hansson@arm.com    }
129511051Sandreas.hansson@arm.com
129611051Sandreas.hansson@arm.com    // If this was a shared writeback, there may still be
129711051Sandreas.hansson@arm.com    // other shared copies above that require invalidation.
129811051Sandreas.hansson@arm.com    // We could be more selective and return here if the
129911051Sandreas.hansson@arm.com    // request is non-exclusive or if the writeback is
130011051Sandreas.hansson@arm.com    // exclusive.
130111051Sandreas.hansson@arm.com    uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false);
130211485Snikos.nikoleris@arm.com
130311051Sandreas.hansson@arm.com    // Override what we did when we first saw the snoop, as we now
130411051Sandreas.hansson@arm.com    // also have the cost of the upwards snoops to account for
130511051Sandreas.hansson@arm.com    pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay +
130611051Sandreas.hansson@arm.com                                         lookupLatency * clockPeriod());
130711051Sandreas.hansson@arm.com}
130811051Sandreas.hansson@arm.com
130911051Sandreas.hansson@arm.comTick
131011051Sandreas.hansson@arm.comCache::recvAtomicSnoop(PacketPtr pkt)
131111051Sandreas.hansson@arm.com{
131211051Sandreas.hansson@arm.com    // Snoops shouldn't happen when bypassing caches
131311051Sandreas.hansson@arm.com    assert(!system->bypassCaches());
131411051Sandreas.hansson@arm.com
131511051Sandreas.hansson@arm.com    // no need to snoop requests that are not in range.
131611051Sandreas.hansson@arm.com    if (!inRange(pkt->getAddr())) {
131711051Sandreas.hansson@arm.com        return 0;
131811051Sandreas.hansson@arm.com    }
131911375Sandreas.hansson@arm.com
132011375Sandreas.hansson@arm.com    CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure());
132111375Sandreas.hansson@arm.com    uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false);
132211375Sandreas.hansson@arm.com    return snoop_delay + lookupLatency * clockPeriod();
132311375Sandreas.hansson@arm.com}
132411453Sandreas.hansson@arm.com
132511453Sandreas.hansson@arm.combool
132611375Sandreas.hansson@arm.comCache::isCachedAbove(PacketPtr pkt, bool is_timing)
132711453Sandreas.hansson@arm.com{
132811375Sandreas.hansson@arm.com    if (!forwardSnoops)
132911375Sandreas.hansson@arm.com        return false;
133011375Sandreas.hansson@arm.com    // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and
133111051Sandreas.hansson@arm.com    // Writeback snoops into upper level caches to check for copies of the
133211051Sandreas.hansson@arm.com    // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict
133311051Sandreas.hansson@arm.com    // packet, the cache can inform the crossbar below of presence or absence
133411051Sandreas.hansson@arm.com    // of the block.
133511051Sandreas.hansson@arm.com    if (is_timing) {
133611051Sandreas.hansson@arm.com        Packet snoop_pkt(pkt, true, false);
133711051Sandreas.hansson@arm.com        snoop_pkt.setExpressSnoop();
133811051Sandreas.hansson@arm.com        // Assert that packet is either Writeback or CleanEvict and not a
133911051Sandreas.hansson@arm.com        // prefetch request because prefetch requests need an MSHR and may
134011051Sandreas.hansson@arm.com        // generate a snoop response.
134111051Sandreas.hansson@arm.com        assert(pkt->isEviction() || pkt->cmd == MemCmd::WriteClean);
134211051Sandreas.hansson@arm.com        snoop_pkt.senderState = nullptr;
134311744Snikos.nikoleris@arm.com        cpuSidePort.sendTimingSnoopReq(&snoop_pkt);
134411744Snikos.nikoleris@arm.com        // Writeback/CleanEvict snoops do not generate a snoop response.
134511051Sandreas.hansson@arm.com        assert(!(snoop_pkt.cacheResponding()));
134611051Sandreas.hansson@arm.com        return snoop_pkt.isBlockCached();
134711744Snikos.nikoleris@arm.com    } else {
134811744Snikos.nikoleris@arm.com        cpuSidePort.sendAtomicSnoop(pkt);
134911051Sandreas.hansson@arm.com        return pkt->isBlockCached();
135011375Sandreas.hansson@arm.com    }
135111375Sandreas.hansson@arm.com}
135211375Sandreas.hansson@arm.com
135311375Sandreas.hansson@arm.combool
135411375Sandreas.hansson@arm.comCache::sendMSHRQueuePacket(MSHR* mshr)
135511375Sandreas.hansson@arm.com{
135611375Sandreas.hansson@arm.com    assert(mshr);
135711375Sandreas.hansson@arm.com
135811375Sandreas.hansson@arm.com    // use request from 1st target
135911375Sandreas.hansson@arm.com    PacketPtr tgt_pkt = mshr->getTarget()->pkt;
136011453Sandreas.hansson@arm.com
136111375Sandreas.hansson@arm.com    if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) {
136211051Sandreas.hansson@arm.com        DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print());
136311051Sandreas.hansson@arm.com
136411051Sandreas.hansson@arm.com        // we should never have hardware prefetches to allocated
136511051Sandreas.hansson@arm.com        // blocks
136611484Snikos.nikoleris@arm.com        assert(!tags->findBlock(mshr->blkAddr, mshr->isSecure));
136711051Sandreas.hansson@arm.com
136811051Sandreas.hansson@arm.com        // We need to check the caches above us to verify that
136911051Sandreas.hansson@arm.com        // they don't have a copy of this block in the dirty state
137011051Sandreas.hansson@arm.com        // at the moment. Without this check we could get a stale
137111051Sandreas.hansson@arm.com        // copy from memory that might get used in place of the
137211051Sandreas.hansson@arm.com        // dirty one.
137311051Sandreas.hansson@arm.com        Packet snoop_pkt(tgt_pkt, true, false);
137411051Sandreas.hansson@arm.com        snoop_pkt.setExpressSnoop();
137511051Sandreas.hansson@arm.com        // We are sending this packet upwards, but if it hits we will
137611051Sandreas.hansson@arm.com        // get a snoop response that we end up treating just like a
137711051Sandreas.hansson@arm.com        // normal response, hence it needs the MSHR as its sender
137811051Sandreas.hansson@arm.com        // state
137911051Sandreas.hansson@arm.com        snoop_pkt.senderState = mshr;
138011051Sandreas.hansson@arm.com        cpuSidePort.sendTimingSnoopReq(&snoop_pkt);
138111051Sandreas.hansson@arm.com
138211051Sandreas.hansson@arm.com        // Check to see if the prefetch was squashed by an upper cache (to
138311051Sandreas.hansson@arm.com        // prevent us from grabbing the line) or if a Check to see if a
138411375Sandreas.hansson@arm.com        // writeback arrived between the time the prefetch was placed in
138511375Sandreas.hansson@arm.com        // the MSHRs and when it was selected to be sent or if the
138611375Sandreas.hansson@arm.com        // prefetch was squashed by an upper cache.
138711375Sandreas.hansson@arm.com
138811375Sandreas.hansson@arm.com        // It is important to check cacheResponding before
138911375Sandreas.hansson@arm.com        // prefetchSquashed. If another cache has committed to
139012348Snikos.nikoleris@arm.com        // responding, it will be sending a dirty response which will
139112348Snikos.nikoleris@arm.com        // arrive at the MSHR allocated for this request. Checking the
139212348Snikos.nikoleris@arm.com        // prefetchSquash first may result in the MSHR being
139312348Snikos.nikoleris@arm.com        // prematurely deallocated.
139412348Snikos.nikoleris@arm.com        if (snoop_pkt.cacheResponding()) {
139512348Snikos.nikoleris@arm.com            auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req);
139612348Snikos.nikoleris@arm.com            assert(r.second);
139712348Snikos.nikoleris@arm.com
139812349Snikos.nikoleris@arm.com            // if we are getting a snoop response with no sharers it
139912349Snikos.nikoleris@arm.com            // will be allocated as Modified
140011284Sandreas.hansson@arm.com            bool pending_modified_resp = !snoop_pkt.hasSharers();
140111177Sandreas.hansson@arm.com            markInService(mshr, pending_modified_resp);
140211177Sandreas.hansson@arm.com
140311051Sandreas.hansson@arm.com            DPRINTF(Cache, "Upward snoop of prefetch for addr"
140411051Sandreas.hansson@arm.com                    " %#x (%s) hit\n",
140511051Sandreas.hansson@arm.com                    tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns");
140611051Sandreas.hansson@arm.com            return false;
140711741Snikos.nikoleris@arm.com        }
140811484Snikos.nikoleris@arm.com
140911051Sandreas.hansson@arm.com        if (snoop_pkt.isBlockCached()) {
141011051Sandreas.hansson@arm.com            DPRINTF(Cache, "Block present, prefetch squashed by cache.  "
141111051Sandreas.hansson@arm.com                    "Deallocating mshr target %#x.\n",
141211051Sandreas.hansson@arm.com                    mshr->blkAddr);
141311136Sandreas.hansson@arm.com
141411051Sandreas.hansson@arm.com            // Deallocate the mshr target
141512349Snikos.nikoleris@arm.com            if (mshrQueue.forceDeallocateTarget(mshr)) {
141612349Snikos.nikoleris@arm.com                // Clear block if this deallocation resulted freed an
141712349Snikos.nikoleris@arm.com                // mshr when all had previously been utilized
141812349Snikos.nikoleris@arm.com                clearBlocked(Blocked_NoMSHRs);
141912349Snikos.nikoleris@arm.com            }
142012349Snikos.nikoleris@arm.com
142111051Sandreas.hansson@arm.com            // given that no response is expected, delete Request and Packet
142211051Sandreas.hansson@arm.com            delete tgt_pkt->req;
142311051Sandreas.hansson@arm.com            delete tgt_pkt;
142411601Sandreas.hansson@arm.com
142511742Snikos.nikoleris@arm.com            return false;
142611742Snikos.nikoleris@arm.com        }
142711742Snikos.nikoleris@arm.com    }
142811742Snikos.nikoleris@arm.com
142911051Sandreas.hansson@arm.com    return BaseCache::sendMSHRQueuePacket(mshr);
143011051Sandreas.hansson@arm.com}
143111051Sandreas.hansson@arm.com
143211051Sandreas.hansson@arm.comCache*
143311051Sandreas.hansson@arm.comCacheParams::create()
143411051Sandreas.hansson@arm.com{
143511051Sandreas.hansson@arm.com    assert(tags);
143611051Sandreas.hansson@arm.com    assert(replacement_policy);
143711483Snikos.nikoleris@arm.com
143811483Snikos.nikoleris@arm.com    return new Cache(this);
143911483Snikos.nikoleris@arm.com}
144011483Snikos.nikoleris@arm.com