cache.cc revision 2810
16145SN/A/*
28683SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
310973Sdavid.hashe@amd.com * All rights reserved.
46145SN/A *
56145SN/A * Redistribution and use in source and binary forms, with or without
66145SN/A * modification, are permitted provided that the following conditions are
76145SN/A * met: redistributions of source code must retain the above copyright
86145SN/A * notice, this list of conditions and the following disclaimer;
96145SN/A * redistributions in binary form must reproduce the above copyright
106145SN/A * notice, this list of conditions and the following disclaimer in the
116145SN/A * documentation and/or other materials provided with the distribution;
126145SN/A * neither the name of the copyright holders nor the names of its
136145SN/A * contributors may be used to endorse or promote products derived from
146145SN/A * this software without specific prior written permission.
156145SN/A *
166145SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
176145SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
186145SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
196145SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
206145SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
216145SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
226145SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
236145SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
246145SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
256145SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
266145SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
276145SN/A *
286145SN/A * Authors: Erik Hallnor
296145SN/A *          Steve Reinhardt
3010441Snilay@cs.wisc.edu *          Lisa Hsu
3110441Snilay@cs.wisc.edu *          Kevin Lim
326145SN/A */
337055SN/A
346145SN/A/**
356145SN/A * @file
367039SN/A * Cache template instantiations.
379104SN/A */
3810301Snilay@cs.wisc.edu
399105SN/A#include "mem/config/cache.hh"
408174SN/A#include "mem/config/compression.hh"
417039SN/A
427039SN/A#include "mem/cache/tags/cache_tags.hh"
437039SN/A
4410970Sdavid.hashe@amd.com#if defined(USE_CACHE_LRU)
4510301Snilay@cs.wisc.edu#include "mem/cache/tags/lru.hh"
4610301Snilay@cs.wisc.edu#endif
477039SN/A
487039SN/A#if defined(USE_CACHE_FALRU)
496145SN/A#include "mem/cache/tags/fa_lru.hh"
507039SN/A#endif
517039SN/A
527039SN/A#if defined(USE_CACHE_IIC)
536876SN/A#include "mem/cache/tags/iic.hh"
547039SN/A#endif
557039SN/A
566145SN/A#if defined(USE_CACHE_SPLIT)
577039SN/A#include "mem/cache/tags/split.hh"
586145SN/A#endif
5911049Snilay@cs.wisc.edu
6011049Snilay@cs.wisc.edu#if defined(USE_CACHE_SPLIT_LIFO)
6111049Snilay@cs.wisc.edu#include "mem/cache/tags/split_lifo.hh"
6211049Snilay@cs.wisc.edu#endif
6311049Snilay@cs.wisc.edu
6411049Snilay@cs.wisc.edu#include "base/compression/null_compression.hh"
6511049Snilay@cs.wisc.edu#if defined(USE_LZSS_COMPRESSION)
6611049Snilay@cs.wisc.edu#include "base/compression/lzss_compression.hh"
6711049Snilay@cs.wisc.edu#endif
687039SN/A
6911025Snilay@cs.wisc.edu#include "mem/cache/miss/miss_queue.hh"
706145SN/A#include "mem/cache/miss/blocking_buffer.hh"
717039SN/A
727039SN/A#include "mem/cache/coherence/uni_coherence.hh"
737039SN/A#include "mem/cache/coherence/simple_coherence.hh"
7411025Snilay@cs.wisc.edu
756145SN/A#include "mem/cache/cache_impl.hh"
767039SN/A
7711025Snilay@cs.wisc.edu// Template Instantiations
7810974Sdavid.hashe@amd.com#ifndef DOXYGEN_SHOULD_SKIP_THIS
7911025Snilay@cs.wisc.edu
8010974Sdavid.hashe@amd.com
8110974Sdavid.hashe@amd.com#if defined(USE_CACHE_FALRU)
8210974Sdavid.hashe@amd.comtemplate class Cache<CacheTags<FALRU,NullCompression>, BlockingBuffer, SimpleCoherence>;
8311025Snilay@cs.wisc.edutemplate class Cache<CacheTags<FALRU,NullCompression>, BlockingBuffer, UniCoherence>;
848193SN/Atemplate class Cache<CacheTags<FALRU,NullCompression>, MissQueue, SimpleCoherence>;
8510974Sdavid.hashe@amd.comtemplate class Cache<CacheTags<FALRU,NullCompression>, MissQueue, UniCoherence>;
868193SN/A#if defined(USE_LZSS_COMPRESSION)
876145SN/Atemplate class Cache<CacheTags<FALRU,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
887039SN/Atemplate class Cache<CacheTags<FALRU,LZSSCompression>, BlockingBuffer, UniCoherence>;
8911025Snilay@cs.wisc.edutemplate class Cache<CacheTags<FALRU,LZSSCompression>, MissQueue, SimpleCoherence>;
906145SN/Atemplate class Cache<CacheTags<FALRU,LZSSCompression>, MissQueue, UniCoherence>;
917039SN/A#endif
9211025Snilay@cs.wisc.edu#endif
936145SN/A
947039SN/A#if defined(USE_CACHE_IIC)
9511025Snilay@cs.wisc.edutemplate class Cache<CacheTags<IIC,NullCompression>, BlockingBuffer, SimpleCoherence>;
9611025Snilay@cs.wisc.edutemplate class Cache<CacheTags<IIC,NullCompression>, BlockingBuffer, UniCoherence>;
976145SN/Atemplate class Cache<CacheTags<IIC,NullCompression>, MissQueue, SimpleCoherence>;
9810969Sdavid.hashe@amd.comtemplate class Cache<CacheTags<IIC,NullCompression>, MissQueue, UniCoherence>;
9910969Sdavid.hashe@amd.com#if defined(USE_LZSS_COMPRESSION)
10010969Sdavid.hashe@amd.comtemplate class Cache<CacheTags<IIC,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
10111049Snilay@cs.wisc.edutemplate class Cache<CacheTags<IIC,LZSSCompression>, BlockingBuffer, UniCoherence>;
10211049Snilay@cs.wisc.edutemplate class Cache<CacheTags<IIC,LZSSCompression>, MissQueue, SimpleCoherence>;
1036285SN/Atemplate class Cache<CacheTags<IIC,LZSSCompression>, MissQueue, UniCoherence>;
1047039SN/A#endif
1058683SN/A#endif
1066145SN/A
1077039SN/A#if defined(USE_CACHE_LRU)
10811025Snilay@cs.wisc.edutemplate class Cache<CacheTags<LRU,NullCompression>, BlockingBuffer, SimpleCoherence>;
1096145SN/Atemplate class Cache<CacheTags<LRU,NullCompression>, BlockingBuffer, UniCoherence>;
11011059Snilay@cs.wisc.edutemplate class Cache<CacheTags<LRU,NullCompression>, MissQueue, SimpleCoherence>;
11111059Snilay@cs.wisc.edutemplate class Cache<CacheTags<LRU,NullCompression>, MissQueue, UniCoherence>;
11211059Snilay@cs.wisc.edu#if defined(USE_LZSS_COMPRESSION)
11311059Snilay@cs.wisc.edutemplate class Cache<CacheTags<LRU,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
11411059Snilay@cs.wisc.edutemplate class Cache<CacheTags<LRU,LZSSCompression>, BlockingBuffer, UniCoherence>;
11511025Snilay@cs.wisc.edutemplate class Cache<CacheTags<LRU,LZSSCompression>, MissQueue, SimpleCoherence>;
11611025Snilay@cs.wisc.edutemplate class Cache<CacheTags<LRU,LZSSCompression>, MissQueue, UniCoherence>;
11711025Snilay@cs.wisc.edu#endif
1189692SN/A#endif
1197039SN/A
1207055SN/A#if defined(USE_CACHE_SPLIT)
1217055SN/Atemplate class Cache<CacheTags<Split,NullCompression>, BlockingBuffer, SimpleCoherence>;
1226145SN/Atemplate class Cache<CacheTags<Split,NullCompression>, BlockingBuffer, UniCoherence>;
1239692SN/Atemplate class Cache<CacheTags<Split,NullCompression>, MissQueue, SimpleCoherence>;
12411025Snilay@cs.wisc.edutemplate class Cache<CacheTags<Split,NullCompression>, MissQueue, UniCoherence>;
12511025Snilay@cs.wisc.edu#if defined(USE_LZSS_COMPRESSION)
1266374SN/Atemplate class Cache<CacheTags<Split,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
1279692SN/Atemplate class Cache<CacheTags<Split,LZSSCompression>, BlockingBuffer, UniCoherence>;
1289692SN/Atemplate class Cache<CacheTags<Split,LZSSCompression>, MissQueue, SimpleCoherence>;
1299692SN/Atemplate class Cache<CacheTags<Split,LZSSCompression>, MissQueue, UniCoherence>;
1309692SN/A#endif
1319692SN/A#endif
1329692SN/A
1339692SN/A#if defined(USE_CACHE_SPLIT_LIFO)
1349692SN/Atemplate class Cache<CacheTags<SplitLIFO,NullCompression>, BlockingBuffer, SimpleCoherence>;
1359692SN/Atemplate class Cache<CacheTags<SplitLIFO,NullCompression>, BlockingBuffer, UniCoherence>;
1369692SN/Atemplate class Cache<CacheTags<SplitLIFO,NullCompression>, MissQueue, SimpleCoherence>;
1379104SN/Atemplate class Cache<CacheTags<SplitLIFO,NullCompression>, MissQueue, UniCoherence>;
1389104SN/A#if defined(USE_LZSS_COMPRESSION)
1399104SN/Atemplate class Cache<CacheTags<SplitLIFO,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
1409104SN/Atemplate class Cache<CacheTags<SplitLIFO,LZSSCompression>, BlockingBuffer, UniCoherence>;
1419104SN/Atemplate class Cache<CacheTags<SplitLIFO,LZSSCompression>, MissQueue, SimpleCoherence>;
1429104SN/Atemplate class Cache<CacheTags<SplitLIFO,LZSSCompression>, MissQueue, UniCoherence>;
1439105SN/A#endif
1449105SN/A#endif
1459692SN/A
14610973Sdavid.hashe@amd.com#endif //DOXYGEN_SHOULD_SKIP_THIS
14710973Sdavid.hashe@amd.com