cache.cc revision 2810
12810Srdreslin@umich.edu/*
22810Srdreslin@umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan
32810Srdreslin@umich.edu * All rights reserved.
42810Srdreslin@umich.edu *
52810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without
62810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are
72810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright
82810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer;
92810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright
102810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the
112810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution;
122810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its
132810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from
142810Srdreslin@umich.edu * this software without specific prior written permission.
152810Srdreslin@umich.edu *
162810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272810Srdreslin@umich.edu *
282810Srdreslin@umich.edu * Authors: Erik Hallnor
292810Srdreslin@umich.edu *          Steve Reinhardt
302810Srdreslin@umich.edu *          Lisa Hsu
312810Srdreslin@umich.edu *          Kevin Lim
322810Srdreslin@umich.edu */
332810Srdreslin@umich.edu
342810Srdreslin@umich.edu/**
352810Srdreslin@umich.edu * @file
362810Srdreslin@umich.edu * Cache template instantiations.
372810Srdreslin@umich.edu */
382810Srdreslin@umich.edu
392810Srdreslin@umich.edu#include "mem/config/cache.hh"
402810Srdreslin@umich.edu#include "mem/config/compression.hh"
412810Srdreslin@umich.edu
422810Srdreslin@umich.edu#include "mem/cache/tags/cache_tags.hh"
432810Srdreslin@umich.edu
442810Srdreslin@umich.edu#if defined(USE_CACHE_LRU)
452810Srdreslin@umich.edu#include "mem/cache/tags/lru.hh"
462810Srdreslin@umich.edu#endif
472810Srdreslin@umich.edu
482810Srdreslin@umich.edu#if defined(USE_CACHE_FALRU)
492810Srdreslin@umich.edu#include "mem/cache/tags/fa_lru.hh"
502810Srdreslin@umich.edu#endif
512810Srdreslin@umich.edu
522810Srdreslin@umich.edu#if defined(USE_CACHE_IIC)
532810Srdreslin@umich.edu#include "mem/cache/tags/iic.hh"
542810Srdreslin@umich.edu#endif
552810Srdreslin@umich.edu
562810Srdreslin@umich.edu#if defined(USE_CACHE_SPLIT)
572810Srdreslin@umich.edu#include "mem/cache/tags/split.hh"
582810Srdreslin@umich.edu#endif
592810Srdreslin@umich.edu
602810Srdreslin@umich.edu#if defined(USE_CACHE_SPLIT_LIFO)
612810Srdreslin@umich.edu#include "mem/cache/tags/split_lifo.hh"
622810Srdreslin@umich.edu#endif
632810Srdreslin@umich.edu
642810Srdreslin@umich.edu#include "base/compression/null_compression.hh"
652810Srdreslin@umich.edu#if defined(USE_LZSS_COMPRESSION)
662810Srdreslin@umich.edu#include "base/compression/lzss_compression.hh"
672810Srdreslin@umich.edu#endif
682810Srdreslin@umich.edu
692810Srdreslin@umich.edu#include "mem/cache/miss/miss_queue.hh"
702810Srdreslin@umich.edu#include "mem/cache/miss/blocking_buffer.hh"
712810Srdreslin@umich.edu
722810Srdreslin@umich.edu#include "mem/cache/coherence/uni_coherence.hh"
732810Srdreslin@umich.edu#include "mem/cache/coherence/simple_coherence.hh"
742810Srdreslin@umich.edu
752810Srdreslin@umich.edu#include "mem/cache/cache_impl.hh"
762810Srdreslin@umich.edu
772810Srdreslin@umich.edu// Template Instantiations
782810Srdreslin@umich.edu#ifndef DOXYGEN_SHOULD_SKIP_THIS
792810Srdreslin@umich.edu
802810Srdreslin@umich.edu
812810Srdreslin@umich.edu#if defined(USE_CACHE_FALRU)
822810Srdreslin@umich.edutemplate class Cache<CacheTags<FALRU,NullCompression>, BlockingBuffer, SimpleCoherence>;
832810Srdreslin@umich.edutemplate class Cache<CacheTags<FALRU,NullCompression>, BlockingBuffer, UniCoherence>;
842810Srdreslin@umich.edutemplate class Cache<CacheTags<FALRU,NullCompression>, MissQueue, SimpleCoherence>;
852810Srdreslin@umich.edutemplate class Cache<CacheTags<FALRU,NullCompression>, MissQueue, UniCoherence>;
862810Srdreslin@umich.edu#if defined(USE_LZSS_COMPRESSION)
872810Srdreslin@umich.edutemplate class Cache<CacheTags<FALRU,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
882810Srdreslin@umich.edutemplate class Cache<CacheTags<FALRU,LZSSCompression>, BlockingBuffer, UniCoherence>;
892810Srdreslin@umich.edutemplate class Cache<CacheTags<FALRU,LZSSCompression>, MissQueue, SimpleCoherence>;
902810Srdreslin@umich.edutemplate class Cache<CacheTags<FALRU,LZSSCompression>, MissQueue, UniCoherence>;
912810Srdreslin@umich.edu#endif
922810Srdreslin@umich.edu#endif
932810Srdreslin@umich.edu
942810Srdreslin@umich.edu#if defined(USE_CACHE_IIC)
952810Srdreslin@umich.edutemplate class Cache<CacheTags<IIC,NullCompression>, BlockingBuffer, SimpleCoherence>;
962810Srdreslin@umich.edutemplate class Cache<CacheTags<IIC,NullCompression>, BlockingBuffer, UniCoherence>;
972810Srdreslin@umich.edutemplate class Cache<CacheTags<IIC,NullCompression>, MissQueue, SimpleCoherence>;
982810Srdreslin@umich.edutemplate class Cache<CacheTags<IIC,NullCompression>, MissQueue, UniCoherence>;
992810Srdreslin@umich.edu#if defined(USE_LZSS_COMPRESSION)
1002810Srdreslin@umich.edutemplate class Cache<CacheTags<IIC,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
1012810Srdreslin@umich.edutemplate class Cache<CacheTags<IIC,LZSSCompression>, BlockingBuffer, UniCoherence>;
1022810Srdreslin@umich.edutemplate class Cache<CacheTags<IIC,LZSSCompression>, MissQueue, SimpleCoherence>;
1032810Srdreslin@umich.edutemplate class Cache<CacheTags<IIC,LZSSCompression>, MissQueue, UniCoherence>;
1042810Srdreslin@umich.edu#endif
1052810Srdreslin@umich.edu#endif
1062810Srdreslin@umich.edu
1072810Srdreslin@umich.edu#if defined(USE_CACHE_LRU)
1082810Srdreslin@umich.edutemplate class Cache<CacheTags<LRU,NullCompression>, BlockingBuffer, SimpleCoherence>;
1092810Srdreslin@umich.edutemplate class Cache<CacheTags<LRU,NullCompression>, BlockingBuffer, UniCoherence>;
1102810Srdreslin@umich.edutemplate class Cache<CacheTags<LRU,NullCompression>, MissQueue, SimpleCoherence>;
1112810Srdreslin@umich.edutemplate class Cache<CacheTags<LRU,NullCompression>, MissQueue, UniCoherence>;
1122810Srdreslin@umich.edu#if defined(USE_LZSS_COMPRESSION)
1132810Srdreslin@umich.edutemplate class Cache<CacheTags<LRU,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
1142810Srdreslin@umich.edutemplate class Cache<CacheTags<LRU,LZSSCompression>, BlockingBuffer, UniCoherence>;
1152810Srdreslin@umich.edutemplate class Cache<CacheTags<LRU,LZSSCompression>, MissQueue, SimpleCoherence>;
1162810Srdreslin@umich.edutemplate class Cache<CacheTags<LRU,LZSSCompression>, MissQueue, UniCoherence>;
1172810Srdreslin@umich.edu#endif
1182810Srdreslin@umich.edu#endif
1192810Srdreslin@umich.edu
1202810Srdreslin@umich.edu#if defined(USE_CACHE_SPLIT)
1212810Srdreslin@umich.edutemplate class Cache<CacheTags<Split,NullCompression>, BlockingBuffer, SimpleCoherence>;
1222810Srdreslin@umich.edutemplate class Cache<CacheTags<Split,NullCompression>, BlockingBuffer, UniCoherence>;
1232810Srdreslin@umich.edutemplate class Cache<CacheTags<Split,NullCompression>, MissQueue, SimpleCoherence>;
1242810Srdreslin@umich.edutemplate class Cache<CacheTags<Split,NullCompression>, MissQueue, UniCoherence>;
1252810Srdreslin@umich.edu#if defined(USE_LZSS_COMPRESSION)
1262810Srdreslin@umich.edutemplate class Cache<CacheTags<Split,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
1272810Srdreslin@umich.edutemplate class Cache<CacheTags<Split,LZSSCompression>, BlockingBuffer, UniCoherence>;
1282810Srdreslin@umich.edutemplate class Cache<CacheTags<Split,LZSSCompression>, MissQueue, SimpleCoherence>;
1292810Srdreslin@umich.edutemplate class Cache<CacheTags<Split,LZSSCompression>, MissQueue, UniCoherence>;
1302810Srdreslin@umich.edu#endif
1312810Srdreslin@umich.edu#endif
1322810Srdreslin@umich.edu
1332810Srdreslin@umich.edu#if defined(USE_CACHE_SPLIT_LIFO)
1342810Srdreslin@umich.edutemplate class Cache<CacheTags<SplitLIFO,NullCompression>, BlockingBuffer, SimpleCoherence>;
1352810Srdreslin@umich.edutemplate class Cache<CacheTags<SplitLIFO,NullCompression>, BlockingBuffer, UniCoherence>;
1362810Srdreslin@umich.edutemplate class Cache<CacheTags<SplitLIFO,NullCompression>, MissQueue, SimpleCoherence>;
1372810Srdreslin@umich.edutemplate class Cache<CacheTags<SplitLIFO,NullCompression>, MissQueue, UniCoherence>;
1382810Srdreslin@umich.edu#if defined(USE_LZSS_COMPRESSION)
1392810Srdreslin@umich.edutemplate class Cache<CacheTags<SplitLIFO,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
1402810Srdreslin@umich.edutemplate class Cache<CacheTags<SplitLIFO,LZSSCompression>, BlockingBuffer, UniCoherence>;
1412810Srdreslin@umich.edutemplate class Cache<CacheTags<SplitLIFO,LZSSCompression>, MissQueue, SimpleCoherence>;
1422810Srdreslin@umich.edutemplate class Cache<CacheTags<SplitLIFO,LZSSCompression>, MissQueue, UniCoherence>;
1432810Srdreslin@umich.edu#endif
1442810Srdreslin@umich.edu#endif
1452810Srdreslin@umich.edu
1462810Srdreslin@umich.edu#endif //DOXYGEN_SHOULD_SKIP_THIS
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