cache.cc revision 14118
12810Srdreslin@umich.edu/* 213732Snikos.nikoleris@arm.com * Copyright (c) 2010-2019 ARM Limited 311051Sandreas.hansson@arm.com * All rights reserved. 411051Sandreas.hansson@arm.com * 511051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911051Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311051Sandreas.hansson@arm.com * 1411051Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511051Sandreas.hansson@arm.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 162810Srdreslin@umich.edu * All rights reserved. 172810Srdreslin@umich.edu * 182810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 192810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 202810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 212810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 222810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 232810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 242810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 252810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 262810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 272810Srdreslin@umich.edu * this software without specific prior written permission. 282810Srdreslin@umich.edu * 292810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810Srdreslin@umich.edu * 412810Srdreslin@umich.edu * Authors: Erik Hallnor 4211051Sandreas.hansson@arm.com * Dave Greene 4311051Sandreas.hansson@arm.com * Nathan Binkert 442810Srdreslin@umich.edu * Steve Reinhardt 4511051Sandreas.hansson@arm.com * Ron Dreslinski 4611051Sandreas.hansson@arm.com * Andreas Sandberg 4712349Snikos.nikoleris@arm.com * Nikos Nikoleris 482810Srdreslin@umich.edu */ 492810Srdreslin@umich.edu 502810Srdreslin@umich.edu/** 512810Srdreslin@umich.edu * @file 5211051Sandreas.hansson@arm.com * Cache definitions. 532810Srdreslin@umich.edu */ 542810Srdreslin@umich.edu 5511051Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 562810Srdreslin@umich.edu 5712724Snikos.nikoleris@arm.com#include <cassert> 5812724Snikos.nikoleris@arm.com 5912724Snikos.nikoleris@arm.com#include "base/compiler.hh" 6012334Sgabeblack@google.com#include "base/logging.hh" 6112724Snikos.nikoleris@arm.com#include "base/trace.hh" 6211051Sandreas.hansson@arm.com#include "base/types.hh" 6311051Sandreas.hansson@arm.com#include "debug/Cache.hh" 6411051Sandreas.hansson@arm.com#include "debug/CacheTags.hh" 6511288Ssteve.reinhardt@amd.com#include "debug/CacheVerbose.hh" 6612724Snikos.nikoleris@arm.com#include "enums/Clusivity.hh" 6713223Sodanrc@yahoo.com.br#include "mem/cache/cache_blk.hh" 6811051Sandreas.hansson@arm.com#include "mem/cache/mshr.hh" 6912724Snikos.nikoleris@arm.com#include "mem/cache/tags/base.hh" 7012724Snikos.nikoleris@arm.com#include "mem/cache/write_queue_entry.hh" 7112724Snikos.nikoleris@arm.com#include "mem/request.hh" 7212724Snikos.nikoleris@arm.com#include "params/Cache.hh" 7311051Sandreas.hansson@arm.com 7411053Sandreas.hansson@arm.comCache::Cache(const CacheParams *p) 7511053Sandreas.hansson@arm.com : BaseCache(p, p->system->cacheLineSize()), 7612724Snikos.nikoleris@arm.com doFastWrites(true) 7711051Sandreas.hansson@arm.com{ 7811051Sandreas.hansson@arm.com} 7911051Sandreas.hansson@arm.com 8011051Sandreas.hansson@arm.comvoid 8111601Sandreas.hansson@arm.comCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, 8211601Sandreas.hansson@arm.com bool deferred_response, bool pending_downgrade) 8311051Sandreas.hansson@arm.com{ 8412724Snikos.nikoleris@arm.com BaseCache::satisfyRequest(pkt, blk); 8511051Sandreas.hansson@arm.com 8612724Snikos.nikoleris@arm.com if (pkt->isRead()) { 8711600Sandreas.hansson@arm.com // determine if this read is from a (coherent) cache or not 8811600Sandreas.hansson@arm.com if (pkt->fromCache()) { 8911051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 9011051Sandreas.hansson@arm.com // special handling for coherent block requests from 9111051Sandreas.hansson@arm.com // upper-level caches 9211284Sandreas.hansson@arm.com if (pkt->needsWritable()) { 9311051Sandreas.hansson@arm.com // sanity check 9411051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::ReadExReq || 9511051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq); 9611602Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 9711051Sandreas.hansson@arm.com 9811051Sandreas.hansson@arm.com // if we have a dirty copy, make sure the recipient 9911284Sandreas.hansson@arm.com // keeps it marked dirty (in the modified state) 10011051Sandreas.hansson@arm.com if (blk->isDirty()) { 10111284Sandreas.hansson@arm.com pkt->setCacheResponding(); 10211602Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 10311051Sandreas.hansson@arm.com } 10411051Sandreas.hansson@arm.com } else if (blk->isWritable() && !pending_downgrade && 10511284Sandreas.hansson@arm.com !pkt->hasSharers() && 10611051Sandreas.hansson@arm.com pkt->cmd != MemCmd::ReadCleanReq) { 10711284Sandreas.hansson@arm.com // we can give the requester a writable copy on a read 10811284Sandreas.hansson@arm.com // request if: 10911284Sandreas.hansson@arm.com // - we have a writable copy at this level (& below) 11011051Sandreas.hansson@arm.com // - we don't have a pending snoop from below 11111051Sandreas.hansson@arm.com // signaling another read request 11211051Sandreas.hansson@arm.com // - no other cache above has a copy (otherwise it 11311284Sandreas.hansson@arm.com // would have set hasSharers flag when 11411284Sandreas.hansson@arm.com // snooping the packet) 11511284Sandreas.hansson@arm.com // - the read has explicitly asked for a clean 11611284Sandreas.hansson@arm.com // copy of the line 11711051Sandreas.hansson@arm.com if (blk->isDirty()) { 11811051Sandreas.hansson@arm.com // special considerations if we're owner: 11911051Sandreas.hansson@arm.com if (!deferred_response) { 12011284Sandreas.hansson@arm.com // respond with the line in Modified state 12111284Sandreas.hansson@arm.com // (cacheResponding set, hasSharers not set) 12211284Sandreas.hansson@arm.com pkt->setCacheResponding(); 12311197Sandreas.hansson@arm.com 12411601Sandreas.hansson@arm.com // if this cache is mostly inclusive, we 12511601Sandreas.hansson@arm.com // keep the block in the Exclusive state, 12611601Sandreas.hansson@arm.com // and pass it upwards as Modified 12711601Sandreas.hansson@arm.com // (writable and dirty), hence we have 12811601Sandreas.hansson@arm.com // multiple caches, all on the same path 12911601Sandreas.hansson@arm.com // towards memory, all considering the 13011601Sandreas.hansson@arm.com // same block writable, but only one 13111601Sandreas.hansson@arm.com // considering it Modified 13211197Sandreas.hansson@arm.com 13311601Sandreas.hansson@arm.com // we get away with multiple caches (on 13411601Sandreas.hansson@arm.com // the same path to memory) considering 13511601Sandreas.hansson@arm.com // the block writeable as we always enter 13611601Sandreas.hansson@arm.com // the cache hierarchy through a cache, 13711601Sandreas.hansson@arm.com // and first snoop upwards in all other 13811601Sandreas.hansson@arm.com // branches 13911601Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 14011051Sandreas.hansson@arm.com } else { 14111051Sandreas.hansson@arm.com // if we're responding after our own miss, 14211051Sandreas.hansson@arm.com // there's a window where the recipient didn't 14311051Sandreas.hansson@arm.com // know it was getting ownership and may not 14411051Sandreas.hansson@arm.com // have responded to snoops correctly, so we 14511284Sandreas.hansson@arm.com // have to respond with a shared line 14611284Sandreas.hansson@arm.com pkt->setHasSharers(); 14711051Sandreas.hansson@arm.com } 14811051Sandreas.hansson@arm.com } 14911051Sandreas.hansson@arm.com } else { 15011051Sandreas.hansson@arm.com // otherwise only respond with a shared copy 15111284Sandreas.hansson@arm.com pkt->setHasSharers(); 15211051Sandreas.hansson@arm.com } 15311051Sandreas.hansson@arm.com } 15411051Sandreas.hansson@arm.com } 15511051Sandreas.hansson@arm.com} 15611051Sandreas.hansson@arm.com 15711051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 15811051Sandreas.hansson@arm.com// 15911051Sandreas.hansson@arm.com// Access path: requests coming in from the CPU side 16011051Sandreas.hansson@arm.com// 16111051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 16211051Sandreas.hansson@arm.com 16311051Sandreas.hansson@arm.combool 16414035Sodanrc@yahoo.com.brCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 16514035Sodanrc@yahoo.com.br PacketList &writebacks) 16611051Sandreas.hansson@arm.com{ 16711051Sandreas.hansson@arm.com 16811051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 16912724Snikos.nikoleris@arm.com assert(pkt->isRequest()); 17012724Snikos.nikoleris@arm.com 17112724Snikos.nikoleris@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 17212724Snikos.nikoleris@arm.com "Should never see a write in a read-only cache %s\n", 17312724Snikos.nikoleris@arm.com name()); 17412724Snikos.nikoleris@arm.com 17512724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s for %s\n", __func__, pkt->print()); 17611051Sandreas.hansson@arm.com 17711051Sandreas.hansson@arm.com // flush and invalidate any existing block 17811051Sandreas.hansson@arm.com CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure())); 17911051Sandreas.hansson@arm.com if (old_blk && old_blk->isValid()) { 18014035Sodanrc@yahoo.com.br BaseCache::evictBlock(old_blk, writebacks); 18111051Sandreas.hansson@arm.com } 18211051Sandreas.hansson@arm.com 18311484Snikos.nikoleris@arm.com blk = nullptr; 18414035Sodanrc@yahoo.com.br // lookupLatency is the latency in case the request is uncacheable. 18514035Sodanrc@yahoo.com.br lat = lookupLatency; 18611051Sandreas.hansson@arm.com return false; 18711051Sandreas.hansson@arm.com } 18811051Sandreas.hansson@arm.com 18914035Sodanrc@yahoo.com.br return BaseCache::access(pkt, blk, lat, writebacks); 19011601Sandreas.hansson@arm.com} 19111601Sandreas.hansson@arm.com 19211601Sandreas.hansson@arm.comvoid 19314035Sodanrc@yahoo.com.brCache::doWritebacks(PacketList& writebacks, Tick forward_time) 19411051Sandreas.hansson@arm.com{ 19514035Sodanrc@yahoo.com.br while (!writebacks.empty()) { 19614035Sodanrc@yahoo.com.br PacketPtr wbPkt = writebacks.front(); 19714035Sodanrc@yahoo.com.br // We use forwardLatency here because we are copying writebacks to 19814035Sodanrc@yahoo.com.br // write buffer. 19912345Snikos.nikoleris@arm.com 20014035Sodanrc@yahoo.com.br // Call isCachedAbove for Writebacks, CleanEvicts and 20114035Sodanrc@yahoo.com.br // WriteCleans to discover if the block is cached above. 20214035Sodanrc@yahoo.com.br if (isCachedAbove(wbPkt)) { 20314035Sodanrc@yahoo.com.br if (wbPkt->cmd == MemCmd::CleanEvict) { 20414035Sodanrc@yahoo.com.br // Delete CleanEvict because cached copies exist above. The 20514035Sodanrc@yahoo.com.br // packet destructor will delete the request object because 20614035Sodanrc@yahoo.com.br // this is a non-snoop request packet which does not require a 20714035Sodanrc@yahoo.com.br // response. 20814035Sodanrc@yahoo.com.br delete wbPkt; 20914035Sodanrc@yahoo.com.br } else if (wbPkt->cmd == MemCmd::WritebackClean) { 21014035Sodanrc@yahoo.com.br // clean writeback, do not send since the block is 21114035Sodanrc@yahoo.com.br // still cached above 21214035Sodanrc@yahoo.com.br assert(writebackClean); 21314035Sodanrc@yahoo.com.br delete wbPkt; 21414035Sodanrc@yahoo.com.br } else { 21514035Sodanrc@yahoo.com.br assert(wbPkt->cmd == MemCmd::WritebackDirty || 21614035Sodanrc@yahoo.com.br wbPkt->cmd == MemCmd::WriteClean); 21714035Sodanrc@yahoo.com.br // Set BLOCK_CACHED flag in Writeback and send below, so that 21814035Sodanrc@yahoo.com.br // the Writeback does not reset the bit corresponding to this 21914035Sodanrc@yahoo.com.br // address in the snoop filter below. 22014035Sodanrc@yahoo.com.br wbPkt->setBlockCached(); 22114035Sodanrc@yahoo.com.br allocateWriteBuffer(wbPkt, forward_time); 22214035Sodanrc@yahoo.com.br } 22311051Sandreas.hansson@arm.com } else { 22414035Sodanrc@yahoo.com.br // If the block is not cached above, send packet below. Both 22514035Sodanrc@yahoo.com.br // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 22614035Sodanrc@yahoo.com.br // reset the bit corresponding to this address in the snoop filter 22714035Sodanrc@yahoo.com.br // below. 22814035Sodanrc@yahoo.com.br allocateWriteBuffer(wbPkt, forward_time); 22911051Sandreas.hansson@arm.com } 23014035Sodanrc@yahoo.com.br writebacks.pop_front(); 23111051Sandreas.hansson@arm.com } 23211051Sandreas.hansson@arm.com} 23311051Sandreas.hansson@arm.com 23411130Sali.jafri@arm.comvoid 23514035Sodanrc@yahoo.com.brCache::doWritebacksAtomic(PacketList& writebacks) 23611130Sali.jafri@arm.com{ 23714035Sodanrc@yahoo.com.br while (!writebacks.empty()) { 23814035Sodanrc@yahoo.com.br PacketPtr wbPkt = writebacks.front(); 23914035Sodanrc@yahoo.com.br // Call isCachedAbove for both Writebacks and CleanEvicts. If 24014035Sodanrc@yahoo.com.br // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks 24114035Sodanrc@yahoo.com.br // and discard CleanEvicts. 24214035Sodanrc@yahoo.com.br if (isCachedAbove(wbPkt, false)) { 24314035Sodanrc@yahoo.com.br if (wbPkt->cmd == MemCmd::WritebackDirty || 24414035Sodanrc@yahoo.com.br wbPkt->cmd == MemCmd::WriteClean) { 24514035Sodanrc@yahoo.com.br // Set BLOCK_CACHED flag in Writeback and send below, 24614035Sodanrc@yahoo.com.br // so that the Writeback does not reset the bit 24714035Sodanrc@yahoo.com.br // corresponding to this address in the snoop filter 24814035Sodanrc@yahoo.com.br // below. We can discard CleanEvicts because cached 24914035Sodanrc@yahoo.com.br // copies exist above. Atomic mode isCachedAbove 25014035Sodanrc@yahoo.com.br // modifies packet to set BLOCK_CACHED flag 25114035Sodanrc@yahoo.com.br memSidePort.sendAtomic(wbPkt); 25214035Sodanrc@yahoo.com.br } 25314035Sodanrc@yahoo.com.br } else { 25414035Sodanrc@yahoo.com.br // If the block is not cached above, send packet below. Both 25514035Sodanrc@yahoo.com.br // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 25614035Sodanrc@yahoo.com.br // reset the bit corresponding to this address in the snoop filter 25714035Sodanrc@yahoo.com.br // below. 25814035Sodanrc@yahoo.com.br memSidePort.sendAtomic(wbPkt); 25911130Sali.jafri@arm.com } 26014035Sodanrc@yahoo.com.br writebacks.pop_front(); 26114035Sodanrc@yahoo.com.br // In case of CleanEvicts, the packet destructor will delete the 26214035Sodanrc@yahoo.com.br // request object because this is a non-snoop request packet which 26314035Sodanrc@yahoo.com.br // does not require a response. 26414035Sodanrc@yahoo.com.br delete wbPkt; 26511130Sali.jafri@arm.com } 26614035Sodanrc@yahoo.com.br} 26713948Sodanrc@yahoo.com.br 26811130Sali.jafri@arm.com 26911051Sandreas.hansson@arm.comvoid 27011051Sandreas.hansson@arm.comCache::recvTimingSnoopResp(PacketPtr pkt) 27111051Sandreas.hansson@arm.com{ 27211744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s for %s\n", __func__, pkt->print()); 27311051Sandreas.hansson@arm.com 27411276Sandreas.hansson@arm.com // determine if the response is from a snoop request we created 27511276Sandreas.hansson@arm.com // (in which case it should be in the outstandingSnoop), or if we 27611276Sandreas.hansson@arm.com // merely forwarded someone else's snoop request 27711276Sandreas.hansson@arm.com const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) == 27811276Sandreas.hansson@arm.com outstandingSnoop.end(); 27911276Sandreas.hansson@arm.com 28011276Sandreas.hansson@arm.com if (!forwardAsSnoop) { 28111276Sandreas.hansson@arm.com // the packet came from this cache, so sink it here and do not 28211276Sandreas.hansson@arm.com // forward it 28311051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::HardPFResp); 28411276Sandreas.hansson@arm.com 28511276Sandreas.hansson@arm.com outstandingSnoop.erase(pkt->req); 28611276Sandreas.hansson@arm.com 28711276Sandreas.hansson@arm.com DPRINTF(Cache, "Got prefetch response from above for addr " 28811276Sandreas.hansson@arm.com "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 28911051Sandreas.hansson@arm.com recvTimingResp(pkt); 29011051Sandreas.hansson@arm.com return; 29111051Sandreas.hansson@arm.com } 29211051Sandreas.hansson@arm.com 29311051Sandreas.hansson@arm.com // forwardLatency is set here because there is a response from an 29411051Sandreas.hansson@arm.com // upper level cache. 29511051Sandreas.hansson@arm.com // To pay the delay that occurs if the packet comes from the bus, 29611051Sandreas.hansson@arm.com // we charge also headerDelay. 29711051Sandreas.hansson@arm.com Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay; 29811051Sandreas.hansson@arm.com // Reset the timing of the packet. 29911051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 30012724Snikos.nikoleris@arm.com memSidePort.schedTimingSnoopResp(pkt, snoop_resp_time); 30111051Sandreas.hansson@arm.com} 30211051Sandreas.hansson@arm.com 30311051Sandreas.hansson@arm.comvoid 30411051Sandreas.hansson@arm.comCache::promoteWholeLineWrites(PacketPtr pkt) 30511051Sandreas.hansson@arm.com{ 30611051Sandreas.hansson@arm.com // Cache line clearing instructions 30711051Sandreas.hansson@arm.com if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) && 30813954Sgiacomo.gabrielli@arm.com (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0) && 30913954Sgiacomo.gabrielli@arm.com !pkt->isMaskedWrite()) { 31011051Sandreas.hansson@arm.com pkt->cmd = MemCmd::WriteLineReq; 31111051Sandreas.hansson@arm.com DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n"); 31211051Sandreas.hansson@arm.com } 31311051Sandreas.hansson@arm.com} 31411051Sandreas.hansson@arm.com 31512630Snikos.nikoleris@arm.comvoid 31612720Snikos.nikoleris@arm.comCache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time) 31712720Snikos.nikoleris@arm.com{ 31812720Snikos.nikoleris@arm.com // should never be satisfying an uncacheable access as we 31912720Snikos.nikoleris@arm.com // flush and invalidate any existing block as part of the 32012720Snikos.nikoleris@arm.com // lookup 32112720Snikos.nikoleris@arm.com assert(!pkt->req->isUncacheable()); 32212720Snikos.nikoleris@arm.com 32312724Snikos.nikoleris@arm.com BaseCache::handleTimingReqHit(pkt, blk, request_time); 32412720Snikos.nikoleris@arm.com} 32512720Snikos.nikoleris@arm.com 32612720Snikos.nikoleris@arm.comvoid 32712720Snikos.nikoleris@arm.comCache::handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, Tick forward_time, 32812720Snikos.nikoleris@arm.com Tick request_time) 32912720Snikos.nikoleris@arm.com{ 33012724Snikos.nikoleris@arm.com if (pkt->req->isUncacheable()) { 33112724Snikos.nikoleris@arm.com // ignore any existing MSHR if we are dealing with an 33212724Snikos.nikoleris@arm.com // uncacheable request 33312724Snikos.nikoleris@arm.com 33412724Snikos.nikoleris@arm.com // should have flushed and have no valid block 33512724Snikos.nikoleris@arm.com assert(!blk || !blk->isValid()); 33612724Snikos.nikoleris@arm.com 33712724Snikos.nikoleris@arm.com mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++; 33812724Snikos.nikoleris@arm.com 33912724Snikos.nikoleris@arm.com if (pkt->isWrite()) { 34012724Snikos.nikoleris@arm.com allocateWriteBuffer(pkt, forward_time); 34112724Snikos.nikoleris@arm.com } else { 34212724Snikos.nikoleris@arm.com assert(pkt->isRead()); 34312724Snikos.nikoleris@arm.com 34412724Snikos.nikoleris@arm.com // uncacheable accesses always allocate a new MSHR 34512724Snikos.nikoleris@arm.com 34612724Snikos.nikoleris@arm.com // Here we are using forward_time, modelling the latency of 34712724Snikos.nikoleris@arm.com // a miss (outbound) just as forwardLatency, neglecting the 34812724Snikos.nikoleris@arm.com // lookupLatency component. 34912724Snikos.nikoleris@arm.com allocateMissBuffer(pkt, forward_time); 35012724Snikos.nikoleris@arm.com } 35112724Snikos.nikoleris@arm.com 35212724Snikos.nikoleris@arm.com return; 35312724Snikos.nikoleris@arm.com } 35412724Snikos.nikoleris@arm.com 35512720Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 35612720Snikos.nikoleris@arm.com 35712724Snikos.nikoleris@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, pkt->isSecure()); 35812720Snikos.nikoleris@arm.com 35912720Snikos.nikoleris@arm.com // Software prefetch handling: 36012720Snikos.nikoleris@arm.com // To keep the core from waiting on data it won't look at 36112720Snikos.nikoleris@arm.com // anyway, send back a response with dummy data. Miss handling 36212720Snikos.nikoleris@arm.com // will continue asynchronously. Unfortunately, the core will 36312720Snikos.nikoleris@arm.com // insist upon freeing original Packet/Request, so we have to 36412720Snikos.nikoleris@arm.com // create a new pair with a different lifecycle. Note that this 36512720Snikos.nikoleris@arm.com // processing happens before any MSHR munging on the behalf of 36612720Snikos.nikoleris@arm.com // this request because this new Request will be the one stored 36712720Snikos.nikoleris@arm.com // into the MSHRs, not the original. 36812720Snikos.nikoleris@arm.com if (pkt->cmd.isSWPrefetch()) { 36912720Snikos.nikoleris@arm.com assert(pkt->needsResponse()); 37012720Snikos.nikoleris@arm.com assert(pkt->req->hasPaddr()); 37112720Snikos.nikoleris@arm.com assert(!pkt->req->isUncacheable()); 37212720Snikos.nikoleris@arm.com 37312720Snikos.nikoleris@arm.com // There's no reason to add a prefetch as an additional target 37412720Snikos.nikoleris@arm.com // to an existing MSHR. If an outstanding request is already 37512720Snikos.nikoleris@arm.com // in progress, there is nothing for the prefetch to do. 37612720Snikos.nikoleris@arm.com // If this is the case, we don't even create a request at all. 37712720Snikos.nikoleris@arm.com PacketPtr pf = nullptr; 37812720Snikos.nikoleris@arm.com 37912720Snikos.nikoleris@arm.com if (!mshr) { 38012720Snikos.nikoleris@arm.com // copy the request and create a new SoftPFReq packet 38112749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>(pkt->req->getPaddr(), 38212749Sgiacomo.travaglini@arm.com pkt->req->getSize(), 38312749Sgiacomo.travaglini@arm.com pkt->req->getFlags(), 38412749Sgiacomo.travaglini@arm.com pkt->req->masterId()); 38512720Snikos.nikoleris@arm.com pf = new Packet(req, pkt->cmd); 38612720Snikos.nikoleris@arm.com pf->allocate(); 38713860Sodanrc@yahoo.com.br assert(pf->matchAddr(pkt)); 38812720Snikos.nikoleris@arm.com assert(pf->getSize() == pkt->getSize()); 38912720Snikos.nikoleris@arm.com } 39012720Snikos.nikoleris@arm.com 39112720Snikos.nikoleris@arm.com pkt->makeTimingResponse(); 39212720Snikos.nikoleris@arm.com 39312720Snikos.nikoleris@arm.com // request_time is used here, taking into account lat and the delay 39412720Snikos.nikoleris@arm.com // charged if the packet comes from the xbar. 39513564Snikos.nikoleris@arm.com cpuSidePort.schedTimingResp(pkt, request_time); 39612720Snikos.nikoleris@arm.com 39712720Snikos.nikoleris@arm.com // If an outstanding request is in progress (we found an 39812720Snikos.nikoleris@arm.com // MSHR) this is set to null 39912720Snikos.nikoleris@arm.com pkt = pf; 40012720Snikos.nikoleris@arm.com } 40112720Snikos.nikoleris@arm.com 40212724Snikos.nikoleris@arm.com BaseCache::handleTimingReqMiss(pkt, mshr, blk, forward_time, request_time); 40312720Snikos.nikoleris@arm.com} 40412720Snikos.nikoleris@arm.com 40512720Snikos.nikoleris@arm.comvoid 40611051Sandreas.hansson@arm.comCache::recvTimingReq(PacketPtr pkt) 40711051Sandreas.hansson@arm.com{ 40811830Sbaz21@cam.ac.uk DPRINTF(CacheTags, "%s tags:\n%s\n", __func__, tags->print()); 40911051Sandreas.hansson@arm.com 41011051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 41111051Sandreas.hansson@arm.com 41211284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 41311051Sandreas.hansson@arm.com // a cache above us (but not where the packet came from) is 41411284Sandreas.hansson@arm.com // responding to the request, in other words it has the line 41511284Sandreas.hansson@arm.com // in Modified or Owned state 41611744Snikos.nikoleris@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 41711744Snikos.nikoleris@arm.com pkt->print()); 41811051Sandreas.hansson@arm.com 41911284Sandreas.hansson@arm.com // if the packet needs the block to be writable, and the cache 42011284Sandreas.hansson@arm.com // that has promised to respond (setting the cache responding 42111284Sandreas.hansson@arm.com // flag) is not providing writable (it is in Owned rather than 42211284Sandreas.hansson@arm.com // the Modified state), we know that there may be other Shared 42311284Sandreas.hansson@arm.com // copies in the system; go out and invalidate them all 42411334Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 42511284Sandreas.hansson@arm.com 42611334Sandreas.hansson@arm.com // an upstream cache that had the line in Owned state 42711334Sandreas.hansson@arm.com // (dirty, but not writable), is responding and thus 42811334Sandreas.hansson@arm.com // transferring the dirty line from one branch of the 42911334Sandreas.hansson@arm.com // cache hierarchy to another 43011284Sandreas.hansson@arm.com 43111334Sandreas.hansson@arm.com // send out an express snoop and invalidate all other 43211334Sandreas.hansson@arm.com // copies (snooping a packet that needs writable is the 43311334Sandreas.hansson@arm.com // same as an invalidation), thus turning the Owned line 43411334Sandreas.hansson@arm.com // into a Modified line, note that we don't invalidate the 43511334Sandreas.hansson@arm.com // block in the current cache or any other cache on the 43611334Sandreas.hansson@arm.com // path to memory 43711051Sandreas.hansson@arm.com 43811334Sandreas.hansson@arm.com // create a downstream express snoop with cleared packet 43911334Sandreas.hansson@arm.com // flags, there is no need to allocate any data as the 44011334Sandreas.hansson@arm.com // packet is merely used to co-ordinate state transitions 44111334Sandreas.hansson@arm.com Packet *snoop_pkt = new Packet(pkt, true, false); 44211051Sandreas.hansson@arm.com 44311334Sandreas.hansson@arm.com // also reset the bus time that the original packet has 44411334Sandreas.hansson@arm.com // not yet paid for 44511334Sandreas.hansson@arm.com snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0; 44611051Sandreas.hansson@arm.com 44711334Sandreas.hansson@arm.com // make this an instantaneous express snoop, and let the 44811334Sandreas.hansson@arm.com // other caches in the system know that the another cache 44911334Sandreas.hansson@arm.com // is responding, because we have found the authorative 45011334Sandreas.hansson@arm.com // copy (Modified or Owned) that will supply the right 45111334Sandreas.hansson@arm.com // data 45211334Sandreas.hansson@arm.com snoop_pkt->setExpressSnoop(); 45311334Sandreas.hansson@arm.com snoop_pkt->setCacheResponding(); 45411051Sandreas.hansson@arm.com 45511334Sandreas.hansson@arm.com // this express snoop travels towards the memory, and at 45611334Sandreas.hansson@arm.com // every crossbar it is snooped upwards thus reaching 45711334Sandreas.hansson@arm.com // every cache in the system 45812724Snikos.nikoleris@arm.com bool M5_VAR_USED success = memSidePort.sendTimingReq(snoop_pkt); 45911334Sandreas.hansson@arm.com // express snoops always succeed 46011334Sandreas.hansson@arm.com assert(success); 46111334Sandreas.hansson@arm.com 46211334Sandreas.hansson@arm.com // main memory will delete the snoop packet 46311051Sandreas.hansson@arm.com 46411284Sandreas.hansson@arm.com // queue for deletion, as opposed to immediate deletion, as 46511284Sandreas.hansson@arm.com // the sending cache is still relying on the packet 46611190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 46711051Sandreas.hansson@arm.com 46811334Sandreas.hansson@arm.com // no need to take any further action in this particular cache 46911334Sandreas.hansson@arm.com // as an upstram cache has already committed to responding, 47011334Sandreas.hansson@arm.com // and we have already sent out any express snoops in the 47111334Sandreas.hansson@arm.com // section above to ensure all other copies in the system are 47211334Sandreas.hansson@arm.com // invalidated 47312630Snikos.nikoleris@arm.com return; 47411051Sandreas.hansson@arm.com } 47511051Sandreas.hansson@arm.com 47612724Snikos.nikoleris@arm.com BaseCache::recvTimingReq(pkt); 47711051Sandreas.hansson@arm.com} 47811051Sandreas.hansson@arm.com 47911051Sandreas.hansson@arm.comPacketPtr 48011452Sandreas.hansson@arm.comCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 48113350Snikos.nikoleris@arm.com bool needsWritable, 48213350Snikos.nikoleris@arm.com bool is_whole_line_write) const 48311051Sandreas.hansson@arm.com{ 48411452Sandreas.hansson@arm.com // should never see evictions here 48511452Sandreas.hansson@arm.com assert(!cpu_pkt->isEviction()); 48611452Sandreas.hansson@arm.com 48711051Sandreas.hansson@arm.com bool blkValid = blk && blk->isValid(); 48811051Sandreas.hansson@arm.com 48911452Sandreas.hansson@arm.com if (cpu_pkt->req->isUncacheable() || 49011745Sandreas.hansson@arm.com (!blkValid && cpu_pkt->isUpgrade()) || 49112349Snikos.nikoleris@arm.com cpu_pkt->cmd == MemCmd::InvalidateReq || cpu_pkt->isClean()) { 49211452Sandreas.hansson@arm.com // uncacheable requests and upgrades from upper-level caches 49311452Sandreas.hansson@arm.com // that missed completely just go through as is 49411452Sandreas.hansson@arm.com return nullptr; 49511051Sandreas.hansson@arm.com } 49611051Sandreas.hansson@arm.com 49711051Sandreas.hansson@arm.com assert(cpu_pkt->needsResponse()); 49811051Sandreas.hansson@arm.com 49911051Sandreas.hansson@arm.com MemCmd cmd; 50011051Sandreas.hansson@arm.com // @TODO make useUpgrades a parameter. 50111051Sandreas.hansson@arm.com // Note that ownership protocols require upgrade, otherwise a 50211051Sandreas.hansson@arm.com // write miss on a shared owned block will generate a ReadExcl, 50311051Sandreas.hansson@arm.com // which will clobber the owned copy. 50411051Sandreas.hansson@arm.com const bool useUpgrades = true; 50513350Snikos.nikoleris@arm.com assert(cpu_pkt->cmd != MemCmd::WriteLineReq || is_whole_line_write); 50613350Snikos.nikoleris@arm.com if (is_whole_line_write) { 50711747Snikos.nikoleris@arm.com assert(!blkValid || !blk->isWritable()); 50811747Snikos.nikoleris@arm.com // forward as invalidate to all other caches, this gives us 50911747Snikos.nikoleris@arm.com // the line in Exclusive state, and invalidates all other 51011747Snikos.nikoleris@arm.com // copies 51111747Snikos.nikoleris@arm.com cmd = MemCmd::InvalidateReq; 51211747Snikos.nikoleris@arm.com } else if (blkValid && useUpgrades) { 51311284Sandreas.hansson@arm.com // only reason to be here is that blk is read only and we need 51411284Sandreas.hansson@arm.com // it to be writable 51511284Sandreas.hansson@arm.com assert(needsWritable); 51611051Sandreas.hansson@arm.com assert(!blk->isWritable()); 51711051Sandreas.hansson@arm.com cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq; 51811051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq || 51911051Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::StoreCondFailReq) { 52011051Sandreas.hansson@arm.com // Even though this SC will fail, we still need to send out the 52111051Sandreas.hansson@arm.com // request and get the data to supply it to other snoopers in the case 52211051Sandreas.hansson@arm.com // where the determination the StoreCond fails is delayed due to 52311051Sandreas.hansson@arm.com // all caches not being on the same local bus. 52411051Sandreas.hansson@arm.com cmd = MemCmd::SCUpgradeFailReq; 52511051Sandreas.hansson@arm.com } else { 52611051Sandreas.hansson@arm.com // block is invalid 52712425Snikos.nikoleris@arm.com 52812425Snikos.nikoleris@arm.com // If the request does not need a writable there are two cases 52912425Snikos.nikoleris@arm.com // where we need to ensure the response will not fetch the 53012425Snikos.nikoleris@arm.com // block in dirty state: 53112425Snikos.nikoleris@arm.com // * this cache is read only and it does not perform 53212425Snikos.nikoleris@arm.com // writebacks, 53312425Snikos.nikoleris@arm.com // * this cache is mostly exclusive and will not fill (since 53412425Snikos.nikoleris@arm.com // it does not fill it will have to writeback the dirty data 53512425Snikos.nikoleris@arm.com // immediately which generates uneccesary writebacks). 53612425Snikos.nikoleris@arm.com bool force_clean_rsp = isReadOnly || clusivity == Enums::mostly_excl; 53711284Sandreas.hansson@arm.com cmd = needsWritable ? MemCmd::ReadExReq : 53812425Snikos.nikoleris@arm.com (force_clean_rsp ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq); 53911051Sandreas.hansson@arm.com } 54011051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize); 54111051Sandreas.hansson@arm.com 54211284Sandreas.hansson@arm.com // if there are upstream caches that have already marked the 54311284Sandreas.hansson@arm.com // packet as having sharers (not passing writable), pass that info 54411284Sandreas.hansson@arm.com // downstream 54511602Sandreas.hansson@arm.com if (cpu_pkt->hasSharers() && !needsWritable) { 54611051Sandreas.hansson@arm.com // note that cpu_pkt may have spent a considerable time in the 54711051Sandreas.hansson@arm.com // MSHR queue and that the information could possibly be out 54811051Sandreas.hansson@arm.com // of date, however, there is no harm in conservatively 54911284Sandreas.hansson@arm.com // assuming the block has sharers 55011284Sandreas.hansson@arm.com pkt->setHasSharers(); 55111744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: passing hasSharers from %s to %s\n", 55211744Snikos.nikoleris@arm.com __func__, cpu_pkt->print(), pkt->print()); 55311051Sandreas.hansson@arm.com } 55411051Sandreas.hansson@arm.com 55511051Sandreas.hansson@arm.com // the packet should be block aligned 55611892Snikos.nikoleris@arm.com assert(pkt->getAddr() == pkt->getBlockAddr(blkSize)); 55711051Sandreas.hansson@arm.com 55811051Sandreas.hansson@arm.com pkt->allocate(); 55911744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: created %s from %s\n", __func__, pkt->print(), 56011744Snikos.nikoleris@arm.com cpu_pkt->print()); 56111051Sandreas.hansson@arm.com return pkt; 56211051Sandreas.hansson@arm.com} 56311051Sandreas.hansson@arm.com 56411051Sandreas.hansson@arm.com 56512721Snikos.nikoleris@arm.comCycles 56614035Sodanrc@yahoo.com.brCache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, 56714035Sodanrc@yahoo.com.br PacketList &writebacks) 56812721Snikos.nikoleris@arm.com{ 56912721Snikos.nikoleris@arm.com // deal with the packets that go through the write path of 57012721Snikos.nikoleris@arm.com // the cache, i.e. any evictions and writes 57112721Snikos.nikoleris@arm.com if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean || 57212721Snikos.nikoleris@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 57312724Snikos.nikoleris@arm.com Cycles latency = ticksToCycles(memSidePort.sendAtomic(pkt)); 57412721Snikos.nikoleris@arm.com 57512721Snikos.nikoleris@arm.com // at this point, if the request was an uncacheable write 57612721Snikos.nikoleris@arm.com // request, it has been satisfied by a memory below and the 57712721Snikos.nikoleris@arm.com // packet carries the response back 57812721Snikos.nikoleris@arm.com assert(!(pkt->req->isUncacheable() && pkt->isWrite()) || 57912721Snikos.nikoleris@arm.com pkt->isResponse()); 58012721Snikos.nikoleris@arm.com 58112721Snikos.nikoleris@arm.com return latency; 58212721Snikos.nikoleris@arm.com } 58312721Snikos.nikoleris@arm.com 58412721Snikos.nikoleris@arm.com // only misses left 58512721Snikos.nikoleris@arm.com 58613350Snikos.nikoleris@arm.com PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable(), 58713350Snikos.nikoleris@arm.com pkt->isWholeLineWrite(blkSize)); 58812721Snikos.nikoleris@arm.com 58912721Snikos.nikoleris@arm.com bool is_forward = (bus_pkt == nullptr); 59012721Snikos.nikoleris@arm.com 59112721Snikos.nikoleris@arm.com if (is_forward) { 59212721Snikos.nikoleris@arm.com // just forwarding the same request to the next level 59312721Snikos.nikoleris@arm.com // no local cache operation involved 59412721Snikos.nikoleris@arm.com bus_pkt = pkt; 59512721Snikos.nikoleris@arm.com } 59612721Snikos.nikoleris@arm.com 59712721Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Sending an atomic %s\n", __func__, 59812721Snikos.nikoleris@arm.com bus_pkt->print()); 59912721Snikos.nikoleris@arm.com 60012721Snikos.nikoleris@arm.com#if TRACING_ON 60112721Snikos.nikoleris@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 60212721Snikos.nikoleris@arm.com#endif 60312721Snikos.nikoleris@arm.com 60412724Snikos.nikoleris@arm.com Cycles latency = ticksToCycles(memSidePort.sendAtomic(bus_pkt)); 60512721Snikos.nikoleris@arm.com 60612721Snikos.nikoleris@arm.com bool is_invalidate = bus_pkt->isInvalidate(); 60712721Snikos.nikoleris@arm.com 60812721Snikos.nikoleris@arm.com // We are now dealing with the response handling 60912721Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Receive response: %s in state %i\n", __func__, 61012721Snikos.nikoleris@arm.com bus_pkt->print(), old_state); 61112721Snikos.nikoleris@arm.com 61212721Snikos.nikoleris@arm.com // If packet was a forward, the response (if any) is already 61312721Snikos.nikoleris@arm.com // in place in the bus_pkt == pkt structure, so we don't need 61412721Snikos.nikoleris@arm.com // to do anything. Otherwise, use the separate bus_pkt to 61512721Snikos.nikoleris@arm.com // generate response to pkt and then delete it. 61612721Snikos.nikoleris@arm.com if (!is_forward) { 61712721Snikos.nikoleris@arm.com if (pkt->needsResponse()) { 61812721Snikos.nikoleris@arm.com assert(bus_pkt->isResponse()); 61912721Snikos.nikoleris@arm.com if (bus_pkt->isError()) { 62012721Snikos.nikoleris@arm.com pkt->makeAtomicResponse(); 62112721Snikos.nikoleris@arm.com pkt->copyError(bus_pkt); 62213350Snikos.nikoleris@arm.com } else if (pkt->isWholeLineWrite(blkSize)) { 62312721Snikos.nikoleris@arm.com // note the use of pkt, not bus_pkt here. 62412721Snikos.nikoleris@arm.com 62512721Snikos.nikoleris@arm.com // write-line request to the cache that promoted 62612721Snikos.nikoleris@arm.com // the write to a whole line 62713352Snikos.nikoleris@arm.com const bool allocate = allocOnFill(pkt->cmd) && 62813352Snikos.nikoleris@arm.com (!writeAllocator || writeAllocator->allocate()); 62914035Sodanrc@yahoo.com.br blk = handleFill(bus_pkt, blk, writebacks, allocate); 63012721Snikos.nikoleris@arm.com assert(blk != NULL); 63112721Snikos.nikoleris@arm.com is_invalidate = false; 63212721Snikos.nikoleris@arm.com satisfyRequest(pkt, blk); 63312721Snikos.nikoleris@arm.com } else if (bus_pkt->isRead() || 63412721Snikos.nikoleris@arm.com bus_pkt->cmd == MemCmd::UpgradeResp) { 63512721Snikos.nikoleris@arm.com // we're updating cache state to allow us to 63612721Snikos.nikoleris@arm.com // satisfy the upstream request from the cache 63714035Sodanrc@yahoo.com.br blk = handleFill(bus_pkt, blk, writebacks, 63814035Sodanrc@yahoo.com.br allocOnFill(pkt->cmd)); 63912721Snikos.nikoleris@arm.com satisfyRequest(pkt, blk); 64012721Snikos.nikoleris@arm.com maintainClusivity(pkt->fromCache(), blk); 64112721Snikos.nikoleris@arm.com } else { 64212721Snikos.nikoleris@arm.com // we're satisfying the upstream request without 64312721Snikos.nikoleris@arm.com // modifying cache state, e.g., a write-through 64412721Snikos.nikoleris@arm.com pkt->makeAtomicResponse(); 64512721Snikos.nikoleris@arm.com } 64612721Snikos.nikoleris@arm.com } 64712721Snikos.nikoleris@arm.com delete bus_pkt; 64812721Snikos.nikoleris@arm.com } 64912721Snikos.nikoleris@arm.com 65012721Snikos.nikoleris@arm.com if (is_invalidate && blk && blk->isValid()) { 65112721Snikos.nikoleris@arm.com invalidateBlock(blk); 65212721Snikos.nikoleris@arm.com } 65312721Snikos.nikoleris@arm.com 65412721Snikos.nikoleris@arm.com return latency; 65512721Snikos.nikoleris@arm.com} 65612721Snikos.nikoleris@arm.com 65711051Sandreas.hansson@arm.comTick 65811051Sandreas.hansson@arm.comCache::recvAtomic(PacketPtr pkt) 65911051Sandreas.hansson@arm.com{ 66011051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 66111051Sandreas.hansson@arm.com 66213412Snikos.nikoleris@arm.com // follow the same flow as in recvTimingReq, and check if a cache 66313412Snikos.nikoleris@arm.com // above us is responding 66413412Snikos.nikoleris@arm.com if (pkt->cacheResponding()) { 66513412Snikos.nikoleris@arm.com assert(!pkt->req->isCacheInvalidate()); 66613412Snikos.nikoleris@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 66713412Snikos.nikoleris@arm.com pkt->print()); 66813412Snikos.nikoleris@arm.com 66913412Snikos.nikoleris@arm.com // if a cache is responding, and it had the line in Owned 67013412Snikos.nikoleris@arm.com // rather than Modified state, we need to invalidate any 67113412Snikos.nikoleris@arm.com // copies that are not on the same path to memory 67213412Snikos.nikoleris@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 67313412Snikos.nikoleris@arm.com 67413412Snikos.nikoleris@arm.com return memSidePort.sendAtomic(pkt); 67513412Snikos.nikoleris@arm.com } 67613412Snikos.nikoleris@arm.com 67712724Snikos.nikoleris@arm.com return BaseCache::recvAtomic(pkt); 67811051Sandreas.hansson@arm.com} 67911051Sandreas.hansson@arm.com 68011051Sandreas.hansson@arm.com 68111051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 68211051Sandreas.hansson@arm.com// 68311051Sandreas.hansson@arm.com// Response handling: responses from the memory side 68411051Sandreas.hansson@arm.com// 68511051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 68611051Sandreas.hansson@arm.com 68711051Sandreas.hansson@arm.com 68811051Sandreas.hansson@arm.comvoid 68913478Sodanrc@yahoo.com.brCache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk) 69011051Sandreas.hansson@arm.com{ 69113859Sodanrc@yahoo.com.br QueueEntry::Target *initial_tgt = mshr->getTarget(); 69212719Snikos.nikoleris@arm.com // First offset for critical word first calculations 69312719Snikos.nikoleris@arm.com const int initial_offset = initial_tgt->pkt->getOffset(blkSize); 69412719Snikos.nikoleris@arm.com 69512719Snikos.nikoleris@arm.com const bool is_error = pkt->isError(); 69611051Sandreas.hansson@arm.com // allow invalidation responses originating from write-line 69711051Sandreas.hansson@arm.com // requests to be discarded 69813350Snikos.nikoleris@arm.com bool is_invalidate = pkt->isInvalidate() && 69913350Snikos.nikoleris@arm.com !mshr->wasWholeLineWrite; 70011051Sandreas.hansson@arm.com 70111742Snikos.nikoleris@arm.com MSHR::TargetList targets = mshr->extractServiceableTargets(pkt); 70211742Snikos.nikoleris@arm.com for (auto &target: targets) { 70311742Snikos.nikoleris@arm.com Packet *tgt_pkt = target.pkt; 70411742Snikos.nikoleris@arm.com switch (target.source) { 70511051Sandreas.hansson@arm.com case MSHR::Target::FromCPU: 70611051Sandreas.hansson@arm.com Tick completion_time; 70711051Sandreas.hansson@arm.com // Here we charge on completion_time the delay of the xbar if the 70811051Sandreas.hansson@arm.com // packet comes from it, charged on headerDelay. 70911051Sandreas.hansson@arm.com completion_time = pkt->headerDelay; 71011051Sandreas.hansson@arm.com 71111051Sandreas.hansson@arm.com // Software prefetch handling for cache closest to core 71211051Sandreas.hansson@arm.com if (tgt_pkt->cmd.isSWPrefetch()) { 71314118Stiago.muck@arm.com if (tgt_pkt->needsWritable()) { 71414118Stiago.muck@arm.com // All other copies of the block were invalidated and we 71514118Stiago.muck@arm.com // have an exclusive copy. 71614118Stiago.muck@arm.com 71714118Stiago.muck@arm.com // The coherence protocol assumes that if we fetched an 71814118Stiago.muck@arm.com // exclusive copy of the block, we have the intention to 71914118Stiago.muck@arm.com // modify it. Therefore the MSHR for the PrefetchExReq has 72014118Stiago.muck@arm.com // been the point of ordering and this cache has commited 72114118Stiago.muck@arm.com // to respond to snoops for the block. 72214118Stiago.muck@arm.com // 72314118Stiago.muck@arm.com // In most cases this is true anyway - a PrefetchExReq 72414118Stiago.muck@arm.com // will be followed by a WriteReq. However, if that 72514118Stiago.muck@arm.com // doesn't happen, the block is not marked as dirty and 72614118Stiago.muck@arm.com // the cache doesn't respond to snoops that has committed 72714118Stiago.muck@arm.com // to do so. 72814118Stiago.muck@arm.com // 72914118Stiago.muck@arm.com // To avoid deadlocks in cases where there is a snoop 73014118Stiago.muck@arm.com // between the PrefetchExReq and the expected WriteReq, we 73114118Stiago.muck@arm.com // proactively mark the block as Dirty. 73214118Stiago.muck@arm.com assert(blk); 73314118Stiago.muck@arm.com blk->status |= BlkDirty; 73414118Stiago.muck@arm.com 73514118Stiago.muck@arm.com panic_if(isReadOnly, "Prefetch exclusive requests from " 73614118Stiago.muck@arm.com "read-only cache %s\n", name()); 73714118Stiago.muck@arm.com } 73814118Stiago.muck@arm.com 73911483Snikos.nikoleris@arm.com // a software prefetch would have already been ack'd 74011483Snikos.nikoleris@arm.com // immediately with dummy data so the core would be able to 74111483Snikos.nikoleris@arm.com // retire it. This request completes right here, so we 74211483Snikos.nikoleris@arm.com // deallocate it. 74311051Sandreas.hansson@arm.com delete tgt_pkt; 74411051Sandreas.hansson@arm.com break; // skip response 74511051Sandreas.hansson@arm.com } 74611051Sandreas.hansson@arm.com 74711051Sandreas.hansson@arm.com // unlike the other packet flows, where data is found in other 74811051Sandreas.hansson@arm.com // caches or memory and brought back, write-line requests always 74911051Sandreas.hansson@arm.com // have the data right away, so the above check for "is fill?" 75011051Sandreas.hansson@arm.com // cannot actually be determined until examining the stored MSHR 75111051Sandreas.hansson@arm.com // state. We "catch up" with that logic here, which is duplicated 75211051Sandreas.hansson@arm.com // from above. 75311051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::WriteLineReq) { 75411051Sandreas.hansson@arm.com assert(!is_error); 75512719Snikos.nikoleris@arm.com assert(blk); 75613350Snikos.nikoleris@arm.com assert(blk->isWritable()); 75711051Sandreas.hansson@arm.com } 75811051Sandreas.hansson@arm.com 75912794Snikos.nikoleris@arm.com if (blk && blk->isValid() && !mshr->isForward) { 76011601Sandreas.hansson@arm.com satisfyRequest(tgt_pkt, blk, true, mshr->hasPostDowngrade()); 76111051Sandreas.hansson@arm.com 76211051Sandreas.hansson@arm.com // How many bytes past the first request is this one 76311051Sandreas.hansson@arm.com int transfer_offset = 76411051Sandreas.hansson@arm.com tgt_pkt->getOffset(blkSize) - initial_offset; 76511051Sandreas.hansson@arm.com if (transfer_offset < 0) { 76611051Sandreas.hansson@arm.com transfer_offset += blkSize; 76711051Sandreas.hansson@arm.com } 76811051Sandreas.hansson@arm.com 76911051Sandreas.hansson@arm.com // If not critical word (offset) return payloadDelay. 77011051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 77111051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 77211051Sandreas.hansson@arm.com // the core. 77311051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 77411051Sandreas.hansson@arm.com (transfer_offset ? pkt->payloadDelay : 0); 77511051Sandreas.hansson@arm.com 77611051Sandreas.hansson@arm.com assert(!tgt_pkt->req->isUncacheable()); 77711051Sandreas.hansson@arm.com 77811051Sandreas.hansson@arm.com assert(tgt_pkt->req->masterId() < system->maxMasters()); 77911051Sandreas.hansson@arm.com missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] += 78011742Snikos.nikoleris@arm.com completion_time - target.recvTime; 78111051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::UpgradeFailResp) { 78211051Sandreas.hansson@arm.com // failed StoreCond upgrade 78311051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::StoreCondReq || 78411051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::StoreCondFailReq || 78511051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::SCUpgradeFailReq); 78611051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 78711051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 78811051Sandreas.hansson@arm.com // the core. 78911051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 79011051Sandreas.hansson@arm.com pkt->payloadDelay; 79111051Sandreas.hansson@arm.com tgt_pkt->req->setExtraData(0); 79211051Sandreas.hansson@arm.com } else { 79311750Snikos.nikoleris@arm.com // We are about to send a response to a cache above 79411750Snikos.nikoleris@arm.com // that asked for an invalidation; we need to 79511750Snikos.nikoleris@arm.com // invalidate our copy immediately as the most 79611750Snikos.nikoleris@arm.com // up-to-date copy of the block will now be in the 79711750Snikos.nikoleris@arm.com // cache above. It will also prevent this cache from 79811750Snikos.nikoleris@arm.com // responding (if the block was previously dirty) to 79911750Snikos.nikoleris@arm.com // snoops as they should snoop the caches above where 80011750Snikos.nikoleris@arm.com // they will get the response from. 80111750Snikos.nikoleris@arm.com if (is_invalidate && blk && blk->isValid()) { 80211750Snikos.nikoleris@arm.com invalidateBlock(blk); 80311750Snikos.nikoleris@arm.com } 80411051Sandreas.hansson@arm.com // not a cache fill, just forwarding response 80511051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 80611051Sandreas.hansson@arm.com // from lower level cahces/memory to the core. 80711051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 80811051Sandreas.hansson@arm.com pkt->payloadDelay; 80911051Sandreas.hansson@arm.com if (pkt->isRead() && !is_error) { 81011051Sandreas.hansson@arm.com // sanity check 81113860Sodanrc@yahoo.com.br assert(pkt->matchAddr(tgt_pkt)); 81211051Sandreas.hansson@arm.com assert(pkt->getSize() >= tgt_pkt->getSize()); 81311051Sandreas.hansson@arm.com 81411051Sandreas.hansson@arm.com tgt_pkt->setData(pkt->getConstPtr<uint8_t>()); 81511051Sandreas.hansson@arm.com } 81613732Snikos.nikoleris@arm.com 81713732Snikos.nikoleris@arm.com // this response did not allocate here and therefore 81813732Snikos.nikoleris@arm.com // it was not consumed, make sure that any flags are 81913732Snikos.nikoleris@arm.com // carried over to cache above 82013732Snikos.nikoleris@arm.com tgt_pkt->copyResponderFlags(pkt); 82111051Sandreas.hansson@arm.com } 82211051Sandreas.hansson@arm.com tgt_pkt->makeTimingResponse(); 82311051Sandreas.hansson@arm.com // if this packet is an error copy that to the new packet 82411051Sandreas.hansson@arm.com if (is_error) 82511051Sandreas.hansson@arm.com tgt_pkt->copyError(pkt); 82611051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::ReadResp && 82711136Sandreas.hansson@arm.com (is_invalidate || mshr->hasPostInvalidate())) { 82811051Sandreas.hansson@arm.com // If intermediate cache got ReadRespWithInvalidate, 82911051Sandreas.hansson@arm.com // propagate that. Response should not have 83011051Sandreas.hansson@arm.com // isInvalidate() set otherwise. 83111051Sandreas.hansson@arm.com tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate; 83211744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: updated cmd to %s\n", __func__, 83311744Snikos.nikoleris@arm.com tgt_pkt->print()); 83411051Sandreas.hansson@arm.com } 83511051Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 83611051Sandreas.hansson@arm.com tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; 83713564Snikos.nikoleris@arm.com cpuSidePort.schedTimingResp(tgt_pkt, completion_time); 83811051Sandreas.hansson@arm.com break; 83911051Sandreas.hansson@arm.com 84011051Sandreas.hansson@arm.com case MSHR::Target::FromPrefetcher: 84111051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::HardPFReq); 84211051Sandreas.hansson@arm.com if (blk) 84311051Sandreas.hansson@arm.com blk->status |= BlkHWPrefetched; 84411051Sandreas.hansson@arm.com delete tgt_pkt; 84511051Sandreas.hansson@arm.com break; 84611051Sandreas.hansson@arm.com 84711051Sandreas.hansson@arm.com case MSHR::Target::FromSnoop: 84811051Sandreas.hansson@arm.com // I don't believe that a snoop can be in an error state 84911051Sandreas.hansson@arm.com assert(!is_error); 85011051Sandreas.hansson@arm.com // response to snoop request 85111051Sandreas.hansson@arm.com DPRINTF(Cache, "processing deferred snoop...\n"); 85211749Snikos.nikoleris@arm.com // If the response is invalidating, a snooping target can 85311749Snikos.nikoleris@arm.com // be satisfied if it is also invalidating. If the reponse is, not 85412349Snikos.nikoleris@arm.com // only invalidating, but more specifically an InvalidateResp and 85512349Snikos.nikoleris@arm.com // the MSHR was created due to an InvalidateReq then a cache above 85612349Snikos.nikoleris@arm.com // is waiting to satisfy a WriteLineReq. In this case even an 85711749Snikos.nikoleris@arm.com // non-invalidating snoop is added as a target here since this is 85811749Snikos.nikoleris@arm.com // the ordering point. When the InvalidateResp reaches this cache, 85911749Snikos.nikoleris@arm.com // the snooping target will snoop further the cache above with the 86011749Snikos.nikoleris@arm.com // WriteLineReq. 86112349Snikos.nikoleris@arm.com assert(!is_invalidate || pkt->cmd == MemCmd::InvalidateResp || 86212349Snikos.nikoleris@arm.com pkt->req->isCacheMaintenance() || 86312349Snikos.nikoleris@arm.com mshr->hasPostInvalidate()); 86411051Sandreas.hansson@arm.com handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate()); 86511051Sandreas.hansson@arm.com break; 86611051Sandreas.hansson@arm.com 86711051Sandreas.hansson@arm.com default: 86811742Snikos.nikoleris@arm.com panic("Illegal target->source enum %d\n", target.source); 86911051Sandreas.hansson@arm.com } 87011051Sandreas.hansson@arm.com } 87111051Sandreas.hansson@arm.com 87212715Snikos.nikoleris@arm.com maintainClusivity(targets.hasFromCache, blk); 87311601Sandreas.hansson@arm.com 87411051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 87511051Sandreas.hansson@arm.com // an invalidate response stemming from a write line request 87611051Sandreas.hansson@arm.com // should not invalidate the block, so check if the 87711051Sandreas.hansson@arm.com // invalidation should be discarded 87811136Sandreas.hansson@arm.com if (is_invalidate || mshr->hasPostInvalidate()) { 87911197Sandreas.hansson@arm.com invalidateBlock(blk); 88011051Sandreas.hansson@arm.com } else if (mshr->hasPostDowngrade()) { 88111051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 88211051Sandreas.hansson@arm.com } 88311051Sandreas.hansson@arm.com } 88412719Snikos.nikoleris@arm.com} 88512719Snikos.nikoleris@arm.com 88611051Sandreas.hansson@arm.comPacketPtr 88712723Snikos.nikoleris@arm.comCache::evictBlock(CacheBlk *blk) 88812723Snikos.nikoleris@arm.com{ 88912723Snikos.nikoleris@arm.com PacketPtr pkt = (blk->isDirty() || writebackClean) ? 89012723Snikos.nikoleris@arm.com writebackBlk(blk) : cleanEvictBlk(blk); 89112723Snikos.nikoleris@arm.com 89212723Snikos.nikoleris@arm.com invalidateBlock(blk); 89312723Snikos.nikoleris@arm.com 89412723Snikos.nikoleris@arm.com return pkt; 89512723Snikos.nikoleris@arm.com} 89612723Snikos.nikoleris@arm.com 89712723Snikos.nikoleris@arm.comPacketPtr 89811051Sandreas.hansson@arm.comCache::cleanEvictBlk(CacheBlk *blk) 89911051Sandreas.hansson@arm.com{ 90011199Sandreas.hansson@arm.com assert(!writebackClean); 90111051Sandreas.hansson@arm.com assert(blk && blk->isValid() && !blk->isDirty()); 90212749Sgiacomo.travaglini@arm.com 90311051Sandreas.hansson@arm.com // Creating a zero sized write, a message to the snoop filter 90412749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>( 90512749Sgiacomo.travaglini@arm.com regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId); 90612748Sgiacomo.travaglini@arm.com 90711051Sandreas.hansson@arm.com if (blk->isSecure()) 90811051Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 90911051Sandreas.hansson@arm.com 91011051Sandreas.hansson@arm.com req->taskId(blk->task_id); 91111051Sandreas.hansson@arm.com 91211051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::CleanEvict); 91311051Sandreas.hansson@arm.com pkt->allocate(); 91411744Snikos.nikoleris@arm.com DPRINTF(Cache, "Create CleanEvict %s\n", pkt->print()); 91511051Sandreas.hansson@arm.com 91611051Sandreas.hansson@arm.com return pkt; 91711051Sandreas.hansson@arm.com} 91811051Sandreas.hansson@arm.com 91911051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 92011051Sandreas.hansson@arm.com// 92111051Sandreas.hansson@arm.com// Snoop path: requests coming in from the memory side 92211051Sandreas.hansson@arm.com// 92311051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 92411051Sandreas.hansson@arm.com 92511051Sandreas.hansson@arm.comvoid 92611051Sandreas.hansson@arm.comCache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 92711051Sandreas.hansson@arm.com bool already_copied, bool pending_inval) 92811051Sandreas.hansson@arm.com{ 92911051Sandreas.hansson@arm.com // sanity check 93011051Sandreas.hansson@arm.com assert(req_pkt->isRequest()); 93111051Sandreas.hansson@arm.com assert(req_pkt->needsResponse()); 93211051Sandreas.hansson@arm.com 93311744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: for %s\n", __func__, req_pkt->print()); 93411051Sandreas.hansson@arm.com // timing-mode snoop responses require a new packet, unless we 93511051Sandreas.hansson@arm.com // already made a copy... 93611051Sandreas.hansson@arm.com PacketPtr pkt = req_pkt; 93711051Sandreas.hansson@arm.com if (!already_copied) 93811051Sandreas.hansson@arm.com // do not clear flags, and allocate space for data if the 93911051Sandreas.hansson@arm.com // packet needs it (the only packets that carry data are read 94011051Sandreas.hansson@arm.com // responses) 94111051Sandreas.hansson@arm.com pkt = new Packet(req_pkt, false, req_pkt->isRead()); 94211051Sandreas.hansson@arm.com 94311051Sandreas.hansson@arm.com assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() || 94411284Sandreas.hansson@arm.com pkt->hasSharers()); 94511051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 94611051Sandreas.hansson@arm.com if (pkt->isRead()) { 94711051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk_data, blkSize); 94811051Sandreas.hansson@arm.com } 94911051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadResp && pending_inval) { 95011051Sandreas.hansson@arm.com // Assume we defer a response to a read from a far-away cache 95111051Sandreas.hansson@arm.com // A, then later defer a ReadExcl from a cache B on the same 95211284Sandreas.hansson@arm.com // bus as us. We'll assert cacheResponding in both cases, but 95311284Sandreas.hansson@arm.com // in the latter case cacheResponding will keep the 95411284Sandreas.hansson@arm.com // invalidation from reaching cache A. This special response 95511284Sandreas.hansson@arm.com // tells cache A that it gets the block to satisfy its read, 95611284Sandreas.hansson@arm.com // but must immediately invalidate it. 95711051Sandreas.hansson@arm.com pkt->cmd = MemCmd::ReadRespWithInvalidate; 95811051Sandreas.hansson@arm.com } 95911051Sandreas.hansson@arm.com // Here we consider forward_time, paying for just forward latency and 96011051Sandreas.hansson@arm.com // also charging the delay provided by the xbar. 96111051Sandreas.hansson@arm.com // forward_time is used as send_time in next allocateWriteBuffer(). 96211051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 96311051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 96411051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 96511744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: created response: %s tick: %lu\n", __func__, 96611744Snikos.nikoleris@arm.com pkt->print(), forward_time); 96713564Snikos.nikoleris@arm.com memSidePort.schedTimingSnoopResp(pkt, forward_time); 96811051Sandreas.hansson@arm.com} 96911051Sandreas.hansson@arm.com 97011127Sandreas.hansson@arm.comuint32_t 97111051Sandreas.hansson@arm.comCache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, 97211051Sandreas.hansson@arm.com bool is_deferred, bool pending_inval) 97311051Sandreas.hansson@arm.com{ 97411744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 97511051Sandreas.hansson@arm.com // deferred snoops can only happen in timing mode 97611051Sandreas.hansson@arm.com assert(!(is_deferred && !is_timing)); 97711051Sandreas.hansson@arm.com // pending_inval only makes sense on deferred snoops 97811051Sandreas.hansson@arm.com assert(!(pending_inval && !is_deferred)); 97911051Sandreas.hansson@arm.com assert(pkt->isRequest()); 98011051Sandreas.hansson@arm.com 98111051Sandreas.hansson@arm.com // the packet may get modified if we or a forwarded snooper 98211051Sandreas.hansson@arm.com // responds in atomic mode, so remember a few things about the 98311051Sandreas.hansson@arm.com // original packet up front 98411051Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 98511284Sandreas.hansson@arm.com bool M5_VAR_USED needs_writable = pkt->needsWritable(); 98611051Sandreas.hansson@arm.com 98711285Sandreas.hansson@arm.com // at the moment we could get an uncacheable write which does not 98811285Sandreas.hansson@arm.com // have the invalidate flag, and we need a suitable way of dealing 98911285Sandreas.hansson@arm.com // with this case 99011285Sandreas.hansson@arm.com panic_if(invalidate && pkt->req->isUncacheable(), 99111744Snikos.nikoleris@arm.com "%s got an invalidating uncacheable snoop request %s", 99211744Snikos.nikoleris@arm.com name(), pkt->print()); 99311285Sandreas.hansson@arm.com 99411127Sandreas.hansson@arm.com uint32_t snoop_delay = 0; 99511127Sandreas.hansson@arm.com 99611051Sandreas.hansson@arm.com if (forwardSnoops) { 99711051Sandreas.hansson@arm.com // first propagate snoop upward to see if anyone above us wants to 99811051Sandreas.hansson@arm.com // handle it. save & restore packet src since it will get 99911051Sandreas.hansson@arm.com // rewritten to be relative to cpu-side bus (if any) 100011051Sandreas.hansson@arm.com if (is_timing) { 100111051Sandreas.hansson@arm.com // copy the packet so that we can clear any flags before 100211051Sandreas.hansson@arm.com // forwarding it upwards, we also allocate data (passing 100311051Sandreas.hansson@arm.com // the pointer along in case of static data), in case 100411051Sandreas.hansson@arm.com // there is a snoop hit in upper levels 100511051Sandreas.hansson@arm.com Packet snoopPkt(pkt, true, true); 100611051Sandreas.hansson@arm.com snoopPkt.setExpressSnoop(); 100711051Sandreas.hansson@arm.com // the snoop packet does not need to wait any additional 100811051Sandreas.hansson@arm.com // time 100911051Sandreas.hansson@arm.com snoopPkt.headerDelay = snoopPkt.payloadDelay = 0; 101012724Snikos.nikoleris@arm.com cpuSidePort.sendTimingSnoopReq(&snoopPkt); 101111127Sandreas.hansson@arm.com 101211127Sandreas.hansson@arm.com // add the header delay (including crossbar and snoop 101311127Sandreas.hansson@arm.com // delays) of the upward snoop to the snoop delay for this 101411127Sandreas.hansson@arm.com // cache 101511127Sandreas.hansson@arm.com snoop_delay += snoopPkt.headerDelay; 101611127Sandreas.hansson@arm.com 101711051Sandreas.hansson@arm.com // If this request is a prefetch or clean evict and an upper level 101811051Sandreas.hansson@arm.com // signals block present, make sure to propagate the block 101911051Sandreas.hansson@arm.com // presence to the requester. 102011051Sandreas.hansson@arm.com if (snoopPkt.isBlockCached()) { 102111051Sandreas.hansson@arm.com pkt->setBlockCached(); 102211051Sandreas.hansson@arm.com } 102312349Snikos.nikoleris@arm.com // If the request was satisfied by snooping the cache 102412349Snikos.nikoleris@arm.com // above, mark the original packet as satisfied too. 102512349Snikos.nikoleris@arm.com if (snoopPkt.satisfied()) { 102612349Snikos.nikoleris@arm.com pkt->setSatisfied(); 102712349Snikos.nikoleris@arm.com } 102813732Snikos.nikoleris@arm.com 102913732Snikos.nikoleris@arm.com // Copy over flags from the snoop response to make sure we 103013732Snikos.nikoleris@arm.com // inform the final destination 103113732Snikos.nikoleris@arm.com pkt->copyResponderFlags(&snoopPkt); 103211051Sandreas.hansson@arm.com } else { 103313732Snikos.nikoleris@arm.com bool already_responded = pkt->cacheResponding(); 103412724Snikos.nikoleris@arm.com cpuSidePort.sendAtomicSnoop(pkt); 103513732Snikos.nikoleris@arm.com if (!already_responded && pkt->cacheResponding()) { 103611051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache: 103711051Sandreas.hansson@arm.com // forward response to original requester 103811051Sandreas.hansson@arm.com assert(pkt->isResponse()); 103911051Sandreas.hansson@arm.com } 104011051Sandreas.hansson@arm.com } 104111051Sandreas.hansson@arm.com } 104211051Sandreas.hansson@arm.com 104312349Snikos.nikoleris@arm.com bool respond = false; 104412349Snikos.nikoleris@arm.com bool blk_valid = blk && blk->isValid(); 104512349Snikos.nikoleris@arm.com if (pkt->isClean()) { 104612349Snikos.nikoleris@arm.com if (blk_valid && blk->isDirty()) { 104712349Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: packet (snoop) %s found block: %s\n", 104812349Snikos.nikoleris@arm.com __func__, pkt->print(), blk->print()); 104912351Snikos.nikoleris@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id); 105014035Sodanrc@yahoo.com.br PacketList writebacks; 105114035Sodanrc@yahoo.com.br writebacks.push_back(wb_pkt); 105212349Snikos.nikoleris@arm.com 105312349Snikos.nikoleris@arm.com if (is_timing) { 105412349Snikos.nikoleris@arm.com // anything that is merely forwarded pays for the forward 105512349Snikos.nikoleris@arm.com // latency and the delay provided by the crossbar 105612349Snikos.nikoleris@arm.com Tick forward_time = clockEdge(forwardLatency) + 105712349Snikos.nikoleris@arm.com pkt->headerDelay; 105814035Sodanrc@yahoo.com.br doWritebacks(writebacks, forward_time); 105912349Snikos.nikoleris@arm.com } else { 106014035Sodanrc@yahoo.com.br doWritebacksAtomic(writebacks); 106112349Snikos.nikoleris@arm.com } 106212349Snikos.nikoleris@arm.com pkt->setSatisfied(); 106312349Snikos.nikoleris@arm.com } 106412349Snikos.nikoleris@arm.com } else if (!blk_valid) { 106511744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: snoop miss for %s\n", __func__, 106611744Snikos.nikoleris@arm.com pkt->print()); 106711493Sandreas.hansson@arm.com if (is_deferred) { 106811493Sandreas.hansson@arm.com // we no longer have the block, and will not respond, but a 106911493Sandreas.hansson@arm.com // packet was allocated in MSHR::handleSnoop and we have 107011493Sandreas.hansson@arm.com // to delete it 107111493Sandreas.hansson@arm.com assert(pkt->needsResponse()); 107211493Sandreas.hansson@arm.com 107311493Sandreas.hansson@arm.com // we have passed the block to a cache upstream, that 107411493Sandreas.hansson@arm.com // cache should be responding 107511493Sandreas.hansson@arm.com assert(pkt->cacheResponding()); 107611493Sandreas.hansson@arm.com 107711493Sandreas.hansson@arm.com delete pkt; 107811493Sandreas.hansson@arm.com } 107911127Sandreas.hansson@arm.com return snoop_delay; 108011051Sandreas.hansson@arm.com } else { 108111744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: snoop hit for %s, old state is %s\n", __func__, 108211744Snikos.nikoleris@arm.com pkt->print(), blk->print()); 108312349Snikos.nikoleris@arm.com 108412349Snikos.nikoleris@arm.com // We may end up modifying both the block state and the packet (if 108512349Snikos.nikoleris@arm.com // we respond in atomic mode), so just figure out what to do now 108612349Snikos.nikoleris@arm.com // and then do it later. We respond to all snoops that need 108712349Snikos.nikoleris@arm.com // responses provided we have the block in dirty state. The 108812349Snikos.nikoleris@arm.com // invalidation itself is taken care of below. We don't respond to 108912349Snikos.nikoleris@arm.com // cache maintenance operations as this is done by the destination 109012349Snikos.nikoleris@arm.com // xbar. 109112349Snikos.nikoleris@arm.com respond = blk->isDirty() && pkt->needsResponse(); 109212349Snikos.nikoleris@arm.com 109312349Snikos.nikoleris@arm.com chatty_assert(!(isReadOnly && blk->isDirty()), "Should never have " 109412349Snikos.nikoleris@arm.com "a dirty block in a read-only cache %s\n", name()); 109511051Sandreas.hansson@arm.com } 109611051Sandreas.hansson@arm.com 109711051Sandreas.hansson@arm.com // Invalidate any prefetch's from below that would strip write permissions 109811051Sandreas.hansson@arm.com // MemCmd::HardPFReq is only observed by upstream caches. After missing 109911051Sandreas.hansson@arm.com // above and in it's own cache, a new MemCmd::ReadReq is created that 110011051Sandreas.hansson@arm.com // downstream caches observe. 110111051Sandreas.hansson@arm.com if (pkt->mustCheckAbove()) { 110211483Snikos.nikoleris@arm.com DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s " 110311744Snikos.nikoleris@arm.com "from lower cache\n", pkt->getAddr(), pkt->print()); 110411051Sandreas.hansson@arm.com pkt->setBlockCached(); 110511127Sandreas.hansson@arm.com return snoop_delay; 110611051Sandreas.hansson@arm.com } 110711051Sandreas.hansson@arm.com 110811285Sandreas.hansson@arm.com if (pkt->isRead() && !invalidate) { 110911285Sandreas.hansson@arm.com // reading without requiring the line in a writable state 111011284Sandreas.hansson@arm.com assert(!needs_writable); 111111284Sandreas.hansson@arm.com pkt->setHasSharers(); 111211285Sandreas.hansson@arm.com 111311285Sandreas.hansson@arm.com // if the requesting packet is uncacheable, retain the line in 111411285Sandreas.hansson@arm.com // the current state, otherwhise unset the writable flag, 111511285Sandreas.hansson@arm.com // which means we go from Modified to Owned (and will respond 111611285Sandreas.hansson@arm.com // below), remain in Owned (and will respond below), from 111711285Sandreas.hansson@arm.com // Exclusive to Shared, or remain in Shared 111811285Sandreas.hansson@arm.com if (!pkt->req->isUncacheable()) 111911285Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 112012349Snikos.nikoleris@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 112111051Sandreas.hansson@arm.com } 112211051Sandreas.hansson@arm.com 112311051Sandreas.hansson@arm.com if (respond) { 112411051Sandreas.hansson@arm.com // prevent anyone else from responding, cache as well as 112511051Sandreas.hansson@arm.com // memory, and also prevent any memory from even seeing the 112611284Sandreas.hansson@arm.com // request 112711284Sandreas.hansson@arm.com pkt->setCacheResponding(); 112812349Snikos.nikoleris@arm.com if (!pkt->isClean() && blk->isWritable()) { 112911284Sandreas.hansson@arm.com // inform the cache hierarchy that this cache had the line 113011284Sandreas.hansson@arm.com // in the Modified state so that we avoid unnecessary 113111284Sandreas.hansson@arm.com // invalidations (see Packet::setResponderHadWritable) 113211284Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 113311284Sandreas.hansson@arm.com 113411081Sandreas.hansson@arm.com // in the case of an uncacheable request there is no point 113511284Sandreas.hansson@arm.com // in setting the responderHadWritable flag, but since the 113611284Sandreas.hansson@arm.com // recipient does not care there is no harm in doing so 113711284Sandreas.hansson@arm.com } else { 113811284Sandreas.hansson@arm.com // if the packet has needsWritable set we invalidate our 113911284Sandreas.hansson@arm.com // copy below and all other copies will be invalidates 114011284Sandreas.hansson@arm.com // through express snoops, and if needsWritable is not set 114111284Sandreas.hansson@arm.com // we already called setHasSharers above 114211051Sandreas.hansson@arm.com } 114311284Sandreas.hansson@arm.com 114411285Sandreas.hansson@arm.com // if we are returning a writable and dirty (Modified) line, 114511285Sandreas.hansson@arm.com // we should be invalidating the line 114611285Sandreas.hansson@arm.com panic_if(!invalidate && !pkt->hasSharers(), 114711744Snikos.nikoleris@arm.com "%s is passing a Modified line through %s, " 114811744Snikos.nikoleris@arm.com "but keeping the block", name(), pkt->print()); 114911285Sandreas.hansson@arm.com 115011051Sandreas.hansson@arm.com if (is_timing) { 115111051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval); 115211051Sandreas.hansson@arm.com } else { 115311051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 115411286Sandreas.hansson@arm.com // packets such as upgrades do not actually have any data 115511286Sandreas.hansson@arm.com // payload 115611286Sandreas.hansson@arm.com if (pkt->hasData()) 115711286Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 115811051Sandreas.hansson@arm.com } 115913945Sodanrc@yahoo.com.br 116013945Sodanrc@yahoo.com.br // When a block is compressed, it must first be decompressed before 116113945Sodanrc@yahoo.com.br // being read, and this increases the snoop delay. 116213945Sodanrc@yahoo.com.br if (compressor && pkt->isRead()) { 116313945Sodanrc@yahoo.com.br snoop_delay += compressor->getDecompressionLatency(blk); 116413945Sodanrc@yahoo.com.br } 116511051Sandreas.hansson@arm.com } 116611051Sandreas.hansson@arm.com 116711602Sandreas.hansson@arm.com if (!respond && is_deferred) { 116811051Sandreas.hansson@arm.com assert(pkt->needsResponse()); 116911051Sandreas.hansson@arm.com delete pkt; 117011051Sandreas.hansson@arm.com } 117111051Sandreas.hansson@arm.com 117211051Sandreas.hansson@arm.com // Do this last in case it deallocates block data or something 117311051Sandreas.hansson@arm.com // like that 117412349Snikos.nikoleris@arm.com if (blk_valid && invalidate) { 117511197Sandreas.hansson@arm.com invalidateBlock(blk); 117612349Snikos.nikoleris@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 117711051Sandreas.hansson@arm.com } 117811051Sandreas.hansson@arm.com 117911127Sandreas.hansson@arm.com return snoop_delay; 118011051Sandreas.hansson@arm.com} 118111051Sandreas.hansson@arm.com 118211051Sandreas.hansson@arm.com 118311051Sandreas.hansson@arm.comvoid 118411051Sandreas.hansson@arm.comCache::recvTimingSnoopReq(PacketPtr pkt) 118511051Sandreas.hansson@arm.com{ 118611744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 118711051Sandreas.hansson@arm.com 118811130Sali.jafri@arm.com // no need to snoop requests that are not in range 118911051Sandreas.hansson@arm.com if (!inRange(pkt->getAddr())) { 119011051Sandreas.hansson@arm.com return; 119111051Sandreas.hansson@arm.com } 119211051Sandreas.hansson@arm.com 119311051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 119411051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 119511051Sandreas.hansson@arm.com 119611892Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 119711051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 119811051Sandreas.hansson@arm.com 119911127Sandreas.hansson@arm.com // Update the latency cost of the snoop so that the crossbar can 120011127Sandreas.hansson@arm.com // account for it. Do not overwrite what other neighbouring caches 120111127Sandreas.hansson@arm.com // have already done, rather take the maximum. The update is 120211127Sandreas.hansson@arm.com // tentative, for cases where we return before an upward snoop 120311127Sandreas.hansson@arm.com // happens below. 120411127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, 120511127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 120611127Sandreas.hansson@arm.com 120711051Sandreas.hansson@arm.com // Inform request(Prefetch, CleanEvict or Writeback) from below of 120811051Sandreas.hansson@arm.com // MSHR hit, set setBlockCached. 120911051Sandreas.hansson@arm.com if (mshr && pkt->mustCheckAbove()) { 121011744Snikos.nikoleris@arm.com DPRINTF(Cache, "Setting block cached for %s from lower cache on " 121111744Snikos.nikoleris@arm.com "mshr hit\n", pkt->print()); 121211051Sandreas.hansson@arm.com pkt->setBlockCached(); 121311051Sandreas.hansson@arm.com return; 121411051Sandreas.hansson@arm.com } 121511051Sandreas.hansson@arm.com 121611051Sandreas.hansson@arm.com // Let the MSHR itself track the snoop and decide whether we want 121711051Sandreas.hansson@arm.com // to go ahead and do the regular cache snoop 121811051Sandreas.hansson@arm.com if (mshr && mshr->handleSnoop(pkt, order++)) { 121911051Sandreas.hansson@arm.com DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)." 122011051Sandreas.hansson@arm.com "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns", 122111051Sandreas.hansson@arm.com mshr->print()); 122211051Sandreas.hansson@arm.com 122311051Sandreas.hansson@arm.com if (mshr->getNumTargets() > numTarget) 122411051Sandreas.hansson@arm.com warn("allocating bonus target for snoop"); //handle later 122511051Sandreas.hansson@arm.com return; 122611051Sandreas.hansson@arm.com } 122711051Sandreas.hansson@arm.com 122811051Sandreas.hansson@arm.com //We also need to check the writeback buffers and handle those 122911375Sandreas.hansson@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(blk_addr, is_secure); 123011375Sandreas.hansson@arm.com if (wb_entry) { 123111051Sandreas.hansson@arm.com DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n", 123211051Sandreas.hansson@arm.com pkt->getAddr(), is_secure ? "s" : "ns"); 123311051Sandreas.hansson@arm.com // Expect to see only Writebacks and/or CleanEvicts here, both of 123411051Sandreas.hansson@arm.com // which should not be generated for uncacheable data. 123511051Sandreas.hansson@arm.com assert(!wb_entry->isUncacheable()); 123611051Sandreas.hansson@arm.com // There should only be a single request responsible for generating 123711051Sandreas.hansson@arm.com // Writebacks/CleanEvicts. 123811051Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 123911051Sandreas.hansson@arm.com PacketPtr wb_pkt = wb_entry->getTarget()->pkt; 124012345Snikos.nikoleris@arm.com assert(wb_pkt->isEviction() || wb_pkt->cmd == MemCmd::WriteClean); 124111051Sandreas.hansson@arm.com 124211199Sandreas.hansson@arm.com if (pkt->isEviction()) { 124311051Sandreas.hansson@arm.com // if the block is found in the write queue, set the BLOCK_CACHED 124411051Sandreas.hansson@arm.com // flag for Writeback/CleanEvict snoop. On return the snoop will 124511051Sandreas.hansson@arm.com // propagate the BLOCK_CACHED flag in Writeback packets and prevent 124611051Sandreas.hansson@arm.com // any CleanEvicts from travelling down the memory hierarchy. 124711051Sandreas.hansson@arm.com pkt->setBlockCached(); 124811744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Squashing %s from lower cache on writequeue " 124911744Snikos.nikoleris@arm.com "hit\n", __func__, pkt->print()); 125011051Sandreas.hansson@arm.com return; 125111051Sandreas.hansson@arm.com } 125211051Sandreas.hansson@arm.com 125311332Sandreas.hansson@arm.com // conceptually writebacks are no different to other blocks in 125411332Sandreas.hansson@arm.com // this cache, so the behaviour is modelled after handleSnoop, 125511332Sandreas.hansson@arm.com // the difference being that instead of querying the block 125611332Sandreas.hansson@arm.com // state to determine if it is dirty and writable, we use the 125711332Sandreas.hansson@arm.com // command and fields of the writeback packet 125811332Sandreas.hansson@arm.com bool respond = wb_pkt->cmd == MemCmd::WritebackDirty && 125911751Snikos.nikoleris@arm.com pkt->needsResponse(); 126011332Sandreas.hansson@arm.com bool have_writable = !wb_pkt->hasSharers(); 126111332Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 126211332Sandreas.hansson@arm.com 126311332Sandreas.hansson@arm.com if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) { 126411332Sandreas.hansson@arm.com assert(!pkt->needsWritable()); 126511332Sandreas.hansson@arm.com pkt->setHasSharers(); 126611332Sandreas.hansson@arm.com wb_pkt->setHasSharers(); 126711332Sandreas.hansson@arm.com } 126811332Sandreas.hansson@arm.com 126911332Sandreas.hansson@arm.com if (respond) { 127011284Sandreas.hansson@arm.com pkt->setCacheResponding(); 127111332Sandreas.hansson@arm.com 127211332Sandreas.hansson@arm.com if (have_writable) { 127311332Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 127411051Sandreas.hansson@arm.com } 127511332Sandreas.hansson@arm.com 127611051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(), 127711051Sandreas.hansson@arm.com false, false); 127811051Sandreas.hansson@arm.com } 127911051Sandreas.hansson@arm.com 128012349Snikos.nikoleris@arm.com if (invalidate && wb_pkt->cmd != MemCmd::WriteClean) { 128111051Sandreas.hansson@arm.com // Invalidation trumps our writeback... discard here 128211051Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 128311375Sandreas.hansson@arm.com markInService(wb_entry); 128411051Sandreas.hansson@arm.com delete wb_pkt; 128511051Sandreas.hansson@arm.com } 128611051Sandreas.hansson@arm.com } 128711051Sandreas.hansson@arm.com 128811051Sandreas.hansson@arm.com // If this was a shared writeback, there may still be 128911051Sandreas.hansson@arm.com // other shared copies above that require invalidation. 129011051Sandreas.hansson@arm.com // We could be more selective and return here if the 129111051Sandreas.hansson@arm.com // request is non-exclusive or if the writeback is 129211051Sandreas.hansson@arm.com // exclusive. 129311127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false); 129411127Sandreas.hansson@arm.com 129511127Sandreas.hansson@arm.com // Override what we did when we first saw the snoop, as we now 129611127Sandreas.hansson@arm.com // also have the cost of the upwards snoops to account for 129711127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay + 129811127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 129911051Sandreas.hansson@arm.com} 130011051Sandreas.hansson@arm.com 130111051Sandreas.hansson@arm.comTick 130211051Sandreas.hansson@arm.comCache::recvAtomicSnoop(PacketPtr pkt) 130311051Sandreas.hansson@arm.com{ 130411130Sali.jafri@arm.com // no need to snoop requests that are not in range. 130511130Sali.jafri@arm.com if (!inRange(pkt->getAddr())) { 130611051Sandreas.hansson@arm.com return 0; 130711051Sandreas.hansson@arm.com } 130811051Sandreas.hansson@arm.com 130911051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 131011127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false); 131111127Sandreas.hansson@arm.com return snoop_delay + lookupLatency * clockPeriod(); 131211051Sandreas.hansson@arm.com} 131311051Sandreas.hansson@arm.com 131411051Sandreas.hansson@arm.combool 131512724Snikos.nikoleris@arm.comCache::isCachedAbove(PacketPtr pkt, bool is_timing) 131611051Sandreas.hansson@arm.com{ 131711051Sandreas.hansson@arm.com if (!forwardSnoops) 131811051Sandreas.hansson@arm.com return false; 131911051Sandreas.hansson@arm.com // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and 132011051Sandreas.hansson@arm.com // Writeback snoops into upper level caches to check for copies of the 132111051Sandreas.hansson@arm.com // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict 132211051Sandreas.hansson@arm.com // packet, the cache can inform the crossbar below of presence or absence 132311051Sandreas.hansson@arm.com // of the block. 132411130Sali.jafri@arm.com if (is_timing) { 132511130Sali.jafri@arm.com Packet snoop_pkt(pkt, true, false); 132611130Sali.jafri@arm.com snoop_pkt.setExpressSnoop(); 132711130Sali.jafri@arm.com // Assert that packet is either Writeback or CleanEvict and not a 132811130Sali.jafri@arm.com // prefetch request because prefetch requests need an MSHR and may 132911130Sali.jafri@arm.com // generate a snoop response. 133012345Snikos.nikoleris@arm.com assert(pkt->isEviction() || pkt->cmd == MemCmd::WriteClean); 133111484Snikos.nikoleris@arm.com snoop_pkt.senderState = nullptr; 133212724Snikos.nikoleris@arm.com cpuSidePort.sendTimingSnoopReq(&snoop_pkt); 133311130Sali.jafri@arm.com // Writeback/CleanEvict snoops do not generate a snoop response. 133411284Sandreas.hansson@arm.com assert(!(snoop_pkt.cacheResponding())); 133511130Sali.jafri@arm.com return snoop_pkt.isBlockCached(); 133611130Sali.jafri@arm.com } else { 133712724Snikos.nikoleris@arm.com cpuSidePort.sendAtomicSnoop(pkt); 133811130Sali.jafri@arm.com return pkt->isBlockCached(); 133911130Sali.jafri@arm.com } 134011051Sandreas.hansson@arm.com} 134111051Sandreas.hansson@arm.com 134211375Sandreas.hansson@arm.combool 134311375Sandreas.hansson@arm.comCache::sendMSHRQueuePacket(MSHR* mshr) 134411375Sandreas.hansson@arm.com{ 134511375Sandreas.hansson@arm.com assert(mshr); 134611375Sandreas.hansson@arm.com 134711051Sandreas.hansson@arm.com // use request from 1st target 134811051Sandreas.hansson@arm.com PacketPtr tgt_pkt = mshr->getTarget()->pkt; 134911375Sandreas.hansson@arm.com 135012724Snikos.nikoleris@arm.com if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) { 135112724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print()); 135211051Sandreas.hansson@arm.com 135311375Sandreas.hansson@arm.com // we should never have hardware prefetches to allocated 135411375Sandreas.hansson@arm.com // blocks 135512724Snikos.nikoleris@arm.com assert(!tags->findBlock(mshr->blkAddr, mshr->isSecure)); 135611375Sandreas.hansson@arm.com 135711051Sandreas.hansson@arm.com // We need to check the caches above us to verify that 135811051Sandreas.hansson@arm.com // they don't have a copy of this block in the dirty state 135911051Sandreas.hansson@arm.com // at the moment. Without this check we could get a stale 136011051Sandreas.hansson@arm.com // copy from memory that might get used in place of the 136111051Sandreas.hansson@arm.com // dirty one. 136211051Sandreas.hansson@arm.com Packet snoop_pkt(tgt_pkt, true, false); 136311051Sandreas.hansson@arm.com snoop_pkt.setExpressSnoop(); 136411275Sandreas.hansson@arm.com // We are sending this packet upwards, but if it hits we will 136511275Sandreas.hansson@arm.com // get a snoop response that we end up treating just like a 136611275Sandreas.hansson@arm.com // normal response, hence it needs the MSHR as its sender 136711275Sandreas.hansson@arm.com // state 136811051Sandreas.hansson@arm.com snoop_pkt.senderState = mshr; 136912724Snikos.nikoleris@arm.com cpuSidePort.sendTimingSnoopReq(&snoop_pkt); 137011051Sandreas.hansson@arm.com 137111051Sandreas.hansson@arm.com // Check to see if the prefetch was squashed by an upper cache (to 137211051Sandreas.hansson@arm.com // prevent us from grabbing the line) or if a Check to see if a 137311051Sandreas.hansson@arm.com // writeback arrived between the time the prefetch was placed in 137411051Sandreas.hansson@arm.com // the MSHRs and when it was selected to be sent or if the 137511051Sandreas.hansson@arm.com // prefetch was squashed by an upper cache. 137611051Sandreas.hansson@arm.com 137711284Sandreas.hansson@arm.com // It is important to check cacheResponding before 137811284Sandreas.hansson@arm.com // prefetchSquashed. If another cache has committed to 137911284Sandreas.hansson@arm.com // responding, it will be sending a dirty response which will 138011284Sandreas.hansson@arm.com // arrive at the MSHR allocated for this request. Checking the 138111284Sandreas.hansson@arm.com // prefetchSquash first may result in the MSHR being 138211284Sandreas.hansson@arm.com // prematurely deallocated. 138311284Sandreas.hansson@arm.com if (snoop_pkt.cacheResponding()) { 138411276Sandreas.hansson@arm.com auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req); 138511276Sandreas.hansson@arm.com assert(r.second); 138611284Sandreas.hansson@arm.com 138711284Sandreas.hansson@arm.com // if we are getting a snoop response with no sharers it 138811284Sandreas.hansson@arm.com // will be allocated as Modified 138911284Sandreas.hansson@arm.com bool pending_modified_resp = !snoop_pkt.hasSharers(); 139011284Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 139111284Sandreas.hansson@arm.com 139211051Sandreas.hansson@arm.com DPRINTF(Cache, "Upward snoop of prefetch for addr" 139311051Sandreas.hansson@arm.com " %#x (%s) hit\n", 139411051Sandreas.hansson@arm.com tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns"); 139511375Sandreas.hansson@arm.com return false; 139611051Sandreas.hansson@arm.com } 139711051Sandreas.hansson@arm.com 139811375Sandreas.hansson@arm.com if (snoop_pkt.isBlockCached()) { 139911051Sandreas.hansson@arm.com DPRINTF(Cache, "Block present, prefetch squashed by cache. " 140011051Sandreas.hansson@arm.com "Deallocating mshr target %#x.\n", 140111051Sandreas.hansson@arm.com mshr->blkAddr); 140211375Sandreas.hansson@arm.com 140311051Sandreas.hansson@arm.com // Deallocate the mshr target 140411375Sandreas.hansson@arm.com if (mshrQueue.forceDeallocateTarget(mshr)) { 140511277Sandreas.hansson@arm.com // Clear block if this deallocation resulted freed an 140611277Sandreas.hansson@arm.com // mshr when all had previously been utilized 140711375Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 140811051Sandreas.hansson@arm.com } 140912167Spau.cabre@metempsy.com 141012167Spau.cabre@metempsy.com // given that no response is expected, delete Request and Packet 141112167Spau.cabre@metempsy.com delete tgt_pkt; 141212167Spau.cabre@metempsy.com 141311375Sandreas.hansson@arm.com return false; 141411051Sandreas.hansson@arm.com } 141511051Sandreas.hansson@arm.com } 141611051Sandreas.hansson@arm.com 141712724Snikos.nikoleris@arm.com return BaseCache::sendMSHRQueuePacket(mshr); 141811051Sandreas.hansson@arm.com} 141911051Sandreas.hansson@arm.com 142011053Sandreas.hansson@arm.comCache* 142111053Sandreas.hansson@arm.comCacheParams::create() 142211053Sandreas.hansson@arm.com{ 142311053Sandreas.hansson@arm.com assert(tags); 142412600Sodanrc@yahoo.com.br assert(replacement_policy); 142511053Sandreas.hansson@arm.com 142611053Sandreas.hansson@arm.com return new Cache(this); 142711053Sandreas.hansson@arm.com} 1428