cache.cc revision 13954
12810Srdreslin@umich.edu/* 213732Snikos.nikoleris@arm.com * Copyright (c) 2010-2019 ARM Limited 311051Sandreas.hansson@arm.com * All rights reserved. 411051Sandreas.hansson@arm.com * 511051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911051Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311051Sandreas.hansson@arm.com * 1411051Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511051Sandreas.hansson@arm.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 162810Srdreslin@umich.edu * All rights reserved. 172810Srdreslin@umich.edu * 182810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 192810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 202810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 212810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 222810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 232810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 242810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 252810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 262810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 272810Srdreslin@umich.edu * this software without specific prior written permission. 282810Srdreslin@umich.edu * 292810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810Srdreslin@umich.edu * 412810Srdreslin@umich.edu * Authors: Erik Hallnor 4211051Sandreas.hansson@arm.com * Dave Greene 4311051Sandreas.hansson@arm.com * Nathan Binkert 442810Srdreslin@umich.edu * Steve Reinhardt 4511051Sandreas.hansson@arm.com * Ron Dreslinski 4611051Sandreas.hansson@arm.com * Andreas Sandberg 4712349Snikos.nikoleris@arm.com * Nikos Nikoleris 482810Srdreslin@umich.edu */ 492810Srdreslin@umich.edu 502810Srdreslin@umich.edu/** 512810Srdreslin@umich.edu * @file 5211051Sandreas.hansson@arm.com * Cache definitions. 532810Srdreslin@umich.edu */ 542810Srdreslin@umich.edu 5511051Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 562810Srdreslin@umich.edu 5712724Snikos.nikoleris@arm.com#include <cassert> 5812724Snikos.nikoleris@arm.com 5912724Snikos.nikoleris@arm.com#include "base/compiler.hh" 6012334Sgabeblack@google.com#include "base/logging.hh" 6112724Snikos.nikoleris@arm.com#include "base/trace.hh" 6211051Sandreas.hansson@arm.com#include "base/types.hh" 6311051Sandreas.hansson@arm.com#include "debug/Cache.hh" 6411051Sandreas.hansson@arm.com#include "debug/CacheTags.hh" 6511288Ssteve.reinhardt@amd.com#include "debug/CacheVerbose.hh" 6612724Snikos.nikoleris@arm.com#include "enums/Clusivity.hh" 6713223Sodanrc@yahoo.com.br#include "mem/cache/cache_blk.hh" 6811051Sandreas.hansson@arm.com#include "mem/cache/mshr.hh" 6912724Snikos.nikoleris@arm.com#include "mem/cache/tags/base.hh" 7012724Snikos.nikoleris@arm.com#include "mem/cache/write_queue_entry.hh" 7112724Snikos.nikoleris@arm.com#include "mem/request.hh" 7212724Snikos.nikoleris@arm.com#include "params/Cache.hh" 7311051Sandreas.hansson@arm.com 7411053Sandreas.hansson@arm.comCache::Cache(const CacheParams *p) 7511053Sandreas.hansson@arm.com : BaseCache(p, p->system->cacheLineSize()), 7612724Snikos.nikoleris@arm.com doFastWrites(true) 7711051Sandreas.hansson@arm.com{ 7811051Sandreas.hansson@arm.com} 7911051Sandreas.hansson@arm.com 8011051Sandreas.hansson@arm.comvoid 8111601Sandreas.hansson@arm.comCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, 8211601Sandreas.hansson@arm.com bool deferred_response, bool pending_downgrade) 8311051Sandreas.hansson@arm.com{ 8412724Snikos.nikoleris@arm.com BaseCache::satisfyRequest(pkt, blk); 8511051Sandreas.hansson@arm.com 8612724Snikos.nikoleris@arm.com if (pkt->isRead()) { 8711600Sandreas.hansson@arm.com // determine if this read is from a (coherent) cache or not 8811600Sandreas.hansson@arm.com if (pkt->fromCache()) { 8911051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 9011051Sandreas.hansson@arm.com // special handling for coherent block requests from 9111051Sandreas.hansson@arm.com // upper-level caches 9211284Sandreas.hansson@arm.com if (pkt->needsWritable()) { 9311051Sandreas.hansson@arm.com // sanity check 9411051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::ReadExReq || 9511051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq); 9611602Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 9711051Sandreas.hansson@arm.com 9811051Sandreas.hansson@arm.com // if we have a dirty copy, make sure the recipient 9911284Sandreas.hansson@arm.com // keeps it marked dirty (in the modified state) 10011051Sandreas.hansson@arm.com if (blk->isDirty()) { 10111284Sandreas.hansson@arm.com pkt->setCacheResponding(); 10211602Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 10311051Sandreas.hansson@arm.com } 10411051Sandreas.hansson@arm.com } else if (blk->isWritable() && !pending_downgrade && 10511284Sandreas.hansson@arm.com !pkt->hasSharers() && 10611051Sandreas.hansson@arm.com pkt->cmd != MemCmd::ReadCleanReq) { 10711284Sandreas.hansson@arm.com // we can give the requester a writable copy on a read 10811284Sandreas.hansson@arm.com // request if: 10911284Sandreas.hansson@arm.com // - we have a writable copy at this level (& below) 11011051Sandreas.hansson@arm.com // - we don't have a pending snoop from below 11111051Sandreas.hansson@arm.com // signaling another read request 11211051Sandreas.hansson@arm.com // - no other cache above has a copy (otherwise it 11311284Sandreas.hansson@arm.com // would have set hasSharers flag when 11411284Sandreas.hansson@arm.com // snooping the packet) 11511284Sandreas.hansson@arm.com // - the read has explicitly asked for a clean 11611284Sandreas.hansson@arm.com // copy of the line 11711051Sandreas.hansson@arm.com if (blk->isDirty()) { 11811051Sandreas.hansson@arm.com // special considerations if we're owner: 11911051Sandreas.hansson@arm.com if (!deferred_response) { 12011284Sandreas.hansson@arm.com // respond with the line in Modified state 12111284Sandreas.hansson@arm.com // (cacheResponding set, hasSharers not set) 12211284Sandreas.hansson@arm.com pkt->setCacheResponding(); 12311197Sandreas.hansson@arm.com 12411601Sandreas.hansson@arm.com // if this cache is mostly inclusive, we 12511601Sandreas.hansson@arm.com // keep the block in the Exclusive state, 12611601Sandreas.hansson@arm.com // and pass it upwards as Modified 12711601Sandreas.hansson@arm.com // (writable and dirty), hence we have 12811601Sandreas.hansson@arm.com // multiple caches, all on the same path 12911601Sandreas.hansson@arm.com // towards memory, all considering the 13011601Sandreas.hansson@arm.com // same block writable, but only one 13111601Sandreas.hansson@arm.com // considering it Modified 13211197Sandreas.hansson@arm.com 13311601Sandreas.hansson@arm.com // we get away with multiple caches (on 13411601Sandreas.hansson@arm.com // the same path to memory) considering 13511601Sandreas.hansson@arm.com // the block writeable as we always enter 13611601Sandreas.hansson@arm.com // the cache hierarchy through a cache, 13711601Sandreas.hansson@arm.com // and first snoop upwards in all other 13811601Sandreas.hansson@arm.com // branches 13911601Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 14011051Sandreas.hansson@arm.com } else { 14111051Sandreas.hansson@arm.com // if we're responding after our own miss, 14211051Sandreas.hansson@arm.com // there's a window where the recipient didn't 14311051Sandreas.hansson@arm.com // know it was getting ownership and may not 14411051Sandreas.hansson@arm.com // have responded to snoops correctly, so we 14511284Sandreas.hansson@arm.com // have to respond with a shared line 14611284Sandreas.hansson@arm.com pkt->setHasSharers(); 14711051Sandreas.hansson@arm.com } 14811051Sandreas.hansson@arm.com } 14911051Sandreas.hansson@arm.com } else { 15011051Sandreas.hansson@arm.com // otherwise only respond with a shared copy 15111284Sandreas.hansson@arm.com pkt->setHasSharers(); 15211051Sandreas.hansson@arm.com } 15311051Sandreas.hansson@arm.com } 15411051Sandreas.hansson@arm.com } 15511051Sandreas.hansson@arm.com} 15611051Sandreas.hansson@arm.com 15711051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 15811051Sandreas.hansson@arm.com// 15911051Sandreas.hansson@arm.com// Access path: requests coming in from the CPU side 16011051Sandreas.hansson@arm.com// 16111051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 16211051Sandreas.hansson@arm.com 16311051Sandreas.hansson@arm.combool 16413948Sodanrc@yahoo.com.brCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat) 16511051Sandreas.hansson@arm.com{ 16611051Sandreas.hansson@arm.com 16711051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 16812724Snikos.nikoleris@arm.com assert(pkt->isRequest()); 16912724Snikos.nikoleris@arm.com 17012724Snikos.nikoleris@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 17112724Snikos.nikoleris@arm.com "Should never see a write in a read-only cache %s\n", 17212724Snikos.nikoleris@arm.com name()); 17312724Snikos.nikoleris@arm.com 17412724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s for %s\n", __func__, pkt->print()); 17511051Sandreas.hansson@arm.com 17613948Sodanrc@yahoo.com.br // lookupLatency is the latency in case the request is uncacheable. 17713948Sodanrc@yahoo.com.br lat = lookupLatency; 17813948Sodanrc@yahoo.com.br 17911051Sandreas.hansson@arm.com // flush and invalidate any existing block 18011051Sandreas.hansson@arm.com CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure())); 18111051Sandreas.hansson@arm.com if (old_blk && old_blk->isValid()) { 18213948Sodanrc@yahoo.com.br BaseCache::evictBlock(old_blk, clockEdge(lat + forwardLatency)); 18311051Sandreas.hansson@arm.com } 18411051Sandreas.hansson@arm.com 18511484Snikos.nikoleris@arm.com blk = nullptr; 18611051Sandreas.hansson@arm.com return false; 18711051Sandreas.hansson@arm.com } 18811051Sandreas.hansson@arm.com 18913948Sodanrc@yahoo.com.br return BaseCache::access(pkt, blk, lat); 19011601Sandreas.hansson@arm.com} 19111601Sandreas.hansson@arm.com 19211601Sandreas.hansson@arm.comvoid 19313948Sodanrc@yahoo.com.brCache::doWritebacks(PacketPtr pkt, Tick forward_time) 19411051Sandreas.hansson@arm.com{ 19513948Sodanrc@yahoo.com.br // We use forwardLatency here because we are copying writebacks to 19613948Sodanrc@yahoo.com.br // write buffer. 19712345Snikos.nikoleris@arm.com 19813948Sodanrc@yahoo.com.br // Call isCachedAbove for Writebacks, CleanEvicts and 19913948Sodanrc@yahoo.com.br // WriteCleans to discover if the block is cached above. 20013948Sodanrc@yahoo.com.br if (isCachedAbove(pkt)) { 20113948Sodanrc@yahoo.com.br if (pkt->cmd == MemCmd::CleanEvict) { 20213948Sodanrc@yahoo.com.br // Delete CleanEvict because cached copies exist above. The 20313948Sodanrc@yahoo.com.br // packet destructor will delete the request object because 20413948Sodanrc@yahoo.com.br // this is a non-snoop request packet which does not require a 20513948Sodanrc@yahoo.com.br // response. 20613948Sodanrc@yahoo.com.br delete pkt; 20713948Sodanrc@yahoo.com.br } else if (pkt->cmd == MemCmd::WritebackClean) { 20813948Sodanrc@yahoo.com.br // clean writeback, do not send since the block is 20913948Sodanrc@yahoo.com.br // still cached above 21013948Sodanrc@yahoo.com.br assert(writebackClean); 21113948Sodanrc@yahoo.com.br delete pkt; 21211051Sandreas.hansson@arm.com } else { 21313948Sodanrc@yahoo.com.br assert(pkt->cmd == MemCmd::WritebackDirty || 21413948Sodanrc@yahoo.com.br pkt->cmd == MemCmd::WriteClean); 21513948Sodanrc@yahoo.com.br // Set BLOCK_CACHED flag in Writeback and send below, so that 21613948Sodanrc@yahoo.com.br // the Writeback does not reset the bit corresponding to this 21713948Sodanrc@yahoo.com.br // address in the snoop filter below. 21813948Sodanrc@yahoo.com.br pkt->setBlockCached(); 21913948Sodanrc@yahoo.com.br allocateWriteBuffer(pkt, forward_time); 22011051Sandreas.hansson@arm.com } 22113948Sodanrc@yahoo.com.br } else { 22213948Sodanrc@yahoo.com.br // If the block is not cached above, send packet below. Both 22313948Sodanrc@yahoo.com.br // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 22413948Sodanrc@yahoo.com.br // reset the bit corresponding to this address in the snoop filter 22513948Sodanrc@yahoo.com.br // below. 22613948Sodanrc@yahoo.com.br allocateWriteBuffer(pkt, forward_time); 22711051Sandreas.hansson@arm.com } 22811051Sandreas.hansson@arm.com} 22911051Sandreas.hansson@arm.com 23011130Sali.jafri@arm.comvoid 23113948Sodanrc@yahoo.com.brCache::doWritebacksAtomic(PacketPtr pkt) 23211130Sali.jafri@arm.com{ 23313948Sodanrc@yahoo.com.br // Call isCachedAbove for both Writebacks and CleanEvicts. If 23413948Sodanrc@yahoo.com.br // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks 23513948Sodanrc@yahoo.com.br // and discard CleanEvicts. 23613948Sodanrc@yahoo.com.br if (isCachedAbove(pkt, false)) { 23713948Sodanrc@yahoo.com.br if (pkt->cmd == MemCmd::WritebackDirty || 23813948Sodanrc@yahoo.com.br pkt->cmd == MemCmd::WriteClean) { 23913948Sodanrc@yahoo.com.br // Set BLOCK_CACHED flag in Writeback and send below, 24013948Sodanrc@yahoo.com.br // so that the Writeback does not reset the bit 24113948Sodanrc@yahoo.com.br // corresponding to this address in the snoop filter 24213948Sodanrc@yahoo.com.br // below. We can discard CleanEvicts because cached 24313948Sodanrc@yahoo.com.br // copies exist above. Atomic mode isCachedAbove 24413948Sodanrc@yahoo.com.br // modifies packet to set BLOCK_CACHED flag 24513948Sodanrc@yahoo.com.br memSidePort.sendAtomic(pkt); 24611130Sali.jafri@arm.com } 24713948Sodanrc@yahoo.com.br } else { 24813948Sodanrc@yahoo.com.br // If the block is not cached above, send packet below. Both 24913948Sodanrc@yahoo.com.br // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 25013948Sodanrc@yahoo.com.br // reset the bit corresponding to this address in the snoop filter 25113948Sodanrc@yahoo.com.br // below. 25213948Sodanrc@yahoo.com.br memSidePort.sendAtomic(pkt); 25311130Sali.jafri@arm.com } 25413948Sodanrc@yahoo.com.br 25513948Sodanrc@yahoo.com.br // In case of CleanEvicts, the packet destructor will delete the 25613948Sodanrc@yahoo.com.br // request object because this is a non-snoop request packet which 25713948Sodanrc@yahoo.com.br // does not require a response. 25813948Sodanrc@yahoo.com.br delete pkt; 25911130Sali.jafri@arm.com} 26011130Sali.jafri@arm.com 26111051Sandreas.hansson@arm.comvoid 26211051Sandreas.hansson@arm.comCache::recvTimingSnoopResp(PacketPtr pkt) 26311051Sandreas.hansson@arm.com{ 26411744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s for %s\n", __func__, pkt->print()); 26511051Sandreas.hansson@arm.com 26611276Sandreas.hansson@arm.com // determine if the response is from a snoop request we created 26711276Sandreas.hansson@arm.com // (in which case it should be in the outstandingSnoop), or if we 26811276Sandreas.hansson@arm.com // merely forwarded someone else's snoop request 26911276Sandreas.hansson@arm.com const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) == 27011276Sandreas.hansson@arm.com outstandingSnoop.end(); 27111276Sandreas.hansson@arm.com 27211276Sandreas.hansson@arm.com if (!forwardAsSnoop) { 27311276Sandreas.hansson@arm.com // the packet came from this cache, so sink it here and do not 27411276Sandreas.hansson@arm.com // forward it 27511051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::HardPFResp); 27611276Sandreas.hansson@arm.com 27711276Sandreas.hansson@arm.com outstandingSnoop.erase(pkt->req); 27811276Sandreas.hansson@arm.com 27911276Sandreas.hansson@arm.com DPRINTF(Cache, "Got prefetch response from above for addr " 28011276Sandreas.hansson@arm.com "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 28111051Sandreas.hansson@arm.com recvTimingResp(pkt); 28211051Sandreas.hansson@arm.com return; 28311051Sandreas.hansson@arm.com } 28411051Sandreas.hansson@arm.com 28511051Sandreas.hansson@arm.com // forwardLatency is set here because there is a response from an 28611051Sandreas.hansson@arm.com // upper level cache. 28711051Sandreas.hansson@arm.com // To pay the delay that occurs if the packet comes from the bus, 28811051Sandreas.hansson@arm.com // we charge also headerDelay. 28911051Sandreas.hansson@arm.com Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay; 29011051Sandreas.hansson@arm.com // Reset the timing of the packet. 29111051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 29212724Snikos.nikoleris@arm.com memSidePort.schedTimingSnoopResp(pkt, snoop_resp_time); 29311051Sandreas.hansson@arm.com} 29411051Sandreas.hansson@arm.com 29511051Sandreas.hansson@arm.comvoid 29611051Sandreas.hansson@arm.comCache::promoteWholeLineWrites(PacketPtr pkt) 29711051Sandreas.hansson@arm.com{ 29811051Sandreas.hansson@arm.com // Cache line clearing instructions 29911051Sandreas.hansson@arm.com if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) && 30013954Sgiacomo.gabrielli@arm.com (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0) && 30113954Sgiacomo.gabrielli@arm.com !pkt->isMaskedWrite()) { 30211051Sandreas.hansson@arm.com pkt->cmd = MemCmd::WriteLineReq; 30311051Sandreas.hansson@arm.com DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n"); 30411051Sandreas.hansson@arm.com } 30511051Sandreas.hansson@arm.com} 30611051Sandreas.hansson@arm.com 30712630Snikos.nikoleris@arm.comvoid 30812720Snikos.nikoleris@arm.comCache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time) 30912720Snikos.nikoleris@arm.com{ 31012720Snikos.nikoleris@arm.com // should never be satisfying an uncacheable access as we 31112720Snikos.nikoleris@arm.com // flush and invalidate any existing block as part of the 31212720Snikos.nikoleris@arm.com // lookup 31312720Snikos.nikoleris@arm.com assert(!pkt->req->isUncacheable()); 31412720Snikos.nikoleris@arm.com 31512724Snikos.nikoleris@arm.com BaseCache::handleTimingReqHit(pkt, blk, request_time); 31612720Snikos.nikoleris@arm.com} 31712720Snikos.nikoleris@arm.com 31812720Snikos.nikoleris@arm.comvoid 31912720Snikos.nikoleris@arm.comCache::handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, Tick forward_time, 32012720Snikos.nikoleris@arm.com Tick request_time) 32112720Snikos.nikoleris@arm.com{ 32212724Snikos.nikoleris@arm.com if (pkt->req->isUncacheable()) { 32312724Snikos.nikoleris@arm.com // ignore any existing MSHR if we are dealing with an 32412724Snikos.nikoleris@arm.com // uncacheable request 32512724Snikos.nikoleris@arm.com 32612724Snikos.nikoleris@arm.com // should have flushed and have no valid block 32712724Snikos.nikoleris@arm.com assert(!blk || !blk->isValid()); 32812724Snikos.nikoleris@arm.com 32912724Snikos.nikoleris@arm.com mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++; 33012724Snikos.nikoleris@arm.com 33112724Snikos.nikoleris@arm.com if (pkt->isWrite()) { 33212724Snikos.nikoleris@arm.com allocateWriteBuffer(pkt, forward_time); 33312724Snikos.nikoleris@arm.com } else { 33412724Snikos.nikoleris@arm.com assert(pkt->isRead()); 33512724Snikos.nikoleris@arm.com 33612724Snikos.nikoleris@arm.com // uncacheable accesses always allocate a new MSHR 33712724Snikos.nikoleris@arm.com 33812724Snikos.nikoleris@arm.com // Here we are using forward_time, modelling the latency of 33912724Snikos.nikoleris@arm.com // a miss (outbound) just as forwardLatency, neglecting the 34012724Snikos.nikoleris@arm.com // lookupLatency component. 34112724Snikos.nikoleris@arm.com allocateMissBuffer(pkt, forward_time); 34212724Snikos.nikoleris@arm.com } 34312724Snikos.nikoleris@arm.com 34412724Snikos.nikoleris@arm.com return; 34512724Snikos.nikoleris@arm.com } 34612724Snikos.nikoleris@arm.com 34712720Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 34812720Snikos.nikoleris@arm.com 34912724Snikos.nikoleris@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, pkt->isSecure()); 35012720Snikos.nikoleris@arm.com 35112720Snikos.nikoleris@arm.com // Software prefetch handling: 35212720Snikos.nikoleris@arm.com // To keep the core from waiting on data it won't look at 35312720Snikos.nikoleris@arm.com // anyway, send back a response with dummy data. Miss handling 35412720Snikos.nikoleris@arm.com // will continue asynchronously. Unfortunately, the core will 35512720Snikos.nikoleris@arm.com // insist upon freeing original Packet/Request, so we have to 35612720Snikos.nikoleris@arm.com // create a new pair with a different lifecycle. Note that this 35712720Snikos.nikoleris@arm.com // processing happens before any MSHR munging on the behalf of 35812720Snikos.nikoleris@arm.com // this request because this new Request will be the one stored 35912720Snikos.nikoleris@arm.com // into the MSHRs, not the original. 36012720Snikos.nikoleris@arm.com if (pkt->cmd.isSWPrefetch()) { 36112720Snikos.nikoleris@arm.com assert(pkt->needsResponse()); 36212720Snikos.nikoleris@arm.com assert(pkt->req->hasPaddr()); 36312720Snikos.nikoleris@arm.com assert(!pkt->req->isUncacheable()); 36412720Snikos.nikoleris@arm.com 36512720Snikos.nikoleris@arm.com // There's no reason to add a prefetch as an additional target 36612720Snikos.nikoleris@arm.com // to an existing MSHR. If an outstanding request is already 36712720Snikos.nikoleris@arm.com // in progress, there is nothing for the prefetch to do. 36812720Snikos.nikoleris@arm.com // If this is the case, we don't even create a request at all. 36912720Snikos.nikoleris@arm.com PacketPtr pf = nullptr; 37012720Snikos.nikoleris@arm.com 37112720Snikos.nikoleris@arm.com if (!mshr) { 37212720Snikos.nikoleris@arm.com // copy the request and create a new SoftPFReq packet 37312749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>(pkt->req->getPaddr(), 37412749Sgiacomo.travaglini@arm.com pkt->req->getSize(), 37512749Sgiacomo.travaglini@arm.com pkt->req->getFlags(), 37612749Sgiacomo.travaglini@arm.com pkt->req->masterId()); 37712720Snikos.nikoleris@arm.com pf = new Packet(req, pkt->cmd); 37812720Snikos.nikoleris@arm.com pf->allocate(); 37913860Sodanrc@yahoo.com.br assert(pf->matchAddr(pkt)); 38012720Snikos.nikoleris@arm.com assert(pf->getSize() == pkt->getSize()); 38112720Snikos.nikoleris@arm.com } 38212720Snikos.nikoleris@arm.com 38312720Snikos.nikoleris@arm.com pkt->makeTimingResponse(); 38412720Snikos.nikoleris@arm.com 38512720Snikos.nikoleris@arm.com // request_time is used here, taking into account lat and the delay 38612720Snikos.nikoleris@arm.com // charged if the packet comes from the xbar. 38713564Snikos.nikoleris@arm.com cpuSidePort.schedTimingResp(pkt, request_time); 38812720Snikos.nikoleris@arm.com 38912720Snikos.nikoleris@arm.com // If an outstanding request is in progress (we found an 39012720Snikos.nikoleris@arm.com // MSHR) this is set to null 39112720Snikos.nikoleris@arm.com pkt = pf; 39212720Snikos.nikoleris@arm.com } 39312720Snikos.nikoleris@arm.com 39412724Snikos.nikoleris@arm.com BaseCache::handleTimingReqMiss(pkt, mshr, blk, forward_time, request_time); 39512720Snikos.nikoleris@arm.com} 39612720Snikos.nikoleris@arm.com 39712720Snikos.nikoleris@arm.comvoid 39811051Sandreas.hansson@arm.comCache::recvTimingReq(PacketPtr pkt) 39911051Sandreas.hansson@arm.com{ 40011830Sbaz21@cam.ac.uk DPRINTF(CacheTags, "%s tags:\n%s\n", __func__, tags->print()); 40111051Sandreas.hansson@arm.com 40211051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 40311051Sandreas.hansson@arm.com 40411284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 40511051Sandreas.hansson@arm.com // a cache above us (but not where the packet came from) is 40611284Sandreas.hansson@arm.com // responding to the request, in other words it has the line 40711284Sandreas.hansson@arm.com // in Modified or Owned state 40811744Snikos.nikoleris@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 40911744Snikos.nikoleris@arm.com pkt->print()); 41011051Sandreas.hansson@arm.com 41111284Sandreas.hansson@arm.com // if the packet needs the block to be writable, and the cache 41211284Sandreas.hansson@arm.com // that has promised to respond (setting the cache responding 41311284Sandreas.hansson@arm.com // flag) is not providing writable (it is in Owned rather than 41411284Sandreas.hansson@arm.com // the Modified state), we know that there may be other Shared 41511284Sandreas.hansson@arm.com // copies in the system; go out and invalidate them all 41611334Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 41711284Sandreas.hansson@arm.com 41811334Sandreas.hansson@arm.com // an upstream cache that had the line in Owned state 41911334Sandreas.hansson@arm.com // (dirty, but not writable), is responding and thus 42011334Sandreas.hansson@arm.com // transferring the dirty line from one branch of the 42111334Sandreas.hansson@arm.com // cache hierarchy to another 42211284Sandreas.hansson@arm.com 42311334Sandreas.hansson@arm.com // send out an express snoop and invalidate all other 42411334Sandreas.hansson@arm.com // copies (snooping a packet that needs writable is the 42511334Sandreas.hansson@arm.com // same as an invalidation), thus turning the Owned line 42611334Sandreas.hansson@arm.com // into a Modified line, note that we don't invalidate the 42711334Sandreas.hansson@arm.com // block in the current cache or any other cache on the 42811334Sandreas.hansson@arm.com // path to memory 42911051Sandreas.hansson@arm.com 43011334Sandreas.hansson@arm.com // create a downstream express snoop with cleared packet 43111334Sandreas.hansson@arm.com // flags, there is no need to allocate any data as the 43211334Sandreas.hansson@arm.com // packet is merely used to co-ordinate state transitions 43311334Sandreas.hansson@arm.com Packet *snoop_pkt = new Packet(pkt, true, false); 43411051Sandreas.hansson@arm.com 43511334Sandreas.hansson@arm.com // also reset the bus time that the original packet has 43611334Sandreas.hansson@arm.com // not yet paid for 43711334Sandreas.hansson@arm.com snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0; 43811051Sandreas.hansson@arm.com 43911334Sandreas.hansson@arm.com // make this an instantaneous express snoop, and let the 44011334Sandreas.hansson@arm.com // other caches in the system know that the another cache 44111334Sandreas.hansson@arm.com // is responding, because we have found the authorative 44211334Sandreas.hansson@arm.com // copy (Modified or Owned) that will supply the right 44311334Sandreas.hansson@arm.com // data 44411334Sandreas.hansson@arm.com snoop_pkt->setExpressSnoop(); 44511334Sandreas.hansson@arm.com snoop_pkt->setCacheResponding(); 44611051Sandreas.hansson@arm.com 44711334Sandreas.hansson@arm.com // this express snoop travels towards the memory, and at 44811334Sandreas.hansson@arm.com // every crossbar it is snooped upwards thus reaching 44911334Sandreas.hansson@arm.com // every cache in the system 45012724Snikos.nikoleris@arm.com bool M5_VAR_USED success = memSidePort.sendTimingReq(snoop_pkt); 45111334Sandreas.hansson@arm.com // express snoops always succeed 45211334Sandreas.hansson@arm.com assert(success); 45311334Sandreas.hansson@arm.com 45411334Sandreas.hansson@arm.com // main memory will delete the snoop packet 45511051Sandreas.hansson@arm.com 45611284Sandreas.hansson@arm.com // queue for deletion, as opposed to immediate deletion, as 45711284Sandreas.hansson@arm.com // the sending cache is still relying on the packet 45811190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 45911051Sandreas.hansson@arm.com 46011334Sandreas.hansson@arm.com // no need to take any further action in this particular cache 46111334Sandreas.hansson@arm.com // as an upstram cache has already committed to responding, 46211334Sandreas.hansson@arm.com // and we have already sent out any express snoops in the 46311334Sandreas.hansson@arm.com // section above to ensure all other copies in the system are 46411334Sandreas.hansson@arm.com // invalidated 46512630Snikos.nikoleris@arm.com return; 46611051Sandreas.hansson@arm.com } 46711051Sandreas.hansson@arm.com 46812724Snikos.nikoleris@arm.com BaseCache::recvTimingReq(pkt); 46911051Sandreas.hansson@arm.com} 47011051Sandreas.hansson@arm.com 47111051Sandreas.hansson@arm.comPacketPtr 47211452Sandreas.hansson@arm.comCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 47313350Snikos.nikoleris@arm.com bool needsWritable, 47413350Snikos.nikoleris@arm.com bool is_whole_line_write) const 47511051Sandreas.hansson@arm.com{ 47611452Sandreas.hansson@arm.com // should never see evictions here 47711452Sandreas.hansson@arm.com assert(!cpu_pkt->isEviction()); 47811452Sandreas.hansson@arm.com 47911051Sandreas.hansson@arm.com bool blkValid = blk && blk->isValid(); 48011051Sandreas.hansson@arm.com 48111452Sandreas.hansson@arm.com if (cpu_pkt->req->isUncacheable() || 48211745Sandreas.hansson@arm.com (!blkValid && cpu_pkt->isUpgrade()) || 48312349Snikos.nikoleris@arm.com cpu_pkt->cmd == MemCmd::InvalidateReq || cpu_pkt->isClean()) { 48411452Sandreas.hansson@arm.com // uncacheable requests and upgrades from upper-level caches 48511452Sandreas.hansson@arm.com // that missed completely just go through as is 48611452Sandreas.hansson@arm.com return nullptr; 48711051Sandreas.hansson@arm.com } 48811051Sandreas.hansson@arm.com 48911051Sandreas.hansson@arm.com assert(cpu_pkt->needsResponse()); 49011051Sandreas.hansson@arm.com 49111051Sandreas.hansson@arm.com MemCmd cmd; 49211051Sandreas.hansson@arm.com // @TODO make useUpgrades a parameter. 49311051Sandreas.hansson@arm.com // Note that ownership protocols require upgrade, otherwise a 49411051Sandreas.hansson@arm.com // write miss on a shared owned block will generate a ReadExcl, 49511051Sandreas.hansson@arm.com // which will clobber the owned copy. 49611051Sandreas.hansson@arm.com const bool useUpgrades = true; 49713350Snikos.nikoleris@arm.com assert(cpu_pkt->cmd != MemCmd::WriteLineReq || is_whole_line_write); 49813350Snikos.nikoleris@arm.com if (is_whole_line_write) { 49911747Snikos.nikoleris@arm.com assert(!blkValid || !blk->isWritable()); 50011747Snikos.nikoleris@arm.com // forward as invalidate to all other caches, this gives us 50111747Snikos.nikoleris@arm.com // the line in Exclusive state, and invalidates all other 50211747Snikos.nikoleris@arm.com // copies 50311747Snikos.nikoleris@arm.com cmd = MemCmd::InvalidateReq; 50411747Snikos.nikoleris@arm.com } else if (blkValid && useUpgrades) { 50511284Sandreas.hansson@arm.com // only reason to be here is that blk is read only and we need 50611284Sandreas.hansson@arm.com // it to be writable 50711284Sandreas.hansson@arm.com assert(needsWritable); 50811051Sandreas.hansson@arm.com assert(!blk->isWritable()); 50911051Sandreas.hansson@arm.com cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq; 51011051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq || 51111051Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::StoreCondFailReq) { 51211051Sandreas.hansson@arm.com // Even though this SC will fail, we still need to send out the 51311051Sandreas.hansson@arm.com // request and get the data to supply it to other snoopers in the case 51411051Sandreas.hansson@arm.com // where the determination the StoreCond fails is delayed due to 51511051Sandreas.hansson@arm.com // all caches not being on the same local bus. 51611051Sandreas.hansson@arm.com cmd = MemCmd::SCUpgradeFailReq; 51711051Sandreas.hansson@arm.com } else { 51811051Sandreas.hansson@arm.com // block is invalid 51912425Snikos.nikoleris@arm.com 52012425Snikos.nikoleris@arm.com // If the request does not need a writable there are two cases 52112425Snikos.nikoleris@arm.com // where we need to ensure the response will not fetch the 52212425Snikos.nikoleris@arm.com // block in dirty state: 52312425Snikos.nikoleris@arm.com // * this cache is read only and it does not perform 52412425Snikos.nikoleris@arm.com // writebacks, 52512425Snikos.nikoleris@arm.com // * this cache is mostly exclusive and will not fill (since 52612425Snikos.nikoleris@arm.com // it does not fill it will have to writeback the dirty data 52712425Snikos.nikoleris@arm.com // immediately which generates uneccesary writebacks). 52812425Snikos.nikoleris@arm.com bool force_clean_rsp = isReadOnly || clusivity == Enums::mostly_excl; 52911284Sandreas.hansson@arm.com cmd = needsWritable ? MemCmd::ReadExReq : 53012425Snikos.nikoleris@arm.com (force_clean_rsp ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq); 53111051Sandreas.hansson@arm.com } 53211051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize); 53311051Sandreas.hansson@arm.com 53411284Sandreas.hansson@arm.com // if there are upstream caches that have already marked the 53511284Sandreas.hansson@arm.com // packet as having sharers (not passing writable), pass that info 53611284Sandreas.hansson@arm.com // downstream 53711602Sandreas.hansson@arm.com if (cpu_pkt->hasSharers() && !needsWritable) { 53811051Sandreas.hansson@arm.com // note that cpu_pkt may have spent a considerable time in the 53911051Sandreas.hansson@arm.com // MSHR queue and that the information could possibly be out 54011051Sandreas.hansson@arm.com // of date, however, there is no harm in conservatively 54111284Sandreas.hansson@arm.com // assuming the block has sharers 54211284Sandreas.hansson@arm.com pkt->setHasSharers(); 54311744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: passing hasSharers from %s to %s\n", 54411744Snikos.nikoleris@arm.com __func__, cpu_pkt->print(), pkt->print()); 54511051Sandreas.hansson@arm.com } 54611051Sandreas.hansson@arm.com 54711051Sandreas.hansson@arm.com // the packet should be block aligned 54811892Snikos.nikoleris@arm.com assert(pkt->getAddr() == pkt->getBlockAddr(blkSize)); 54911051Sandreas.hansson@arm.com 55011051Sandreas.hansson@arm.com pkt->allocate(); 55111744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: created %s from %s\n", __func__, pkt->print(), 55211744Snikos.nikoleris@arm.com cpu_pkt->print()); 55311051Sandreas.hansson@arm.com return pkt; 55411051Sandreas.hansson@arm.com} 55511051Sandreas.hansson@arm.com 55611051Sandreas.hansson@arm.com 55712721Snikos.nikoleris@arm.comCycles 55813948Sodanrc@yahoo.com.brCache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk) 55912721Snikos.nikoleris@arm.com{ 56012721Snikos.nikoleris@arm.com // deal with the packets that go through the write path of 56112721Snikos.nikoleris@arm.com // the cache, i.e. any evictions and writes 56212721Snikos.nikoleris@arm.com if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean || 56312721Snikos.nikoleris@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 56412724Snikos.nikoleris@arm.com Cycles latency = ticksToCycles(memSidePort.sendAtomic(pkt)); 56512721Snikos.nikoleris@arm.com 56612721Snikos.nikoleris@arm.com // at this point, if the request was an uncacheable write 56712721Snikos.nikoleris@arm.com // request, it has been satisfied by a memory below and the 56812721Snikos.nikoleris@arm.com // packet carries the response back 56912721Snikos.nikoleris@arm.com assert(!(pkt->req->isUncacheable() && pkt->isWrite()) || 57012721Snikos.nikoleris@arm.com pkt->isResponse()); 57112721Snikos.nikoleris@arm.com 57212721Snikos.nikoleris@arm.com return latency; 57312721Snikos.nikoleris@arm.com } 57412721Snikos.nikoleris@arm.com 57512721Snikos.nikoleris@arm.com // only misses left 57612721Snikos.nikoleris@arm.com 57713350Snikos.nikoleris@arm.com PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable(), 57813350Snikos.nikoleris@arm.com pkt->isWholeLineWrite(blkSize)); 57912721Snikos.nikoleris@arm.com 58012721Snikos.nikoleris@arm.com bool is_forward = (bus_pkt == nullptr); 58112721Snikos.nikoleris@arm.com 58212721Snikos.nikoleris@arm.com if (is_forward) { 58312721Snikos.nikoleris@arm.com // just forwarding the same request to the next level 58412721Snikos.nikoleris@arm.com // no local cache operation involved 58512721Snikos.nikoleris@arm.com bus_pkt = pkt; 58612721Snikos.nikoleris@arm.com } 58712721Snikos.nikoleris@arm.com 58812721Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Sending an atomic %s\n", __func__, 58912721Snikos.nikoleris@arm.com bus_pkt->print()); 59012721Snikos.nikoleris@arm.com 59112721Snikos.nikoleris@arm.com#if TRACING_ON 59212721Snikos.nikoleris@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 59312721Snikos.nikoleris@arm.com#endif 59412721Snikos.nikoleris@arm.com 59512724Snikos.nikoleris@arm.com Cycles latency = ticksToCycles(memSidePort.sendAtomic(bus_pkt)); 59612721Snikos.nikoleris@arm.com 59712721Snikos.nikoleris@arm.com bool is_invalidate = bus_pkt->isInvalidate(); 59812721Snikos.nikoleris@arm.com 59912721Snikos.nikoleris@arm.com // We are now dealing with the response handling 60012721Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Receive response: %s in state %i\n", __func__, 60112721Snikos.nikoleris@arm.com bus_pkt->print(), old_state); 60212721Snikos.nikoleris@arm.com 60312721Snikos.nikoleris@arm.com // If packet was a forward, the response (if any) is already 60412721Snikos.nikoleris@arm.com // in place in the bus_pkt == pkt structure, so we don't need 60512721Snikos.nikoleris@arm.com // to do anything. Otherwise, use the separate bus_pkt to 60612721Snikos.nikoleris@arm.com // generate response to pkt and then delete it. 60712721Snikos.nikoleris@arm.com if (!is_forward) { 60812721Snikos.nikoleris@arm.com if (pkt->needsResponse()) { 60912721Snikos.nikoleris@arm.com assert(bus_pkt->isResponse()); 61012721Snikos.nikoleris@arm.com if (bus_pkt->isError()) { 61112721Snikos.nikoleris@arm.com pkt->makeAtomicResponse(); 61212721Snikos.nikoleris@arm.com pkt->copyError(bus_pkt); 61313350Snikos.nikoleris@arm.com } else if (pkt->isWholeLineWrite(blkSize)) { 61412721Snikos.nikoleris@arm.com // note the use of pkt, not bus_pkt here. 61512721Snikos.nikoleris@arm.com 61612721Snikos.nikoleris@arm.com // write-line request to the cache that promoted 61712721Snikos.nikoleris@arm.com // the write to a whole line 61813352Snikos.nikoleris@arm.com const bool allocate = allocOnFill(pkt->cmd) && 61913352Snikos.nikoleris@arm.com (!writeAllocator || writeAllocator->allocate()); 62013948Sodanrc@yahoo.com.br blk = handleFill(bus_pkt, blk, allocate); 62112721Snikos.nikoleris@arm.com assert(blk != NULL); 62212721Snikos.nikoleris@arm.com is_invalidate = false; 62312721Snikos.nikoleris@arm.com satisfyRequest(pkt, blk); 62412721Snikos.nikoleris@arm.com } else if (bus_pkt->isRead() || 62512721Snikos.nikoleris@arm.com bus_pkt->cmd == MemCmd::UpgradeResp) { 62612721Snikos.nikoleris@arm.com // we're updating cache state to allow us to 62712721Snikos.nikoleris@arm.com // satisfy the upstream request from the cache 62813948Sodanrc@yahoo.com.br blk = handleFill(bus_pkt, blk, allocOnFill(pkt->cmd)); 62912721Snikos.nikoleris@arm.com satisfyRequest(pkt, blk); 63012721Snikos.nikoleris@arm.com maintainClusivity(pkt->fromCache(), blk); 63112721Snikos.nikoleris@arm.com } else { 63212721Snikos.nikoleris@arm.com // we're satisfying the upstream request without 63312721Snikos.nikoleris@arm.com // modifying cache state, e.g., a write-through 63412721Snikos.nikoleris@arm.com pkt->makeAtomicResponse(); 63512721Snikos.nikoleris@arm.com } 63612721Snikos.nikoleris@arm.com } 63712721Snikos.nikoleris@arm.com delete bus_pkt; 63812721Snikos.nikoleris@arm.com } 63912721Snikos.nikoleris@arm.com 64012721Snikos.nikoleris@arm.com if (is_invalidate && blk && blk->isValid()) { 64112721Snikos.nikoleris@arm.com invalidateBlock(blk); 64212721Snikos.nikoleris@arm.com } 64312721Snikos.nikoleris@arm.com 64412721Snikos.nikoleris@arm.com return latency; 64512721Snikos.nikoleris@arm.com} 64612721Snikos.nikoleris@arm.com 64711051Sandreas.hansson@arm.comTick 64811051Sandreas.hansson@arm.comCache::recvAtomic(PacketPtr pkt) 64911051Sandreas.hansson@arm.com{ 65011051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 65111051Sandreas.hansson@arm.com 65213412Snikos.nikoleris@arm.com // follow the same flow as in recvTimingReq, and check if a cache 65313412Snikos.nikoleris@arm.com // above us is responding 65413412Snikos.nikoleris@arm.com if (pkt->cacheResponding()) { 65513412Snikos.nikoleris@arm.com assert(!pkt->req->isCacheInvalidate()); 65613412Snikos.nikoleris@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 65713412Snikos.nikoleris@arm.com pkt->print()); 65813412Snikos.nikoleris@arm.com 65913412Snikos.nikoleris@arm.com // if a cache is responding, and it had the line in Owned 66013412Snikos.nikoleris@arm.com // rather than Modified state, we need to invalidate any 66113412Snikos.nikoleris@arm.com // copies that are not on the same path to memory 66213412Snikos.nikoleris@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 66313412Snikos.nikoleris@arm.com 66413412Snikos.nikoleris@arm.com return memSidePort.sendAtomic(pkt); 66513412Snikos.nikoleris@arm.com } 66613412Snikos.nikoleris@arm.com 66712724Snikos.nikoleris@arm.com return BaseCache::recvAtomic(pkt); 66811051Sandreas.hansson@arm.com} 66911051Sandreas.hansson@arm.com 67011051Sandreas.hansson@arm.com 67111051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 67211051Sandreas.hansson@arm.com// 67311051Sandreas.hansson@arm.com// Response handling: responses from the memory side 67411051Sandreas.hansson@arm.com// 67511051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 67611051Sandreas.hansson@arm.com 67711051Sandreas.hansson@arm.com 67811051Sandreas.hansson@arm.comvoid 67913478Sodanrc@yahoo.com.brCache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk) 68011051Sandreas.hansson@arm.com{ 68113859Sodanrc@yahoo.com.br QueueEntry::Target *initial_tgt = mshr->getTarget(); 68212719Snikos.nikoleris@arm.com // First offset for critical word first calculations 68312719Snikos.nikoleris@arm.com const int initial_offset = initial_tgt->pkt->getOffset(blkSize); 68412719Snikos.nikoleris@arm.com 68512719Snikos.nikoleris@arm.com const bool is_error = pkt->isError(); 68611051Sandreas.hansson@arm.com // allow invalidation responses originating from write-line 68711051Sandreas.hansson@arm.com // requests to be discarded 68813350Snikos.nikoleris@arm.com bool is_invalidate = pkt->isInvalidate() && 68913350Snikos.nikoleris@arm.com !mshr->wasWholeLineWrite; 69011051Sandreas.hansson@arm.com 69111742Snikos.nikoleris@arm.com MSHR::TargetList targets = mshr->extractServiceableTargets(pkt); 69211742Snikos.nikoleris@arm.com for (auto &target: targets) { 69311742Snikos.nikoleris@arm.com Packet *tgt_pkt = target.pkt; 69411742Snikos.nikoleris@arm.com switch (target.source) { 69511051Sandreas.hansson@arm.com case MSHR::Target::FromCPU: 69611051Sandreas.hansson@arm.com Tick completion_time; 69711051Sandreas.hansson@arm.com // Here we charge on completion_time the delay of the xbar if the 69811051Sandreas.hansson@arm.com // packet comes from it, charged on headerDelay. 69911051Sandreas.hansson@arm.com completion_time = pkt->headerDelay; 70011051Sandreas.hansson@arm.com 70111051Sandreas.hansson@arm.com // Software prefetch handling for cache closest to core 70211051Sandreas.hansson@arm.com if (tgt_pkt->cmd.isSWPrefetch()) { 70311483Snikos.nikoleris@arm.com // a software prefetch would have already been ack'd 70411483Snikos.nikoleris@arm.com // immediately with dummy data so the core would be able to 70511483Snikos.nikoleris@arm.com // retire it. This request completes right here, so we 70611483Snikos.nikoleris@arm.com // deallocate it. 70711051Sandreas.hansson@arm.com delete tgt_pkt; 70811051Sandreas.hansson@arm.com break; // skip response 70911051Sandreas.hansson@arm.com } 71011051Sandreas.hansson@arm.com 71111051Sandreas.hansson@arm.com // unlike the other packet flows, where data is found in other 71211051Sandreas.hansson@arm.com // caches or memory and brought back, write-line requests always 71311051Sandreas.hansson@arm.com // have the data right away, so the above check for "is fill?" 71411051Sandreas.hansson@arm.com // cannot actually be determined until examining the stored MSHR 71511051Sandreas.hansson@arm.com // state. We "catch up" with that logic here, which is duplicated 71611051Sandreas.hansson@arm.com // from above. 71711051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::WriteLineReq) { 71811051Sandreas.hansson@arm.com assert(!is_error); 71912719Snikos.nikoleris@arm.com assert(blk); 72013350Snikos.nikoleris@arm.com assert(blk->isWritable()); 72111051Sandreas.hansson@arm.com } 72211051Sandreas.hansson@arm.com 72312794Snikos.nikoleris@arm.com if (blk && blk->isValid() && !mshr->isForward) { 72411601Sandreas.hansson@arm.com satisfyRequest(tgt_pkt, blk, true, mshr->hasPostDowngrade()); 72511051Sandreas.hansson@arm.com 72611051Sandreas.hansson@arm.com // How many bytes past the first request is this one 72711051Sandreas.hansson@arm.com int transfer_offset = 72811051Sandreas.hansson@arm.com tgt_pkt->getOffset(blkSize) - initial_offset; 72911051Sandreas.hansson@arm.com if (transfer_offset < 0) { 73011051Sandreas.hansson@arm.com transfer_offset += blkSize; 73111051Sandreas.hansson@arm.com } 73211051Sandreas.hansson@arm.com 73311051Sandreas.hansson@arm.com // If not critical word (offset) return payloadDelay. 73411051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 73511051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 73611051Sandreas.hansson@arm.com // the core. 73711051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 73811051Sandreas.hansson@arm.com (transfer_offset ? pkt->payloadDelay : 0); 73911051Sandreas.hansson@arm.com 74011051Sandreas.hansson@arm.com assert(!tgt_pkt->req->isUncacheable()); 74111051Sandreas.hansson@arm.com 74211051Sandreas.hansson@arm.com assert(tgt_pkt->req->masterId() < system->maxMasters()); 74311051Sandreas.hansson@arm.com missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] += 74411742Snikos.nikoleris@arm.com completion_time - target.recvTime; 74511051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::UpgradeFailResp) { 74611051Sandreas.hansson@arm.com // failed StoreCond upgrade 74711051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::StoreCondReq || 74811051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::StoreCondFailReq || 74911051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::SCUpgradeFailReq); 75011051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 75111051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 75211051Sandreas.hansson@arm.com // the core. 75311051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 75411051Sandreas.hansson@arm.com pkt->payloadDelay; 75511051Sandreas.hansson@arm.com tgt_pkt->req->setExtraData(0); 75611051Sandreas.hansson@arm.com } else { 75711750Snikos.nikoleris@arm.com // We are about to send a response to a cache above 75811750Snikos.nikoleris@arm.com // that asked for an invalidation; we need to 75911750Snikos.nikoleris@arm.com // invalidate our copy immediately as the most 76011750Snikos.nikoleris@arm.com // up-to-date copy of the block will now be in the 76111750Snikos.nikoleris@arm.com // cache above. It will also prevent this cache from 76211750Snikos.nikoleris@arm.com // responding (if the block was previously dirty) to 76311750Snikos.nikoleris@arm.com // snoops as they should snoop the caches above where 76411750Snikos.nikoleris@arm.com // they will get the response from. 76511750Snikos.nikoleris@arm.com if (is_invalidate && blk && blk->isValid()) { 76611750Snikos.nikoleris@arm.com invalidateBlock(blk); 76711750Snikos.nikoleris@arm.com } 76811051Sandreas.hansson@arm.com // not a cache fill, just forwarding response 76911051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 77011051Sandreas.hansson@arm.com // from lower level cahces/memory to the core. 77111051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 77211051Sandreas.hansson@arm.com pkt->payloadDelay; 77311051Sandreas.hansson@arm.com if (pkt->isRead() && !is_error) { 77411051Sandreas.hansson@arm.com // sanity check 77513860Sodanrc@yahoo.com.br assert(pkt->matchAddr(tgt_pkt)); 77611051Sandreas.hansson@arm.com assert(pkt->getSize() >= tgt_pkt->getSize()); 77711051Sandreas.hansson@arm.com 77811051Sandreas.hansson@arm.com tgt_pkt->setData(pkt->getConstPtr<uint8_t>()); 77911051Sandreas.hansson@arm.com } 78013732Snikos.nikoleris@arm.com 78113732Snikos.nikoleris@arm.com // this response did not allocate here and therefore 78213732Snikos.nikoleris@arm.com // it was not consumed, make sure that any flags are 78313732Snikos.nikoleris@arm.com // carried over to cache above 78413732Snikos.nikoleris@arm.com tgt_pkt->copyResponderFlags(pkt); 78511051Sandreas.hansson@arm.com } 78611051Sandreas.hansson@arm.com tgt_pkt->makeTimingResponse(); 78711051Sandreas.hansson@arm.com // if this packet is an error copy that to the new packet 78811051Sandreas.hansson@arm.com if (is_error) 78911051Sandreas.hansson@arm.com tgt_pkt->copyError(pkt); 79011051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::ReadResp && 79111136Sandreas.hansson@arm.com (is_invalidate || mshr->hasPostInvalidate())) { 79211051Sandreas.hansson@arm.com // If intermediate cache got ReadRespWithInvalidate, 79311051Sandreas.hansson@arm.com // propagate that. Response should not have 79411051Sandreas.hansson@arm.com // isInvalidate() set otherwise. 79511051Sandreas.hansson@arm.com tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate; 79611744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: updated cmd to %s\n", __func__, 79711744Snikos.nikoleris@arm.com tgt_pkt->print()); 79811051Sandreas.hansson@arm.com } 79911051Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 80011051Sandreas.hansson@arm.com tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; 80113564Snikos.nikoleris@arm.com cpuSidePort.schedTimingResp(tgt_pkt, completion_time); 80211051Sandreas.hansson@arm.com break; 80311051Sandreas.hansson@arm.com 80411051Sandreas.hansson@arm.com case MSHR::Target::FromPrefetcher: 80511051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::HardPFReq); 80611051Sandreas.hansson@arm.com if (blk) 80711051Sandreas.hansson@arm.com blk->status |= BlkHWPrefetched; 80811051Sandreas.hansson@arm.com delete tgt_pkt; 80911051Sandreas.hansson@arm.com break; 81011051Sandreas.hansson@arm.com 81111051Sandreas.hansson@arm.com case MSHR::Target::FromSnoop: 81211051Sandreas.hansson@arm.com // I don't believe that a snoop can be in an error state 81311051Sandreas.hansson@arm.com assert(!is_error); 81411051Sandreas.hansson@arm.com // response to snoop request 81511051Sandreas.hansson@arm.com DPRINTF(Cache, "processing deferred snoop...\n"); 81611749Snikos.nikoleris@arm.com // If the response is invalidating, a snooping target can 81711749Snikos.nikoleris@arm.com // be satisfied if it is also invalidating. If the reponse is, not 81812349Snikos.nikoleris@arm.com // only invalidating, but more specifically an InvalidateResp and 81912349Snikos.nikoleris@arm.com // the MSHR was created due to an InvalidateReq then a cache above 82012349Snikos.nikoleris@arm.com // is waiting to satisfy a WriteLineReq. In this case even an 82111749Snikos.nikoleris@arm.com // non-invalidating snoop is added as a target here since this is 82211749Snikos.nikoleris@arm.com // the ordering point. When the InvalidateResp reaches this cache, 82311749Snikos.nikoleris@arm.com // the snooping target will snoop further the cache above with the 82411749Snikos.nikoleris@arm.com // WriteLineReq. 82512349Snikos.nikoleris@arm.com assert(!is_invalidate || pkt->cmd == MemCmd::InvalidateResp || 82612349Snikos.nikoleris@arm.com pkt->req->isCacheMaintenance() || 82712349Snikos.nikoleris@arm.com mshr->hasPostInvalidate()); 82811051Sandreas.hansson@arm.com handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate()); 82911051Sandreas.hansson@arm.com break; 83011051Sandreas.hansson@arm.com 83111051Sandreas.hansson@arm.com default: 83211742Snikos.nikoleris@arm.com panic("Illegal target->source enum %d\n", target.source); 83311051Sandreas.hansson@arm.com } 83411051Sandreas.hansson@arm.com } 83511051Sandreas.hansson@arm.com 83612715Snikos.nikoleris@arm.com maintainClusivity(targets.hasFromCache, blk); 83711601Sandreas.hansson@arm.com 83811051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 83911051Sandreas.hansson@arm.com // an invalidate response stemming from a write line request 84011051Sandreas.hansson@arm.com // should not invalidate the block, so check if the 84111051Sandreas.hansson@arm.com // invalidation should be discarded 84211136Sandreas.hansson@arm.com if (is_invalidate || mshr->hasPostInvalidate()) { 84311197Sandreas.hansson@arm.com invalidateBlock(blk); 84411051Sandreas.hansson@arm.com } else if (mshr->hasPostDowngrade()) { 84511051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 84611051Sandreas.hansson@arm.com } 84711051Sandreas.hansson@arm.com } 84812719Snikos.nikoleris@arm.com} 84912719Snikos.nikoleris@arm.com 85011051Sandreas.hansson@arm.comPacketPtr 85112723Snikos.nikoleris@arm.comCache::evictBlock(CacheBlk *blk) 85212723Snikos.nikoleris@arm.com{ 85312723Snikos.nikoleris@arm.com PacketPtr pkt = (blk->isDirty() || writebackClean) ? 85412723Snikos.nikoleris@arm.com writebackBlk(blk) : cleanEvictBlk(blk); 85512723Snikos.nikoleris@arm.com 85612723Snikos.nikoleris@arm.com invalidateBlock(blk); 85712723Snikos.nikoleris@arm.com 85812723Snikos.nikoleris@arm.com return pkt; 85912723Snikos.nikoleris@arm.com} 86012723Snikos.nikoleris@arm.com 86112723Snikos.nikoleris@arm.comPacketPtr 86211051Sandreas.hansson@arm.comCache::cleanEvictBlk(CacheBlk *blk) 86311051Sandreas.hansson@arm.com{ 86411199Sandreas.hansson@arm.com assert(!writebackClean); 86511051Sandreas.hansson@arm.com assert(blk && blk->isValid() && !blk->isDirty()); 86612749Sgiacomo.travaglini@arm.com 86711051Sandreas.hansson@arm.com // Creating a zero sized write, a message to the snoop filter 86812749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>( 86912749Sgiacomo.travaglini@arm.com regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId); 87012748Sgiacomo.travaglini@arm.com 87111051Sandreas.hansson@arm.com if (blk->isSecure()) 87211051Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 87311051Sandreas.hansson@arm.com 87411051Sandreas.hansson@arm.com req->taskId(blk->task_id); 87511051Sandreas.hansson@arm.com 87611051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::CleanEvict); 87711051Sandreas.hansson@arm.com pkt->allocate(); 87811744Snikos.nikoleris@arm.com DPRINTF(Cache, "Create CleanEvict %s\n", pkt->print()); 87911051Sandreas.hansson@arm.com 88011051Sandreas.hansson@arm.com return pkt; 88111051Sandreas.hansson@arm.com} 88211051Sandreas.hansson@arm.com 88311051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 88411051Sandreas.hansson@arm.com// 88511051Sandreas.hansson@arm.com// Snoop path: requests coming in from the memory side 88611051Sandreas.hansson@arm.com// 88711051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 88811051Sandreas.hansson@arm.com 88911051Sandreas.hansson@arm.comvoid 89011051Sandreas.hansson@arm.comCache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 89111051Sandreas.hansson@arm.com bool already_copied, bool pending_inval) 89211051Sandreas.hansson@arm.com{ 89311051Sandreas.hansson@arm.com // sanity check 89411051Sandreas.hansson@arm.com assert(req_pkt->isRequest()); 89511051Sandreas.hansson@arm.com assert(req_pkt->needsResponse()); 89611051Sandreas.hansson@arm.com 89711744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: for %s\n", __func__, req_pkt->print()); 89811051Sandreas.hansson@arm.com // timing-mode snoop responses require a new packet, unless we 89911051Sandreas.hansson@arm.com // already made a copy... 90011051Sandreas.hansson@arm.com PacketPtr pkt = req_pkt; 90111051Sandreas.hansson@arm.com if (!already_copied) 90211051Sandreas.hansson@arm.com // do not clear flags, and allocate space for data if the 90311051Sandreas.hansson@arm.com // packet needs it (the only packets that carry data are read 90411051Sandreas.hansson@arm.com // responses) 90511051Sandreas.hansson@arm.com pkt = new Packet(req_pkt, false, req_pkt->isRead()); 90611051Sandreas.hansson@arm.com 90711051Sandreas.hansson@arm.com assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() || 90811284Sandreas.hansson@arm.com pkt->hasSharers()); 90911051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 91011051Sandreas.hansson@arm.com if (pkt->isRead()) { 91111051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk_data, blkSize); 91211051Sandreas.hansson@arm.com } 91311051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadResp && pending_inval) { 91411051Sandreas.hansson@arm.com // Assume we defer a response to a read from a far-away cache 91511051Sandreas.hansson@arm.com // A, then later defer a ReadExcl from a cache B on the same 91611284Sandreas.hansson@arm.com // bus as us. We'll assert cacheResponding in both cases, but 91711284Sandreas.hansson@arm.com // in the latter case cacheResponding will keep the 91811284Sandreas.hansson@arm.com // invalidation from reaching cache A. This special response 91911284Sandreas.hansson@arm.com // tells cache A that it gets the block to satisfy its read, 92011284Sandreas.hansson@arm.com // but must immediately invalidate it. 92111051Sandreas.hansson@arm.com pkt->cmd = MemCmd::ReadRespWithInvalidate; 92211051Sandreas.hansson@arm.com } 92311051Sandreas.hansson@arm.com // Here we consider forward_time, paying for just forward latency and 92411051Sandreas.hansson@arm.com // also charging the delay provided by the xbar. 92511051Sandreas.hansson@arm.com // forward_time is used as send_time in next allocateWriteBuffer(). 92611051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 92711051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 92811051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 92911744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: created response: %s tick: %lu\n", __func__, 93011744Snikos.nikoleris@arm.com pkt->print(), forward_time); 93113564Snikos.nikoleris@arm.com memSidePort.schedTimingSnoopResp(pkt, forward_time); 93211051Sandreas.hansson@arm.com} 93311051Sandreas.hansson@arm.com 93411127Sandreas.hansson@arm.comuint32_t 93511051Sandreas.hansson@arm.comCache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, 93611051Sandreas.hansson@arm.com bool is_deferred, bool pending_inval) 93711051Sandreas.hansson@arm.com{ 93811744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 93911051Sandreas.hansson@arm.com // deferred snoops can only happen in timing mode 94011051Sandreas.hansson@arm.com assert(!(is_deferred && !is_timing)); 94111051Sandreas.hansson@arm.com // pending_inval only makes sense on deferred snoops 94211051Sandreas.hansson@arm.com assert(!(pending_inval && !is_deferred)); 94311051Sandreas.hansson@arm.com assert(pkt->isRequest()); 94411051Sandreas.hansson@arm.com 94511051Sandreas.hansson@arm.com // the packet may get modified if we or a forwarded snooper 94611051Sandreas.hansson@arm.com // responds in atomic mode, so remember a few things about the 94711051Sandreas.hansson@arm.com // original packet up front 94811051Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 94911284Sandreas.hansson@arm.com bool M5_VAR_USED needs_writable = pkt->needsWritable(); 95011051Sandreas.hansson@arm.com 95111285Sandreas.hansson@arm.com // at the moment we could get an uncacheable write which does not 95211285Sandreas.hansson@arm.com // have the invalidate flag, and we need a suitable way of dealing 95311285Sandreas.hansson@arm.com // with this case 95411285Sandreas.hansson@arm.com panic_if(invalidate && pkt->req->isUncacheable(), 95511744Snikos.nikoleris@arm.com "%s got an invalidating uncacheable snoop request %s", 95611744Snikos.nikoleris@arm.com name(), pkt->print()); 95711285Sandreas.hansson@arm.com 95811127Sandreas.hansson@arm.com uint32_t snoop_delay = 0; 95911127Sandreas.hansson@arm.com 96011051Sandreas.hansson@arm.com if (forwardSnoops) { 96111051Sandreas.hansson@arm.com // first propagate snoop upward to see if anyone above us wants to 96211051Sandreas.hansson@arm.com // handle it. save & restore packet src since it will get 96311051Sandreas.hansson@arm.com // rewritten to be relative to cpu-side bus (if any) 96411051Sandreas.hansson@arm.com if (is_timing) { 96511051Sandreas.hansson@arm.com // copy the packet so that we can clear any flags before 96611051Sandreas.hansson@arm.com // forwarding it upwards, we also allocate data (passing 96711051Sandreas.hansson@arm.com // the pointer along in case of static data), in case 96811051Sandreas.hansson@arm.com // there is a snoop hit in upper levels 96911051Sandreas.hansson@arm.com Packet snoopPkt(pkt, true, true); 97011051Sandreas.hansson@arm.com snoopPkt.setExpressSnoop(); 97111051Sandreas.hansson@arm.com // the snoop packet does not need to wait any additional 97211051Sandreas.hansson@arm.com // time 97311051Sandreas.hansson@arm.com snoopPkt.headerDelay = snoopPkt.payloadDelay = 0; 97412724Snikos.nikoleris@arm.com cpuSidePort.sendTimingSnoopReq(&snoopPkt); 97511127Sandreas.hansson@arm.com 97611127Sandreas.hansson@arm.com // add the header delay (including crossbar and snoop 97711127Sandreas.hansson@arm.com // delays) of the upward snoop to the snoop delay for this 97811127Sandreas.hansson@arm.com // cache 97911127Sandreas.hansson@arm.com snoop_delay += snoopPkt.headerDelay; 98011127Sandreas.hansson@arm.com 98111051Sandreas.hansson@arm.com // If this request is a prefetch or clean evict and an upper level 98211051Sandreas.hansson@arm.com // signals block present, make sure to propagate the block 98311051Sandreas.hansson@arm.com // presence to the requester. 98411051Sandreas.hansson@arm.com if (snoopPkt.isBlockCached()) { 98511051Sandreas.hansson@arm.com pkt->setBlockCached(); 98611051Sandreas.hansson@arm.com } 98712349Snikos.nikoleris@arm.com // If the request was satisfied by snooping the cache 98812349Snikos.nikoleris@arm.com // above, mark the original packet as satisfied too. 98912349Snikos.nikoleris@arm.com if (snoopPkt.satisfied()) { 99012349Snikos.nikoleris@arm.com pkt->setSatisfied(); 99112349Snikos.nikoleris@arm.com } 99213732Snikos.nikoleris@arm.com 99313732Snikos.nikoleris@arm.com // Copy over flags from the snoop response to make sure we 99413732Snikos.nikoleris@arm.com // inform the final destination 99513732Snikos.nikoleris@arm.com pkt->copyResponderFlags(&snoopPkt); 99611051Sandreas.hansson@arm.com } else { 99713732Snikos.nikoleris@arm.com bool already_responded = pkt->cacheResponding(); 99812724Snikos.nikoleris@arm.com cpuSidePort.sendAtomicSnoop(pkt); 99913732Snikos.nikoleris@arm.com if (!already_responded && pkt->cacheResponding()) { 100011051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache: 100111051Sandreas.hansson@arm.com // forward response to original requester 100211051Sandreas.hansson@arm.com assert(pkt->isResponse()); 100311051Sandreas.hansson@arm.com } 100411051Sandreas.hansson@arm.com } 100511051Sandreas.hansson@arm.com } 100611051Sandreas.hansson@arm.com 100712349Snikos.nikoleris@arm.com bool respond = false; 100812349Snikos.nikoleris@arm.com bool blk_valid = blk && blk->isValid(); 100912349Snikos.nikoleris@arm.com if (pkt->isClean()) { 101012349Snikos.nikoleris@arm.com if (blk_valid && blk->isDirty()) { 101112349Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: packet (snoop) %s found block: %s\n", 101212349Snikos.nikoleris@arm.com __func__, pkt->print(), blk->print()); 101312351Snikos.nikoleris@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id); 101412349Snikos.nikoleris@arm.com 101512349Snikos.nikoleris@arm.com if (is_timing) { 101612349Snikos.nikoleris@arm.com // anything that is merely forwarded pays for the forward 101712349Snikos.nikoleris@arm.com // latency and the delay provided by the crossbar 101812349Snikos.nikoleris@arm.com Tick forward_time = clockEdge(forwardLatency) + 101912349Snikos.nikoleris@arm.com pkt->headerDelay; 102013948Sodanrc@yahoo.com.br doWritebacks(wb_pkt, forward_time); 102112349Snikos.nikoleris@arm.com } else { 102213948Sodanrc@yahoo.com.br doWritebacksAtomic(wb_pkt); 102312349Snikos.nikoleris@arm.com } 102412349Snikos.nikoleris@arm.com pkt->setSatisfied(); 102512349Snikos.nikoleris@arm.com } 102612349Snikos.nikoleris@arm.com } else if (!blk_valid) { 102711744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: snoop miss for %s\n", __func__, 102811744Snikos.nikoleris@arm.com pkt->print()); 102911493Sandreas.hansson@arm.com if (is_deferred) { 103011493Sandreas.hansson@arm.com // we no longer have the block, and will not respond, but a 103111493Sandreas.hansson@arm.com // packet was allocated in MSHR::handleSnoop and we have 103211493Sandreas.hansson@arm.com // to delete it 103311493Sandreas.hansson@arm.com assert(pkt->needsResponse()); 103411493Sandreas.hansson@arm.com 103511493Sandreas.hansson@arm.com // we have passed the block to a cache upstream, that 103611493Sandreas.hansson@arm.com // cache should be responding 103711493Sandreas.hansson@arm.com assert(pkt->cacheResponding()); 103811493Sandreas.hansson@arm.com 103911493Sandreas.hansson@arm.com delete pkt; 104011493Sandreas.hansson@arm.com } 104111127Sandreas.hansson@arm.com return snoop_delay; 104211051Sandreas.hansson@arm.com } else { 104311744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: snoop hit for %s, old state is %s\n", __func__, 104411744Snikos.nikoleris@arm.com pkt->print(), blk->print()); 104512349Snikos.nikoleris@arm.com 104612349Snikos.nikoleris@arm.com // We may end up modifying both the block state and the packet (if 104712349Snikos.nikoleris@arm.com // we respond in atomic mode), so just figure out what to do now 104812349Snikos.nikoleris@arm.com // and then do it later. We respond to all snoops that need 104912349Snikos.nikoleris@arm.com // responses provided we have the block in dirty state. The 105012349Snikos.nikoleris@arm.com // invalidation itself is taken care of below. We don't respond to 105112349Snikos.nikoleris@arm.com // cache maintenance operations as this is done by the destination 105212349Snikos.nikoleris@arm.com // xbar. 105312349Snikos.nikoleris@arm.com respond = blk->isDirty() && pkt->needsResponse(); 105412349Snikos.nikoleris@arm.com 105512349Snikos.nikoleris@arm.com chatty_assert(!(isReadOnly && blk->isDirty()), "Should never have " 105612349Snikos.nikoleris@arm.com "a dirty block in a read-only cache %s\n", name()); 105711051Sandreas.hansson@arm.com } 105811051Sandreas.hansson@arm.com 105911051Sandreas.hansson@arm.com // Invalidate any prefetch's from below that would strip write permissions 106011051Sandreas.hansson@arm.com // MemCmd::HardPFReq is only observed by upstream caches. After missing 106111051Sandreas.hansson@arm.com // above and in it's own cache, a new MemCmd::ReadReq is created that 106211051Sandreas.hansson@arm.com // downstream caches observe. 106311051Sandreas.hansson@arm.com if (pkt->mustCheckAbove()) { 106411483Snikos.nikoleris@arm.com DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s " 106511744Snikos.nikoleris@arm.com "from lower cache\n", pkt->getAddr(), pkt->print()); 106611051Sandreas.hansson@arm.com pkt->setBlockCached(); 106711127Sandreas.hansson@arm.com return snoop_delay; 106811051Sandreas.hansson@arm.com } 106911051Sandreas.hansson@arm.com 107011285Sandreas.hansson@arm.com if (pkt->isRead() && !invalidate) { 107111285Sandreas.hansson@arm.com // reading without requiring the line in a writable state 107211284Sandreas.hansson@arm.com assert(!needs_writable); 107311284Sandreas.hansson@arm.com pkt->setHasSharers(); 107411285Sandreas.hansson@arm.com 107511285Sandreas.hansson@arm.com // if the requesting packet is uncacheable, retain the line in 107611285Sandreas.hansson@arm.com // the current state, otherwhise unset the writable flag, 107711285Sandreas.hansson@arm.com // which means we go from Modified to Owned (and will respond 107811285Sandreas.hansson@arm.com // below), remain in Owned (and will respond below), from 107911285Sandreas.hansson@arm.com // Exclusive to Shared, or remain in Shared 108011285Sandreas.hansson@arm.com if (!pkt->req->isUncacheable()) 108111285Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 108212349Snikos.nikoleris@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 108311051Sandreas.hansson@arm.com } 108411051Sandreas.hansson@arm.com 108511051Sandreas.hansson@arm.com if (respond) { 108611051Sandreas.hansson@arm.com // prevent anyone else from responding, cache as well as 108711051Sandreas.hansson@arm.com // memory, and also prevent any memory from even seeing the 108811284Sandreas.hansson@arm.com // request 108911284Sandreas.hansson@arm.com pkt->setCacheResponding(); 109012349Snikos.nikoleris@arm.com if (!pkt->isClean() && blk->isWritable()) { 109111284Sandreas.hansson@arm.com // inform the cache hierarchy that this cache had the line 109211284Sandreas.hansson@arm.com // in the Modified state so that we avoid unnecessary 109311284Sandreas.hansson@arm.com // invalidations (see Packet::setResponderHadWritable) 109411284Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 109511284Sandreas.hansson@arm.com 109611081Sandreas.hansson@arm.com // in the case of an uncacheable request there is no point 109711284Sandreas.hansson@arm.com // in setting the responderHadWritable flag, but since the 109811284Sandreas.hansson@arm.com // recipient does not care there is no harm in doing so 109911284Sandreas.hansson@arm.com } else { 110011284Sandreas.hansson@arm.com // if the packet has needsWritable set we invalidate our 110111284Sandreas.hansson@arm.com // copy below and all other copies will be invalidates 110211284Sandreas.hansson@arm.com // through express snoops, and if needsWritable is not set 110311284Sandreas.hansson@arm.com // we already called setHasSharers above 110411051Sandreas.hansson@arm.com } 110511284Sandreas.hansson@arm.com 110611285Sandreas.hansson@arm.com // if we are returning a writable and dirty (Modified) line, 110711285Sandreas.hansson@arm.com // we should be invalidating the line 110811285Sandreas.hansson@arm.com panic_if(!invalidate && !pkt->hasSharers(), 110911744Snikos.nikoleris@arm.com "%s is passing a Modified line through %s, " 111011744Snikos.nikoleris@arm.com "but keeping the block", name(), pkt->print()); 111111285Sandreas.hansson@arm.com 111211051Sandreas.hansson@arm.com if (is_timing) { 111311051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval); 111411051Sandreas.hansson@arm.com } else { 111511051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 111611286Sandreas.hansson@arm.com // packets such as upgrades do not actually have any data 111711286Sandreas.hansson@arm.com // payload 111811286Sandreas.hansson@arm.com if (pkt->hasData()) 111911286Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 112011051Sandreas.hansson@arm.com } 112113945Sodanrc@yahoo.com.br 112213945Sodanrc@yahoo.com.br // When a block is compressed, it must first be decompressed before 112313945Sodanrc@yahoo.com.br // being read, and this increases the snoop delay. 112413945Sodanrc@yahoo.com.br if (compressor && pkt->isRead()) { 112513945Sodanrc@yahoo.com.br snoop_delay += compressor->getDecompressionLatency(blk); 112613945Sodanrc@yahoo.com.br } 112711051Sandreas.hansson@arm.com } 112811051Sandreas.hansson@arm.com 112911602Sandreas.hansson@arm.com if (!respond && is_deferred) { 113011051Sandreas.hansson@arm.com assert(pkt->needsResponse()); 113111051Sandreas.hansson@arm.com delete pkt; 113211051Sandreas.hansson@arm.com } 113311051Sandreas.hansson@arm.com 113411051Sandreas.hansson@arm.com // Do this last in case it deallocates block data or something 113511051Sandreas.hansson@arm.com // like that 113612349Snikos.nikoleris@arm.com if (blk_valid && invalidate) { 113711197Sandreas.hansson@arm.com invalidateBlock(blk); 113812349Snikos.nikoleris@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 113911051Sandreas.hansson@arm.com } 114011051Sandreas.hansson@arm.com 114111127Sandreas.hansson@arm.com return snoop_delay; 114211051Sandreas.hansson@arm.com} 114311051Sandreas.hansson@arm.com 114411051Sandreas.hansson@arm.com 114511051Sandreas.hansson@arm.comvoid 114611051Sandreas.hansson@arm.comCache::recvTimingSnoopReq(PacketPtr pkt) 114711051Sandreas.hansson@arm.com{ 114811744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 114911051Sandreas.hansson@arm.com 115011130Sali.jafri@arm.com // no need to snoop requests that are not in range 115111051Sandreas.hansson@arm.com if (!inRange(pkt->getAddr())) { 115211051Sandreas.hansson@arm.com return; 115311051Sandreas.hansson@arm.com } 115411051Sandreas.hansson@arm.com 115511051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 115611051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 115711051Sandreas.hansson@arm.com 115811892Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 115911051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 116011051Sandreas.hansson@arm.com 116111127Sandreas.hansson@arm.com // Update the latency cost of the snoop so that the crossbar can 116211127Sandreas.hansson@arm.com // account for it. Do not overwrite what other neighbouring caches 116311127Sandreas.hansson@arm.com // have already done, rather take the maximum. The update is 116411127Sandreas.hansson@arm.com // tentative, for cases where we return before an upward snoop 116511127Sandreas.hansson@arm.com // happens below. 116611127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, 116711127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 116811127Sandreas.hansson@arm.com 116911051Sandreas.hansson@arm.com // Inform request(Prefetch, CleanEvict or Writeback) from below of 117011051Sandreas.hansson@arm.com // MSHR hit, set setBlockCached. 117111051Sandreas.hansson@arm.com if (mshr && pkt->mustCheckAbove()) { 117211744Snikos.nikoleris@arm.com DPRINTF(Cache, "Setting block cached for %s from lower cache on " 117311744Snikos.nikoleris@arm.com "mshr hit\n", pkt->print()); 117411051Sandreas.hansson@arm.com pkt->setBlockCached(); 117511051Sandreas.hansson@arm.com return; 117611051Sandreas.hansson@arm.com } 117711051Sandreas.hansson@arm.com 117811051Sandreas.hansson@arm.com // Let the MSHR itself track the snoop and decide whether we want 117911051Sandreas.hansson@arm.com // to go ahead and do the regular cache snoop 118011051Sandreas.hansson@arm.com if (mshr && mshr->handleSnoop(pkt, order++)) { 118111051Sandreas.hansson@arm.com DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)." 118211051Sandreas.hansson@arm.com "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns", 118311051Sandreas.hansson@arm.com mshr->print()); 118411051Sandreas.hansson@arm.com 118511051Sandreas.hansson@arm.com if (mshr->getNumTargets() > numTarget) 118611051Sandreas.hansson@arm.com warn("allocating bonus target for snoop"); //handle later 118711051Sandreas.hansson@arm.com return; 118811051Sandreas.hansson@arm.com } 118911051Sandreas.hansson@arm.com 119011051Sandreas.hansson@arm.com //We also need to check the writeback buffers and handle those 119111375Sandreas.hansson@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(blk_addr, is_secure); 119211375Sandreas.hansson@arm.com if (wb_entry) { 119311051Sandreas.hansson@arm.com DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n", 119411051Sandreas.hansson@arm.com pkt->getAddr(), is_secure ? "s" : "ns"); 119511051Sandreas.hansson@arm.com // Expect to see only Writebacks and/or CleanEvicts here, both of 119611051Sandreas.hansson@arm.com // which should not be generated for uncacheable data. 119711051Sandreas.hansson@arm.com assert(!wb_entry->isUncacheable()); 119811051Sandreas.hansson@arm.com // There should only be a single request responsible for generating 119911051Sandreas.hansson@arm.com // Writebacks/CleanEvicts. 120011051Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 120111051Sandreas.hansson@arm.com PacketPtr wb_pkt = wb_entry->getTarget()->pkt; 120212345Snikos.nikoleris@arm.com assert(wb_pkt->isEviction() || wb_pkt->cmd == MemCmd::WriteClean); 120311051Sandreas.hansson@arm.com 120411199Sandreas.hansson@arm.com if (pkt->isEviction()) { 120511051Sandreas.hansson@arm.com // if the block is found in the write queue, set the BLOCK_CACHED 120611051Sandreas.hansson@arm.com // flag for Writeback/CleanEvict snoop. On return the snoop will 120711051Sandreas.hansson@arm.com // propagate the BLOCK_CACHED flag in Writeback packets and prevent 120811051Sandreas.hansson@arm.com // any CleanEvicts from travelling down the memory hierarchy. 120911051Sandreas.hansson@arm.com pkt->setBlockCached(); 121011744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Squashing %s from lower cache on writequeue " 121111744Snikos.nikoleris@arm.com "hit\n", __func__, pkt->print()); 121211051Sandreas.hansson@arm.com return; 121311051Sandreas.hansson@arm.com } 121411051Sandreas.hansson@arm.com 121511332Sandreas.hansson@arm.com // conceptually writebacks are no different to other blocks in 121611332Sandreas.hansson@arm.com // this cache, so the behaviour is modelled after handleSnoop, 121711332Sandreas.hansson@arm.com // the difference being that instead of querying the block 121811332Sandreas.hansson@arm.com // state to determine if it is dirty and writable, we use the 121911332Sandreas.hansson@arm.com // command and fields of the writeback packet 122011332Sandreas.hansson@arm.com bool respond = wb_pkt->cmd == MemCmd::WritebackDirty && 122111751Snikos.nikoleris@arm.com pkt->needsResponse(); 122211332Sandreas.hansson@arm.com bool have_writable = !wb_pkt->hasSharers(); 122311332Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 122411332Sandreas.hansson@arm.com 122511332Sandreas.hansson@arm.com if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) { 122611332Sandreas.hansson@arm.com assert(!pkt->needsWritable()); 122711332Sandreas.hansson@arm.com pkt->setHasSharers(); 122811332Sandreas.hansson@arm.com wb_pkt->setHasSharers(); 122911332Sandreas.hansson@arm.com } 123011332Sandreas.hansson@arm.com 123111332Sandreas.hansson@arm.com if (respond) { 123211284Sandreas.hansson@arm.com pkt->setCacheResponding(); 123311332Sandreas.hansson@arm.com 123411332Sandreas.hansson@arm.com if (have_writable) { 123511332Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 123611051Sandreas.hansson@arm.com } 123711332Sandreas.hansson@arm.com 123811051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(), 123911051Sandreas.hansson@arm.com false, false); 124011051Sandreas.hansson@arm.com } 124111051Sandreas.hansson@arm.com 124212349Snikos.nikoleris@arm.com if (invalidate && wb_pkt->cmd != MemCmd::WriteClean) { 124311051Sandreas.hansson@arm.com // Invalidation trumps our writeback... discard here 124411051Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 124511375Sandreas.hansson@arm.com markInService(wb_entry); 124611051Sandreas.hansson@arm.com delete wb_pkt; 124711051Sandreas.hansson@arm.com } 124811051Sandreas.hansson@arm.com } 124911051Sandreas.hansson@arm.com 125011051Sandreas.hansson@arm.com // If this was a shared writeback, there may still be 125111051Sandreas.hansson@arm.com // other shared copies above that require invalidation. 125211051Sandreas.hansson@arm.com // We could be more selective and return here if the 125311051Sandreas.hansson@arm.com // request is non-exclusive or if the writeback is 125411051Sandreas.hansson@arm.com // exclusive. 125511127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false); 125611127Sandreas.hansson@arm.com 125711127Sandreas.hansson@arm.com // Override what we did when we first saw the snoop, as we now 125811127Sandreas.hansson@arm.com // also have the cost of the upwards snoops to account for 125911127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay + 126011127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 126111051Sandreas.hansson@arm.com} 126211051Sandreas.hansson@arm.com 126311051Sandreas.hansson@arm.comTick 126411051Sandreas.hansson@arm.comCache::recvAtomicSnoop(PacketPtr pkt) 126511051Sandreas.hansson@arm.com{ 126611130Sali.jafri@arm.com // no need to snoop requests that are not in range. 126711130Sali.jafri@arm.com if (!inRange(pkt->getAddr())) { 126811051Sandreas.hansson@arm.com return 0; 126911051Sandreas.hansson@arm.com } 127011051Sandreas.hansson@arm.com 127111051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 127211127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false); 127311127Sandreas.hansson@arm.com return snoop_delay + lookupLatency * clockPeriod(); 127411051Sandreas.hansson@arm.com} 127511051Sandreas.hansson@arm.com 127611051Sandreas.hansson@arm.combool 127712724Snikos.nikoleris@arm.comCache::isCachedAbove(PacketPtr pkt, bool is_timing) 127811051Sandreas.hansson@arm.com{ 127911051Sandreas.hansson@arm.com if (!forwardSnoops) 128011051Sandreas.hansson@arm.com return false; 128111051Sandreas.hansson@arm.com // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and 128211051Sandreas.hansson@arm.com // Writeback snoops into upper level caches to check for copies of the 128311051Sandreas.hansson@arm.com // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict 128411051Sandreas.hansson@arm.com // packet, the cache can inform the crossbar below of presence or absence 128511051Sandreas.hansson@arm.com // of the block. 128611130Sali.jafri@arm.com if (is_timing) { 128711130Sali.jafri@arm.com Packet snoop_pkt(pkt, true, false); 128811130Sali.jafri@arm.com snoop_pkt.setExpressSnoop(); 128911130Sali.jafri@arm.com // Assert that packet is either Writeback or CleanEvict and not a 129011130Sali.jafri@arm.com // prefetch request because prefetch requests need an MSHR and may 129111130Sali.jafri@arm.com // generate a snoop response. 129212345Snikos.nikoleris@arm.com assert(pkt->isEviction() || pkt->cmd == MemCmd::WriteClean); 129311484Snikos.nikoleris@arm.com snoop_pkt.senderState = nullptr; 129412724Snikos.nikoleris@arm.com cpuSidePort.sendTimingSnoopReq(&snoop_pkt); 129511130Sali.jafri@arm.com // Writeback/CleanEvict snoops do not generate a snoop response. 129611284Sandreas.hansson@arm.com assert(!(snoop_pkt.cacheResponding())); 129711130Sali.jafri@arm.com return snoop_pkt.isBlockCached(); 129811130Sali.jafri@arm.com } else { 129912724Snikos.nikoleris@arm.com cpuSidePort.sendAtomicSnoop(pkt); 130011130Sali.jafri@arm.com return pkt->isBlockCached(); 130111130Sali.jafri@arm.com } 130211051Sandreas.hansson@arm.com} 130311051Sandreas.hansson@arm.com 130411375Sandreas.hansson@arm.combool 130511375Sandreas.hansson@arm.comCache::sendMSHRQueuePacket(MSHR* mshr) 130611375Sandreas.hansson@arm.com{ 130711375Sandreas.hansson@arm.com assert(mshr); 130811375Sandreas.hansson@arm.com 130911051Sandreas.hansson@arm.com // use request from 1st target 131011051Sandreas.hansson@arm.com PacketPtr tgt_pkt = mshr->getTarget()->pkt; 131111375Sandreas.hansson@arm.com 131212724Snikos.nikoleris@arm.com if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) { 131312724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print()); 131411051Sandreas.hansson@arm.com 131511375Sandreas.hansson@arm.com // we should never have hardware prefetches to allocated 131611375Sandreas.hansson@arm.com // blocks 131712724Snikos.nikoleris@arm.com assert(!tags->findBlock(mshr->blkAddr, mshr->isSecure)); 131811375Sandreas.hansson@arm.com 131911051Sandreas.hansson@arm.com // We need to check the caches above us to verify that 132011051Sandreas.hansson@arm.com // they don't have a copy of this block in the dirty state 132111051Sandreas.hansson@arm.com // at the moment. Without this check we could get a stale 132211051Sandreas.hansson@arm.com // copy from memory that might get used in place of the 132311051Sandreas.hansson@arm.com // dirty one. 132411051Sandreas.hansson@arm.com Packet snoop_pkt(tgt_pkt, true, false); 132511051Sandreas.hansson@arm.com snoop_pkt.setExpressSnoop(); 132611275Sandreas.hansson@arm.com // We are sending this packet upwards, but if it hits we will 132711275Sandreas.hansson@arm.com // get a snoop response that we end up treating just like a 132811275Sandreas.hansson@arm.com // normal response, hence it needs the MSHR as its sender 132911275Sandreas.hansson@arm.com // state 133011051Sandreas.hansson@arm.com snoop_pkt.senderState = mshr; 133112724Snikos.nikoleris@arm.com cpuSidePort.sendTimingSnoopReq(&snoop_pkt); 133211051Sandreas.hansson@arm.com 133311051Sandreas.hansson@arm.com // Check to see if the prefetch was squashed by an upper cache (to 133411051Sandreas.hansson@arm.com // prevent us from grabbing the line) or if a Check to see if a 133511051Sandreas.hansson@arm.com // writeback arrived between the time the prefetch was placed in 133611051Sandreas.hansson@arm.com // the MSHRs and when it was selected to be sent or if the 133711051Sandreas.hansson@arm.com // prefetch was squashed by an upper cache. 133811051Sandreas.hansson@arm.com 133911284Sandreas.hansson@arm.com // It is important to check cacheResponding before 134011284Sandreas.hansson@arm.com // prefetchSquashed. If another cache has committed to 134111284Sandreas.hansson@arm.com // responding, it will be sending a dirty response which will 134211284Sandreas.hansson@arm.com // arrive at the MSHR allocated for this request. Checking the 134311284Sandreas.hansson@arm.com // prefetchSquash first may result in the MSHR being 134411284Sandreas.hansson@arm.com // prematurely deallocated. 134511284Sandreas.hansson@arm.com if (snoop_pkt.cacheResponding()) { 134611276Sandreas.hansson@arm.com auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req); 134711276Sandreas.hansson@arm.com assert(r.second); 134811284Sandreas.hansson@arm.com 134911284Sandreas.hansson@arm.com // if we are getting a snoop response with no sharers it 135011284Sandreas.hansson@arm.com // will be allocated as Modified 135111284Sandreas.hansson@arm.com bool pending_modified_resp = !snoop_pkt.hasSharers(); 135211284Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 135311284Sandreas.hansson@arm.com 135411051Sandreas.hansson@arm.com DPRINTF(Cache, "Upward snoop of prefetch for addr" 135511051Sandreas.hansson@arm.com " %#x (%s) hit\n", 135611051Sandreas.hansson@arm.com tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns"); 135711375Sandreas.hansson@arm.com return false; 135811051Sandreas.hansson@arm.com } 135911051Sandreas.hansson@arm.com 136011375Sandreas.hansson@arm.com if (snoop_pkt.isBlockCached()) { 136111051Sandreas.hansson@arm.com DPRINTF(Cache, "Block present, prefetch squashed by cache. " 136211051Sandreas.hansson@arm.com "Deallocating mshr target %#x.\n", 136311051Sandreas.hansson@arm.com mshr->blkAddr); 136411375Sandreas.hansson@arm.com 136511051Sandreas.hansson@arm.com // Deallocate the mshr target 136611375Sandreas.hansson@arm.com if (mshrQueue.forceDeallocateTarget(mshr)) { 136711277Sandreas.hansson@arm.com // Clear block if this deallocation resulted freed an 136811277Sandreas.hansson@arm.com // mshr when all had previously been utilized 136911375Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 137011051Sandreas.hansson@arm.com } 137112167Spau.cabre@metempsy.com 137212167Spau.cabre@metempsy.com // given that no response is expected, delete Request and Packet 137312167Spau.cabre@metempsy.com delete tgt_pkt; 137412167Spau.cabre@metempsy.com 137511375Sandreas.hansson@arm.com return false; 137611051Sandreas.hansson@arm.com } 137711051Sandreas.hansson@arm.com } 137811051Sandreas.hansson@arm.com 137912724Snikos.nikoleris@arm.com return BaseCache::sendMSHRQueuePacket(mshr); 138011051Sandreas.hansson@arm.com} 138111051Sandreas.hansson@arm.com 138211053Sandreas.hansson@arm.comCache* 138311053Sandreas.hansson@arm.comCacheParams::create() 138411053Sandreas.hansson@arm.com{ 138511053Sandreas.hansson@arm.com assert(tags); 138612600Sodanrc@yahoo.com.br assert(replacement_policy); 138711053Sandreas.hansson@arm.com 138811053Sandreas.hansson@arm.com return new Cache(this); 138911053Sandreas.hansson@arm.com} 1390