cache.cc revision 13352
15086Sgblack@eecs.umich.edu/* 25086Sgblack@eecs.umich.edu * Copyright (c) 2010-2018 ARM Limited 38466Snilay@cs.wisc.edu * All rights reserved. 45086Sgblack@eecs.umich.edu * 55086Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67087Snate@binkert.org * not be construed as granting a license to any other intellectual 77087Snate@binkert.org * property including but not limited to intellectual property relating 87087Snate@binkert.org * to a hardware implementation of the functionality of the software 97087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 127087Snate@binkert.org * modified or unmodified, in source code or in binary form. 137087Snate@binkert.org * 145086Sgblack@eecs.umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 157087Snate@binkert.org * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 167087Snate@binkert.org * All rights reserved. 177087Snate@binkert.org * 187087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 197087Snate@binkert.org * modification, are permitted provided that the following conditions are 207087Snate@binkert.org * met: redistributions of source code must retain the above copyright 217087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 227087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 235086Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 247087Snate@binkert.org * documentation and/or other materials provided with the distribution; 255086Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 265086Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 275086Sgblack@eecs.umich.edu * this software without specific prior written permission. 285086Sgblack@eecs.umich.edu * 295086Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 305086Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 315086Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 325086Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 335086Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 345086Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 355086Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 365086Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 375086Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 385086Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 395086Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 405086Sgblack@eecs.umich.edu * 415647Sgblack@eecs.umich.edu * Authors: Erik Hallnor 428466Snilay@cs.wisc.edu * Dave Greene 438466Snilay@cs.wisc.edu * Nathan Binkert 445086Sgblack@eecs.umich.edu * Steve Reinhardt 455135Sgblack@eecs.umich.edu * Ron Dreslinski 465647Sgblack@eecs.umich.edu * Andreas Sandberg 479889Sandreas@sandberg.pp.se * Nikos Nikoleris 485234Sgblack@eecs.umich.edu */ 495086Sgblack@eecs.umich.edu 505086Sgblack@eecs.umich.edu/** 515086Sgblack@eecs.umich.edu * @file 527707Sgblack@eecs.umich.edu * Cache definitions. 537707Sgblack@eecs.umich.edu */ 547707Sgblack@eecs.umich.edu 5510553Salexandru.dutu@amd.com#include "mem/cache/cache.hh" 569887Sandreas@sandberg.pp.se 579887Sandreas@sandberg.pp.se#include <cassert> 589887Sandreas@sandberg.pp.se 599887Sandreas@sandberg.pp.se#include "base/compiler.hh" 609887Sandreas@sandberg.pp.se#include "base/logging.hh" 619887Sandreas@sandberg.pp.se#include "base/trace.hh" 629887Sandreas@sandberg.pp.se#include "base/types.hh" 639887Sandreas@sandberg.pp.se#include "debug/Cache.hh" 649887Sandreas@sandberg.pp.se#include "debug/CacheTags.hh" 659887Sandreas@sandberg.pp.se#include "debug/CacheVerbose.hh" 669887Sandreas@sandberg.pp.se#include "enums/Clusivity.hh" 679887Sandreas@sandberg.pp.se#include "mem/cache/cache_blk.hh" 689887Sandreas@sandberg.pp.se#include "mem/cache/mshr.hh" 699887Sandreas@sandberg.pp.se#include "mem/cache/tags/base.hh" 709887Sandreas@sandberg.pp.se#include "mem/cache/write_queue_entry.hh" 719887Sandreas@sandberg.pp.se#include "mem/request.hh" 725086Sgblack@eecs.umich.edu#include "params/Cache.hh" 735135Sgblack@eecs.umich.edu 745135Sgblack@eecs.umich.eduCache::Cache(const CacheParams *p) 755135Sgblack@eecs.umich.edu : BaseCache(p, p->system->cacheLineSize()), 766048Sgblack@eecs.umich.edu doFastWrites(true) 776048Sgblack@eecs.umich.edu{ 786048Sgblack@eecs.umich.edu} 796048Sgblack@eecs.umich.edu 806048Sgblack@eecs.umich.eduvoid 816048Sgblack@eecs.umich.eduCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, 827720Sgblack@eecs.umich.edu bool deferred_response, bool pending_downgrade) 837720Sgblack@eecs.umich.edu{ 847720Sgblack@eecs.umich.edu BaseCache::satisfyRequest(pkt, blk); 857720Sgblack@eecs.umich.edu 865135Sgblack@eecs.umich.edu if (pkt->isRead()) { 875135Sgblack@eecs.umich.edu // determine if this read is from a (coherent) cache or not 885135Sgblack@eecs.umich.edu if (pkt->fromCache()) { 895135Sgblack@eecs.umich.edu assert(pkt->getSize() == blkSize); 905135Sgblack@eecs.umich.edu // special handling for coherent block requests from 915135Sgblack@eecs.umich.edu // upper-level caches 925135Sgblack@eecs.umich.edu if (pkt->needsWritable()) { 935135Sgblack@eecs.umich.edu // sanity check 945135Sgblack@eecs.umich.edu assert(pkt->cmd == MemCmd::ReadExReq || 955135Sgblack@eecs.umich.edu pkt->cmd == MemCmd::SCUpgradeFailReq); 965135Sgblack@eecs.umich.edu assert(!pkt->hasSharers()); 975135Sgblack@eecs.umich.edu 985135Sgblack@eecs.umich.edu // if we have a dirty copy, make sure the recipient 995135Sgblack@eecs.umich.edu // keeps it marked dirty (in the modified state) 1005135Sgblack@eecs.umich.edu if (blk->isDirty()) { 1015135Sgblack@eecs.umich.edu pkt->setCacheResponding(); 1025135Sgblack@eecs.umich.edu blk->status &= ~BlkDirty; 1035264Sgblack@eecs.umich.edu } 1045135Sgblack@eecs.umich.edu } else if (blk->isWritable() && !pending_downgrade && 1055135Sgblack@eecs.umich.edu !pkt->hasSharers() && 1065135Sgblack@eecs.umich.edu pkt->cmd != MemCmd::ReadCleanReq) { 1075135Sgblack@eecs.umich.edu // we can give the requester a writable copy on a read 1085141Sgblack@eecs.umich.edu // request if: 1095141Sgblack@eecs.umich.edu // - we have a writable copy at this level (& below) 1105141Sgblack@eecs.umich.edu // - we don't have a pending snoop from below 1115141Sgblack@eecs.umich.edu // signaling another read request 1125141Sgblack@eecs.umich.edu // - no other cache above has a copy (otherwise it 1135141Sgblack@eecs.umich.edu // would have set hasSharers flag when 1145141Sgblack@eecs.umich.edu // snooping the packet) 1155141Sgblack@eecs.umich.edu // - the read has explicitly asked for a clean 1165141Sgblack@eecs.umich.edu // copy of the line 1175182Sgblack@eecs.umich.edu if (blk->isDirty()) { 1185141Sgblack@eecs.umich.edu // special considerations if we're owner: 1195141Sgblack@eecs.umich.edu if (!deferred_response) { 1205141Sgblack@eecs.umich.edu // respond with the line in Modified state 1215141Sgblack@eecs.umich.edu // (cacheResponding set, hasSharers not set) 1225141Sgblack@eecs.umich.edu pkt->setCacheResponding(); 1235141Sgblack@eecs.umich.edu 1245135Sgblack@eecs.umich.edu // if this cache is mostly inclusive, we 1255141Sgblack@eecs.umich.edu // keep the block in the Exclusive state, 1265141Sgblack@eecs.umich.edu // and pass it upwards as Modified 1275141Sgblack@eecs.umich.edu // (writable and dirty), hence we have 1285141Sgblack@eecs.umich.edu // multiple caches, all on the same path 1295141Sgblack@eecs.umich.edu // towards memory, all considering the 1305141Sgblack@eecs.umich.edu // same block writable, but only one 1315141Sgblack@eecs.umich.edu // considering it Modified 1325141Sgblack@eecs.umich.edu 1335141Sgblack@eecs.umich.edu // we get away with multiple caches (on 1345141Sgblack@eecs.umich.edu // the same path to memory) considering 1355141Sgblack@eecs.umich.edu // the block writeable as we always enter 1365141Sgblack@eecs.umich.edu // the cache hierarchy through a cache, 1375135Sgblack@eecs.umich.edu // and first snoop upwards in all other 1385141Sgblack@eecs.umich.edu // branches 1395141Sgblack@eecs.umich.edu blk->status &= ~BlkDirty; 1405135Sgblack@eecs.umich.edu } else { 1415141Sgblack@eecs.umich.edu // if we're responding after our own miss, 1425141Sgblack@eecs.umich.edu // there's a window where the recipient didn't 1435141Sgblack@eecs.umich.edu // know it was getting ownership and may not 1445141Sgblack@eecs.umich.edu // have responded to snoops correctly, so we 1455135Sgblack@eecs.umich.edu // have to respond with a shared line 1465141Sgblack@eecs.umich.edu pkt->setHasSharers(); 1475141Sgblack@eecs.umich.edu } 1485141Sgblack@eecs.umich.edu } 1495141Sgblack@eecs.umich.edu } else { 1505141Sgblack@eecs.umich.edu // otherwise only respond with a shared copy 1515141Sgblack@eecs.umich.edu pkt->setHasSharers(); 1525141Sgblack@eecs.umich.edu } 1535141Sgblack@eecs.umich.edu } 1545141Sgblack@eecs.umich.edu } 1555141Sgblack@eecs.umich.edu} 1565141Sgblack@eecs.umich.edu 1575141Sgblack@eecs.umich.edu///////////////////////////////////////////////////// 1585264Sgblack@eecs.umich.edu// 1595141Sgblack@eecs.umich.edu// Access path: requests coming in from the CPU side 1605141Sgblack@eecs.umich.edu// 1615141Sgblack@eecs.umich.edu///////////////////////////////////////////////////// 1625141Sgblack@eecs.umich.edu 1635141Sgblack@eecs.umich.edubool 1645141Sgblack@eecs.umich.eduCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 1655141Sgblack@eecs.umich.edu PacketList &writebacks) 1665141Sgblack@eecs.umich.edu{ 1675141Sgblack@eecs.umich.edu 1685141Sgblack@eecs.umich.edu if (pkt->req->isUncacheable()) { 1695141Sgblack@eecs.umich.edu assert(pkt->isRequest()); 1705141Sgblack@eecs.umich.edu 1715141Sgblack@eecs.umich.edu chatty_assert(!(isReadOnly && pkt->isWrite()), 1725141Sgblack@eecs.umich.edu "Should never see a write in a read-only cache %s\n", 1735141Sgblack@eecs.umich.edu name()); 1745141Sgblack@eecs.umich.edu 1755141Sgblack@eecs.umich.edu DPRINTF(Cache, "%s for %s\n", __func__, pkt->print()); 1765135Sgblack@eecs.umich.edu 1775135Sgblack@eecs.umich.edu // flush and invalidate any existing block 1785135Sgblack@eecs.umich.edu CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure())); 1795360Sgblack@eecs.umich.edu if (old_blk && old_blk->isValid()) { 1805360Sgblack@eecs.umich.edu evictBlock(old_blk, writebacks); 1815360Sgblack@eecs.umich.edu } 1825360Sgblack@eecs.umich.edu 1835360Sgblack@eecs.umich.edu blk = nullptr; 1845360Sgblack@eecs.umich.edu // lookupLatency is the latency in case the request is uncacheable. 1855647Sgblack@eecs.umich.edu lat = lookupLatency; 18611150Smitch.hayenga@arm.com return false; 1875647Sgblack@eecs.umich.edu } 1885360Sgblack@eecs.umich.edu 1895647Sgblack@eecs.umich.edu return BaseCache::access(pkt, blk, lat, writebacks); 1905647Sgblack@eecs.umich.edu} 1915647Sgblack@eecs.umich.edu 1929157Sandreas.hansson@arm.comvoid 1935141Sgblack@eecs.umich.eduCache::doWritebacks(PacketList& writebacks, Tick forward_time) 1945141Sgblack@eecs.umich.edu{ 1955141Sgblack@eecs.umich.edu while (!writebacks.empty()) { 1965141Sgblack@eecs.umich.edu PacketPtr wbPkt = writebacks.front(); 1975141Sgblack@eecs.umich.edu // We use forwardLatency here because we are copying writebacks to 1985141Sgblack@eecs.umich.edu // write buffer. 1995135Sgblack@eecs.umich.edu 2005135Sgblack@eecs.umich.edu // Call isCachedAbove for Writebacks, CleanEvicts and 2015135Sgblack@eecs.umich.edu // WriteCleans to discover if the block is cached above. 2025135Sgblack@eecs.umich.edu if (isCachedAbove(wbPkt)) { 2038768Sgblack@eecs.umich.edu if (wbPkt->cmd == MemCmd::CleanEvict) { 20410407Smitch.hayenga@arm.com // Delete CleanEvict because cached copies exist above. The 2055135Sgblack@eecs.umich.edu // packet destructor will delete the request object because 2065135Sgblack@eecs.umich.edu // this is a non-snoop request packet which does not require a 2075135Sgblack@eecs.umich.edu // response. 2085135Sgblack@eecs.umich.edu delete wbPkt; 20910407Smitch.hayenga@arm.com } else if (wbPkt->cmd == MemCmd::WritebackClean) { 2105135Sgblack@eecs.umich.edu // clean writeback, do not send since the block is 2115135Sgblack@eecs.umich.edu // still cached above 2125135Sgblack@eecs.umich.edu assert(writebackClean); 2136329Sgblack@eecs.umich.edu delete wbPkt; 2146329Sgblack@eecs.umich.edu } else { 2156329Sgblack@eecs.umich.edu assert(wbPkt->cmd == MemCmd::WritebackDirty || 2168466Snilay@cs.wisc.edu wbPkt->cmd == MemCmd::WriteClean); 2178466Snilay@cs.wisc.edu // Set BLOCK_CACHED flag in Writeback and send below, so that 2188466Snilay@cs.wisc.edu // the Writeback does not reset the bit corresponding to this 2196329Sgblack@eecs.umich.edu // address in the snoop filter below. 22011324Ssteve.reinhardt@amd.com wbPkt->setBlockCached(); 2216329Sgblack@eecs.umich.edu allocateWriteBuffer(wbPkt, forward_time); 22211324Ssteve.reinhardt@amd.com } 2236329Sgblack@eecs.umich.edu } else { 2246329Sgblack@eecs.umich.edu // If the block is not cached above, send packet below. Both 2258466Snilay@cs.wisc.edu // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 2269751Sandreas@sandberg.pp.se // reset the bit corresponding to this address in the snoop filter 2279751Sandreas@sandberg.pp.se // below. 2289751Sandreas@sandberg.pp.se allocateWriteBuffer(wbPkt, forward_time); 2299751Sandreas@sandberg.pp.se } 2309423SAndreas.Sandberg@arm.com writebacks.pop_front(); 2319423SAndreas.Sandberg@arm.com } 2326329Sgblack@eecs.umich.edu} 2336329Sgblack@eecs.umich.edu 2346329Sgblack@eecs.umich.eduvoid 2356329Sgblack@eecs.umich.eduCache::doWritebacksAtomic(PacketList& writebacks) 2366329Sgblack@eecs.umich.edu{ 2376329Sgblack@eecs.umich.edu while (!writebacks.empty()) { 2388466Snilay@cs.wisc.edu PacketPtr wbPkt = writebacks.front(); 23910058Sandreas@sandberg.pp.se // Call isCachedAbove for both Writebacks and CleanEvicts. If 2406329Sgblack@eecs.umich.edu // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks 2418466Snilay@cs.wisc.edu // and discard CleanEvicts. 24210058Sandreas@sandberg.pp.se if (isCachedAbove(wbPkt, false)) { 2439921Syasuko.eckert@amd.com if (wbPkt->cmd == MemCmd::WritebackDirty || 2449921Syasuko.eckert@amd.com wbPkt->cmd == MemCmd::WriteClean) { 24510058Sandreas@sandberg.pp.se // Set BLOCK_CACHED flag in Writeback and send below, 2466329Sgblack@eecs.umich.edu // so that the Writeback does not reset the bit 2477720Sgblack@eecs.umich.edu // corresponding to this address in the snoop filter 2486329Sgblack@eecs.umich.edu // below. We can discard CleanEvicts because cached 2496329Sgblack@eecs.umich.edu // copies exist above. Atomic mode isCachedAbove 2507693SAli.Saidi@ARM.com // modifies packet to set BLOCK_CACHED flag 2517693SAli.Saidi@ARM.com memSidePort.sendAtomic(wbPkt); 2527693SAli.Saidi@ARM.com } 2537693SAli.Saidi@ARM.com } else { 2547693SAli.Saidi@ARM.com // If the block is not cached above, send packet below. Both 2557693SAli.Saidi@ARM.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 2569759Sandreas@sandberg.pp.se // reset the bit corresponding to this address in the snoop filter 2579759Sandreas@sandberg.pp.se // below. 2589759Sandreas@sandberg.pp.se memSidePort.sendAtomic(wbPkt); 2599759Sandreas@sandberg.pp.se } 26010057Snikos.nikoleris@gmail.com writebacks.pop_front(); 26110057Snikos.nikoleris@gmail.com // In case of CleanEvicts, the packet destructor will delete the 26210057Snikos.nikoleris@gmail.com // request object because this is a non-snoop request packet which 2639759Sandreas@sandberg.pp.se // does not require a response. 2649759Sandreas@sandberg.pp.se delete wbPkt; 2659759Sandreas@sandberg.pp.se } 2669759Sandreas@sandberg.pp.se} 2679759Sandreas@sandberg.pp.se 2689759Sandreas@sandberg.pp.se 2699759Sandreas@sandberg.pp.sevoid 2709759Sandreas@sandberg.pp.seCache::recvTimingSnoopResp(PacketPtr pkt) 2719759Sandreas@sandberg.pp.se{ 2729759Sandreas@sandberg.pp.se DPRINTF(Cache, "%s for %s\n", __func__, pkt->print()); 2739759Sandreas@sandberg.pp.se 2749759Sandreas@sandberg.pp.se // determine if the response is from a snoop request we created 27510057Snikos.nikoleris@gmail.com // (in which case it should be in the outstandingSnoop), or if we 27610057Snikos.nikoleris@gmail.com // merely forwarded someone else's snoop request 27710057Snikos.nikoleris@gmail.com const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) == 2789759Sandreas@sandberg.pp.se outstandingSnoop.end(); 2799759Sandreas@sandberg.pp.se 28010057Snikos.nikoleris@gmail.com if (!forwardAsSnoop) { 28110057Snikos.nikoleris@gmail.com // the packet came from this cache, so sink it here and do not 2829759Sandreas@sandberg.pp.se // forward it 2839759Sandreas@sandberg.pp.se assert(pkt->cmd == MemCmd::HardPFResp); 2849759Sandreas@sandberg.pp.se 2859759Sandreas@sandberg.pp.se outstandingSnoop.erase(pkt->req); 2869759Sandreas@sandberg.pp.se 2877693SAli.Saidi@ARM.com DPRINTF(Cache, "Got prefetch response from above for addr " 2889880Sandreas@sandberg.pp.se "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 2899880Sandreas@sandberg.pp.se recvTimingResp(pkt); 2909880Sandreas@sandberg.pp.se return; 2919880Sandreas@sandberg.pp.se } 2929880Sandreas@sandberg.pp.se 2939880Sandreas@sandberg.pp.se // forwardLatency is set here because there is a response from an 2949880Sandreas@sandberg.pp.se // upper level cache. 2959880Sandreas@sandberg.pp.se // To pay the delay that occurs if the packet comes from the bus, 2969880Sandreas@sandberg.pp.se // we charge also headerDelay. 2979880Sandreas@sandberg.pp.se Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay; 2989880Sandreas@sandberg.pp.se // Reset the timing of the packet. 2999880Sandreas@sandberg.pp.se pkt->headerDelay = pkt->payloadDelay = 0; 3009880Sandreas@sandberg.pp.se memSidePort.schedTimingSnoopResp(pkt, snoop_resp_time); 3019880Sandreas@sandberg.pp.se} 3029880Sandreas@sandberg.pp.se 3039880Sandreas@sandberg.pp.sevoid 3049880Sandreas@sandberg.pp.seCache::promoteWholeLineWrites(PacketPtr pkt) 3059880Sandreas@sandberg.pp.se{ 3069880Sandreas@sandberg.pp.se // Cache line clearing instructions 3079880Sandreas@sandberg.pp.se if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) && 3089880Sandreas@sandberg.pp.se (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) { 3099880Sandreas@sandberg.pp.se pkt->cmd = MemCmd::WriteLineReq; 3109880Sandreas@sandberg.pp.se DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n"); 3119880Sandreas@sandberg.pp.se } 3129880Sandreas@sandberg.pp.se} 3139880Sandreas@sandberg.pp.se 3149880Sandreas@sandberg.pp.sevoid 3159880Sandreas@sandberg.pp.seCache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time) 3169880Sandreas@sandberg.pp.se{ 3179880Sandreas@sandberg.pp.se // should never be satisfying an uncacheable access as we 3189880Sandreas@sandberg.pp.se // flush and invalidate any existing block as part of the 3199880Sandreas@sandberg.pp.se // lookup 3209880Sandreas@sandberg.pp.se assert(!pkt->req->isUncacheable()); 3219880Sandreas@sandberg.pp.se 3229880Sandreas@sandberg.pp.se BaseCache::handleTimingReqHit(pkt, blk, request_time); 3239880Sandreas@sandberg.pp.se} 3249880Sandreas@sandberg.pp.se 3259880Sandreas@sandberg.pp.sevoid 3269880Sandreas@sandberg.pp.seCache::handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, Tick forward_time, 3279880Sandreas@sandberg.pp.se Tick request_time) 3289880Sandreas@sandberg.pp.se{ 3299880Sandreas@sandberg.pp.se if (pkt->req->isUncacheable()) { 3309880Sandreas@sandberg.pp.se // ignore any existing MSHR if we are dealing with an 3319880Sandreas@sandberg.pp.se // uncacheable request 3329880Sandreas@sandberg.pp.se 3339880Sandreas@sandberg.pp.se // should have flushed and have no valid block 3349765Sandreas@sandberg.pp.se assert(!blk || !blk->isValid()); 3359765Sandreas@sandberg.pp.se 3369765Sandreas@sandberg.pp.se mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++; 3379765Sandreas@sandberg.pp.se 3389765Sandreas@sandberg.pp.se if (pkt->isWrite()) { 3399765Sandreas@sandberg.pp.se allocateWriteBuffer(pkt, forward_time); 3409765Sandreas@sandberg.pp.se } else { 3419765Sandreas@sandberg.pp.se assert(pkt->isRead()); 3429765Sandreas@sandberg.pp.se 3439765Sandreas@sandberg.pp.se // uncacheable accesses always allocate a new MSHR 3449765Sandreas@sandberg.pp.se 3459765Sandreas@sandberg.pp.se // Here we are using forward_time, modelling the latency of 3469765Sandreas@sandberg.pp.se // a miss (outbound) just as forwardLatency, neglecting the 3479765Sandreas@sandberg.pp.se // lookupLatency component. 3489765Sandreas@sandberg.pp.se allocateMissBuffer(pkt, forward_time); 3499765Sandreas@sandberg.pp.se } 3509765Sandreas@sandberg.pp.se 3519765Sandreas@sandberg.pp.se return; 3529765Sandreas@sandberg.pp.se } 3539765Sandreas@sandberg.pp.se 3549889Sandreas@sandberg.pp.se Addr blk_addr = pkt->getBlockAddr(blkSize); 3559889Sandreas@sandberg.pp.se 3569889Sandreas@sandberg.pp.se MSHR *mshr = mshrQueue.findMatch(blk_addr, pkt->isSecure()); 35711709Santhony.gutierrez@amd.com 35811709Santhony.gutierrez@amd.com // Software prefetch handling: 3599889Sandreas@sandberg.pp.se // To keep the core from waiting on data it won't look at 36011709Santhony.gutierrez@amd.com // anyway, send back a response with dummy data. Miss handling 3619889Sandreas@sandberg.pp.se // will continue asynchronously. Unfortunately, the core will 3629889Sandreas@sandberg.pp.se // insist upon freeing original Packet/Request, so we have to 3639889Sandreas@sandberg.pp.se // create a new pair with a different lifecycle. Note that this 3649889Sandreas@sandberg.pp.se // processing happens before any MSHR munging on the behalf of 3659889Sandreas@sandberg.pp.se // this request because this new Request will be the one stored 36611709Santhony.gutierrez@amd.com // into the MSHRs, not the original. 36711709Santhony.gutierrez@amd.com if (pkt->cmd.isSWPrefetch()) { 3689889Sandreas@sandberg.pp.se assert(pkt->needsResponse()); 3699889Sandreas@sandberg.pp.se assert(pkt->req->hasPaddr()); 3707811Ssteve.reinhardt@amd.com assert(!pkt->req->isUncacheable()); 371 372 // There's no reason to add a prefetch as an additional target 373 // to an existing MSHR. If an outstanding request is already 374 // in progress, there is nothing for the prefetch to do. 375 // If this is the case, we don't even create a request at all. 376 PacketPtr pf = nullptr; 377 378 if (!mshr) { 379 // copy the request and create a new SoftPFReq packet 380 RequestPtr req = std::make_shared<Request>(pkt->req->getPaddr(), 381 pkt->req->getSize(), 382 pkt->req->getFlags(), 383 pkt->req->masterId()); 384 pf = new Packet(req, pkt->cmd); 385 pf->allocate(); 386 assert(pf->getAddr() == pkt->getAddr()); 387 assert(pf->getSize() == pkt->getSize()); 388 } 389 390 pkt->makeTimingResponse(); 391 392 // request_time is used here, taking into account lat and the delay 393 // charged if the packet comes from the xbar. 394 cpuSidePort.schedTimingResp(pkt, request_time, true); 395 396 // If an outstanding request is in progress (we found an 397 // MSHR) this is set to null 398 pkt = pf; 399 } 400 401 BaseCache::handleTimingReqMiss(pkt, mshr, blk, forward_time, request_time); 402} 403 404void 405Cache::recvTimingReq(PacketPtr pkt) 406{ 407 DPRINTF(CacheTags, "%s tags:\n%s\n", __func__, tags->print()); 408 409 promoteWholeLineWrites(pkt); 410 411 if (pkt->cacheResponding()) { 412 // a cache above us (but not where the packet came from) is 413 // responding to the request, in other words it has the line 414 // in Modified or Owned state 415 DPRINTF(Cache, "Cache above responding to %s: not responding\n", 416 pkt->print()); 417 418 // if the packet needs the block to be writable, and the cache 419 // that has promised to respond (setting the cache responding 420 // flag) is not providing writable (it is in Owned rather than 421 // the Modified state), we know that there may be other Shared 422 // copies in the system; go out and invalidate them all 423 assert(pkt->needsWritable() && !pkt->responderHadWritable()); 424 425 // an upstream cache that had the line in Owned state 426 // (dirty, but not writable), is responding and thus 427 // transferring the dirty line from one branch of the 428 // cache hierarchy to another 429 430 // send out an express snoop and invalidate all other 431 // copies (snooping a packet that needs writable is the 432 // same as an invalidation), thus turning the Owned line 433 // into a Modified line, note that we don't invalidate the 434 // block in the current cache or any other cache on the 435 // path to memory 436 437 // create a downstream express snoop with cleared packet 438 // flags, there is no need to allocate any data as the 439 // packet is merely used to co-ordinate state transitions 440 Packet *snoop_pkt = new Packet(pkt, true, false); 441 442 // also reset the bus time that the original packet has 443 // not yet paid for 444 snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0; 445 446 // make this an instantaneous express snoop, and let the 447 // other caches in the system know that the another cache 448 // is responding, because we have found the authorative 449 // copy (Modified or Owned) that will supply the right 450 // data 451 snoop_pkt->setExpressSnoop(); 452 snoop_pkt->setCacheResponding(); 453 454 // this express snoop travels towards the memory, and at 455 // every crossbar it is snooped upwards thus reaching 456 // every cache in the system 457 bool M5_VAR_USED success = memSidePort.sendTimingReq(snoop_pkt); 458 // express snoops always succeed 459 assert(success); 460 461 // main memory will delete the snoop packet 462 463 // queue for deletion, as opposed to immediate deletion, as 464 // the sending cache is still relying on the packet 465 pendingDelete.reset(pkt); 466 467 // no need to take any further action in this particular cache 468 // as an upstram cache has already committed to responding, 469 // and we have already sent out any express snoops in the 470 // section above to ensure all other copies in the system are 471 // invalidated 472 return; 473 } 474 475 BaseCache::recvTimingReq(pkt); 476} 477 478PacketPtr 479Cache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 480 bool needsWritable, 481 bool is_whole_line_write) const 482{ 483 // should never see evictions here 484 assert(!cpu_pkt->isEviction()); 485 486 bool blkValid = blk && blk->isValid(); 487 488 if (cpu_pkt->req->isUncacheable() || 489 (!blkValid && cpu_pkt->isUpgrade()) || 490 cpu_pkt->cmd == MemCmd::InvalidateReq || cpu_pkt->isClean()) { 491 // uncacheable requests and upgrades from upper-level caches 492 // that missed completely just go through as is 493 return nullptr; 494 } 495 496 assert(cpu_pkt->needsResponse()); 497 498 MemCmd cmd; 499 // @TODO make useUpgrades a parameter. 500 // Note that ownership protocols require upgrade, otherwise a 501 // write miss on a shared owned block will generate a ReadExcl, 502 // which will clobber the owned copy. 503 const bool useUpgrades = true; 504 assert(cpu_pkt->cmd != MemCmd::WriteLineReq || is_whole_line_write); 505 if (is_whole_line_write) { 506 assert(!blkValid || !blk->isWritable()); 507 // forward as invalidate to all other caches, this gives us 508 // the line in Exclusive state, and invalidates all other 509 // copies 510 cmd = MemCmd::InvalidateReq; 511 } else if (blkValid && useUpgrades) { 512 // only reason to be here is that blk is read only and we need 513 // it to be writable 514 assert(needsWritable); 515 assert(!blk->isWritable()); 516 cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq; 517 } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq || 518 cpu_pkt->cmd == MemCmd::StoreCondFailReq) { 519 // Even though this SC will fail, we still need to send out the 520 // request and get the data to supply it to other snoopers in the case 521 // where the determination the StoreCond fails is delayed due to 522 // all caches not being on the same local bus. 523 cmd = MemCmd::SCUpgradeFailReq; 524 } else { 525 // block is invalid 526 527 // If the request does not need a writable there are two cases 528 // where we need to ensure the response will not fetch the 529 // block in dirty state: 530 // * this cache is read only and it does not perform 531 // writebacks, 532 // * this cache is mostly exclusive and will not fill (since 533 // it does not fill it will have to writeback the dirty data 534 // immediately which generates uneccesary writebacks). 535 bool force_clean_rsp = isReadOnly || clusivity == Enums::mostly_excl; 536 cmd = needsWritable ? MemCmd::ReadExReq : 537 (force_clean_rsp ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq); 538 } 539 PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize); 540 541 // if there are upstream caches that have already marked the 542 // packet as having sharers (not passing writable), pass that info 543 // downstream 544 if (cpu_pkt->hasSharers() && !needsWritable) { 545 // note that cpu_pkt may have spent a considerable time in the 546 // MSHR queue and that the information could possibly be out 547 // of date, however, there is no harm in conservatively 548 // assuming the block has sharers 549 pkt->setHasSharers(); 550 DPRINTF(Cache, "%s: passing hasSharers from %s to %s\n", 551 __func__, cpu_pkt->print(), pkt->print()); 552 } 553 554 // the packet should be block aligned 555 assert(pkt->getAddr() == pkt->getBlockAddr(blkSize)); 556 557 pkt->allocate(); 558 DPRINTF(Cache, "%s: created %s from %s\n", __func__, pkt->print(), 559 cpu_pkt->print()); 560 return pkt; 561} 562 563 564Cycles 565Cache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, 566 PacketList &writebacks) 567{ 568 // deal with the packets that go through the write path of 569 // the cache, i.e. any evictions and writes 570 if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean || 571 (pkt->req->isUncacheable() && pkt->isWrite())) { 572 Cycles latency = ticksToCycles(memSidePort.sendAtomic(pkt)); 573 574 // at this point, if the request was an uncacheable write 575 // request, it has been satisfied by a memory below and the 576 // packet carries the response back 577 assert(!(pkt->req->isUncacheable() && pkt->isWrite()) || 578 pkt->isResponse()); 579 580 return latency; 581 } 582 583 // only misses left 584 585 PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable(), 586 pkt->isWholeLineWrite(blkSize)); 587 588 bool is_forward = (bus_pkt == nullptr); 589 590 if (is_forward) { 591 // just forwarding the same request to the next level 592 // no local cache operation involved 593 bus_pkt = pkt; 594 } 595 596 DPRINTF(Cache, "%s: Sending an atomic %s\n", __func__, 597 bus_pkt->print()); 598 599#if TRACING_ON 600 CacheBlk::State old_state = blk ? blk->status : 0; 601#endif 602 603 Cycles latency = ticksToCycles(memSidePort.sendAtomic(bus_pkt)); 604 605 bool is_invalidate = bus_pkt->isInvalidate(); 606 607 // We are now dealing with the response handling 608 DPRINTF(Cache, "%s: Receive response: %s in state %i\n", __func__, 609 bus_pkt->print(), old_state); 610 611 // If packet was a forward, the response (if any) is already 612 // in place in the bus_pkt == pkt structure, so we don't need 613 // to do anything. Otherwise, use the separate bus_pkt to 614 // generate response to pkt and then delete it. 615 if (!is_forward) { 616 if (pkt->needsResponse()) { 617 assert(bus_pkt->isResponse()); 618 if (bus_pkt->isError()) { 619 pkt->makeAtomicResponse(); 620 pkt->copyError(bus_pkt); 621 } else if (pkt->isWholeLineWrite(blkSize)) { 622 // note the use of pkt, not bus_pkt here. 623 624 // write-line request to the cache that promoted 625 // the write to a whole line 626 const bool allocate = allocOnFill(pkt->cmd) && 627 (!writeAllocator || writeAllocator->allocate()); 628 blk = handleFill(bus_pkt, blk, writebacks, allocate); 629 assert(blk != NULL); 630 is_invalidate = false; 631 satisfyRequest(pkt, blk); 632 } else if (bus_pkt->isRead() || 633 bus_pkt->cmd == MemCmd::UpgradeResp) { 634 // we're updating cache state to allow us to 635 // satisfy the upstream request from the cache 636 blk = handleFill(bus_pkt, blk, writebacks, 637 allocOnFill(pkt->cmd)); 638 satisfyRequest(pkt, blk); 639 maintainClusivity(pkt->fromCache(), blk); 640 } else { 641 // we're satisfying the upstream request without 642 // modifying cache state, e.g., a write-through 643 pkt->makeAtomicResponse(); 644 } 645 } 646 delete bus_pkt; 647 } 648 649 if (is_invalidate && blk && blk->isValid()) { 650 invalidateBlock(blk); 651 } 652 653 return latency; 654} 655 656Tick 657Cache::recvAtomic(PacketPtr pkt) 658{ 659 promoteWholeLineWrites(pkt); 660 661 return BaseCache::recvAtomic(pkt); 662} 663 664 665///////////////////////////////////////////////////// 666// 667// Response handling: responses from the memory side 668// 669///////////////////////////////////////////////////// 670 671 672void 673Cache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk, 674 PacketList &writebacks) 675{ 676 MSHR::Target *initial_tgt = mshr->getTarget(); 677 // First offset for critical word first calculations 678 const int initial_offset = initial_tgt->pkt->getOffset(blkSize); 679 680 const bool is_error = pkt->isError(); 681 // allow invalidation responses originating from write-line 682 // requests to be discarded 683 bool is_invalidate = pkt->isInvalidate() && 684 !mshr->wasWholeLineWrite; 685 686 MSHR::TargetList targets = mshr->extractServiceableTargets(pkt); 687 for (auto &target: targets) { 688 Packet *tgt_pkt = target.pkt; 689 switch (target.source) { 690 case MSHR::Target::FromCPU: 691 Tick completion_time; 692 // Here we charge on completion_time the delay of the xbar if the 693 // packet comes from it, charged on headerDelay. 694 completion_time = pkt->headerDelay; 695 696 // Software prefetch handling for cache closest to core 697 if (tgt_pkt->cmd.isSWPrefetch()) { 698 // a software prefetch would have already been ack'd 699 // immediately with dummy data so the core would be able to 700 // retire it. This request completes right here, so we 701 // deallocate it. 702 delete tgt_pkt; 703 break; // skip response 704 } 705 706 // unlike the other packet flows, where data is found in other 707 // caches or memory and brought back, write-line requests always 708 // have the data right away, so the above check for "is fill?" 709 // cannot actually be determined until examining the stored MSHR 710 // state. We "catch up" with that logic here, which is duplicated 711 // from above. 712 if (tgt_pkt->cmd == MemCmd::WriteLineReq) { 713 assert(!is_error); 714 assert(blk); 715 assert(blk->isWritable()); 716 } 717 718 if (blk && blk->isValid() && !mshr->isForward) { 719 satisfyRequest(tgt_pkt, blk, true, mshr->hasPostDowngrade()); 720 721 // How many bytes past the first request is this one 722 int transfer_offset = 723 tgt_pkt->getOffset(blkSize) - initial_offset; 724 if (transfer_offset < 0) { 725 transfer_offset += blkSize; 726 } 727 728 // If not critical word (offset) return payloadDelay. 729 // responseLatency is the latency of the return path 730 // from lower level caches/memory to an upper level cache or 731 // the core. 732 completion_time += clockEdge(responseLatency) + 733 (transfer_offset ? pkt->payloadDelay : 0); 734 735 assert(!tgt_pkt->req->isUncacheable()); 736 737 assert(tgt_pkt->req->masterId() < system->maxMasters()); 738 missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] += 739 completion_time - target.recvTime; 740 } else if (pkt->cmd == MemCmd::UpgradeFailResp) { 741 // failed StoreCond upgrade 742 assert(tgt_pkt->cmd == MemCmd::StoreCondReq || 743 tgt_pkt->cmd == MemCmd::StoreCondFailReq || 744 tgt_pkt->cmd == MemCmd::SCUpgradeFailReq); 745 // responseLatency is the latency of the return path 746 // from lower level caches/memory to an upper level cache or 747 // the core. 748 completion_time += clockEdge(responseLatency) + 749 pkt->payloadDelay; 750 tgt_pkt->req->setExtraData(0); 751 } else { 752 // We are about to send a response to a cache above 753 // that asked for an invalidation; we need to 754 // invalidate our copy immediately as the most 755 // up-to-date copy of the block will now be in the 756 // cache above. It will also prevent this cache from 757 // responding (if the block was previously dirty) to 758 // snoops as they should snoop the caches above where 759 // they will get the response from. 760 if (is_invalidate && blk && blk->isValid()) { 761 invalidateBlock(blk); 762 } 763 // not a cache fill, just forwarding response 764 // responseLatency is the latency of the return path 765 // from lower level cahces/memory to the core. 766 completion_time += clockEdge(responseLatency) + 767 pkt->payloadDelay; 768 if (pkt->isRead() && !is_error) { 769 // sanity check 770 assert(pkt->getAddr() == tgt_pkt->getAddr()); 771 assert(pkt->getSize() >= tgt_pkt->getSize()); 772 773 tgt_pkt->setData(pkt->getConstPtr<uint8_t>()); 774 } 775 } 776 tgt_pkt->makeTimingResponse(); 777 // if this packet is an error copy that to the new packet 778 if (is_error) 779 tgt_pkt->copyError(pkt); 780 if (tgt_pkt->cmd == MemCmd::ReadResp && 781 (is_invalidate || mshr->hasPostInvalidate())) { 782 // If intermediate cache got ReadRespWithInvalidate, 783 // propagate that. Response should not have 784 // isInvalidate() set otherwise. 785 tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate; 786 DPRINTF(Cache, "%s: updated cmd to %s\n", __func__, 787 tgt_pkt->print()); 788 } 789 // Reset the bus additional time as it is now accounted for 790 tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; 791 cpuSidePort.schedTimingResp(tgt_pkt, completion_time, true); 792 break; 793 794 case MSHR::Target::FromPrefetcher: 795 assert(tgt_pkt->cmd == MemCmd::HardPFReq); 796 if (blk) 797 blk->status |= BlkHWPrefetched; 798 delete tgt_pkt; 799 break; 800 801 case MSHR::Target::FromSnoop: 802 // I don't believe that a snoop can be in an error state 803 assert(!is_error); 804 // response to snoop request 805 DPRINTF(Cache, "processing deferred snoop...\n"); 806 // If the response is invalidating, a snooping target can 807 // be satisfied if it is also invalidating. If the reponse is, not 808 // only invalidating, but more specifically an InvalidateResp and 809 // the MSHR was created due to an InvalidateReq then a cache above 810 // is waiting to satisfy a WriteLineReq. In this case even an 811 // non-invalidating snoop is added as a target here since this is 812 // the ordering point. When the InvalidateResp reaches this cache, 813 // the snooping target will snoop further the cache above with the 814 // WriteLineReq. 815 assert(!is_invalidate || pkt->cmd == MemCmd::InvalidateResp || 816 pkt->req->isCacheMaintenance() || 817 mshr->hasPostInvalidate()); 818 handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate()); 819 break; 820 821 default: 822 panic("Illegal target->source enum %d\n", target.source); 823 } 824 } 825 826 maintainClusivity(targets.hasFromCache, blk); 827 828 if (blk && blk->isValid()) { 829 // an invalidate response stemming from a write line request 830 // should not invalidate the block, so check if the 831 // invalidation should be discarded 832 if (is_invalidate || mshr->hasPostInvalidate()) { 833 invalidateBlock(blk); 834 } else if (mshr->hasPostDowngrade()) { 835 blk->status &= ~BlkWritable; 836 } 837 } 838} 839 840PacketPtr 841Cache::evictBlock(CacheBlk *blk) 842{ 843 PacketPtr pkt = (blk->isDirty() || writebackClean) ? 844 writebackBlk(blk) : cleanEvictBlk(blk); 845 846 invalidateBlock(blk); 847 848 return pkt; 849} 850 851void 852Cache::evictBlock(CacheBlk *blk, PacketList &writebacks) 853{ 854 PacketPtr pkt = evictBlock(blk); 855 if (pkt) { 856 writebacks.push_back(pkt); 857 } 858} 859 860PacketPtr 861Cache::cleanEvictBlk(CacheBlk *blk) 862{ 863 assert(!writebackClean); 864 assert(blk && blk->isValid() && !blk->isDirty()); 865 866 // Creating a zero sized write, a message to the snoop filter 867 RequestPtr req = std::make_shared<Request>( 868 regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId); 869 870 if (blk->isSecure()) 871 req->setFlags(Request::SECURE); 872 873 req->taskId(blk->task_id); 874 875 PacketPtr pkt = new Packet(req, MemCmd::CleanEvict); 876 pkt->allocate(); 877 DPRINTF(Cache, "Create CleanEvict %s\n", pkt->print()); 878 879 return pkt; 880} 881 882///////////////////////////////////////////////////// 883// 884// Snoop path: requests coming in from the memory side 885// 886///////////////////////////////////////////////////// 887 888void 889Cache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 890 bool already_copied, bool pending_inval) 891{ 892 // sanity check 893 assert(req_pkt->isRequest()); 894 assert(req_pkt->needsResponse()); 895 896 DPRINTF(Cache, "%s: for %s\n", __func__, req_pkt->print()); 897 // timing-mode snoop responses require a new packet, unless we 898 // already made a copy... 899 PacketPtr pkt = req_pkt; 900 if (!already_copied) 901 // do not clear flags, and allocate space for data if the 902 // packet needs it (the only packets that carry data are read 903 // responses) 904 pkt = new Packet(req_pkt, false, req_pkt->isRead()); 905 906 assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() || 907 pkt->hasSharers()); 908 pkt->makeTimingResponse(); 909 if (pkt->isRead()) { 910 pkt->setDataFromBlock(blk_data, blkSize); 911 } 912 if (pkt->cmd == MemCmd::ReadResp && pending_inval) { 913 // Assume we defer a response to a read from a far-away cache 914 // A, then later defer a ReadExcl from a cache B on the same 915 // bus as us. We'll assert cacheResponding in both cases, but 916 // in the latter case cacheResponding will keep the 917 // invalidation from reaching cache A. This special response 918 // tells cache A that it gets the block to satisfy its read, 919 // but must immediately invalidate it. 920 pkt->cmd = MemCmd::ReadRespWithInvalidate; 921 } 922 // Here we consider forward_time, paying for just forward latency and 923 // also charging the delay provided by the xbar. 924 // forward_time is used as send_time in next allocateWriteBuffer(). 925 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 926 // Here we reset the timing of the packet. 927 pkt->headerDelay = pkt->payloadDelay = 0; 928 DPRINTF(CacheVerbose, "%s: created response: %s tick: %lu\n", __func__, 929 pkt->print(), forward_time); 930 memSidePort.schedTimingSnoopResp(pkt, forward_time, true); 931} 932 933uint32_t 934Cache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, 935 bool is_deferred, bool pending_inval) 936{ 937 DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 938 // deferred snoops can only happen in timing mode 939 assert(!(is_deferred && !is_timing)); 940 // pending_inval only makes sense on deferred snoops 941 assert(!(pending_inval && !is_deferred)); 942 assert(pkt->isRequest()); 943 944 // the packet may get modified if we or a forwarded snooper 945 // responds in atomic mode, so remember a few things about the 946 // original packet up front 947 bool invalidate = pkt->isInvalidate(); 948 bool M5_VAR_USED needs_writable = pkt->needsWritable(); 949 950 // at the moment we could get an uncacheable write which does not 951 // have the invalidate flag, and we need a suitable way of dealing 952 // with this case 953 panic_if(invalidate && pkt->req->isUncacheable(), 954 "%s got an invalidating uncacheable snoop request %s", 955 name(), pkt->print()); 956 957 uint32_t snoop_delay = 0; 958 959 if (forwardSnoops) { 960 // first propagate snoop upward to see if anyone above us wants to 961 // handle it. save & restore packet src since it will get 962 // rewritten to be relative to cpu-side bus (if any) 963 bool alreadyResponded = pkt->cacheResponding(); 964 if (is_timing) { 965 // copy the packet so that we can clear any flags before 966 // forwarding it upwards, we also allocate data (passing 967 // the pointer along in case of static data), in case 968 // there is a snoop hit in upper levels 969 Packet snoopPkt(pkt, true, true); 970 snoopPkt.setExpressSnoop(); 971 // the snoop packet does not need to wait any additional 972 // time 973 snoopPkt.headerDelay = snoopPkt.payloadDelay = 0; 974 cpuSidePort.sendTimingSnoopReq(&snoopPkt); 975 976 // add the header delay (including crossbar and snoop 977 // delays) of the upward snoop to the snoop delay for this 978 // cache 979 snoop_delay += snoopPkt.headerDelay; 980 981 if (snoopPkt.cacheResponding()) { 982 // cache-to-cache response from some upper cache 983 assert(!alreadyResponded); 984 pkt->setCacheResponding(); 985 } 986 // upstream cache has the block, or has an outstanding 987 // MSHR, pass the flag on 988 if (snoopPkt.hasSharers()) { 989 pkt->setHasSharers(); 990 } 991 // If this request is a prefetch or clean evict and an upper level 992 // signals block present, make sure to propagate the block 993 // presence to the requester. 994 if (snoopPkt.isBlockCached()) { 995 pkt->setBlockCached(); 996 } 997 // If the request was satisfied by snooping the cache 998 // above, mark the original packet as satisfied too. 999 if (snoopPkt.satisfied()) { 1000 pkt->setSatisfied(); 1001 } 1002 } else { 1003 cpuSidePort.sendAtomicSnoop(pkt); 1004 if (!alreadyResponded && pkt->cacheResponding()) { 1005 // cache-to-cache response from some upper cache: 1006 // forward response to original requester 1007 assert(pkt->isResponse()); 1008 } 1009 } 1010 } 1011 1012 bool respond = false; 1013 bool blk_valid = blk && blk->isValid(); 1014 if (pkt->isClean()) { 1015 if (blk_valid && blk->isDirty()) { 1016 DPRINTF(CacheVerbose, "%s: packet (snoop) %s found block: %s\n", 1017 __func__, pkt->print(), blk->print()); 1018 PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id); 1019 PacketList writebacks; 1020 writebacks.push_back(wb_pkt); 1021 1022 if (is_timing) { 1023 // anything that is merely forwarded pays for the forward 1024 // latency and the delay provided by the crossbar 1025 Tick forward_time = clockEdge(forwardLatency) + 1026 pkt->headerDelay; 1027 doWritebacks(writebacks, forward_time); 1028 } else { 1029 doWritebacksAtomic(writebacks); 1030 } 1031 pkt->setSatisfied(); 1032 } 1033 } else if (!blk_valid) { 1034 DPRINTF(CacheVerbose, "%s: snoop miss for %s\n", __func__, 1035 pkt->print()); 1036 if (is_deferred) { 1037 // we no longer have the block, and will not respond, but a 1038 // packet was allocated in MSHR::handleSnoop and we have 1039 // to delete it 1040 assert(pkt->needsResponse()); 1041 1042 // we have passed the block to a cache upstream, that 1043 // cache should be responding 1044 assert(pkt->cacheResponding()); 1045 1046 delete pkt; 1047 } 1048 return snoop_delay; 1049 } else { 1050 DPRINTF(Cache, "%s: snoop hit for %s, old state is %s\n", __func__, 1051 pkt->print(), blk->print()); 1052 1053 // We may end up modifying both the block state and the packet (if 1054 // we respond in atomic mode), so just figure out what to do now 1055 // and then do it later. We respond to all snoops that need 1056 // responses provided we have the block in dirty state. The 1057 // invalidation itself is taken care of below. We don't respond to 1058 // cache maintenance operations as this is done by the destination 1059 // xbar. 1060 respond = blk->isDirty() && pkt->needsResponse(); 1061 1062 chatty_assert(!(isReadOnly && blk->isDirty()), "Should never have " 1063 "a dirty block in a read-only cache %s\n", name()); 1064 } 1065 1066 // Invalidate any prefetch's from below that would strip write permissions 1067 // MemCmd::HardPFReq is only observed by upstream caches. After missing 1068 // above and in it's own cache, a new MemCmd::ReadReq is created that 1069 // downstream caches observe. 1070 if (pkt->mustCheckAbove()) { 1071 DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s " 1072 "from lower cache\n", pkt->getAddr(), pkt->print()); 1073 pkt->setBlockCached(); 1074 return snoop_delay; 1075 } 1076 1077 if (pkt->isRead() && !invalidate) { 1078 // reading without requiring the line in a writable state 1079 assert(!needs_writable); 1080 pkt->setHasSharers(); 1081 1082 // if the requesting packet is uncacheable, retain the line in 1083 // the current state, otherwhise unset the writable flag, 1084 // which means we go from Modified to Owned (and will respond 1085 // below), remain in Owned (and will respond below), from 1086 // Exclusive to Shared, or remain in Shared 1087 if (!pkt->req->isUncacheable()) 1088 blk->status &= ~BlkWritable; 1089 DPRINTF(Cache, "new state is %s\n", blk->print()); 1090 } 1091 1092 if (respond) { 1093 // prevent anyone else from responding, cache as well as 1094 // memory, and also prevent any memory from even seeing the 1095 // request 1096 pkt->setCacheResponding(); 1097 if (!pkt->isClean() && blk->isWritable()) { 1098 // inform the cache hierarchy that this cache had the line 1099 // in the Modified state so that we avoid unnecessary 1100 // invalidations (see Packet::setResponderHadWritable) 1101 pkt->setResponderHadWritable(); 1102 1103 // in the case of an uncacheable request there is no point 1104 // in setting the responderHadWritable flag, but since the 1105 // recipient does not care there is no harm in doing so 1106 } else { 1107 // if the packet has needsWritable set we invalidate our 1108 // copy below and all other copies will be invalidates 1109 // through express snoops, and if needsWritable is not set 1110 // we already called setHasSharers above 1111 } 1112 1113 // if we are returning a writable and dirty (Modified) line, 1114 // we should be invalidating the line 1115 panic_if(!invalidate && !pkt->hasSharers(), 1116 "%s is passing a Modified line through %s, " 1117 "but keeping the block", name(), pkt->print()); 1118 1119 if (is_timing) { 1120 doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval); 1121 } else { 1122 pkt->makeAtomicResponse(); 1123 // packets such as upgrades do not actually have any data 1124 // payload 1125 if (pkt->hasData()) 1126 pkt->setDataFromBlock(blk->data, blkSize); 1127 } 1128 } 1129 1130 if (!respond && is_deferred) { 1131 assert(pkt->needsResponse()); 1132 delete pkt; 1133 } 1134 1135 // Do this last in case it deallocates block data or something 1136 // like that 1137 if (blk_valid && invalidate) { 1138 invalidateBlock(blk); 1139 DPRINTF(Cache, "new state is %s\n", blk->print()); 1140 } 1141 1142 return snoop_delay; 1143} 1144 1145 1146void 1147Cache::recvTimingSnoopReq(PacketPtr pkt) 1148{ 1149 DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 1150 1151 // no need to snoop requests that are not in range 1152 if (!inRange(pkt->getAddr())) { 1153 return; 1154 } 1155 1156 bool is_secure = pkt->isSecure(); 1157 CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 1158 1159 Addr blk_addr = pkt->getBlockAddr(blkSize); 1160 MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 1161 1162 // Update the latency cost of the snoop so that the crossbar can 1163 // account for it. Do not overwrite what other neighbouring caches 1164 // have already done, rather take the maximum. The update is 1165 // tentative, for cases where we return before an upward snoop 1166 // happens below. 1167 pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, 1168 lookupLatency * clockPeriod()); 1169 1170 // Inform request(Prefetch, CleanEvict or Writeback) from below of 1171 // MSHR hit, set setBlockCached. 1172 if (mshr && pkt->mustCheckAbove()) { 1173 DPRINTF(Cache, "Setting block cached for %s from lower cache on " 1174 "mshr hit\n", pkt->print()); 1175 pkt->setBlockCached(); 1176 return; 1177 } 1178 1179 // Bypass any existing cache maintenance requests if the request 1180 // has been satisfied already (i.e., the dirty block has been 1181 // found). 1182 if (mshr && pkt->req->isCacheMaintenance() && pkt->satisfied()) { 1183 return; 1184 } 1185 1186 // Let the MSHR itself track the snoop and decide whether we want 1187 // to go ahead and do the regular cache snoop 1188 if (mshr && mshr->handleSnoop(pkt, order++)) { 1189 DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)." 1190 "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns", 1191 mshr->print()); 1192 1193 if (mshr->getNumTargets() > numTarget) 1194 warn("allocating bonus target for snoop"); //handle later 1195 return; 1196 } 1197 1198 //We also need to check the writeback buffers and handle those 1199 WriteQueueEntry *wb_entry = writeBuffer.findMatch(blk_addr, is_secure); 1200 if (wb_entry) { 1201 DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n", 1202 pkt->getAddr(), is_secure ? "s" : "ns"); 1203 // Expect to see only Writebacks and/or CleanEvicts here, both of 1204 // which should not be generated for uncacheable data. 1205 assert(!wb_entry->isUncacheable()); 1206 // There should only be a single request responsible for generating 1207 // Writebacks/CleanEvicts. 1208 assert(wb_entry->getNumTargets() == 1); 1209 PacketPtr wb_pkt = wb_entry->getTarget()->pkt; 1210 assert(wb_pkt->isEviction() || wb_pkt->cmd == MemCmd::WriteClean); 1211 1212 if (pkt->isEviction()) { 1213 // if the block is found in the write queue, set the BLOCK_CACHED 1214 // flag for Writeback/CleanEvict snoop. On return the snoop will 1215 // propagate the BLOCK_CACHED flag in Writeback packets and prevent 1216 // any CleanEvicts from travelling down the memory hierarchy. 1217 pkt->setBlockCached(); 1218 DPRINTF(Cache, "%s: Squashing %s from lower cache on writequeue " 1219 "hit\n", __func__, pkt->print()); 1220 return; 1221 } 1222 1223 // conceptually writebacks are no different to other blocks in 1224 // this cache, so the behaviour is modelled after handleSnoop, 1225 // the difference being that instead of querying the block 1226 // state to determine if it is dirty and writable, we use the 1227 // command and fields of the writeback packet 1228 bool respond = wb_pkt->cmd == MemCmd::WritebackDirty && 1229 pkt->needsResponse(); 1230 bool have_writable = !wb_pkt->hasSharers(); 1231 bool invalidate = pkt->isInvalidate(); 1232 1233 if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) { 1234 assert(!pkt->needsWritable()); 1235 pkt->setHasSharers(); 1236 wb_pkt->setHasSharers(); 1237 } 1238 1239 if (respond) { 1240 pkt->setCacheResponding(); 1241 1242 if (have_writable) { 1243 pkt->setResponderHadWritable(); 1244 } 1245 1246 doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(), 1247 false, false); 1248 } 1249 1250 if (invalidate && wb_pkt->cmd != MemCmd::WriteClean) { 1251 // Invalidation trumps our writeback... discard here 1252 // Note: markInService will remove entry from writeback buffer. 1253 markInService(wb_entry); 1254 delete wb_pkt; 1255 } 1256 } 1257 1258 // If this was a shared writeback, there may still be 1259 // other shared copies above that require invalidation. 1260 // We could be more selective and return here if the 1261 // request is non-exclusive or if the writeback is 1262 // exclusive. 1263 uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false); 1264 1265 // Override what we did when we first saw the snoop, as we now 1266 // also have the cost of the upwards snoops to account for 1267 pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay + 1268 lookupLatency * clockPeriod()); 1269} 1270 1271Tick 1272Cache::recvAtomicSnoop(PacketPtr pkt) 1273{ 1274 // no need to snoop requests that are not in range. 1275 if (!inRange(pkt->getAddr())) { 1276 return 0; 1277 } 1278 1279 CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 1280 uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false); 1281 return snoop_delay + lookupLatency * clockPeriod(); 1282} 1283 1284bool 1285Cache::isCachedAbove(PacketPtr pkt, bool is_timing) 1286{ 1287 if (!forwardSnoops) 1288 return false; 1289 // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and 1290 // Writeback snoops into upper level caches to check for copies of the 1291 // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict 1292 // packet, the cache can inform the crossbar below of presence or absence 1293 // of the block. 1294 if (is_timing) { 1295 Packet snoop_pkt(pkt, true, false); 1296 snoop_pkt.setExpressSnoop(); 1297 // Assert that packet is either Writeback or CleanEvict and not a 1298 // prefetch request because prefetch requests need an MSHR and may 1299 // generate a snoop response. 1300 assert(pkt->isEviction() || pkt->cmd == MemCmd::WriteClean); 1301 snoop_pkt.senderState = nullptr; 1302 cpuSidePort.sendTimingSnoopReq(&snoop_pkt); 1303 // Writeback/CleanEvict snoops do not generate a snoop response. 1304 assert(!(snoop_pkt.cacheResponding())); 1305 return snoop_pkt.isBlockCached(); 1306 } else { 1307 cpuSidePort.sendAtomicSnoop(pkt); 1308 return pkt->isBlockCached(); 1309 } 1310} 1311 1312bool 1313Cache::sendMSHRQueuePacket(MSHR* mshr) 1314{ 1315 assert(mshr); 1316 1317 // use request from 1st target 1318 PacketPtr tgt_pkt = mshr->getTarget()->pkt; 1319 1320 if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) { 1321 DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print()); 1322 1323 // we should never have hardware prefetches to allocated 1324 // blocks 1325 assert(!tags->findBlock(mshr->blkAddr, mshr->isSecure)); 1326 1327 // We need to check the caches above us to verify that 1328 // they don't have a copy of this block in the dirty state 1329 // at the moment. Without this check we could get a stale 1330 // copy from memory that might get used in place of the 1331 // dirty one. 1332 Packet snoop_pkt(tgt_pkt, true, false); 1333 snoop_pkt.setExpressSnoop(); 1334 // We are sending this packet upwards, but if it hits we will 1335 // get a snoop response that we end up treating just like a 1336 // normal response, hence it needs the MSHR as its sender 1337 // state 1338 snoop_pkt.senderState = mshr; 1339 cpuSidePort.sendTimingSnoopReq(&snoop_pkt); 1340 1341 // Check to see if the prefetch was squashed by an upper cache (to 1342 // prevent us from grabbing the line) or if a Check to see if a 1343 // writeback arrived between the time the prefetch was placed in 1344 // the MSHRs and when it was selected to be sent or if the 1345 // prefetch was squashed by an upper cache. 1346 1347 // It is important to check cacheResponding before 1348 // prefetchSquashed. If another cache has committed to 1349 // responding, it will be sending a dirty response which will 1350 // arrive at the MSHR allocated for this request. Checking the 1351 // prefetchSquash first may result in the MSHR being 1352 // prematurely deallocated. 1353 if (snoop_pkt.cacheResponding()) { 1354 auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req); 1355 assert(r.second); 1356 1357 // if we are getting a snoop response with no sharers it 1358 // will be allocated as Modified 1359 bool pending_modified_resp = !snoop_pkt.hasSharers(); 1360 markInService(mshr, pending_modified_resp); 1361 1362 DPRINTF(Cache, "Upward snoop of prefetch for addr" 1363 " %#x (%s) hit\n", 1364 tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns"); 1365 return false; 1366 } 1367 1368 if (snoop_pkt.isBlockCached()) { 1369 DPRINTF(Cache, "Block present, prefetch squashed by cache. " 1370 "Deallocating mshr target %#x.\n", 1371 mshr->blkAddr); 1372 1373 // Deallocate the mshr target 1374 if (mshrQueue.forceDeallocateTarget(mshr)) { 1375 // Clear block if this deallocation resulted freed an 1376 // mshr when all had previously been utilized 1377 clearBlocked(Blocked_NoMSHRs); 1378 } 1379 1380 // given that no response is expected, delete Request and Packet 1381 delete tgt_pkt; 1382 1383 return false; 1384 } 1385 } 1386 1387 return BaseCache::sendMSHRQueuePacket(mshr); 1388} 1389 1390Cache* 1391CacheParams::create() 1392{ 1393 assert(tags); 1394 assert(replacement_policy); 1395 1396 return new Cache(this); 1397} 1398