cache.cc revision 12721
12810Srdreslin@umich.edu/* 212500Snikos.nikoleris@arm.com * Copyright (c) 2010-2018 ARM Limited 311051Sandreas.hansson@arm.com * All rights reserved. 411051Sandreas.hansson@arm.com * 511051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911051Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311051Sandreas.hansson@arm.com * 1411051Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511051Sandreas.hansson@arm.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 162810Srdreslin@umich.edu * All rights reserved. 172810Srdreslin@umich.edu * 182810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 192810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 202810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 212810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 222810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 232810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 242810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 252810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 262810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 272810Srdreslin@umich.edu * this software without specific prior written permission. 282810Srdreslin@umich.edu * 292810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810Srdreslin@umich.edu * 412810Srdreslin@umich.edu * Authors: Erik Hallnor 4211051Sandreas.hansson@arm.com * Dave Greene 4311051Sandreas.hansson@arm.com * Nathan Binkert 442810Srdreslin@umich.edu * Steve Reinhardt 4511051Sandreas.hansson@arm.com * Ron Dreslinski 4611051Sandreas.hansson@arm.com * Andreas Sandberg 4712349Snikos.nikoleris@arm.com * Nikos Nikoleris 482810Srdreslin@umich.edu */ 492810Srdreslin@umich.edu 502810Srdreslin@umich.edu/** 512810Srdreslin@umich.edu * @file 5211051Sandreas.hansson@arm.com * Cache definitions. 532810Srdreslin@umich.edu */ 542810Srdreslin@umich.edu 5511051Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 562810Srdreslin@umich.edu 5712334Sgabeblack@google.com#include "base/logging.hh" 5811051Sandreas.hansson@arm.com#include "base/types.hh" 5911051Sandreas.hansson@arm.com#include "debug/Cache.hh" 6011051Sandreas.hansson@arm.com#include "debug/CachePort.hh" 6111051Sandreas.hansson@arm.com#include "debug/CacheTags.hh" 6211288Ssteve.reinhardt@amd.com#include "debug/CacheVerbose.hh" 6311051Sandreas.hansson@arm.com#include "mem/cache/blk.hh" 6411051Sandreas.hansson@arm.com#include "mem/cache/mshr.hh" 6511051Sandreas.hansson@arm.com#include "mem/cache/prefetch/base.hh" 6611051Sandreas.hansson@arm.com#include "sim/sim_exit.hh" 6711051Sandreas.hansson@arm.com 6811053Sandreas.hansson@arm.comCache::Cache(const CacheParams *p) 6911053Sandreas.hansson@arm.com : BaseCache(p, p->system->cacheLineSize()), 7011051Sandreas.hansson@arm.com tags(p->tags), 7111051Sandreas.hansson@arm.com prefetcher(p->prefetcher), 7211051Sandreas.hansson@arm.com doFastWrites(true), 7311197Sandreas.hansson@arm.com prefetchOnAccess(p->prefetch_on_access), 7411197Sandreas.hansson@arm.com clusivity(p->clusivity), 7511199Sandreas.hansson@arm.com writebackClean(p->writeback_clean), 7611197Sandreas.hansson@arm.com tempBlockWriteback(nullptr), 7712084Sspwilson2@wisc.edu writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); }, 7812084Sspwilson2@wisc.edu name(), false, 7911197Sandreas.hansson@arm.com EventBase::Delayed_Writeback_Pri) 8011051Sandreas.hansson@arm.com{ 8111051Sandreas.hansson@arm.com tempBlock = new CacheBlk(); 8211051Sandreas.hansson@arm.com tempBlock->data = new uint8_t[blkSize]; 8311051Sandreas.hansson@arm.com 8411051Sandreas.hansson@arm.com cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this, 8511051Sandreas.hansson@arm.com "CpuSidePort"); 8611051Sandreas.hansson@arm.com memSidePort = new MemSidePort(p->name + ".mem_side", this, 8711051Sandreas.hansson@arm.com "MemSidePort"); 8811051Sandreas.hansson@arm.com 8911051Sandreas.hansson@arm.com tags->setCache(this); 9011051Sandreas.hansson@arm.com if (prefetcher) 9111051Sandreas.hansson@arm.com prefetcher->setCache(this); 9211051Sandreas.hansson@arm.com} 9311051Sandreas.hansson@arm.com 9411051Sandreas.hansson@arm.comCache::~Cache() 9511051Sandreas.hansson@arm.com{ 9611051Sandreas.hansson@arm.com delete [] tempBlock->data; 9711051Sandreas.hansson@arm.com delete tempBlock; 9811051Sandreas.hansson@arm.com 9911051Sandreas.hansson@arm.com delete cpuSidePort; 10011051Sandreas.hansson@arm.com delete memSidePort; 10111051Sandreas.hansson@arm.com} 10211051Sandreas.hansson@arm.com 10311051Sandreas.hansson@arm.comvoid 10411051Sandreas.hansson@arm.comCache::regStats() 10511051Sandreas.hansson@arm.com{ 10611051Sandreas.hansson@arm.com BaseCache::regStats(); 10711051Sandreas.hansson@arm.com} 10811051Sandreas.hansson@arm.com 10911051Sandreas.hansson@arm.comvoid 11011051Sandreas.hansson@arm.comCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 11111051Sandreas.hansson@arm.com{ 11211051Sandreas.hansson@arm.com assert(pkt->isRequest()); 11311051Sandreas.hansson@arm.com 11411051Sandreas.hansson@arm.com uint64_t overwrite_val; 11511051Sandreas.hansson@arm.com bool overwrite_mem; 11611051Sandreas.hansson@arm.com uint64_t condition_val64; 11711051Sandreas.hansson@arm.com uint32_t condition_val32; 11811051Sandreas.hansson@arm.com 11911051Sandreas.hansson@arm.com int offset = tags->extractBlkOffset(pkt->getAddr()); 12011051Sandreas.hansson@arm.com uint8_t *blk_data = blk->data + offset; 12111051Sandreas.hansson@arm.com 12211051Sandreas.hansson@arm.com assert(sizeof(uint64_t) >= pkt->getSize()); 12311051Sandreas.hansson@arm.com 12411051Sandreas.hansson@arm.com overwrite_mem = true; 12511051Sandreas.hansson@arm.com // keep a copy of our possible write value, and copy what is at the 12611051Sandreas.hansson@arm.com // memory address into the packet 12711051Sandreas.hansson@arm.com pkt->writeData((uint8_t *)&overwrite_val); 12811051Sandreas.hansson@arm.com pkt->setData(blk_data); 12911051Sandreas.hansson@arm.com 13011051Sandreas.hansson@arm.com if (pkt->req->isCondSwap()) { 13111051Sandreas.hansson@arm.com if (pkt->getSize() == sizeof(uint64_t)) { 13211051Sandreas.hansson@arm.com condition_val64 = pkt->req->getExtraData(); 13311051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val64, blk_data, 13411051Sandreas.hansson@arm.com sizeof(uint64_t)); 13511051Sandreas.hansson@arm.com } else if (pkt->getSize() == sizeof(uint32_t)) { 13611051Sandreas.hansson@arm.com condition_val32 = (uint32_t)pkt->req->getExtraData(); 13711051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val32, blk_data, 13811051Sandreas.hansson@arm.com sizeof(uint32_t)); 13911051Sandreas.hansson@arm.com } else 14011051Sandreas.hansson@arm.com panic("Invalid size for conditional read/write\n"); 14111051Sandreas.hansson@arm.com } 14211051Sandreas.hansson@arm.com 14311051Sandreas.hansson@arm.com if (overwrite_mem) { 14411051Sandreas.hansson@arm.com std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 14511051Sandreas.hansson@arm.com blk->status |= BlkDirty; 14611051Sandreas.hansson@arm.com } 14711051Sandreas.hansson@arm.com} 14811051Sandreas.hansson@arm.com 14911051Sandreas.hansson@arm.com 15011051Sandreas.hansson@arm.comvoid 15111601Sandreas.hansson@arm.comCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, 15211601Sandreas.hansson@arm.com bool deferred_response, bool pending_downgrade) 15311051Sandreas.hansson@arm.com{ 15411051Sandreas.hansson@arm.com assert(pkt->isRequest()); 15511051Sandreas.hansson@arm.com 15611051Sandreas.hansson@arm.com assert(blk && blk->isValid()); 15711051Sandreas.hansson@arm.com // Occasionally this is not true... if we are a lower-level cache 15811051Sandreas.hansson@arm.com // satisfying a string of Read and ReadEx requests from 15911051Sandreas.hansson@arm.com // upper-level caches, a Read will mark the block as shared but we 16011051Sandreas.hansson@arm.com // can satisfy a following ReadEx anyway since we can rely on the 16111051Sandreas.hansson@arm.com // Read requester(s) to have buffered the ReadEx snoop and to 16211051Sandreas.hansson@arm.com // invalidate their blocks after receiving them. 16311284Sandreas.hansson@arm.com // assert(!pkt->needsWritable() || blk->isWritable()); 16411051Sandreas.hansson@arm.com assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 16511051Sandreas.hansson@arm.com 16611051Sandreas.hansson@arm.com // Check RMW operations first since both isRead() and 16711051Sandreas.hansson@arm.com // isWrite() will be true for them 16811051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::SwapReq) { 16911051Sandreas.hansson@arm.com cmpAndSwap(blk, pkt); 17011051Sandreas.hansson@arm.com } else if (pkt->isWrite()) { 17111284Sandreas.hansson@arm.com // we have the block in a writable state and can go ahead, 17211284Sandreas.hansson@arm.com // note that the line may be also be considered writable in 17311284Sandreas.hansson@arm.com // downstream caches along the path to memory, but always 17411284Sandreas.hansson@arm.com // Exclusive, and never Modified 17511051Sandreas.hansson@arm.com assert(blk->isWritable()); 17611284Sandreas.hansson@arm.com // Write or WriteLine at the first cache with block in writable state 17711051Sandreas.hansson@arm.com if (blk->checkWrite(pkt)) { 17811051Sandreas.hansson@arm.com pkt->writeDataToBlock(blk->data, blkSize); 17911051Sandreas.hansson@arm.com } 18011284Sandreas.hansson@arm.com // Always mark the line as dirty (and thus transition to the 18111284Sandreas.hansson@arm.com // Modified state) even if we are a failed StoreCond so we 18211284Sandreas.hansson@arm.com // supply data to any snoops that have appended themselves to 18311284Sandreas.hansson@arm.com // this cache before knowing the store will fail. 18411051Sandreas.hansson@arm.com blk->status |= BlkDirty; 18511744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s (write)\n", __func__, pkt->print()); 18611051Sandreas.hansson@arm.com } else if (pkt->isRead()) { 18711051Sandreas.hansson@arm.com if (pkt->isLLSC()) { 18811051Sandreas.hansson@arm.com blk->trackLoadLocked(pkt); 18911051Sandreas.hansson@arm.com } 19011286Sandreas.hansson@arm.com 19111286Sandreas.hansson@arm.com // all read responses have a data payload 19211286Sandreas.hansson@arm.com assert(pkt->hasRespData()); 19311051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 19411286Sandreas.hansson@arm.com 19511600Sandreas.hansson@arm.com // determine if this read is from a (coherent) cache or not 19611600Sandreas.hansson@arm.com if (pkt->fromCache()) { 19711051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 19811051Sandreas.hansson@arm.com // special handling for coherent block requests from 19911051Sandreas.hansson@arm.com // upper-level caches 20011284Sandreas.hansson@arm.com if (pkt->needsWritable()) { 20111051Sandreas.hansson@arm.com // sanity check 20211051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::ReadExReq || 20311051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq); 20411602Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 20511051Sandreas.hansson@arm.com 20611051Sandreas.hansson@arm.com // if we have a dirty copy, make sure the recipient 20711284Sandreas.hansson@arm.com // keeps it marked dirty (in the modified state) 20811051Sandreas.hansson@arm.com if (blk->isDirty()) { 20911284Sandreas.hansson@arm.com pkt->setCacheResponding(); 21011602Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 21111051Sandreas.hansson@arm.com } 21211051Sandreas.hansson@arm.com } else if (blk->isWritable() && !pending_downgrade && 21311284Sandreas.hansson@arm.com !pkt->hasSharers() && 21411051Sandreas.hansson@arm.com pkt->cmd != MemCmd::ReadCleanReq) { 21511284Sandreas.hansson@arm.com // we can give the requester a writable copy on a read 21611284Sandreas.hansson@arm.com // request if: 21711284Sandreas.hansson@arm.com // - we have a writable copy at this level (& below) 21811051Sandreas.hansson@arm.com // - we don't have a pending snoop from below 21911051Sandreas.hansson@arm.com // signaling another read request 22011051Sandreas.hansson@arm.com // - no other cache above has a copy (otherwise it 22111284Sandreas.hansson@arm.com // would have set hasSharers flag when 22211284Sandreas.hansson@arm.com // snooping the packet) 22311284Sandreas.hansson@arm.com // - the read has explicitly asked for a clean 22411284Sandreas.hansson@arm.com // copy of the line 22511051Sandreas.hansson@arm.com if (blk->isDirty()) { 22611051Sandreas.hansson@arm.com // special considerations if we're owner: 22711051Sandreas.hansson@arm.com if (!deferred_response) { 22811284Sandreas.hansson@arm.com // respond with the line in Modified state 22911284Sandreas.hansson@arm.com // (cacheResponding set, hasSharers not set) 23011284Sandreas.hansson@arm.com pkt->setCacheResponding(); 23111197Sandreas.hansson@arm.com 23211601Sandreas.hansson@arm.com // if this cache is mostly inclusive, we 23311601Sandreas.hansson@arm.com // keep the block in the Exclusive state, 23411601Sandreas.hansson@arm.com // and pass it upwards as Modified 23511601Sandreas.hansson@arm.com // (writable and dirty), hence we have 23611601Sandreas.hansson@arm.com // multiple caches, all on the same path 23711601Sandreas.hansson@arm.com // towards memory, all considering the 23811601Sandreas.hansson@arm.com // same block writable, but only one 23911601Sandreas.hansson@arm.com // considering it Modified 24011197Sandreas.hansson@arm.com 24111601Sandreas.hansson@arm.com // we get away with multiple caches (on 24211601Sandreas.hansson@arm.com // the same path to memory) considering 24311601Sandreas.hansson@arm.com // the block writeable as we always enter 24411601Sandreas.hansson@arm.com // the cache hierarchy through a cache, 24511601Sandreas.hansson@arm.com // and first snoop upwards in all other 24611601Sandreas.hansson@arm.com // branches 24711601Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 24811051Sandreas.hansson@arm.com } else { 24911051Sandreas.hansson@arm.com // if we're responding after our own miss, 25011051Sandreas.hansson@arm.com // there's a window where the recipient didn't 25111051Sandreas.hansson@arm.com // know it was getting ownership and may not 25211051Sandreas.hansson@arm.com // have responded to snoops correctly, so we 25311284Sandreas.hansson@arm.com // have to respond with a shared line 25411284Sandreas.hansson@arm.com pkt->setHasSharers(); 25511051Sandreas.hansson@arm.com } 25611051Sandreas.hansson@arm.com } 25711051Sandreas.hansson@arm.com } else { 25811051Sandreas.hansson@arm.com // otherwise only respond with a shared copy 25911284Sandreas.hansson@arm.com pkt->setHasSharers(); 26011051Sandreas.hansson@arm.com } 26111051Sandreas.hansson@arm.com } 26211602Sandreas.hansson@arm.com } else if (pkt->isUpgrade()) { 26311602Sandreas.hansson@arm.com // sanity check 26411602Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 26511602Sandreas.hansson@arm.com 26611602Sandreas.hansson@arm.com if (blk->isDirty()) { 26711602Sandreas.hansson@arm.com // we were in the Owned state, and a cache above us that 26811602Sandreas.hansson@arm.com // has the line in Shared state needs to be made aware 26911602Sandreas.hansson@arm.com // that the data it already has is in fact dirty 27011602Sandreas.hansson@arm.com pkt->setCacheResponding(); 27111602Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 27211602Sandreas.hansson@arm.com } 27311051Sandreas.hansson@arm.com } else { 27411602Sandreas.hansson@arm.com assert(pkt->isInvalidate()); 27511197Sandreas.hansson@arm.com invalidateBlock(blk); 27611744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s (invalidation)\n", __func__, 27711744Snikos.nikoleris@arm.com pkt->print()); 27811051Sandreas.hansson@arm.com } 27911051Sandreas.hansson@arm.com} 28011051Sandreas.hansson@arm.com 28111051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28211051Sandreas.hansson@arm.com// 28311051Sandreas.hansson@arm.com// Access path: requests coming in from the CPU side 28411051Sandreas.hansson@arm.com// 28511051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28611051Sandreas.hansson@arm.com 28711051Sandreas.hansson@arm.combool 28811051Sandreas.hansson@arm.comCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 28911051Sandreas.hansson@arm.com PacketList &writebacks) 29011051Sandreas.hansson@arm.com{ 29111051Sandreas.hansson@arm.com // sanity check 29211051Sandreas.hansson@arm.com assert(pkt->isRequest()); 29311051Sandreas.hansson@arm.com 29411051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 29511051Sandreas.hansson@arm.com "Should never see a write in a read-only cache %s\n", 29611051Sandreas.hansson@arm.com name()); 29711051Sandreas.hansson@arm.com 29811744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s\n", __func__, pkt->print()); 29911051Sandreas.hansson@arm.com 30011051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 30111744Snikos.nikoleris@arm.com DPRINTF(Cache, "uncacheable: %s\n", pkt->print()); 30211051Sandreas.hansson@arm.com 30311051Sandreas.hansson@arm.com // flush and invalidate any existing block 30411051Sandreas.hansson@arm.com CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure())); 30511051Sandreas.hansson@arm.com if (old_blk && old_blk->isValid()) { 30611199Sandreas.hansson@arm.com if (old_blk->isDirty() || writebackClean) 30711051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(old_blk)); 30811051Sandreas.hansson@arm.com else 30911051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(old_blk)); 31011867Snikos.nikoleris@arm.com invalidateBlock(old_blk); 31111051Sandreas.hansson@arm.com } 31211051Sandreas.hansson@arm.com 31311484Snikos.nikoleris@arm.com blk = nullptr; 31411051Sandreas.hansson@arm.com // lookupLatency is the latency in case the request is uncacheable. 31511051Sandreas.hansson@arm.com lat = lookupLatency; 31611051Sandreas.hansson@arm.com return false; 31711051Sandreas.hansson@arm.com } 31811051Sandreas.hansson@arm.com 31911051Sandreas.hansson@arm.com // Here lat is the value passed as parameter to accessBlock() function 32011051Sandreas.hansson@arm.com // that can modify its value. 32111870Snikos.nikoleris@arm.com blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat); 32211051Sandreas.hansson@arm.com 32311744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s %s\n", pkt->print(), 32411051Sandreas.hansson@arm.com blk ? "hit " + blk->print() : "miss"); 32511051Sandreas.hansson@arm.com 32612349Snikos.nikoleris@arm.com if (pkt->req->isCacheMaintenance()) { 32712349Snikos.nikoleris@arm.com // A cache maintenance operation is always forwarded to the 32812349Snikos.nikoleris@arm.com // memory below even if the block is found in dirty state. 32912349Snikos.nikoleris@arm.com 33012349Snikos.nikoleris@arm.com // We defer any changes to the state of the block until we 33112349Snikos.nikoleris@arm.com // create and mark as in service the mshr for the downstream 33212349Snikos.nikoleris@arm.com // packet. 33312349Snikos.nikoleris@arm.com return false; 33412349Snikos.nikoleris@arm.com } 33511051Sandreas.hansson@arm.com 33611199Sandreas.hansson@arm.com if (pkt->isEviction()) { 33711051Sandreas.hansson@arm.com // We check for presence of block in above caches before issuing 33811051Sandreas.hansson@arm.com // Writeback or CleanEvict to write buffer. Therefore the only 33911051Sandreas.hansson@arm.com // possible cases can be of a CleanEvict packet coming from above 34011051Sandreas.hansson@arm.com // encountering a Writeback generated in this cache peer cache and 34111051Sandreas.hansson@arm.com // waiting in the write buffer. Cases of upper level peer caches 34211051Sandreas.hansson@arm.com // generating CleanEvict and Writeback or simply CleanEvict and 34311051Sandreas.hansson@arm.com // CleanEvict almost simultaneously will be caught by snoops sent out 34411051Sandreas.hansson@arm.com // by crossbar. 34511375Sandreas.hansson@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(), 34611375Sandreas.hansson@arm.com pkt->isSecure()); 34711375Sandreas.hansson@arm.com if (wb_entry) { 34811199Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 34911199Sandreas.hansson@arm.com PacketPtr wbPkt = wb_entry->getTarget()->pkt; 35011199Sandreas.hansson@arm.com assert(wbPkt->isWriteback()); 35111199Sandreas.hansson@arm.com 35211199Sandreas.hansson@arm.com if (pkt->isCleanEviction()) { 35311199Sandreas.hansson@arm.com // The CleanEvict and WritebackClean snoops into other 35411199Sandreas.hansson@arm.com // peer caches of the same level while traversing the 35511199Sandreas.hansson@arm.com // crossbar. If a copy of the block is found, the 35611199Sandreas.hansson@arm.com // packet is deleted in the crossbar. Hence, none of 35711199Sandreas.hansson@arm.com // the other upper level caches connected to this 35811199Sandreas.hansson@arm.com // cache have the block, so we can clear the 35911199Sandreas.hansson@arm.com // BLOCK_CACHED flag in the Writeback if set and 36011199Sandreas.hansson@arm.com // discard the CleanEvict by returning true. 36111199Sandreas.hansson@arm.com wbPkt->clearBlockCached(); 36211199Sandreas.hansson@arm.com return true; 36311199Sandreas.hansson@arm.com } else { 36411199Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::WritebackDirty); 36511199Sandreas.hansson@arm.com // Dirty writeback from above trumps our clean 36611199Sandreas.hansson@arm.com // writeback... discard here 36711199Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 36811375Sandreas.hansson@arm.com markInService(wb_entry); 36911199Sandreas.hansson@arm.com delete wbPkt; 37011199Sandreas.hansson@arm.com } 37111051Sandreas.hansson@arm.com } 37211051Sandreas.hansson@arm.com } 37311051Sandreas.hansson@arm.com 37411051Sandreas.hansson@arm.com // Writeback handling is special case. We can write the block into 37511051Sandreas.hansson@arm.com // the cache without having a writeable copy (or any copy at all). 37611199Sandreas.hansson@arm.com if (pkt->isWriteback()) { 37711051Sandreas.hansson@arm.com assert(blkSize == pkt->getSize()); 37811199Sandreas.hansson@arm.com 37911199Sandreas.hansson@arm.com // we could get a clean writeback while we are having 38011199Sandreas.hansson@arm.com // outstanding accesses to a block, do the simple thing for 38111199Sandreas.hansson@arm.com // now and drop the clean writeback so that we do not upset 38211199Sandreas.hansson@arm.com // any ordering/decisions about ownership already taken 38311199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackClean && 38411199Sandreas.hansson@arm.com mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) { 38511199Sandreas.hansson@arm.com DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, " 38611199Sandreas.hansson@arm.com "dropping\n", pkt->getAddr()); 38711199Sandreas.hansson@arm.com return true; 38811199Sandreas.hansson@arm.com } 38911199Sandreas.hansson@arm.com 39011484Snikos.nikoleris@arm.com if (blk == nullptr) { 39111051Sandreas.hansson@arm.com // need to do a replacement 39211051Sandreas.hansson@arm.com blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks); 39311484Snikos.nikoleris@arm.com if (blk == nullptr) { 39411051Sandreas.hansson@arm.com // no replaceable block available: give up, fwd to next level. 39511051Sandreas.hansson@arm.com incMissCount(pkt); 39611051Sandreas.hansson@arm.com return false; 39711051Sandreas.hansson@arm.com } 39811051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 39911051Sandreas.hansson@arm.com 40012691Sodanrc@yahoo.com.br blk->status |= (BlkValid | BlkReadable); 40111051Sandreas.hansson@arm.com } 40211199Sandreas.hansson@arm.com // only mark the block dirty if we got a writeback command, 40311199Sandreas.hansson@arm.com // and leave it as is for a clean writeback 40411199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackDirty) { 40512500Snikos.nikoleris@arm.com assert(!blk->isDirty()); 40611199Sandreas.hansson@arm.com blk->status |= BlkDirty; 40711199Sandreas.hansson@arm.com } 40811284Sandreas.hansson@arm.com // if the packet does not have sharers, it is passing 40911284Sandreas.hansson@arm.com // writable, and we got the writeback in Modified or Exclusive 41011284Sandreas.hansson@arm.com // state, if not we are in the Owned or Shared state 41111284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 41211051Sandreas.hansson@arm.com blk->status |= BlkWritable; 41311051Sandreas.hansson@arm.com } 41411051Sandreas.hansson@arm.com // nothing else to do; writeback doesn't expect response 41511051Sandreas.hansson@arm.com assert(!pkt->needsResponse()); 41612633Sodanrc@yahoo.com.br pkt->writeDataToBlock(blk->data, blkSize); 41711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 41811051Sandreas.hansson@arm.com incHitCount(pkt); 41912556Snikos.nikoleris@arm.com // populate the time when the block will be ready to access. 42012556Snikos.nikoleris@arm.com blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay + 42112556Snikos.nikoleris@arm.com pkt->payloadDelay; 42211051Sandreas.hansson@arm.com return true; 42311051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::CleanEvict) { 42411484Snikos.nikoleris@arm.com if (blk != nullptr) { 42511051Sandreas.hansson@arm.com // Found the block in the tags, need to stop CleanEvict from 42611051Sandreas.hansson@arm.com // propagating further down the hierarchy. Returning true will 42711051Sandreas.hansson@arm.com // treat the CleanEvict like a satisfied write request and delete 42811051Sandreas.hansson@arm.com // it. 42911051Sandreas.hansson@arm.com return true; 43011051Sandreas.hansson@arm.com } 43111051Sandreas.hansson@arm.com // We didn't find the block here, propagate the CleanEvict further 43211051Sandreas.hansson@arm.com // down the memory hierarchy. Returning false will treat the CleanEvict 43311051Sandreas.hansson@arm.com // like a Writeback which could not find a replaceable block so has to 43411051Sandreas.hansson@arm.com // go to next level. 43511051Sandreas.hansson@arm.com return false; 43612345Snikos.nikoleris@arm.com } else if (pkt->cmd == MemCmd::WriteClean) { 43712345Snikos.nikoleris@arm.com // WriteClean handling is a special case. We can allocate a 43812345Snikos.nikoleris@arm.com // block directly if it doesn't exist and we can update the 43912345Snikos.nikoleris@arm.com // block immediately. The WriteClean transfers the ownership 44012345Snikos.nikoleris@arm.com // of the block as well. 44112345Snikos.nikoleris@arm.com assert(blkSize == pkt->getSize()); 44212345Snikos.nikoleris@arm.com 44312345Snikos.nikoleris@arm.com if (!blk) { 44412346Snikos.nikoleris@arm.com if (pkt->writeThrough()) { 44512346Snikos.nikoleris@arm.com // if this is a write through packet, we don't try to 44612346Snikos.nikoleris@arm.com // allocate if the block is not present 44712345Snikos.nikoleris@arm.com return false; 44812346Snikos.nikoleris@arm.com } else { 44912346Snikos.nikoleris@arm.com // a writeback that misses needs to allocate a new block 45012346Snikos.nikoleris@arm.com blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), 45112346Snikos.nikoleris@arm.com writebacks); 45212346Snikos.nikoleris@arm.com if (!blk) { 45312346Snikos.nikoleris@arm.com // no replaceable block available: give up, fwd to 45412346Snikos.nikoleris@arm.com // next level. 45512346Snikos.nikoleris@arm.com incMissCount(pkt); 45612346Snikos.nikoleris@arm.com return false; 45712346Snikos.nikoleris@arm.com } 45812346Snikos.nikoleris@arm.com tags->insertBlock(pkt, blk); 45912346Snikos.nikoleris@arm.com 46012691Sodanrc@yahoo.com.br blk->status |= (BlkValid | BlkReadable); 46112345Snikos.nikoleris@arm.com } 46212345Snikos.nikoleris@arm.com } 46312345Snikos.nikoleris@arm.com 46412345Snikos.nikoleris@arm.com // at this point either this is a writeback or a write-through 46512345Snikos.nikoleris@arm.com // write clean operation and the block is already in this 46612345Snikos.nikoleris@arm.com // cache, we need to update the data and the block flags 46712345Snikos.nikoleris@arm.com assert(blk); 46812500Snikos.nikoleris@arm.com assert(!blk->isDirty()); 46912346Snikos.nikoleris@arm.com if (!pkt->writeThrough()) { 47012346Snikos.nikoleris@arm.com blk->status |= BlkDirty; 47112346Snikos.nikoleris@arm.com } 47212345Snikos.nikoleris@arm.com // nothing else to do; writeback doesn't expect response 47312345Snikos.nikoleris@arm.com assert(!pkt->needsResponse()); 47412633Sodanrc@yahoo.com.br pkt->writeDataToBlock(blk->data, blkSize); 47512345Snikos.nikoleris@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 47612345Snikos.nikoleris@arm.com 47712345Snikos.nikoleris@arm.com incHitCount(pkt); 47812345Snikos.nikoleris@arm.com // populate the time when the block will be ready to access. 47912345Snikos.nikoleris@arm.com blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay + 48012345Snikos.nikoleris@arm.com pkt->payloadDelay; 48112346Snikos.nikoleris@arm.com // if this a write-through packet it will be sent to cache 48212346Snikos.nikoleris@arm.com // below 48312346Snikos.nikoleris@arm.com return !pkt->writeThrough(); 48411601Sandreas.hansson@arm.com } else if (blk && (pkt->needsWritable() ? blk->isWritable() : 48511601Sandreas.hansson@arm.com blk->isReadable())) { 48611051Sandreas.hansson@arm.com // OK to satisfy access 48711051Sandreas.hansson@arm.com incHitCount(pkt); 48811601Sandreas.hansson@arm.com satisfyRequest(pkt, blk); 48911601Sandreas.hansson@arm.com maintainClusivity(pkt->fromCache(), blk); 49011601Sandreas.hansson@arm.com 49111051Sandreas.hansson@arm.com return true; 49211051Sandreas.hansson@arm.com } 49311051Sandreas.hansson@arm.com 49411484Snikos.nikoleris@arm.com // Can't satisfy access normally... either no block (blk == nullptr) 49511284Sandreas.hansson@arm.com // or have block but need writable 49611051Sandreas.hansson@arm.com 49711051Sandreas.hansson@arm.com incMissCount(pkt); 49811051Sandreas.hansson@arm.com 49911484Snikos.nikoleris@arm.com if (blk == nullptr && pkt->isLLSC() && pkt->isWrite()) { 50011051Sandreas.hansson@arm.com // complete miss on store conditional... just give up now 50111051Sandreas.hansson@arm.com pkt->req->setExtraData(0); 50211051Sandreas.hansson@arm.com return true; 50311051Sandreas.hansson@arm.com } 50411051Sandreas.hansson@arm.com 50511051Sandreas.hansson@arm.com return false; 50611051Sandreas.hansson@arm.com} 50711051Sandreas.hansson@arm.com 50811051Sandreas.hansson@arm.comvoid 50911601Sandreas.hansson@arm.comCache::maintainClusivity(bool from_cache, CacheBlk *blk) 51011601Sandreas.hansson@arm.com{ 51111601Sandreas.hansson@arm.com if (from_cache && blk && blk->isValid() && !blk->isDirty() && 51211601Sandreas.hansson@arm.com clusivity == Enums::mostly_excl) { 51311601Sandreas.hansson@arm.com // if we have responded to a cache, and our block is still 51411601Sandreas.hansson@arm.com // valid, but not dirty, and this cache is mostly exclusive 51511601Sandreas.hansson@arm.com // with respect to the cache above, drop the block 51611601Sandreas.hansson@arm.com invalidateBlock(blk); 51711601Sandreas.hansson@arm.com } 51811601Sandreas.hansson@arm.com} 51911601Sandreas.hansson@arm.com 52011601Sandreas.hansson@arm.comvoid 52111051Sandreas.hansson@arm.comCache::doWritebacks(PacketList& writebacks, Tick forward_time) 52211051Sandreas.hansson@arm.com{ 52311051Sandreas.hansson@arm.com while (!writebacks.empty()) { 52411051Sandreas.hansson@arm.com PacketPtr wbPkt = writebacks.front(); 52511051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying writebacks to 52612345Snikos.nikoleris@arm.com // write buffer. 52712345Snikos.nikoleris@arm.com 52812345Snikos.nikoleris@arm.com // Call isCachedAbove for Writebacks, CleanEvicts and 52912345Snikos.nikoleris@arm.com // WriteCleans to discover if the block is cached above. 53011051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) { 53111051Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::CleanEvict) { 53211051Sandreas.hansson@arm.com // Delete CleanEvict because cached copies exist above. The 53311051Sandreas.hansson@arm.com // packet destructor will delete the request object because 53411051Sandreas.hansson@arm.com // this is a non-snoop request packet which does not require a 53511051Sandreas.hansson@arm.com // response. 53611051Sandreas.hansson@arm.com delete wbPkt; 53711199Sandreas.hansson@arm.com } else if (wbPkt->cmd == MemCmd::WritebackClean) { 53811199Sandreas.hansson@arm.com // clean writeback, do not send since the block is 53911199Sandreas.hansson@arm.com // still cached above 54011199Sandreas.hansson@arm.com assert(writebackClean); 54111199Sandreas.hansson@arm.com delete wbPkt; 54211051Sandreas.hansson@arm.com } else { 54312345Snikos.nikoleris@arm.com assert(wbPkt->cmd == MemCmd::WritebackDirty || 54412345Snikos.nikoleris@arm.com wbPkt->cmd == MemCmd::WriteClean); 54511051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag in Writeback and send below, so that 54611051Sandreas.hansson@arm.com // the Writeback does not reset the bit corresponding to this 54711051Sandreas.hansson@arm.com // address in the snoop filter below. 54811051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 54911051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 55011051Sandreas.hansson@arm.com } 55111051Sandreas.hansson@arm.com } else { 55211051Sandreas.hansson@arm.com // If the block is not cached above, send packet below. Both 55311051Sandreas.hansson@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 55411051Sandreas.hansson@arm.com // reset the bit corresponding to this address in the snoop filter 55511051Sandreas.hansson@arm.com // below. 55611051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 55711051Sandreas.hansson@arm.com } 55811051Sandreas.hansson@arm.com writebacks.pop_front(); 55911051Sandreas.hansson@arm.com } 56011051Sandreas.hansson@arm.com} 56111051Sandreas.hansson@arm.com 56211130Sali.jafri@arm.comvoid 56311130Sali.jafri@arm.comCache::doWritebacksAtomic(PacketList& writebacks) 56411130Sali.jafri@arm.com{ 56511130Sali.jafri@arm.com while (!writebacks.empty()) { 56611130Sali.jafri@arm.com PacketPtr wbPkt = writebacks.front(); 56711130Sali.jafri@arm.com // Call isCachedAbove for both Writebacks and CleanEvicts. If 56811130Sali.jafri@arm.com // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks 56911130Sali.jafri@arm.com // and discard CleanEvicts. 57011130Sali.jafri@arm.com if (isCachedAbove(wbPkt, false)) { 57112345Snikos.nikoleris@arm.com if (wbPkt->cmd == MemCmd::WritebackDirty || 57212345Snikos.nikoleris@arm.com wbPkt->cmd == MemCmd::WriteClean) { 57311130Sali.jafri@arm.com // Set BLOCK_CACHED flag in Writeback and send below, 57411130Sali.jafri@arm.com // so that the Writeback does not reset the bit 57511130Sali.jafri@arm.com // corresponding to this address in the snoop filter 57611130Sali.jafri@arm.com // below. We can discard CleanEvicts because cached 57711130Sali.jafri@arm.com // copies exist above. Atomic mode isCachedAbove 57811130Sali.jafri@arm.com // modifies packet to set BLOCK_CACHED flag 57911130Sali.jafri@arm.com memSidePort->sendAtomic(wbPkt); 58011130Sali.jafri@arm.com } 58111130Sali.jafri@arm.com } else { 58211130Sali.jafri@arm.com // If the block is not cached above, send packet below. Both 58311130Sali.jafri@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 58411130Sali.jafri@arm.com // reset the bit corresponding to this address in the snoop filter 58511130Sali.jafri@arm.com // below. 58611130Sali.jafri@arm.com memSidePort->sendAtomic(wbPkt); 58711130Sali.jafri@arm.com } 58811130Sali.jafri@arm.com writebacks.pop_front(); 58911130Sali.jafri@arm.com // In case of CleanEvicts, the packet destructor will delete the 59011130Sali.jafri@arm.com // request object because this is a non-snoop request packet which 59111130Sali.jafri@arm.com // does not require a response. 59211130Sali.jafri@arm.com delete wbPkt; 59311130Sali.jafri@arm.com } 59411130Sali.jafri@arm.com} 59511130Sali.jafri@arm.com 59611051Sandreas.hansson@arm.com 59711051Sandreas.hansson@arm.comvoid 59811051Sandreas.hansson@arm.comCache::recvTimingSnoopResp(PacketPtr pkt) 59911051Sandreas.hansson@arm.com{ 60011744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s for %s\n", __func__, pkt->print()); 60111051Sandreas.hansson@arm.com 60211051Sandreas.hansson@arm.com assert(pkt->isResponse()); 60311051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 60411051Sandreas.hansson@arm.com 60511276Sandreas.hansson@arm.com // determine if the response is from a snoop request we created 60611276Sandreas.hansson@arm.com // (in which case it should be in the outstandingSnoop), or if we 60711276Sandreas.hansson@arm.com // merely forwarded someone else's snoop request 60811276Sandreas.hansson@arm.com const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) == 60911276Sandreas.hansson@arm.com outstandingSnoop.end(); 61011276Sandreas.hansson@arm.com 61111276Sandreas.hansson@arm.com if (!forwardAsSnoop) { 61211276Sandreas.hansson@arm.com // the packet came from this cache, so sink it here and do not 61311276Sandreas.hansson@arm.com // forward it 61411051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::HardPFResp); 61511276Sandreas.hansson@arm.com 61611276Sandreas.hansson@arm.com outstandingSnoop.erase(pkt->req); 61711276Sandreas.hansson@arm.com 61811276Sandreas.hansson@arm.com DPRINTF(Cache, "Got prefetch response from above for addr " 61911276Sandreas.hansson@arm.com "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 62011051Sandreas.hansson@arm.com recvTimingResp(pkt); 62111051Sandreas.hansson@arm.com return; 62211051Sandreas.hansson@arm.com } 62311051Sandreas.hansson@arm.com 62411051Sandreas.hansson@arm.com // forwardLatency is set here because there is a response from an 62511051Sandreas.hansson@arm.com // upper level cache. 62611051Sandreas.hansson@arm.com // To pay the delay that occurs if the packet comes from the bus, 62711051Sandreas.hansson@arm.com // we charge also headerDelay. 62811051Sandreas.hansson@arm.com Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay; 62911051Sandreas.hansson@arm.com // Reset the timing of the packet. 63011051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 63111051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, snoop_resp_time); 63211051Sandreas.hansson@arm.com} 63311051Sandreas.hansson@arm.com 63411051Sandreas.hansson@arm.comvoid 63511051Sandreas.hansson@arm.comCache::promoteWholeLineWrites(PacketPtr pkt) 63611051Sandreas.hansson@arm.com{ 63711051Sandreas.hansson@arm.com // Cache line clearing instructions 63811051Sandreas.hansson@arm.com if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) && 63911051Sandreas.hansson@arm.com (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) { 64011051Sandreas.hansson@arm.com pkt->cmd = MemCmd::WriteLineReq; 64111051Sandreas.hansson@arm.com DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n"); 64211051Sandreas.hansson@arm.com } 64311051Sandreas.hansson@arm.com} 64411051Sandreas.hansson@arm.com 64512630Snikos.nikoleris@arm.comvoid 64612720Snikos.nikoleris@arm.comCache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time) 64712720Snikos.nikoleris@arm.com{ 64812720Snikos.nikoleris@arm.com // should never be satisfying an uncacheable access as we 64912720Snikos.nikoleris@arm.com // flush and invalidate any existing block as part of the 65012720Snikos.nikoleris@arm.com // lookup 65112720Snikos.nikoleris@arm.com assert(!pkt->req->isUncacheable()); 65212720Snikos.nikoleris@arm.com 65312720Snikos.nikoleris@arm.com if (pkt->needsResponse()) { 65412720Snikos.nikoleris@arm.com pkt->makeTimingResponse(); 65512720Snikos.nikoleris@arm.com // @todo: Make someone pay for this 65612720Snikos.nikoleris@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 65712720Snikos.nikoleris@arm.com 65812720Snikos.nikoleris@arm.com // In this case we are considering request_time that takes 65912720Snikos.nikoleris@arm.com // into account the delay of the xbar, if any, and just 66012720Snikos.nikoleris@arm.com // lat, neglecting responseLatency, modelling hit latency 66112720Snikos.nikoleris@arm.com // just as lookupLatency or or the value of lat overriden 66212720Snikos.nikoleris@arm.com // by access(), that calls accessBlock() function. 66312720Snikos.nikoleris@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 66412720Snikos.nikoleris@arm.com } else { 66512720Snikos.nikoleris@arm.com DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__, 66612720Snikos.nikoleris@arm.com pkt->print()); 66712720Snikos.nikoleris@arm.com 66812720Snikos.nikoleris@arm.com // queue the packet for deletion, as the sending cache is 66912720Snikos.nikoleris@arm.com // still relying on it; if the block is found in access(), 67012720Snikos.nikoleris@arm.com // CleanEvict and Writeback messages will be deleted 67112720Snikos.nikoleris@arm.com // here as well 67212720Snikos.nikoleris@arm.com pendingDelete.reset(pkt); 67312720Snikos.nikoleris@arm.com } 67412720Snikos.nikoleris@arm.com} 67512720Snikos.nikoleris@arm.com 67612720Snikos.nikoleris@arm.comvoid 67712720Snikos.nikoleris@arm.comCache::handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, Tick forward_time, 67812720Snikos.nikoleris@arm.com Tick request_time) 67912720Snikos.nikoleris@arm.com{ 68012720Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 68112720Snikos.nikoleris@arm.com 68212720Snikos.nikoleris@arm.com // ignore any existing MSHR if we are dealing with an 68312720Snikos.nikoleris@arm.com // uncacheable request 68412720Snikos.nikoleris@arm.com MSHR *mshr = pkt->req->isUncacheable() ? nullptr : 68512720Snikos.nikoleris@arm.com mshrQueue.findMatch(blk_addr, pkt->isSecure()); 68612720Snikos.nikoleris@arm.com 68712720Snikos.nikoleris@arm.com // Software prefetch handling: 68812720Snikos.nikoleris@arm.com // To keep the core from waiting on data it won't look at 68912720Snikos.nikoleris@arm.com // anyway, send back a response with dummy data. Miss handling 69012720Snikos.nikoleris@arm.com // will continue asynchronously. Unfortunately, the core will 69112720Snikos.nikoleris@arm.com // insist upon freeing original Packet/Request, so we have to 69212720Snikos.nikoleris@arm.com // create a new pair with a different lifecycle. Note that this 69312720Snikos.nikoleris@arm.com // processing happens before any MSHR munging on the behalf of 69412720Snikos.nikoleris@arm.com // this request because this new Request will be the one stored 69512720Snikos.nikoleris@arm.com // into the MSHRs, not the original. 69612720Snikos.nikoleris@arm.com if (pkt->cmd.isSWPrefetch()) { 69712720Snikos.nikoleris@arm.com assert(pkt->needsResponse()); 69812720Snikos.nikoleris@arm.com assert(pkt->req->hasPaddr()); 69912720Snikos.nikoleris@arm.com assert(!pkt->req->isUncacheable()); 70012720Snikos.nikoleris@arm.com 70112720Snikos.nikoleris@arm.com // There's no reason to add a prefetch as an additional target 70212720Snikos.nikoleris@arm.com // to an existing MSHR. If an outstanding request is already 70312720Snikos.nikoleris@arm.com // in progress, there is nothing for the prefetch to do. 70412720Snikos.nikoleris@arm.com // If this is the case, we don't even create a request at all. 70512720Snikos.nikoleris@arm.com PacketPtr pf = nullptr; 70612720Snikos.nikoleris@arm.com 70712720Snikos.nikoleris@arm.com if (!mshr) { 70812720Snikos.nikoleris@arm.com // copy the request and create a new SoftPFReq packet 70912720Snikos.nikoleris@arm.com RequestPtr req = new Request(pkt->req->getPaddr(), 71012720Snikos.nikoleris@arm.com pkt->req->getSize(), 71112720Snikos.nikoleris@arm.com pkt->req->getFlags(), 71212720Snikos.nikoleris@arm.com pkt->req->masterId()); 71312720Snikos.nikoleris@arm.com pf = new Packet(req, pkt->cmd); 71412720Snikos.nikoleris@arm.com pf->allocate(); 71512720Snikos.nikoleris@arm.com assert(pf->getAddr() == pkt->getAddr()); 71612720Snikos.nikoleris@arm.com assert(pf->getSize() == pkt->getSize()); 71712720Snikos.nikoleris@arm.com } 71812720Snikos.nikoleris@arm.com 71912720Snikos.nikoleris@arm.com pkt->makeTimingResponse(); 72012720Snikos.nikoleris@arm.com 72112720Snikos.nikoleris@arm.com // request_time is used here, taking into account lat and the delay 72212720Snikos.nikoleris@arm.com // charged if the packet comes from the xbar. 72312720Snikos.nikoleris@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 72412720Snikos.nikoleris@arm.com 72512720Snikos.nikoleris@arm.com // If an outstanding request is in progress (we found an 72612720Snikos.nikoleris@arm.com // MSHR) this is set to null 72712720Snikos.nikoleris@arm.com pkt = pf; 72812720Snikos.nikoleris@arm.com } 72912720Snikos.nikoleris@arm.com 73012720Snikos.nikoleris@arm.com if (mshr) { 73112720Snikos.nikoleris@arm.com /// MSHR hit 73212720Snikos.nikoleris@arm.com /// @note writebacks will be checked in getNextMSHR() 73312720Snikos.nikoleris@arm.com /// for any conflicting requests to the same block 73412720Snikos.nikoleris@arm.com 73512720Snikos.nikoleris@arm.com //@todo remove hw_pf here 73612720Snikos.nikoleris@arm.com 73712720Snikos.nikoleris@arm.com // Coalesce unless it was a software prefetch (see above). 73812720Snikos.nikoleris@arm.com if (pkt) { 73912720Snikos.nikoleris@arm.com assert(!pkt->isWriteback()); 74012720Snikos.nikoleris@arm.com // CleanEvicts corresponding to blocks which have 74112720Snikos.nikoleris@arm.com // outstanding requests in MSHRs are simply sunk here 74212720Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::CleanEvict) { 74312720Snikos.nikoleris@arm.com pendingDelete.reset(pkt); 74412720Snikos.nikoleris@arm.com } else if (pkt->cmd == MemCmd::WriteClean) { 74512720Snikos.nikoleris@arm.com // A WriteClean should never coalesce with any 74612720Snikos.nikoleris@arm.com // outstanding cache maintenance requests. 74712720Snikos.nikoleris@arm.com 74812720Snikos.nikoleris@arm.com // We use forward_time here because there is an 74912720Snikos.nikoleris@arm.com // uncached memory write, forwarded to WriteBuffer. 75012720Snikos.nikoleris@arm.com allocateWriteBuffer(pkt, forward_time); 75112720Snikos.nikoleris@arm.com } else { 75212720Snikos.nikoleris@arm.com DPRINTF(Cache, "%s coalescing MSHR for %s\n", __func__, 75312720Snikos.nikoleris@arm.com pkt->print()); 75412720Snikos.nikoleris@arm.com 75512720Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 75612720Snikos.nikoleris@arm.com mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 75712720Snikos.nikoleris@arm.com 75812720Snikos.nikoleris@arm.com // uncacheable accesses always allocate a new 75912720Snikos.nikoleris@arm.com // MSHR, and cacheable accesses ignore any 76012720Snikos.nikoleris@arm.com // uncacheable MSHRs, thus we should never have 76112720Snikos.nikoleris@arm.com // targets addded if originally allocated 76212720Snikos.nikoleris@arm.com // uncacheable 76312720Snikos.nikoleris@arm.com assert(!mshr->isUncacheable()); 76412720Snikos.nikoleris@arm.com 76512720Snikos.nikoleris@arm.com // We use forward_time here because it is the same 76612720Snikos.nikoleris@arm.com // considering new targets. We have multiple 76712720Snikos.nikoleris@arm.com // requests for the same address here. It 76812720Snikos.nikoleris@arm.com // specifies the latency to allocate an internal 76912720Snikos.nikoleris@arm.com // buffer and to schedule an event to the queued 77012720Snikos.nikoleris@arm.com // port and also takes into account the additional 77112720Snikos.nikoleris@arm.com // delay of the xbar. 77212720Snikos.nikoleris@arm.com mshr->allocateTarget(pkt, forward_time, order++, 77312720Snikos.nikoleris@arm.com allocOnFill(pkt->cmd)); 77412720Snikos.nikoleris@arm.com if (mshr->getNumTargets() == numTarget) { 77512720Snikos.nikoleris@arm.com noTargetMSHR = mshr; 77612720Snikos.nikoleris@arm.com setBlocked(Blocked_NoTargets); 77712720Snikos.nikoleris@arm.com // need to be careful with this... if this mshr isn't 77812720Snikos.nikoleris@arm.com // ready yet (i.e. time > curTick()), we don't want to 77912720Snikos.nikoleris@arm.com // move it ahead of mshrs that are ready 78012720Snikos.nikoleris@arm.com // mshrQueue.moveToFront(mshr); 78112720Snikos.nikoleris@arm.com } 78212720Snikos.nikoleris@arm.com } 78312720Snikos.nikoleris@arm.com } 78412720Snikos.nikoleris@arm.com } else { 78512720Snikos.nikoleris@arm.com // no MSHR 78612720Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 78712720Snikos.nikoleris@arm.com if (pkt->req->isUncacheable()) { 78812720Snikos.nikoleris@arm.com mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++; 78912720Snikos.nikoleris@arm.com } else { 79012720Snikos.nikoleris@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 79112720Snikos.nikoleris@arm.com } 79212720Snikos.nikoleris@arm.com 79312720Snikos.nikoleris@arm.com if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean || 79412720Snikos.nikoleris@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 79512720Snikos.nikoleris@arm.com // We use forward_time here because there is an 79612720Snikos.nikoleris@arm.com // uncached memory write, forwarded to WriteBuffer. 79712720Snikos.nikoleris@arm.com allocateWriteBuffer(pkt, forward_time); 79812720Snikos.nikoleris@arm.com } else { 79912720Snikos.nikoleris@arm.com if (blk && blk->isValid()) { 80012720Snikos.nikoleris@arm.com // should have flushed and have no valid block 80112720Snikos.nikoleris@arm.com assert(!pkt->req->isUncacheable()); 80212720Snikos.nikoleris@arm.com 80312720Snikos.nikoleris@arm.com // If we have a write miss to a valid block, we 80412720Snikos.nikoleris@arm.com // need to mark the block non-readable. Otherwise 80512720Snikos.nikoleris@arm.com // if we allow reads while there's an outstanding 80612720Snikos.nikoleris@arm.com // write miss, the read could return stale data 80712720Snikos.nikoleris@arm.com // out of the cache block... a more aggressive 80812720Snikos.nikoleris@arm.com // system could detect the overlap (if any) and 80912720Snikos.nikoleris@arm.com // forward data out of the MSHRs, but we don't do 81012720Snikos.nikoleris@arm.com // that yet. Note that we do need to leave the 81112720Snikos.nikoleris@arm.com // block valid so that it stays in the cache, in 81212720Snikos.nikoleris@arm.com // case we get an upgrade response (and hence no 81312720Snikos.nikoleris@arm.com // new data) when the write miss completes. 81412720Snikos.nikoleris@arm.com // As long as CPUs do proper store/load forwarding 81512720Snikos.nikoleris@arm.com // internally, and have a sufficiently weak memory 81612720Snikos.nikoleris@arm.com // model, this is probably unnecessary, but at some 81712720Snikos.nikoleris@arm.com // point it must have seemed like we needed it... 81812720Snikos.nikoleris@arm.com assert((pkt->needsWritable() && !blk->isWritable()) || 81912720Snikos.nikoleris@arm.com pkt->req->isCacheMaintenance()); 82012720Snikos.nikoleris@arm.com blk->status &= ~BlkReadable; 82112720Snikos.nikoleris@arm.com } 82212720Snikos.nikoleris@arm.com // Here we are using forward_time, modelling the latency of 82312720Snikos.nikoleris@arm.com // a miss (outbound) just as forwardLatency, neglecting the 82412720Snikos.nikoleris@arm.com // lookupLatency component. 82512720Snikos.nikoleris@arm.com allocateMissBuffer(pkt, forward_time); 82612720Snikos.nikoleris@arm.com } 82712720Snikos.nikoleris@arm.com } 82812720Snikos.nikoleris@arm.com} 82912720Snikos.nikoleris@arm.com 83012720Snikos.nikoleris@arm.comvoid 83111051Sandreas.hansson@arm.comCache::recvTimingReq(PacketPtr pkt) 83211051Sandreas.hansson@arm.com{ 83311830Sbaz21@cam.ac.uk DPRINTF(CacheTags, "%s tags:\n%s\n", __func__, tags->print()); 83411051Sandreas.hansson@arm.com 83511051Sandreas.hansson@arm.com assert(pkt->isRequest()); 83611051Sandreas.hansson@arm.com 83711051Sandreas.hansson@arm.com // Just forward the packet if caches are disabled. 83811051Sandreas.hansson@arm.com if (system->bypassCaches()) { 83911051Sandreas.hansson@arm.com // @todo This should really enqueue the packet rather 84011051Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt); 84111051Sandreas.hansson@arm.com assert(success); 84212630Snikos.nikoleris@arm.com return; 84311051Sandreas.hansson@arm.com } 84411051Sandreas.hansson@arm.com 84511051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 84611051Sandreas.hansson@arm.com 84712349Snikos.nikoleris@arm.com // Cache maintenance operations have to visit all the caches down 84812349Snikos.nikoleris@arm.com // to the specified xbar (PoC, PoU, etc.). Even if a cache above 84912349Snikos.nikoleris@arm.com // is responding we forward the packet to the memory below rather 85012349Snikos.nikoleris@arm.com // than creating an express snoop. 85111284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 85211051Sandreas.hansson@arm.com // a cache above us (but not where the packet came from) is 85311284Sandreas.hansson@arm.com // responding to the request, in other words it has the line 85411284Sandreas.hansson@arm.com // in Modified or Owned state 85511744Snikos.nikoleris@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 85611744Snikos.nikoleris@arm.com pkt->print()); 85711051Sandreas.hansson@arm.com 85811284Sandreas.hansson@arm.com // if the packet needs the block to be writable, and the cache 85911284Sandreas.hansson@arm.com // that has promised to respond (setting the cache responding 86011284Sandreas.hansson@arm.com // flag) is not providing writable (it is in Owned rather than 86111284Sandreas.hansson@arm.com // the Modified state), we know that there may be other Shared 86211284Sandreas.hansson@arm.com // copies in the system; go out and invalidate them all 86311334Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 86411284Sandreas.hansson@arm.com 86511334Sandreas.hansson@arm.com // an upstream cache that had the line in Owned state 86611334Sandreas.hansson@arm.com // (dirty, but not writable), is responding and thus 86711334Sandreas.hansson@arm.com // transferring the dirty line from one branch of the 86811334Sandreas.hansson@arm.com // cache hierarchy to another 86911284Sandreas.hansson@arm.com 87011334Sandreas.hansson@arm.com // send out an express snoop and invalidate all other 87111334Sandreas.hansson@arm.com // copies (snooping a packet that needs writable is the 87211334Sandreas.hansson@arm.com // same as an invalidation), thus turning the Owned line 87311334Sandreas.hansson@arm.com // into a Modified line, note that we don't invalidate the 87411334Sandreas.hansson@arm.com // block in the current cache or any other cache on the 87511334Sandreas.hansson@arm.com // path to memory 87611051Sandreas.hansson@arm.com 87711334Sandreas.hansson@arm.com // create a downstream express snoop with cleared packet 87811334Sandreas.hansson@arm.com // flags, there is no need to allocate any data as the 87911334Sandreas.hansson@arm.com // packet is merely used to co-ordinate state transitions 88011334Sandreas.hansson@arm.com Packet *snoop_pkt = new Packet(pkt, true, false); 88111051Sandreas.hansson@arm.com 88211334Sandreas.hansson@arm.com // also reset the bus time that the original packet has 88311334Sandreas.hansson@arm.com // not yet paid for 88411334Sandreas.hansson@arm.com snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0; 88511051Sandreas.hansson@arm.com 88611334Sandreas.hansson@arm.com // make this an instantaneous express snoop, and let the 88711334Sandreas.hansson@arm.com // other caches in the system know that the another cache 88811334Sandreas.hansson@arm.com // is responding, because we have found the authorative 88911334Sandreas.hansson@arm.com // copy (Modified or Owned) that will supply the right 89011334Sandreas.hansson@arm.com // data 89111334Sandreas.hansson@arm.com snoop_pkt->setExpressSnoop(); 89211334Sandreas.hansson@arm.com snoop_pkt->setCacheResponding(); 89311051Sandreas.hansson@arm.com 89411334Sandreas.hansson@arm.com // this express snoop travels towards the memory, and at 89511334Sandreas.hansson@arm.com // every crossbar it is snooped upwards thus reaching 89611334Sandreas.hansson@arm.com // every cache in the system 89711334Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(snoop_pkt); 89811334Sandreas.hansson@arm.com // express snoops always succeed 89911334Sandreas.hansson@arm.com assert(success); 90011334Sandreas.hansson@arm.com 90111334Sandreas.hansson@arm.com // main memory will delete the snoop packet 90211051Sandreas.hansson@arm.com 90311284Sandreas.hansson@arm.com // queue for deletion, as opposed to immediate deletion, as 90411284Sandreas.hansson@arm.com // the sending cache is still relying on the packet 90511190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 90611051Sandreas.hansson@arm.com 90711334Sandreas.hansson@arm.com // no need to take any further action in this particular cache 90811334Sandreas.hansson@arm.com // as an upstram cache has already committed to responding, 90911334Sandreas.hansson@arm.com // and we have already sent out any express snoops in the 91011334Sandreas.hansson@arm.com // section above to ensure all other copies in the system are 91111334Sandreas.hansson@arm.com // invalidated 91212630Snikos.nikoleris@arm.com return; 91311051Sandreas.hansson@arm.com } 91411051Sandreas.hansson@arm.com 91511051Sandreas.hansson@arm.com // anything that is merely forwarded pays for the forward latency and 91611051Sandreas.hansson@arm.com // the delay provided by the crossbar 91711051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 91811051Sandreas.hansson@arm.com 91911051Sandreas.hansson@arm.com // We use lookupLatency here because it is used to specify the latency 92011051Sandreas.hansson@arm.com // to access. 92111051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 92211484Snikos.nikoleris@arm.com CacheBlk *blk = nullptr; 92311051Sandreas.hansson@arm.com bool satisfied = false; 92411051Sandreas.hansson@arm.com { 92511051Sandreas.hansson@arm.com PacketList writebacks; 92611051Sandreas.hansson@arm.com // Note that lat is passed by reference here. The function 92711051Sandreas.hansson@arm.com // access() calls accessBlock() which can modify lat value. 92811051Sandreas.hansson@arm.com satisfied = access(pkt, blk, lat, writebacks); 92911051Sandreas.hansson@arm.com 93011051Sandreas.hansson@arm.com // copy writebacks to write buffer here to ensure they logically 93111051Sandreas.hansson@arm.com // proceed anything happening below 93211051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 93311051Sandreas.hansson@arm.com } 93411051Sandreas.hansson@arm.com 93511051Sandreas.hansson@arm.com // Here we charge the headerDelay that takes into account the latencies 93611051Sandreas.hansson@arm.com // of the bus, if the packet comes from it. 93711051Sandreas.hansson@arm.com // The latency charged it is just lat that is the value of lookupLatency 93811051Sandreas.hansson@arm.com // modified by access() function, or if not just lookupLatency. 93911051Sandreas.hansson@arm.com // In case of a hit we are neglecting response latency. 94011051Sandreas.hansson@arm.com // In case of a miss we are neglecting forward latency. 94111051Sandreas.hansson@arm.com Tick request_time = clockEdge(lat) + pkt->headerDelay; 94211051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 94311051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 94411051Sandreas.hansson@arm.com 94511051Sandreas.hansson@arm.com // track time of availability of next prefetch, if any 94611051Sandreas.hansson@arm.com Tick next_pf_time = MaxTick; 94711051Sandreas.hansson@arm.com 94811051Sandreas.hansson@arm.com if (satisfied) { 94912720Snikos.nikoleris@arm.com // if need to notify the prefetcher we need to do it anything 95012720Snikos.nikoleris@arm.com // else, handleTimingReqHit might turn the packet into a 95112720Snikos.nikoleris@arm.com // response 95212720Snikos.nikoleris@arm.com if (prefetcher && 95312720Snikos.nikoleris@arm.com (prefetchOnAccess || (blk && blk->wasPrefetched()))) { 95411051Sandreas.hansson@arm.com if (blk) 95511051Sandreas.hansson@arm.com blk->status &= ~BlkHWPrefetched; 95611051Sandreas.hansson@arm.com 95711051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 95812349Snikos.nikoleris@arm.com if (!pkt->cmd.isSWPrefetch()) { 95912349Snikos.nikoleris@arm.com assert(!pkt->req->isCacheMaintenance()); 96011051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 96112349Snikos.nikoleris@arm.com } 96211051Sandreas.hansson@arm.com } 96311051Sandreas.hansson@arm.com 96412720Snikos.nikoleris@arm.com handleTimingReqHit(pkt, blk, request_time); 96511051Sandreas.hansson@arm.com } else { 96612720Snikos.nikoleris@arm.com handleTimingReqMiss(pkt, blk, forward_time, request_time); 96712720Snikos.nikoleris@arm.com 96812720Snikos.nikoleris@arm.com // We should call the prefetcher reguardless if the request is 96912720Snikos.nikoleris@arm.com // satisfied or not, reguardless if the request is in the MSHR 97012720Snikos.nikoleris@arm.com // or not. The request could be a ReadReq hit, but still not 97112720Snikos.nikoleris@arm.com // satisfied (potentially because of a prior write to the same 97212720Snikos.nikoleris@arm.com // cache line. So, even when not satisfied, there is an MSHR 97312720Snikos.nikoleris@arm.com // already allocated for this, we need to let the prefetcher 97412720Snikos.nikoleris@arm.com // know about the request 97512720Snikos.nikoleris@arm.com if (prefetcher && pkt && 97612720Snikos.nikoleris@arm.com !pkt->cmd.isSWPrefetch() && 97712720Snikos.nikoleris@arm.com !pkt->req->isCacheMaintenance()) { 97812720Snikos.nikoleris@arm.com next_pf_time = prefetcher->notify(pkt); 97911051Sandreas.hansson@arm.com } 98011051Sandreas.hansson@arm.com } 98111051Sandreas.hansson@arm.com 98211051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 98311051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 98411051Sandreas.hansson@arm.com} 98511051Sandreas.hansson@arm.com 98611051Sandreas.hansson@arm.comPacketPtr 98711452Sandreas.hansson@arm.comCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 98811452Sandreas.hansson@arm.com bool needsWritable) const 98911051Sandreas.hansson@arm.com{ 99011452Sandreas.hansson@arm.com // should never see evictions here 99111452Sandreas.hansson@arm.com assert(!cpu_pkt->isEviction()); 99211452Sandreas.hansson@arm.com 99311051Sandreas.hansson@arm.com bool blkValid = blk && blk->isValid(); 99411051Sandreas.hansson@arm.com 99511452Sandreas.hansson@arm.com if (cpu_pkt->req->isUncacheable() || 99611745Sandreas.hansson@arm.com (!blkValid && cpu_pkt->isUpgrade()) || 99712349Snikos.nikoleris@arm.com cpu_pkt->cmd == MemCmd::InvalidateReq || cpu_pkt->isClean()) { 99811452Sandreas.hansson@arm.com // uncacheable requests and upgrades from upper-level caches 99911452Sandreas.hansson@arm.com // that missed completely just go through as is 100011452Sandreas.hansson@arm.com return nullptr; 100111051Sandreas.hansson@arm.com } 100211051Sandreas.hansson@arm.com 100311051Sandreas.hansson@arm.com assert(cpu_pkt->needsResponse()); 100411051Sandreas.hansson@arm.com 100511051Sandreas.hansson@arm.com MemCmd cmd; 100611051Sandreas.hansson@arm.com // @TODO make useUpgrades a parameter. 100711051Sandreas.hansson@arm.com // Note that ownership protocols require upgrade, otherwise a 100811051Sandreas.hansson@arm.com // write miss on a shared owned block will generate a ReadExcl, 100911051Sandreas.hansson@arm.com // which will clobber the owned copy. 101011051Sandreas.hansson@arm.com const bool useUpgrades = true; 101111747Snikos.nikoleris@arm.com if (cpu_pkt->cmd == MemCmd::WriteLineReq) { 101211747Snikos.nikoleris@arm.com assert(!blkValid || !blk->isWritable()); 101311747Snikos.nikoleris@arm.com // forward as invalidate to all other caches, this gives us 101411747Snikos.nikoleris@arm.com // the line in Exclusive state, and invalidates all other 101511747Snikos.nikoleris@arm.com // copies 101611747Snikos.nikoleris@arm.com cmd = MemCmd::InvalidateReq; 101711747Snikos.nikoleris@arm.com } else if (blkValid && useUpgrades) { 101811284Sandreas.hansson@arm.com // only reason to be here is that blk is read only and we need 101911284Sandreas.hansson@arm.com // it to be writable 102011284Sandreas.hansson@arm.com assert(needsWritable); 102111051Sandreas.hansson@arm.com assert(!blk->isWritable()); 102211051Sandreas.hansson@arm.com cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq; 102311051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq || 102411051Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::StoreCondFailReq) { 102511051Sandreas.hansson@arm.com // Even though this SC will fail, we still need to send out the 102611051Sandreas.hansson@arm.com // request and get the data to supply it to other snoopers in the case 102711051Sandreas.hansson@arm.com // where the determination the StoreCond fails is delayed due to 102811051Sandreas.hansson@arm.com // all caches not being on the same local bus. 102911051Sandreas.hansson@arm.com cmd = MemCmd::SCUpgradeFailReq; 103011051Sandreas.hansson@arm.com } else { 103111051Sandreas.hansson@arm.com // block is invalid 103212425Snikos.nikoleris@arm.com 103312425Snikos.nikoleris@arm.com // If the request does not need a writable there are two cases 103412425Snikos.nikoleris@arm.com // where we need to ensure the response will not fetch the 103512425Snikos.nikoleris@arm.com // block in dirty state: 103612425Snikos.nikoleris@arm.com // * this cache is read only and it does not perform 103712425Snikos.nikoleris@arm.com // writebacks, 103812425Snikos.nikoleris@arm.com // * this cache is mostly exclusive and will not fill (since 103912425Snikos.nikoleris@arm.com // it does not fill it will have to writeback the dirty data 104012425Snikos.nikoleris@arm.com // immediately which generates uneccesary writebacks). 104112425Snikos.nikoleris@arm.com bool force_clean_rsp = isReadOnly || clusivity == Enums::mostly_excl; 104211284Sandreas.hansson@arm.com cmd = needsWritable ? MemCmd::ReadExReq : 104312425Snikos.nikoleris@arm.com (force_clean_rsp ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq); 104411051Sandreas.hansson@arm.com } 104511051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize); 104611051Sandreas.hansson@arm.com 104711284Sandreas.hansson@arm.com // if there are upstream caches that have already marked the 104811284Sandreas.hansson@arm.com // packet as having sharers (not passing writable), pass that info 104911284Sandreas.hansson@arm.com // downstream 105011602Sandreas.hansson@arm.com if (cpu_pkt->hasSharers() && !needsWritable) { 105111051Sandreas.hansson@arm.com // note that cpu_pkt may have spent a considerable time in the 105211051Sandreas.hansson@arm.com // MSHR queue and that the information could possibly be out 105311051Sandreas.hansson@arm.com // of date, however, there is no harm in conservatively 105411284Sandreas.hansson@arm.com // assuming the block has sharers 105511284Sandreas.hansson@arm.com pkt->setHasSharers(); 105611744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: passing hasSharers from %s to %s\n", 105711744Snikos.nikoleris@arm.com __func__, cpu_pkt->print(), pkt->print()); 105811051Sandreas.hansson@arm.com } 105911051Sandreas.hansson@arm.com 106011051Sandreas.hansson@arm.com // the packet should be block aligned 106111892Snikos.nikoleris@arm.com assert(pkt->getAddr() == pkt->getBlockAddr(blkSize)); 106211051Sandreas.hansson@arm.com 106311051Sandreas.hansson@arm.com pkt->allocate(); 106411744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: created %s from %s\n", __func__, pkt->print(), 106511744Snikos.nikoleris@arm.com cpu_pkt->print()); 106611051Sandreas.hansson@arm.com return pkt; 106711051Sandreas.hansson@arm.com} 106811051Sandreas.hansson@arm.com 106911051Sandreas.hansson@arm.com 107012721Snikos.nikoleris@arm.comCycles 107112721Snikos.nikoleris@arm.comCache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk, 107212721Snikos.nikoleris@arm.com PacketList &writebacks) 107312721Snikos.nikoleris@arm.com{ 107412721Snikos.nikoleris@arm.com // deal with the packets that go through the write path of 107512721Snikos.nikoleris@arm.com // the cache, i.e. any evictions and writes 107612721Snikos.nikoleris@arm.com if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean || 107712721Snikos.nikoleris@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 107812721Snikos.nikoleris@arm.com Cycles latency = ticksToCycles(memSidePort->sendAtomic(pkt)); 107912721Snikos.nikoleris@arm.com 108012721Snikos.nikoleris@arm.com // at this point, if the request was an uncacheable write 108112721Snikos.nikoleris@arm.com // request, it has been satisfied by a memory below and the 108212721Snikos.nikoleris@arm.com // packet carries the response back 108312721Snikos.nikoleris@arm.com assert(!(pkt->req->isUncacheable() && pkt->isWrite()) || 108412721Snikos.nikoleris@arm.com pkt->isResponse()); 108512721Snikos.nikoleris@arm.com 108612721Snikos.nikoleris@arm.com return latency; 108712721Snikos.nikoleris@arm.com } 108812721Snikos.nikoleris@arm.com 108912721Snikos.nikoleris@arm.com // only misses left 109012721Snikos.nikoleris@arm.com 109112721Snikos.nikoleris@arm.com PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable()); 109212721Snikos.nikoleris@arm.com 109312721Snikos.nikoleris@arm.com bool is_forward = (bus_pkt == nullptr); 109412721Snikos.nikoleris@arm.com 109512721Snikos.nikoleris@arm.com if (is_forward) { 109612721Snikos.nikoleris@arm.com // just forwarding the same request to the next level 109712721Snikos.nikoleris@arm.com // no local cache operation involved 109812721Snikos.nikoleris@arm.com bus_pkt = pkt; 109912721Snikos.nikoleris@arm.com } 110012721Snikos.nikoleris@arm.com 110112721Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Sending an atomic %s\n", __func__, 110212721Snikos.nikoleris@arm.com bus_pkt->print()); 110312721Snikos.nikoleris@arm.com 110412721Snikos.nikoleris@arm.com#if TRACING_ON 110512721Snikos.nikoleris@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 110612721Snikos.nikoleris@arm.com#endif 110712721Snikos.nikoleris@arm.com 110812721Snikos.nikoleris@arm.com Cycles latency = ticksToCycles(memSidePort->sendAtomic(bus_pkt)); 110912721Snikos.nikoleris@arm.com 111012721Snikos.nikoleris@arm.com bool is_invalidate = bus_pkt->isInvalidate(); 111112721Snikos.nikoleris@arm.com 111212721Snikos.nikoleris@arm.com // We are now dealing with the response handling 111312721Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Receive response: %s in state %i\n", __func__, 111412721Snikos.nikoleris@arm.com bus_pkt->print(), old_state); 111512721Snikos.nikoleris@arm.com 111612721Snikos.nikoleris@arm.com // If packet was a forward, the response (if any) is already 111712721Snikos.nikoleris@arm.com // in place in the bus_pkt == pkt structure, so we don't need 111812721Snikos.nikoleris@arm.com // to do anything. Otherwise, use the separate bus_pkt to 111912721Snikos.nikoleris@arm.com // generate response to pkt and then delete it. 112012721Snikos.nikoleris@arm.com if (!is_forward) { 112112721Snikos.nikoleris@arm.com if (pkt->needsResponse()) { 112212721Snikos.nikoleris@arm.com assert(bus_pkt->isResponse()); 112312721Snikos.nikoleris@arm.com if (bus_pkt->isError()) { 112412721Snikos.nikoleris@arm.com pkt->makeAtomicResponse(); 112512721Snikos.nikoleris@arm.com pkt->copyError(bus_pkt); 112612721Snikos.nikoleris@arm.com } else if (pkt->cmd == MemCmd::WriteLineReq) { 112712721Snikos.nikoleris@arm.com // note the use of pkt, not bus_pkt here. 112812721Snikos.nikoleris@arm.com 112912721Snikos.nikoleris@arm.com // write-line request to the cache that promoted 113012721Snikos.nikoleris@arm.com // the write to a whole line 113112721Snikos.nikoleris@arm.com blk = handleFill(pkt, blk, writebacks, 113212721Snikos.nikoleris@arm.com allocOnFill(pkt->cmd)); 113312721Snikos.nikoleris@arm.com assert(blk != NULL); 113412721Snikos.nikoleris@arm.com is_invalidate = false; 113512721Snikos.nikoleris@arm.com satisfyRequest(pkt, blk); 113612721Snikos.nikoleris@arm.com } else if (bus_pkt->isRead() || 113712721Snikos.nikoleris@arm.com bus_pkt->cmd == MemCmd::UpgradeResp) { 113812721Snikos.nikoleris@arm.com // we're updating cache state to allow us to 113912721Snikos.nikoleris@arm.com // satisfy the upstream request from the cache 114012721Snikos.nikoleris@arm.com blk = handleFill(bus_pkt, blk, writebacks, 114112721Snikos.nikoleris@arm.com allocOnFill(pkt->cmd)); 114212721Snikos.nikoleris@arm.com satisfyRequest(pkt, blk); 114312721Snikos.nikoleris@arm.com maintainClusivity(pkt->fromCache(), blk); 114412721Snikos.nikoleris@arm.com } else { 114512721Snikos.nikoleris@arm.com // we're satisfying the upstream request without 114612721Snikos.nikoleris@arm.com // modifying cache state, e.g., a write-through 114712721Snikos.nikoleris@arm.com pkt->makeAtomicResponse(); 114812721Snikos.nikoleris@arm.com } 114912721Snikos.nikoleris@arm.com } 115012721Snikos.nikoleris@arm.com delete bus_pkt; 115112721Snikos.nikoleris@arm.com } 115212721Snikos.nikoleris@arm.com 115312721Snikos.nikoleris@arm.com if (is_invalidate && blk && blk->isValid()) { 115412721Snikos.nikoleris@arm.com invalidateBlock(blk); 115512721Snikos.nikoleris@arm.com } 115612721Snikos.nikoleris@arm.com 115712721Snikos.nikoleris@arm.com return latency; 115812721Snikos.nikoleris@arm.com} 115912721Snikos.nikoleris@arm.com 116011051Sandreas.hansson@arm.comTick 116111051Sandreas.hansson@arm.comCache::recvAtomic(PacketPtr pkt) 116211051Sandreas.hansson@arm.com{ 116311051Sandreas.hansson@arm.com // We are in atomic mode so we pay just for lookupLatency here. 116411051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 116511051Sandreas.hansson@arm.com 116611051Sandreas.hansson@arm.com // Forward the request if the system is in cache bypass mode. 116711051Sandreas.hansson@arm.com if (system->bypassCaches()) 116811051Sandreas.hansson@arm.com return ticksToCycles(memSidePort->sendAtomic(pkt)); 116911051Sandreas.hansson@arm.com 117011051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 117111051Sandreas.hansson@arm.com 117211333Sandreas.hansson@arm.com // follow the same flow as in recvTimingReq, and check if a cache 117311333Sandreas.hansson@arm.com // above us is responding 117412349Snikos.nikoleris@arm.com if (pkt->cacheResponding() && !pkt->isClean()) { 117512349Snikos.nikoleris@arm.com assert(!pkt->req->isCacheInvalidate()); 117611744Snikos.nikoleris@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 117711744Snikos.nikoleris@arm.com pkt->print()); 117811333Sandreas.hansson@arm.com 117911333Sandreas.hansson@arm.com // if a cache is responding, and it had the line in Owned 118011333Sandreas.hansson@arm.com // rather than Modified state, we need to invalidate any 118111333Sandreas.hansson@arm.com // copies that are not on the same path to memory 118211334Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 118311334Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 118411051Sandreas.hansson@arm.com 118511051Sandreas.hansson@arm.com return lat * clockPeriod(); 118611051Sandreas.hansson@arm.com } 118711051Sandreas.hansson@arm.com 118811051Sandreas.hansson@arm.com // should assert here that there are no outstanding MSHRs or 118911051Sandreas.hansson@arm.com // writebacks... that would mean that someone used an atomic 119011051Sandreas.hansson@arm.com // access in timing mode 119111051Sandreas.hansson@arm.com 119211484Snikos.nikoleris@arm.com CacheBlk *blk = nullptr; 119311051Sandreas.hansson@arm.com PacketList writebacks; 119411051Sandreas.hansson@arm.com bool satisfied = access(pkt, blk, lat, writebacks); 119511051Sandreas.hansson@arm.com 119612349Snikos.nikoleris@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 119712349Snikos.nikoleris@arm.com // A cache clean opearation is looking for a dirty 119812349Snikos.nikoleris@arm.com // block. If a dirty block is encountered a WriteClean 119912349Snikos.nikoleris@arm.com // will update any copies to the path to the memory 120012349Snikos.nikoleris@arm.com // until the point of reference. 120112349Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 120212349Snikos.nikoleris@arm.com __func__, pkt->print(), blk->print()); 120312351Snikos.nikoleris@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id); 120412349Snikos.nikoleris@arm.com writebacks.push_back(wb_pkt); 120512349Snikos.nikoleris@arm.com pkt->setSatisfied(); 120612349Snikos.nikoleris@arm.com } 120712349Snikos.nikoleris@arm.com 120811051Sandreas.hansson@arm.com // handle writebacks resulting from the access here to ensure they 120911051Sandreas.hansson@arm.com // logically proceed anything happening below 121011130Sali.jafri@arm.com doWritebacksAtomic(writebacks); 121112721Snikos.nikoleris@arm.com assert(writebacks.empty()); 121211051Sandreas.hansson@arm.com 121311051Sandreas.hansson@arm.com if (!satisfied) { 121412721Snikos.nikoleris@arm.com lat += handleAtomicReqMiss(pkt, blk, writebacks); 121511051Sandreas.hansson@arm.com } 121611051Sandreas.hansson@arm.com 121711051Sandreas.hansson@arm.com // Note that we don't invoke the prefetcher at all in atomic mode. 121811051Sandreas.hansson@arm.com // It's not clear how to do it properly, particularly for 121911051Sandreas.hansson@arm.com // prefetchers that aggressively generate prefetch candidates and 122011051Sandreas.hansson@arm.com // rely on bandwidth contention to throttle them; these will tend 122111051Sandreas.hansson@arm.com // to pollute the cache in atomic mode since there is no bandwidth 122211051Sandreas.hansson@arm.com // contention. If we ever do want to enable prefetching in atomic 122311051Sandreas.hansson@arm.com // mode, though, this is the place to do it... see timingAccess() 122411051Sandreas.hansson@arm.com // for an example (though we'd want to issue the prefetch(es) 122511051Sandreas.hansson@arm.com // immediately rather than calling requestMemSideBus() as we do 122611051Sandreas.hansson@arm.com // there). 122711051Sandreas.hansson@arm.com 122811197Sandreas.hansson@arm.com // do any writebacks resulting from the response handling 122911130Sali.jafri@arm.com doWritebacksAtomic(writebacks); 123011051Sandreas.hansson@arm.com 123111197Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and if so 123211197Sandreas.hansson@arm.com // clear it out, but only do so after the call to recvAtomic is 123311197Sandreas.hansson@arm.com // finished so that any downstream observers (such as a snoop 123411197Sandreas.hansson@arm.com // filter), first see the fill, and only then see the eviction 123511197Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 123611197Sandreas.hansson@arm.com // the atomic CPU calls recvAtomic for fetch and load/store 123711197Sandreas.hansson@arm.com // sequentuially, and we may already have a tempBlock 123811197Sandreas.hansson@arm.com // writeback from the fetch that we have not yet sent 123911197Sandreas.hansson@arm.com if (tempBlockWriteback) { 124011197Sandreas.hansson@arm.com // if that is the case, write the prevoius one back, and 124111197Sandreas.hansson@arm.com // do not schedule any new event 124211197Sandreas.hansson@arm.com writebackTempBlockAtomic(); 124311197Sandreas.hansson@arm.com } else { 124411197Sandreas.hansson@arm.com // the writeback/clean eviction happens after the call to 124511197Sandreas.hansson@arm.com // recvAtomic has finished (but before any successive 124611197Sandreas.hansson@arm.com // calls), so that the response handling from the fill is 124711197Sandreas.hansson@arm.com // allowed to happen first 124811197Sandreas.hansson@arm.com schedule(writebackTempBlockAtomicEvent, curTick()); 124911197Sandreas.hansson@arm.com } 125011197Sandreas.hansson@arm.com 125111199Sandreas.hansson@arm.com tempBlockWriteback = (blk->isDirty() || writebackClean) ? 125211199Sandreas.hansson@arm.com writebackBlk(blk) : cleanEvictBlk(blk); 125311867Snikos.nikoleris@arm.com invalidateBlock(blk); 125411197Sandreas.hansson@arm.com } 125511197Sandreas.hansson@arm.com 125611051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 125711051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 125811051Sandreas.hansson@arm.com } 125911051Sandreas.hansson@arm.com 126011051Sandreas.hansson@arm.com return lat * clockPeriod(); 126111051Sandreas.hansson@arm.com} 126211051Sandreas.hansson@arm.com 126311051Sandreas.hansson@arm.com 126411051Sandreas.hansson@arm.comvoid 126511051Sandreas.hansson@arm.comCache::functionalAccess(PacketPtr pkt, bool fromCpuSide) 126611051Sandreas.hansson@arm.com{ 126711051Sandreas.hansson@arm.com if (system->bypassCaches()) { 126811051Sandreas.hansson@arm.com // Packets from the memory side are snoop request and 126911051Sandreas.hansson@arm.com // shouldn't happen in bypass mode. 127011051Sandreas.hansson@arm.com assert(fromCpuSide); 127111051Sandreas.hansson@arm.com 127211051Sandreas.hansson@arm.com // The cache should be flushed if we are in cache bypass mode, 127311051Sandreas.hansson@arm.com // so we don't need to check if we need to update anything. 127411051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 127511051Sandreas.hansson@arm.com return; 127611051Sandreas.hansson@arm.com } 127711051Sandreas.hansson@arm.com 127811892Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 127911051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 128011051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 128111051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 128211051Sandreas.hansson@arm.com 128311051Sandreas.hansson@arm.com pkt->pushLabel(name()); 128411051Sandreas.hansson@arm.com 128511051Sandreas.hansson@arm.com CacheBlkPrintWrapper cbpw(blk); 128611051Sandreas.hansson@arm.com 128711051Sandreas.hansson@arm.com // Note that just because an L2/L3 has valid data doesn't mean an 128811051Sandreas.hansson@arm.com // L1 doesn't have a more up-to-date modified copy that still 128911051Sandreas.hansson@arm.com // needs to be found. As a result we always update the request if 129011051Sandreas.hansson@arm.com // we have it, but only declare it satisfied if we are the owner. 129111051Sandreas.hansson@arm.com 129211051Sandreas.hansson@arm.com // see if we have data at all (owned or otherwise) 129311051Sandreas.hansson@arm.com bool have_data = blk && blk->isValid() 129411051Sandreas.hansson@arm.com && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize, 129511051Sandreas.hansson@arm.com blk->data); 129611051Sandreas.hansson@arm.com 129711284Sandreas.hansson@arm.com // data we have is dirty if marked as such or if we have an 129811284Sandreas.hansson@arm.com // in-service MSHR that is pending a modified line 129911051Sandreas.hansson@arm.com bool have_dirty = 130011051Sandreas.hansson@arm.com have_data && (blk->isDirty() || 130111284Sandreas.hansson@arm.com (mshr && mshr->inService && mshr->isPendingModified())); 130211051Sandreas.hansson@arm.com 130311051Sandreas.hansson@arm.com bool done = have_dirty 130411051Sandreas.hansson@arm.com || cpuSidePort->checkFunctional(pkt) 130511051Sandreas.hansson@arm.com || mshrQueue.checkFunctional(pkt, blk_addr) 130611051Sandreas.hansson@arm.com || writeBuffer.checkFunctional(pkt, blk_addr) 130711051Sandreas.hansson@arm.com || memSidePort->checkFunctional(pkt); 130811051Sandreas.hansson@arm.com 130911744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: %s %s%s%s\n", __func__, pkt->print(), 131011051Sandreas.hansson@arm.com (blk && blk->isValid()) ? "valid " : "", 131111051Sandreas.hansson@arm.com have_data ? "data " : "", done ? "done " : ""); 131211051Sandreas.hansson@arm.com 131311051Sandreas.hansson@arm.com // We're leaving the cache, so pop cache->name() label 131411051Sandreas.hansson@arm.com pkt->popLabel(); 131511051Sandreas.hansson@arm.com 131611051Sandreas.hansson@arm.com if (done) { 131711051Sandreas.hansson@arm.com pkt->makeResponse(); 131811051Sandreas.hansson@arm.com } else { 131911051Sandreas.hansson@arm.com // if it came as a request from the CPU side then make sure it 132011051Sandreas.hansson@arm.com // continues towards the memory side 132111051Sandreas.hansson@arm.com if (fromCpuSide) { 132211051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 132311485Snikos.nikoleris@arm.com } else if (cpuSidePort->isSnooping()) { 132411051Sandreas.hansson@arm.com // if it came from the memory side, it must be a snoop request 132511051Sandreas.hansson@arm.com // and we should only forward it if we are forwarding snoops 132611051Sandreas.hansson@arm.com cpuSidePort->sendFunctionalSnoop(pkt); 132711051Sandreas.hansson@arm.com } 132811051Sandreas.hansson@arm.com } 132911051Sandreas.hansson@arm.com} 133011051Sandreas.hansson@arm.com 133111051Sandreas.hansson@arm.com 133211051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 133311051Sandreas.hansson@arm.com// 133411051Sandreas.hansson@arm.com// Response handling: responses from the memory side 133511051Sandreas.hansson@arm.com// 133611051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 133711051Sandreas.hansson@arm.com 133811051Sandreas.hansson@arm.com 133911051Sandreas.hansson@arm.comvoid 134011375Sandreas.hansson@arm.comCache::handleUncacheableWriteResp(PacketPtr pkt) 134111375Sandreas.hansson@arm.com{ 134211375Sandreas.hansson@arm.com Tick completion_time = clockEdge(responseLatency) + 134311375Sandreas.hansson@arm.com pkt->headerDelay + pkt->payloadDelay; 134411375Sandreas.hansson@arm.com 134511453Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 134611453Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 134711375Sandreas.hansson@arm.com 134811453Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(pkt, completion_time, true); 134911375Sandreas.hansson@arm.com} 135011375Sandreas.hansson@arm.com 135111375Sandreas.hansson@arm.comvoid 135212719Snikos.nikoleris@arm.comCache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk, 135312719Snikos.nikoleris@arm.com PacketList &writebacks) 135411051Sandreas.hansson@arm.com{ 135511051Sandreas.hansson@arm.com MSHR::Target *initial_tgt = mshr->getTarget(); 135612719Snikos.nikoleris@arm.com // First offset for critical word first calculations 135712719Snikos.nikoleris@arm.com const int initial_offset = initial_tgt->pkt->getOffset(blkSize); 135812719Snikos.nikoleris@arm.com 135912719Snikos.nikoleris@arm.com const bool is_error = pkt->isError(); 136012348Snikos.nikoleris@arm.com bool is_fill = !mshr->isForward && 136112348Snikos.nikoleris@arm.com (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp); 136211051Sandreas.hansson@arm.com // allow invalidation responses originating from write-line 136311051Sandreas.hansson@arm.com // requests to be discarded 136411136Sandreas.hansson@arm.com bool is_invalidate = pkt->isInvalidate(); 136511051Sandreas.hansson@arm.com 136611742Snikos.nikoleris@arm.com MSHR::TargetList targets = mshr->extractServiceableTargets(pkt); 136711742Snikos.nikoleris@arm.com for (auto &target: targets) { 136811742Snikos.nikoleris@arm.com Packet *tgt_pkt = target.pkt; 136911742Snikos.nikoleris@arm.com switch (target.source) { 137011051Sandreas.hansson@arm.com case MSHR::Target::FromCPU: 137111051Sandreas.hansson@arm.com Tick completion_time; 137211051Sandreas.hansson@arm.com // Here we charge on completion_time the delay of the xbar if the 137311051Sandreas.hansson@arm.com // packet comes from it, charged on headerDelay. 137411051Sandreas.hansson@arm.com completion_time = pkt->headerDelay; 137511051Sandreas.hansson@arm.com 137611051Sandreas.hansson@arm.com // Software prefetch handling for cache closest to core 137711051Sandreas.hansson@arm.com if (tgt_pkt->cmd.isSWPrefetch()) { 137811483Snikos.nikoleris@arm.com // a software prefetch would have already been ack'd 137911483Snikos.nikoleris@arm.com // immediately with dummy data so the core would be able to 138011483Snikos.nikoleris@arm.com // retire it. This request completes right here, so we 138111483Snikos.nikoleris@arm.com // deallocate it. 138211051Sandreas.hansson@arm.com delete tgt_pkt->req; 138311051Sandreas.hansson@arm.com delete tgt_pkt; 138411051Sandreas.hansson@arm.com break; // skip response 138511051Sandreas.hansson@arm.com } 138611051Sandreas.hansson@arm.com 138711051Sandreas.hansson@arm.com // unlike the other packet flows, where data is found in other 138811051Sandreas.hansson@arm.com // caches or memory and brought back, write-line requests always 138911051Sandreas.hansson@arm.com // have the data right away, so the above check for "is fill?" 139011051Sandreas.hansson@arm.com // cannot actually be determined until examining the stored MSHR 139111051Sandreas.hansson@arm.com // state. We "catch up" with that logic here, which is duplicated 139211051Sandreas.hansson@arm.com // from above. 139311051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::WriteLineReq) { 139411051Sandreas.hansson@arm.com assert(!is_error); 139511284Sandreas.hansson@arm.com // we got the block in a writable state, so promote 139611284Sandreas.hansson@arm.com // any deferred targets if possible 139711284Sandreas.hansson@arm.com mshr->promoteWritable(); 139811051Sandreas.hansson@arm.com // NB: we use the original packet here and not the response! 139911741Snikos.nikoleris@arm.com blk = handleFill(tgt_pkt, blk, writebacks, 140011742Snikos.nikoleris@arm.com targets.allocOnFill); 140112719Snikos.nikoleris@arm.com assert(blk); 140211051Sandreas.hansson@arm.com 140311051Sandreas.hansson@arm.com // treat as a fill, and discard the invalidation 140411051Sandreas.hansson@arm.com // response 140511051Sandreas.hansson@arm.com is_fill = true; 140611136Sandreas.hansson@arm.com is_invalidate = false; 140711051Sandreas.hansson@arm.com } 140811051Sandreas.hansson@arm.com 140911051Sandreas.hansson@arm.com if (is_fill) { 141011601Sandreas.hansson@arm.com satisfyRequest(tgt_pkt, blk, true, mshr->hasPostDowngrade()); 141111051Sandreas.hansson@arm.com 141211051Sandreas.hansson@arm.com // How many bytes past the first request is this one 141311051Sandreas.hansson@arm.com int transfer_offset = 141411051Sandreas.hansson@arm.com tgt_pkt->getOffset(blkSize) - initial_offset; 141511051Sandreas.hansson@arm.com if (transfer_offset < 0) { 141611051Sandreas.hansson@arm.com transfer_offset += blkSize; 141711051Sandreas.hansson@arm.com } 141811051Sandreas.hansson@arm.com 141911051Sandreas.hansson@arm.com // If not critical word (offset) return payloadDelay. 142011051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 142111051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 142211051Sandreas.hansson@arm.com // the core. 142311051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 142411051Sandreas.hansson@arm.com (transfer_offset ? pkt->payloadDelay : 0); 142511051Sandreas.hansson@arm.com 142611051Sandreas.hansson@arm.com assert(!tgt_pkt->req->isUncacheable()); 142711051Sandreas.hansson@arm.com 142811051Sandreas.hansson@arm.com assert(tgt_pkt->req->masterId() < system->maxMasters()); 142911051Sandreas.hansson@arm.com missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] += 143011742Snikos.nikoleris@arm.com completion_time - target.recvTime; 143111051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::UpgradeFailResp) { 143211051Sandreas.hansson@arm.com // failed StoreCond upgrade 143311051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::StoreCondReq || 143411051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::StoreCondFailReq || 143511051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::SCUpgradeFailReq); 143611051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 143711051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 143811051Sandreas.hansson@arm.com // the core. 143911051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 144011051Sandreas.hansson@arm.com pkt->payloadDelay; 144111051Sandreas.hansson@arm.com tgt_pkt->req->setExtraData(0); 144211051Sandreas.hansson@arm.com } else { 144311750Snikos.nikoleris@arm.com // We are about to send a response to a cache above 144411750Snikos.nikoleris@arm.com // that asked for an invalidation; we need to 144511750Snikos.nikoleris@arm.com // invalidate our copy immediately as the most 144611750Snikos.nikoleris@arm.com // up-to-date copy of the block will now be in the 144711750Snikos.nikoleris@arm.com // cache above. It will also prevent this cache from 144811750Snikos.nikoleris@arm.com // responding (if the block was previously dirty) to 144911750Snikos.nikoleris@arm.com // snoops as they should snoop the caches above where 145011750Snikos.nikoleris@arm.com // they will get the response from. 145111750Snikos.nikoleris@arm.com if (is_invalidate && blk && blk->isValid()) { 145211750Snikos.nikoleris@arm.com invalidateBlock(blk); 145311750Snikos.nikoleris@arm.com } 145411051Sandreas.hansson@arm.com // not a cache fill, just forwarding response 145511051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 145611051Sandreas.hansson@arm.com // from lower level cahces/memory to the core. 145711051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 145811051Sandreas.hansson@arm.com pkt->payloadDelay; 145911051Sandreas.hansson@arm.com if (pkt->isRead() && !is_error) { 146011051Sandreas.hansson@arm.com // sanity check 146111051Sandreas.hansson@arm.com assert(pkt->getAddr() == tgt_pkt->getAddr()); 146211051Sandreas.hansson@arm.com assert(pkt->getSize() >= tgt_pkt->getSize()); 146311051Sandreas.hansson@arm.com 146411051Sandreas.hansson@arm.com tgt_pkt->setData(pkt->getConstPtr<uint8_t>()); 146511051Sandreas.hansson@arm.com } 146611051Sandreas.hansson@arm.com } 146711051Sandreas.hansson@arm.com tgt_pkt->makeTimingResponse(); 146811051Sandreas.hansson@arm.com // if this packet is an error copy that to the new packet 146911051Sandreas.hansson@arm.com if (is_error) 147011051Sandreas.hansson@arm.com tgt_pkt->copyError(pkt); 147111051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::ReadResp && 147211136Sandreas.hansson@arm.com (is_invalidate || mshr->hasPostInvalidate())) { 147311051Sandreas.hansson@arm.com // If intermediate cache got ReadRespWithInvalidate, 147411051Sandreas.hansson@arm.com // propagate that. Response should not have 147511051Sandreas.hansson@arm.com // isInvalidate() set otherwise. 147611051Sandreas.hansson@arm.com tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate; 147711744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: updated cmd to %s\n", __func__, 147811744Snikos.nikoleris@arm.com tgt_pkt->print()); 147911051Sandreas.hansson@arm.com } 148011051Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 148111051Sandreas.hansson@arm.com tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; 148211194Sali.jafri@arm.com cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true); 148311051Sandreas.hansson@arm.com break; 148411051Sandreas.hansson@arm.com 148511051Sandreas.hansson@arm.com case MSHR::Target::FromPrefetcher: 148611051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::HardPFReq); 148711051Sandreas.hansson@arm.com if (blk) 148811051Sandreas.hansson@arm.com blk->status |= BlkHWPrefetched; 148911051Sandreas.hansson@arm.com delete tgt_pkt->req; 149011051Sandreas.hansson@arm.com delete tgt_pkt; 149111051Sandreas.hansson@arm.com break; 149211051Sandreas.hansson@arm.com 149311051Sandreas.hansson@arm.com case MSHR::Target::FromSnoop: 149411051Sandreas.hansson@arm.com // I don't believe that a snoop can be in an error state 149511051Sandreas.hansson@arm.com assert(!is_error); 149611051Sandreas.hansson@arm.com // response to snoop request 149711051Sandreas.hansson@arm.com DPRINTF(Cache, "processing deferred snoop...\n"); 149811749Snikos.nikoleris@arm.com // If the response is invalidating, a snooping target can 149911749Snikos.nikoleris@arm.com // be satisfied if it is also invalidating. If the reponse is, not 150012349Snikos.nikoleris@arm.com // only invalidating, but more specifically an InvalidateResp and 150112349Snikos.nikoleris@arm.com // the MSHR was created due to an InvalidateReq then a cache above 150212349Snikos.nikoleris@arm.com // is waiting to satisfy a WriteLineReq. In this case even an 150311749Snikos.nikoleris@arm.com // non-invalidating snoop is added as a target here since this is 150411749Snikos.nikoleris@arm.com // the ordering point. When the InvalidateResp reaches this cache, 150511749Snikos.nikoleris@arm.com // the snooping target will snoop further the cache above with the 150611749Snikos.nikoleris@arm.com // WriteLineReq. 150712349Snikos.nikoleris@arm.com assert(!is_invalidate || pkt->cmd == MemCmd::InvalidateResp || 150812349Snikos.nikoleris@arm.com pkt->req->isCacheMaintenance() || 150912349Snikos.nikoleris@arm.com mshr->hasPostInvalidate()); 151011051Sandreas.hansson@arm.com handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate()); 151111051Sandreas.hansson@arm.com break; 151211051Sandreas.hansson@arm.com 151311051Sandreas.hansson@arm.com default: 151411742Snikos.nikoleris@arm.com panic("Illegal target->source enum %d\n", target.source); 151511051Sandreas.hansson@arm.com } 151611051Sandreas.hansson@arm.com } 151711051Sandreas.hansson@arm.com 151812715Snikos.nikoleris@arm.com maintainClusivity(targets.hasFromCache, blk); 151911601Sandreas.hansson@arm.com 152011051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 152111051Sandreas.hansson@arm.com // an invalidate response stemming from a write line request 152211051Sandreas.hansson@arm.com // should not invalidate the block, so check if the 152311051Sandreas.hansson@arm.com // invalidation should be discarded 152411136Sandreas.hansson@arm.com if (is_invalidate || mshr->hasPostInvalidate()) { 152511197Sandreas.hansson@arm.com invalidateBlock(blk); 152611051Sandreas.hansson@arm.com } else if (mshr->hasPostDowngrade()) { 152711051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 152811051Sandreas.hansson@arm.com } 152911051Sandreas.hansson@arm.com } 153012719Snikos.nikoleris@arm.com} 153112719Snikos.nikoleris@arm.com 153212719Snikos.nikoleris@arm.comvoid 153312719Snikos.nikoleris@arm.comCache::recvTimingResp(PacketPtr pkt) 153412719Snikos.nikoleris@arm.com{ 153512719Snikos.nikoleris@arm.com assert(pkt->isResponse()); 153612719Snikos.nikoleris@arm.com 153712719Snikos.nikoleris@arm.com // all header delay should be paid for by the crossbar, unless 153812719Snikos.nikoleris@arm.com // this is a prefetch response from above 153912719Snikos.nikoleris@arm.com panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 154012719Snikos.nikoleris@arm.com "%s saw a non-zero packet delay\n", name()); 154112719Snikos.nikoleris@arm.com 154212719Snikos.nikoleris@arm.com const bool is_error = pkt->isError(); 154312719Snikos.nikoleris@arm.com 154412719Snikos.nikoleris@arm.com if (is_error) { 154512719Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Cache received %s with error\n", __func__, 154612719Snikos.nikoleris@arm.com pkt->print()); 154712719Snikos.nikoleris@arm.com } 154812719Snikos.nikoleris@arm.com 154912719Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Handling response %s\n", __func__, 155012719Snikos.nikoleris@arm.com pkt->print()); 155112719Snikos.nikoleris@arm.com 155212719Snikos.nikoleris@arm.com // if this is a write, we should be looking at an uncacheable 155312719Snikos.nikoleris@arm.com // write 155412719Snikos.nikoleris@arm.com if (pkt->isWrite()) { 155512719Snikos.nikoleris@arm.com assert(pkt->req->isUncacheable()); 155612719Snikos.nikoleris@arm.com handleUncacheableWriteResp(pkt); 155712719Snikos.nikoleris@arm.com return; 155812719Snikos.nikoleris@arm.com } 155912719Snikos.nikoleris@arm.com 156012719Snikos.nikoleris@arm.com // we have dealt with any (uncacheable) writes above, from here on 156112719Snikos.nikoleris@arm.com // we know we are dealing with an MSHR due to a miss or a prefetch 156212719Snikos.nikoleris@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState()); 156312719Snikos.nikoleris@arm.com assert(mshr); 156412719Snikos.nikoleris@arm.com 156512719Snikos.nikoleris@arm.com if (mshr == noTargetMSHR) { 156612719Snikos.nikoleris@arm.com // we always clear at least one target 156712719Snikos.nikoleris@arm.com clearBlocked(Blocked_NoTargets); 156812719Snikos.nikoleris@arm.com noTargetMSHR = nullptr; 156912719Snikos.nikoleris@arm.com } 157012719Snikos.nikoleris@arm.com 157112719Snikos.nikoleris@arm.com // Initial target is used just for stats 157212719Snikos.nikoleris@arm.com MSHR::Target *initial_tgt = mshr->getTarget(); 157312719Snikos.nikoleris@arm.com int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 157412719Snikos.nikoleris@arm.com Tick miss_latency = curTick() - initial_tgt->recvTime; 157512719Snikos.nikoleris@arm.com 157612719Snikos.nikoleris@arm.com if (pkt->req->isUncacheable()) { 157712719Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 157812719Snikos.nikoleris@arm.com mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 157912719Snikos.nikoleris@arm.com miss_latency; 158012719Snikos.nikoleris@arm.com } else { 158112719Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 158212719Snikos.nikoleris@arm.com mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 158312719Snikos.nikoleris@arm.com miss_latency; 158412719Snikos.nikoleris@arm.com } 158512719Snikos.nikoleris@arm.com 158612719Snikos.nikoleris@arm.com PacketList writebacks; 158712719Snikos.nikoleris@arm.com 158812719Snikos.nikoleris@arm.com bool is_fill = !mshr->isForward && 158912719Snikos.nikoleris@arm.com (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp); 159012719Snikos.nikoleris@arm.com 159112719Snikos.nikoleris@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 159212719Snikos.nikoleris@arm.com 159312719Snikos.nikoleris@arm.com if (is_fill && !is_error) { 159412719Snikos.nikoleris@arm.com DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 159512719Snikos.nikoleris@arm.com pkt->getAddr()); 159612719Snikos.nikoleris@arm.com 159712719Snikos.nikoleris@arm.com blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill()); 159812719Snikos.nikoleris@arm.com assert(blk != nullptr); 159912719Snikos.nikoleris@arm.com } 160012719Snikos.nikoleris@arm.com 160112719Snikos.nikoleris@arm.com if (blk && blk->isValid() && pkt->isClean() && !pkt->isInvalidate()) { 160212719Snikos.nikoleris@arm.com // The block was marked not readable while there was a pending 160312719Snikos.nikoleris@arm.com // cache maintenance operation, restore its flag. 160412719Snikos.nikoleris@arm.com blk->status |= BlkReadable; 160512719Snikos.nikoleris@arm.com } 160612719Snikos.nikoleris@arm.com 160712719Snikos.nikoleris@arm.com if (blk && blk->isWritable() && !pkt->req->isCacheInvalidate()) { 160812719Snikos.nikoleris@arm.com // If at this point the referenced block is writable and the 160912719Snikos.nikoleris@arm.com // response is not a cache invalidate, we promote targets that 161012719Snikos.nikoleris@arm.com // were deferred as we couldn't guarrantee a writable copy 161112719Snikos.nikoleris@arm.com mshr->promoteWritable(); 161212719Snikos.nikoleris@arm.com } 161312719Snikos.nikoleris@arm.com 161412719Snikos.nikoleris@arm.com serviceMSHRTargets(mshr, pkt, blk, writebacks); 161511051Sandreas.hansson@arm.com 161611051Sandreas.hansson@arm.com if (mshr->promoteDeferredTargets()) { 161711051Sandreas.hansson@arm.com // avoid later read getting stale data while write miss is 161811051Sandreas.hansson@arm.com // outstanding.. see comment in timingAccess() 161911051Sandreas.hansson@arm.com if (blk) { 162011051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 162111051Sandreas.hansson@arm.com } 162211375Sandreas.hansson@arm.com mshrQueue.markPending(mshr); 162311051Sandreas.hansson@arm.com schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 162411051Sandreas.hansson@arm.com } else { 162512719Snikos.nikoleris@arm.com // while we deallocate an mshr from the queue we still have to 162612719Snikos.nikoleris@arm.com // check the isFull condition before and after as we might 162712719Snikos.nikoleris@arm.com // have been using the reserved entries already 162812719Snikos.nikoleris@arm.com const bool was_full = mshrQueue.isFull(); 162911375Sandreas.hansson@arm.com mshrQueue.deallocate(mshr); 163012719Snikos.nikoleris@arm.com if (was_full && !mshrQueue.isFull()) { 163111375Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 163211051Sandreas.hansson@arm.com } 163311051Sandreas.hansson@arm.com 163411051Sandreas.hansson@arm.com // Request the bus for a prefetch if this deallocation freed enough 163511051Sandreas.hansson@arm.com // MSHRs for a prefetch to take place 163611375Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 163711051Sandreas.hansson@arm.com Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 163811051Sandreas.hansson@arm.com clockEdge()); 163911051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 164011051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 164111051Sandreas.hansson@arm.com } 164211051Sandreas.hansson@arm.com } 164311051Sandreas.hansson@arm.com 164412700Snikos.nikoleris@arm.com // if we used temp block, check to see if its valid and then clear it out 164512700Snikos.nikoleris@arm.com if (blk == tempBlock && tempBlock->isValid()) { 164612700Snikos.nikoleris@arm.com PacketPtr wb_pkt = tempBlock->isDirty() || writebackClean ? 164712700Snikos.nikoleris@arm.com writebackBlk(blk) : cleanEvictBlk(blk); 164812700Snikos.nikoleris@arm.com writebacks.push_back(wb_pkt); 164912700Snikos.nikoleris@arm.com invalidateBlock(tempBlock); 165012700Snikos.nikoleris@arm.com } 165112700Snikos.nikoleris@arm.com 165212719Snikos.nikoleris@arm.com const Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 165311051Sandreas.hansson@arm.com // copy writebacks to write buffer 165411051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 165511051Sandreas.hansson@arm.com 165611744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print()); 165711051Sandreas.hansson@arm.com delete pkt; 165811051Sandreas.hansson@arm.com} 165911051Sandreas.hansson@arm.com 166011051Sandreas.hansson@arm.comPacketPtr 166111051Sandreas.hansson@arm.comCache::writebackBlk(CacheBlk *blk) 166211051Sandreas.hansson@arm.com{ 166311199Sandreas.hansson@arm.com chatty_assert(!isReadOnly || writebackClean, 166411199Sandreas.hansson@arm.com "Writeback from read-only cache"); 166511199Sandreas.hansson@arm.com assert(blk && blk->isValid() && (blk->isDirty() || writebackClean)); 166611051Sandreas.hansson@arm.com 166711051Sandreas.hansson@arm.com writebacks[Request::wbMasterId]++; 166811051Sandreas.hansson@arm.com 166912574Sodanrc@yahoo.com.br Request *req = new Request(tags->regenerateBlkAddr(blk), blkSize, 0, 167012574Sodanrc@yahoo.com.br Request::wbMasterId); 167111051Sandreas.hansson@arm.com if (blk->isSecure()) 167211199Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 167311051Sandreas.hansson@arm.com 167411199Sandreas.hansson@arm.com req->taskId(blk->task_id); 167511051Sandreas.hansson@arm.com 167611199Sandreas.hansson@arm.com PacketPtr pkt = 167711199Sandreas.hansson@arm.com new Packet(req, blk->isDirty() ? 167811199Sandreas.hansson@arm.com MemCmd::WritebackDirty : MemCmd::WritebackClean); 167911199Sandreas.hansson@arm.com 168011744Snikos.nikoleris@arm.com DPRINTF(Cache, "Create Writeback %s writable: %d, dirty: %d\n", 168111744Snikos.nikoleris@arm.com pkt->print(), blk->isWritable(), blk->isDirty()); 168211199Sandreas.hansson@arm.com 168311051Sandreas.hansson@arm.com if (blk->isWritable()) { 168411051Sandreas.hansson@arm.com // not asserting shared means we pass the block in modified 168511051Sandreas.hansson@arm.com // state, mark our own block non-writeable 168611051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 168711051Sandreas.hansson@arm.com } else { 168811284Sandreas.hansson@arm.com // we are in the Owned state, tell the receiver 168911284Sandreas.hansson@arm.com pkt->setHasSharers(); 169011051Sandreas.hansson@arm.com } 169111051Sandreas.hansson@arm.com 169211199Sandreas.hansson@arm.com // make sure the block is not marked dirty 169311199Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 169411051Sandreas.hansson@arm.com 169511199Sandreas.hansson@arm.com pkt->allocate(); 169612633Sodanrc@yahoo.com.br pkt->setDataFromBlock(blk->data, blkSize); 169711199Sandreas.hansson@arm.com 169811199Sandreas.hansson@arm.com return pkt; 169911051Sandreas.hansson@arm.com} 170011051Sandreas.hansson@arm.com 170111051Sandreas.hansson@arm.comPacketPtr 170212351Snikos.nikoleris@arm.comCache::writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id) 170312345Snikos.nikoleris@arm.com{ 170412574Sodanrc@yahoo.com.br Request *req = new Request(tags->regenerateBlkAddr(blk), blkSize, 0, 170512574Sodanrc@yahoo.com.br Request::wbMasterId); 170612345Snikos.nikoleris@arm.com if (blk->isSecure()) { 170712345Snikos.nikoleris@arm.com req->setFlags(Request::SECURE); 170812345Snikos.nikoleris@arm.com } 170912345Snikos.nikoleris@arm.com req->taskId(blk->task_id); 171012500Snikos.nikoleris@arm.com 171112351Snikos.nikoleris@arm.com PacketPtr pkt = new Packet(req, MemCmd::WriteClean, blkSize, id); 171212500Snikos.nikoleris@arm.com 171312346Snikos.nikoleris@arm.com if (dest) { 171412346Snikos.nikoleris@arm.com req->setFlags(dest); 171512346Snikos.nikoleris@arm.com pkt->setWriteThrough(); 171612346Snikos.nikoleris@arm.com } 171712500Snikos.nikoleris@arm.com 171812500Snikos.nikoleris@arm.com DPRINTF(Cache, "Create %s writable: %d, dirty: %d\n", pkt->print(), 171912500Snikos.nikoleris@arm.com blk->isWritable(), blk->isDirty()); 172012500Snikos.nikoleris@arm.com 172112500Snikos.nikoleris@arm.com if (blk->isWritable()) { 172212500Snikos.nikoleris@arm.com // not asserting shared means we pass the block in modified 172312500Snikos.nikoleris@arm.com // state, mark our own block non-writeable 172412500Snikos.nikoleris@arm.com blk->status &= ~BlkWritable; 172512500Snikos.nikoleris@arm.com } else { 172612500Snikos.nikoleris@arm.com // we are in the Owned state, tell the receiver 172712500Snikos.nikoleris@arm.com pkt->setHasSharers(); 172812500Snikos.nikoleris@arm.com } 172912500Snikos.nikoleris@arm.com 173012500Snikos.nikoleris@arm.com // make sure the block is not marked dirty 173112500Snikos.nikoleris@arm.com blk->status &= ~BlkDirty; 173212500Snikos.nikoleris@arm.com 173312500Snikos.nikoleris@arm.com pkt->allocate(); 173412633Sodanrc@yahoo.com.br pkt->setDataFromBlock(blk->data, blkSize); 173512500Snikos.nikoleris@arm.com 173612345Snikos.nikoleris@arm.com return pkt; 173712345Snikos.nikoleris@arm.com} 173812345Snikos.nikoleris@arm.com 173912345Snikos.nikoleris@arm.com 174012345Snikos.nikoleris@arm.comPacketPtr 174111051Sandreas.hansson@arm.comCache::cleanEvictBlk(CacheBlk *blk) 174211051Sandreas.hansson@arm.com{ 174311199Sandreas.hansson@arm.com assert(!writebackClean); 174411051Sandreas.hansson@arm.com assert(blk && blk->isValid() && !blk->isDirty()); 174511051Sandreas.hansson@arm.com // Creating a zero sized write, a message to the snoop filter 174611051Sandreas.hansson@arm.com Request *req = 174712574Sodanrc@yahoo.com.br new Request(tags->regenerateBlkAddr(blk), blkSize, 0, 174811051Sandreas.hansson@arm.com Request::wbMasterId); 174911051Sandreas.hansson@arm.com if (blk->isSecure()) 175011051Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 175111051Sandreas.hansson@arm.com 175211051Sandreas.hansson@arm.com req->taskId(blk->task_id); 175311051Sandreas.hansson@arm.com 175411051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::CleanEvict); 175511051Sandreas.hansson@arm.com pkt->allocate(); 175611744Snikos.nikoleris@arm.com DPRINTF(Cache, "Create CleanEvict %s\n", pkt->print()); 175711051Sandreas.hansson@arm.com 175811051Sandreas.hansson@arm.com return pkt; 175911051Sandreas.hansson@arm.com} 176011051Sandreas.hansson@arm.com 176111051Sandreas.hansson@arm.comvoid 176211051Sandreas.hansson@arm.comCache::memWriteback() 176311051Sandreas.hansson@arm.com{ 176411051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::writebackVisitor); 176511051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 176611051Sandreas.hansson@arm.com} 176711051Sandreas.hansson@arm.com 176811051Sandreas.hansson@arm.comvoid 176911051Sandreas.hansson@arm.comCache::memInvalidate() 177011051Sandreas.hansson@arm.com{ 177111051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::invalidateVisitor); 177211051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 177311051Sandreas.hansson@arm.com} 177411051Sandreas.hansson@arm.com 177511051Sandreas.hansson@arm.combool 177611051Sandreas.hansson@arm.comCache::isDirty() const 177711051Sandreas.hansson@arm.com{ 177811051Sandreas.hansson@arm.com CacheBlkIsDirtyVisitor visitor; 177911051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 178011051Sandreas.hansson@arm.com 178111051Sandreas.hansson@arm.com return visitor.isDirty(); 178211051Sandreas.hansson@arm.com} 178311051Sandreas.hansson@arm.com 178411051Sandreas.hansson@arm.combool 178511051Sandreas.hansson@arm.comCache::writebackVisitor(CacheBlk &blk) 178611051Sandreas.hansson@arm.com{ 178711051Sandreas.hansson@arm.com if (blk.isDirty()) { 178811051Sandreas.hansson@arm.com assert(blk.isValid()); 178911051Sandreas.hansson@arm.com 179012574Sodanrc@yahoo.com.br Request request(tags->regenerateBlkAddr(&blk), blkSize, 0, 179112574Sodanrc@yahoo.com.br Request::funcMasterId); 179211051Sandreas.hansson@arm.com request.taskId(blk.task_id); 179311865Snikos.nikoleris@arm.com if (blk.isSecure()) { 179411865Snikos.nikoleris@arm.com request.setFlags(Request::SECURE); 179511865Snikos.nikoleris@arm.com } 179611051Sandreas.hansson@arm.com 179711051Sandreas.hansson@arm.com Packet packet(&request, MemCmd::WriteReq); 179811051Sandreas.hansson@arm.com packet.dataStatic(blk.data); 179911051Sandreas.hansson@arm.com 180011051Sandreas.hansson@arm.com memSidePort->sendFunctional(&packet); 180111051Sandreas.hansson@arm.com 180211051Sandreas.hansson@arm.com blk.status &= ~BlkDirty; 180311051Sandreas.hansson@arm.com } 180411051Sandreas.hansson@arm.com 180511051Sandreas.hansson@arm.com return true; 180611051Sandreas.hansson@arm.com} 180711051Sandreas.hansson@arm.com 180811051Sandreas.hansson@arm.combool 180911051Sandreas.hansson@arm.comCache::invalidateVisitor(CacheBlk &blk) 181011051Sandreas.hansson@arm.com{ 181111051Sandreas.hansson@arm.com 181211051Sandreas.hansson@arm.com if (blk.isDirty()) 181311051Sandreas.hansson@arm.com warn_once("Invalidating dirty cache lines. Expect things to break.\n"); 181411051Sandreas.hansson@arm.com 181511051Sandreas.hansson@arm.com if (blk.isValid()) { 181611051Sandreas.hansson@arm.com assert(!blk.isDirty()); 181711867Snikos.nikoleris@arm.com invalidateBlock(&blk); 181811051Sandreas.hansson@arm.com } 181911051Sandreas.hansson@arm.com 182011051Sandreas.hansson@arm.com return true; 182111051Sandreas.hansson@arm.com} 182211051Sandreas.hansson@arm.com 182311051Sandreas.hansson@arm.comCacheBlk* 182411051Sandreas.hansson@arm.comCache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks) 182511051Sandreas.hansson@arm.com{ 182612600Sodanrc@yahoo.com.br // Find replacement victim 182711051Sandreas.hansson@arm.com CacheBlk *blk = tags->findVictim(addr); 182811051Sandreas.hansson@arm.com 182911484Snikos.nikoleris@arm.com // It is valid to return nullptr if there is no victim 183011051Sandreas.hansson@arm.com if (!blk) 183111051Sandreas.hansson@arm.com return nullptr; 183211051Sandreas.hansson@arm.com 183311051Sandreas.hansson@arm.com if (blk->isValid()) { 183412574Sodanrc@yahoo.com.br Addr repl_addr = tags->regenerateBlkAddr(blk); 183511051Sandreas.hansson@arm.com MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure()); 183611051Sandreas.hansson@arm.com if (repl_mshr) { 183712599Snikos.nikoleris@arm.com // must be an outstanding upgrade or clean request 183811051Sandreas.hansson@arm.com // on a block we're about to replace... 183912599Snikos.nikoleris@arm.com assert((!blk->isWritable() && repl_mshr->needsWritable()) || 184012599Snikos.nikoleris@arm.com repl_mshr->isCleaning()); 184111051Sandreas.hansson@arm.com // too hard to replace block with transient state 184211051Sandreas.hansson@arm.com // allocation failed, block not inserted 184311484Snikos.nikoleris@arm.com return nullptr; 184411051Sandreas.hansson@arm.com } else { 184511483Snikos.nikoleris@arm.com DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx " 184611483Snikos.nikoleris@arm.com "(%s): %s\n", repl_addr, blk->isSecure() ? "s" : "ns", 184711051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", 184811051Sandreas.hansson@arm.com blk->isDirty() ? "writeback" : "clean"); 184911051Sandreas.hansson@arm.com 185011436SRekai.GonzalezAlberquilla@arm.com if (blk->wasPrefetched()) { 185111436SRekai.GonzalezAlberquilla@arm.com unusedPrefetches++; 185211436SRekai.GonzalezAlberquilla@arm.com } 185311051Sandreas.hansson@arm.com // Will send up Writeback/CleanEvict snoops via isCachedAbove 185411051Sandreas.hansson@arm.com // when pushing this writeback list into the write buffer. 185511199Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 185611051Sandreas.hansson@arm.com // Save writeback packet for handling by caller 185711051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(blk)); 185811051Sandreas.hansson@arm.com } else { 185911051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(blk)); 186011051Sandreas.hansson@arm.com } 186112702Snikos.nikoleris@arm.com replacements++; 186211051Sandreas.hansson@arm.com } 186311051Sandreas.hansson@arm.com } 186411051Sandreas.hansson@arm.com 186511051Sandreas.hansson@arm.com return blk; 186611051Sandreas.hansson@arm.com} 186711051Sandreas.hansson@arm.com 186811197Sandreas.hansson@arm.comvoid 186911197Sandreas.hansson@arm.comCache::invalidateBlock(CacheBlk *blk) 187011197Sandreas.hansson@arm.com{ 187111197Sandreas.hansson@arm.com if (blk != tempBlock) 187211197Sandreas.hansson@arm.com tags->invalidate(blk); 187311197Sandreas.hansson@arm.com blk->invalidate(); 187411197Sandreas.hansson@arm.com} 187511051Sandreas.hansson@arm.com 187611051Sandreas.hansson@arm.com// Note that the reason we return a list of writebacks rather than 187711051Sandreas.hansson@arm.com// inserting them directly in the write buffer is that this function 187811051Sandreas.hansson@arm.com// is called by both atomic and timing-mode accesses, and in atomic 187911051Sandreas.hansson@arm.com// mode we don't mess with the write buffer (we just perform the 188011051Sandreas.hansson@arm.com// writebacks atomically once the original request is complete). 188111051Sandreas.hansson@arm.comCacheBlk* 188211197Sandreas.hansson@arm.comCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, 188311197Sandreas.hansson@arm.com bool allocate) 188411051Sandreas.hansson@arm.com{ 188511051Sandreas.hansson@arm.com assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq); 188611051Sandreas.hansson@arm.com Addr addr = pkt->getAddr(); 188711051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 188811051Sandreas.hansson@arm.com#if TRACING_ON 188911051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 189011051Sandreas.hansson@arm.com#endif 189111051Sandreas.hansson@arm.com 189211375Sandreas.hansson@arm.com // When handling a fill, we should have no writes to this line. 189311892Snikos.nikoleris@arm.com assert(addr == pkt->getBlockAddr(blkSize)); 189411375Sandreas.hansson@arm.com assert(!writeBuffer.findMatch(addr, is_secure)); 189511051Sandreas.hansson@arm.com 189611484Snikos.nikoleris@arm.com if (blk == nullptr) { 189711051Sandreas.hansson@arm.com // better have read new data... 189811051Sandreas.hansson@arm.com assert(pkt->hasData()); 189911051Sandreas.hansson@arm.com 190011051Sandreas.hansson@arm.com // only read responses and write-line requests have data; 190111051Sandreas.hansson@arm.com // note that we don't write the data here for write-line - that 190211601Sandreas.hansson@arm.com // happens in the subsequent call to satisfyRequest 190311051Sandreas.hansson@arm.com assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq); 190411051Sandreas.hansson@arm.com 190511197Sandreas.hansson@arm.com // need to do a replacement if allocating, otherwise we stick 190611197Sandreas.hansson@arm.com // with the temporary storage 190711484Snikos.nikoleris@arm.com blk = allocate ? allocateBlock(addr, is_secure, writebacks) : nullptr; 190811197Sandreas.hansson@arm.com 190911484Snikos.nikoleris@arm.com if (blk == nullptr) { 191011197Sandreas.hansson@arm.com // No replaceable block or a mostly exclusive 191111197Sandreas.hansson@arm.com // cache... just use temporary storage to complete the 191211197Sandreas.hansson@arm.com // current request and then get rid of it 191311051Sandreas.hansson@arm.com assert(!tempBlock->isValid()); 191411051Sandreas.hansson@arm.com blk = tempBlock; 191511051Sandreas.hansson@arm.com tempBlock->set = tags->extractSet(addr); 191611051Sandreas.hansson@arm.com tempBlock->tag = tags->extractTag(addr); 191712552Snikos.nikoleris@arm.com if (is_secure) { 191812552Snikos.nikoleris@arm.com tempBlock->status |= BlkSecure; 191912552Snikos.nikoleris@arm.com } 192011051Sandreas.hansson@arm.com DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr, 192111051Sandreas.hansson@arm.com is_secure ? "s" : "ns"); 192211051Sandreas.hansson@arm.com } else { 192311051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 192411051Sandreas.hansson@arm.com } 192511051Sandreas.hansson@arm.com 192611051Sandreas.hansson@arm.com // we should never be overwriting a valid block 192711051Sandreas.hansson@arm.com assert(!blk->isValid()); 192811051Sandreas.hansson@arm.com } else { 192911051Sandreas.hansson@arm.com // existing block... probably an upgrade 193011051Sandreas.hansson@arm.com assert(blk->tag == tags->extractTag(addr)); 193111051Sandreas.hansson@arm.com // either we're getting new data or the block should already be valid 193211051Sandreas.hansson@arm.com assert(pkt->hasData() || blk->isValid()); 193311051Sandreas.hansson@arm.com // don't clear block status... if block is already dirty we 193411051Sandreas.hansson@arm.com // don't want to lose that 193511051Sandreas.hansson@arm.com } 193611051Sandreas.hansson@arm.com 193711051Sandreas.hansson@arm.com if (is_secure) 193811051Sandreas.hansson@arm.com blk->status |= BlkSecure; 193911051Sandreas.hansson@arm.com blk->status |= BlkValid | BlkReadable; 194011051Sandreas.hansson@arm.com 194111137Sandreas.hansson@arm.com // sanity check for whole-line writes, which should always be 194211137Sandreas.hansson@arm.com // marked as writable as part of the fill, and then later marked 194311601Sandreas.hansson@arm.com // dirty as part of satisfyRequest 194411137Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WriteLineReq) { 194511284Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 194611137Sandreas.hansson@arm.com } 194711137Sandreas.hansson@arm.com 194811284Sandreas.hansson@arm.com // here we deal with setting the appropriate state of the line, 194911284Sandreas.hansson@arm.com // and we start by looking at the hasSharers flag, and ignore the 195011284Sandreas.hansson@arm.com // cacheResponding flag (normally signalling dirty data) if the 195111284Sandreas.hansson@arm.com // packet has sharers, thus the line is never allocated as Owned 195211284Sandreas.hansson@arm.com // (dirty but not writable), and always ends up being either 195311284Sandreas.hansson@arm.com // Shared, Exclusive or Modified, see Packet::setCacheResponding 195411284Sandreas.hansson@arm.com // for more details 195511284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 195611284Sandreas.hansson@arm.com // we could get a writable line from memory (rather than a 195711284Sandreas.hansson@arm.com // cache) even in a read-only cache, note that we set this bit 195811284Sandreas.hansson@arm.com // even for a read-only cache, possibly revisit this decision 195911051Sandreas.hansson@arm.com blk->status |= BlkWritable; 196011051Sandreas.hansson@arm.com 196111284Sandreas.hansson@arm.com // check if we got this via cache-to-cache transfer (i.e., from a 196211284Sandreas.hansson@arm.com // cache that had the block in Modified or Owned state) 196311284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 196411284Sandreas.hansson@arm.com // we got the block in Modified state, and invalidated the 196511284Sandreas.hansson@arm.com // owners copy 196611051Sandreas.hansson@arm.com blk->status |= BlkDirty; 196711051Sandreas.hansson@arm.com 196811051Sandreas.hansson@arm.com chatty_assert(!isReadOnly, "Should never see dirty snoop response " 196911051Sandreas.hansson@arm.com "in read-only cache %s\n", name()); 197011051Sandreas.hansson@arm.com } 197111051Sandreas.hansson@arm.com } 197211051Sandreas.hansson@arm.com 197311051Sandreas.hansson@arm.com DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n", 197411051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", old_state, blk->print()); 197511051Sandreas.hansson@arm.com 197611051Sandreas.hansson@arm.com // if we got new data, copy it in (checking for a read response 197711051Sandreas.hansson@arm.com // and a response that has data is the same in the end) 197811051Sandreas.hansson@arm.com if (pkt->isRead()) { 197911051Sandreas.hansson@arm.com // sanity checks 198011051Sandreas.hansson@arm.com assert(pkt->hasData()); 198111051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 198211051Sandreas.hansson@arm.com 198312633Sodanrc@yahoo.com.br pkt->writeDataToBlock(blk->data, blkSize); 198411051Sandreas.hansson@arm.com } 198511051Sandreas.hansson@arm.com // We pay for fillLatency here. 198611051Sandreas.hansson@arm.com blk->whenReady = clockEdge() + fillLatency * clockPeriod() + 198711051Sandreas.hansson@arm.com pkt->payloadDelay; 198811051Sandreas.hansson@arm.com 198911051Sandreas.hansson@arm.com return blk; 199011051Sandreas.hansson@arm.com} 199111051Sandreas.hansson@arm.com 199211051Sandreas.hansson@arm.com 199311051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 199411051Sandreas.hansson@arm.com// 199511051Sandreas.hansson@arm.com// Snoop path: requests coming in from the memory side 199611051Sandreas.hansson@arm.com// 199711051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 199811051Sandreas.hansson@arm.com 199911051Sandreas.hansson@arm.comvoid 200011051Sandreas.hansson@arm.comCache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 200111051Sandreas.hansson@arm.com bool already_copied, bool pending_inval) 200211051Sandreas.hansson@arm.com{ 200311051Sandreas.hansson@arm.com // sanity check 200411051Sandreas.hansson@arm.com assert(req_pkt->isRequest()); 200511051Sandreas.hansson@arm.com assert(req_pkt->needsResponse()); 200611051Sandreas.hansson@arm.com 200711744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: for %s\n", __func__, req_pkt->print()); 200811051Sandreas.hansson@arm.com // timing-mode snoop responses require a new packet, unless we 200911051Sandreas.hansson@arm.com // already made a copy... 201011051Sandreas.hansson@arm.com PacketPtr pkt = req_pkt; 201111051Sandreas.hansson@arm.com if (!already_copied) 201211051Sandreas.hansson@arm.com // do not clear flags, and allocate space for data if the 201311051Sandreas.hansson@arm.com // packet needs it (the only packets that carry data are read 201411051Sandreas.hansson@arm.com // responses) 201511051Sandreas.hansson@arm.com pkt = new Packet(req_pkt, false, req_pkt->isRead()); 201611051Sandreas.hansson@arm.com 201711051Sandreas.hansson@arm.com assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() || 201811284Sandreas.hansson@arm.com pkt->hasSharers()); 201911051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 202011051Sandreas.hansson@arm.com if (pkt->isRead()) { 202111051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk_data, blkSize); 202211051Sandreas.hansson@arm.com } 202311051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadResp && pending_inval) { 202411051Sandreas.hansson@arm.com // Assume we defer a response to a read from a far-away cache 202511051Sandreas.hansson@arm.com // A, then later defer a ReadExcl from a cache B on the same 202611284Sandreas.hansson@arm.com // bus as us. We'll assert cacheResponding in both cases, but 202711284Sandreas.hansson@arm.com // in the latter case cacheResponding will keep the 202811284Sandreas.hansson@arm.com // invalidation from reaching cache A. This special response 202911284Sandreas.hansson@arm.com // tells cache A that it gets the block to satisfy its read, 203011284Sandreas.hansson@arm.com // but must immediately invalidate it. 203111051Sandreas.hansson@arm.com pkt->cmd = MemCmd::ReadRespWithInvalidate; 203211051Sandreas.hansson@arm.com } 203311051Sandreas.hansson@arm.com // Here we consider forward_time, paying for just forward latency and 203411051Sandreas.hansson@arm.com // also charging the delay provided by the xbar. 203511051Sandreas.hansson@arm.com // forward_time is used as send_time in next allocateWriteBuffer(). 203611051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 203711051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 203811051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 203911744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: created response: %s tick: %lu\n", __func__, 204011744Snikos.nikoleris@arm.com pkt->print(), forward_time); 204111051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, forward_time, true); 204211051Sandreas.hansson@arm.com} 204311051Sandreas.hansson@arm.com 204411127Sandreas.hansson@arm.comuint32_t 204511051Sandreas.hansson@arm.comCache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, 204611051Sandreas.hansson@arm.com bool is_deferred, bool pending_inval) 204711051Sandreas.hansson@arm.com{ 204811744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 204911051Sandreas.hansson@arm.com // deferred snoops can only happen in timing mode 205011051Sandreas.hansson@arm.com assert(!(is_deferred && !is_timing)); 205111051Sandreas.hansson@arm.com // pending_inval only makes sense on deferred snoops 205211051Sandreas.hansson@arm.com assert(!(pending_inval && !is_deferred)); 205311051Sandreas.hansson@arm.com assert(pkt->isRequest()); 205411051Sandreas.hansson@arm.com 205511051Sandreas.hansson@arm.com // the packet may get modified if we or a forwarded snooper 205611051Sandreas.hansson@arm.com // responds in atomic mode, so remember a few things about the 205711051Sandreas.hansson@arm.com // original packet up front 205811051Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 205911284Sandreas.hansson@arm.com bool M5_VAR_USED needs_writable = pkt->needsWritable(); 206011051Sandreas.hansson@arm.com 206111285Sandreas.hansson@arm.com // at the moment we could get an uncacheable write which does not 206211285Sandreas.hansson@arm.com // have the invalidate flag, and we need a suitable way of dealing 206311285Sandreas.hansson@arm.com // with this case 206411285Sandreas.hansson@arm.com panic_if(invalidate && pkt->req->isUncacheable(), 206511744Snikos.nikoleris@arm.com "%s got an invalidating uncacheable snoop request %s", 206611744Snikos.nikoleris@arm.com name(), pkt->print()); 206711285Sandreas.hansson@arm.com 206811127Sandreas.hansson@arm.com uint32_t snoop_delay = 0; 206911127Sandreas.hansson@arm.com 207011051Sandreas.hansson@arm.com if (forwardSnoops) { 207111051Sandreas.hansson@arm.com // first propagate snoop upward to see if anyone above us wants to 207211051Sandreas.hansson@arm.com // handle it. save & restore packet src since it will get 207311051Sandreas.hansson@arm.com // rewritten to be relative to cpu-side bus (if any) 207411284Sandreas.hansson@arm.com bool alreadyResponded = pkt->cacheResponding(); 207511051Sandreas.hansson@arm.com if (is_timing) { 207611051Sandreas.hansson@arm.com // copy the packet so that we can clear any flags before 207711051Sandreas.hansson@arm.com // forwarding it upwards, we also allocate data (passing 207811051Sandreas.hansson@arm.com // the pointer along in case of static data), in case 207911051Sandreas.hansson@arm.com // there is a snoop hit in upper levels 208011051Sandreas.hansson@arm.com Packet snoopPkt(pkt, true, true); 208111051Sandreas.hansson@arm.com snoopPkt.setExpressSnoop(); 208211051Sandreas.hansson@arm.com // the snoop packet does not need to wait any additional 208311051Sandreas.hansson@arm.com // time 208411051Sandreas.hansson@arm.com snoopPkt.headerDelay = snoopPkt.payloadDelay = 0; 208511051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoopPkt); 208611127Sandreas.hansson@arm.com 208711127Sandreas.hansson@arm.com // add the header delay (including crossbar and snoop 208811127Sandreas.hansson@arm.com // delays) of the upward snoop to the snoop delay for this 208911127Sandreas.hansson@arm.com // cache 209011127Sandreas.hansson@arm.com snoop_delay += snoopPkt.headerDelay; 209111127Sandreas.hansson@arm.com 209211284Sandreas.hansson@arm.com if (snoopPkt.cacheResponding()) { 209311051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache 209411051Sandreas.hansson@arm.com assert(!alreadyResponded); 209511284Sandreas.hansson@arm.com pkt->setCacheResponding(); 209611051Sandreas.hansson@arm.com } 209711284Sandreas.hansson@arm.com // upstream cache has the block, or has an outstanding 209811284Sandreas.hansson@arm.com // MSHR, pass the flag on 209911284Sandreas.hansson@arm.com if (snoopPkt.hasSharers()) { 210011284Sandreas.hansson@arm.com pkt->setHasSharers(); 210111051Sandreas.hansson@arm.com } 210211051Sandreas.hansson@arm.com // If this request is a prefetch or clean evict and an upper level 210311051Sandreas.hansson@arm.com // signals block present, make sure to propagate the block 210411051Sandreas.hansson@arm.com // presence to the requester. 210511051Sandreas.hansson@arm.com if (snoopPkt.isBlockCached()) { 210611051Sandreas.hansson@arm.com pkt->setBlockCached(); 210711051Sandreas.hansson@arm.com } 210812349Snikos.nikoleris@arm.com // If the request was satisfied by snooping the cache 210912349Snikos.nikoleris@arm.com // above, mark the original packet as satisfied too. 211012349Snikos.nikoleris@arm.com if (snoopPkt.satisfied()) { 211112349Snikos.nikoleris@arm.com pkt->setSatisfied(); 211212349Snikos.nikoleris@arm.com } 211311051Sandreas.hansson@arm.com } else { 211411051Sandreas.hansson@arm.com cpuSidePort->sendAtomicSnoop(pkt); 211511284Sandreas.hansson@arm.com if (!alreadyResponded && pkt->cacheResponding()) { 211611051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache: 211711051Sandreas.hansson@arm.com // forward response to original requester 211811051Sandreas.hansson@arm.com assert(pkt->isResponse()); 211911051Sandreas.hansson@arm.com } 212011051Sandreas.hansson@arm.com } 212111051Sandreas.hansson@arm.com } 212211051Sandreas.hansson@arm.com 212312349Snikos.nikoleris@arm.com bool respond = false; 212412349Snikos.nikoleris@arm.com bool blk_valid = blk && blk->isValid(); 212512349Snikos.nikoleris@arm.com if (pkt->isClean()) { 212612349Snikos.nikoleris@arm.com if (blk_valid && blk->isDirty()) { 212712349Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: packet (snoop) %s found block: %s\n", 212812349Snikos.nikoleris@arm.com __func__, pkt->print(), blk->print()); 212912351Snikos.nikoleris@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id); 213012349Snikos.nikoleris@arm.com PacketList writebacks; 213112349Snikos.nikoleris@arm.com writebacks.push_back(wb_pkt); 213212349Snikos.nikoleris@arm.com 213312349Snikos.nikoleris@arm.com if (is_timing) { 213412349Snikos.nikoleris@arm.com // anything that is merely forwarded pays for the forward 213512349Snikos.nikoleris@arm.com // latency and the delay provided by the crossbar 213612349Snikos.nikoleris@arm.com Tick forward_time = clockEdge(forwardLatency) + 213712349Snikos.nikoleris@arm.com pkt->headerDelay; 213812349Snikos.nikoleris@arm.com doWritebacks(writebacks, forward_time); 213912349Snikos.nikoleris@arm.com } else { 214012349Snikos.nikoleris@arm.com doWritebacksAtomic(writebacks); 214112349Snikos.nikoleris@arm.com } 214212349Snikos.nikoleris@arm.com pkt->setSatisfied(); 214312349Snikos.nikoleris@arm.com } 214412349Snikos.nikoleris@arm.com } else if (!blk_valid) { 214511744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: snoop miss for %s\n", __func__, 214611744Snikos.nikoleris@arm.com pkt->print()); 214711493Sandreas.hansson@arm.com if (is_deferred) { 214811493Sandreas.hansson@arm.com // we no longer have the block, and will not respond, but a 214911493Sandreas.hansson@arm.com // packet was allocated in MSHR::handleSnoop and we have 215011493Sandreas.hansson@arm.com // to delete it 215111493Sandreas.hansson@arm.com assert(pkt->needsResponse()); 215211493Sandreas.hansson@arm.com 215311493Sandreas.hansson@arm.com // we have passed the block to a cache upstream, that 215411493Sandreas.hansson@arm.com // cache should be responding 215511493Sandreas.hansson@arm.com assert(pkt->cacheResponding()); 215611493Sandreas.hansson@arm.com 215711493Sandreas.hansson@arm.com delete pkt; 215811493Sandreas.hansson@arm.com } 215911127Sandreas.hansson@arm.com return snoop_delay; 216011051Sandreas.hansson@arm.com } else { 216111744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: snoop hit for %s, old state is %s\n", __func__, 216211744Snikos.nikoleris@arm.com pkt->print(), blk->print()); 216312349Snikos.nikoleris@arm.com 216412349Snikos.nikoleris@arm.com // We may end up modifying both the block state and the packet (if 216512349Snikos.nikoleris@arm.com // we respond in atomic mode), so just figure out what to do now 216612349Snikos.nikoleris@arm.com // and then do it later. We respond to all snoops that need 216712349Snikos.nikoleris@arm.com // responses provided we have the block in dirty state. The 216812349Snikos.nikoleris@arm.com // invalidation itself is taken care of below. We don't respond to 216912349Snikos.nikoleris@arm.com // cache maintenance operations as this is done by the destination 217012349Snikos.nikoleris@arm.com // xbar. 217112349Snikos.nikoleris@arm.com respond = blk->isDirty() && pkt->needsResponse(); 217212349Snikos.nikoleris@arm.com 217312349Snikos.nikoleris@arm.com chatty_assert(!(isReadOnly && blk->isDirty()), "Should never have " 217412349Snikos.nikoleris@arm.com "a dirty block in a read-only cache %s\n", name()); 217511051Sandreas.hansson@arm.com } 217611051Sandreas.hansson@arm.com 217711051Sandreas.hansson@arm.com // Invalidate any prefetch's from below that would strip write permissions 217811051Sandreas.hansson@arm.com // MemCmd::HardPFReq is only observed by upstream caches. After missing 217911051Sandreas.hansson@arm.com // above and in it's own cache, a new MemCmd::ReadReq is created that 218011051Sandreas.hansson@arm.com // downstream caches observe. 218111051Sandreas.hansson@arm.com if (pkt->mustCheckAbove()) { 218211483Snikos.nikoleris@arm.com DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s " 218311744Snikos.nikoleris@arm.com "from lower cache\n", pkt->getAddr(), pkt->print()); 218411051Sandreas.hansson@arm.com pkt->setBlockCached(); 218511127Sandreas.hansson@arm.com return snoop_delay; 218611051Sandreas.hansson@arm.com } 218711051Sandreas.hansson@arm.com 218811285Sandreas.hansson@arm.com if (pkt->isRead() && !invalidate) { 218911285Sandreas.hansson@arm.com // reading without requiring the line in a writable state 219011284Sandreas.hansson@arm.com assert(!needs_writable); 219111284Sandreas.hansson@arm.com pkt->setHasSharers(); 219211285Sandreas.hansson@arm.com 219311285Sandreas.hansson@arm.com // if the requesting packet is uncacheable, retain the line in 219411285Sandreas.hansson@arm.com // the current state, otherwhise unset the writable flag, 219511285Sandreas.hansson@arm.com // which means we go from Modified to Owned (and will respond 219611285Sandreas.hansson@arm.com // below), remain in Owned (and will respond below), from 219711285Sandreas.hansson@arm.com // Exclusive to Shared, or remain in Shared 219811285Sandreas.hansson@arm.com if (!pkt->req->isUncacheable()) 219911285Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 220012349Snikos.nikoleris@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 220111051Sandreas.hansson@arm.com } 220211051Sandreas.hansson@arm.com 220311051Sandreas.hansson@arm.com if (respond) { 220411051Sandreas.hansson@arm.com // prevent anyone else from responding, cache as well as 220511051Sandreas.hansson@arm.com // memory, and also prevent any memory from even seeing the 220611284Sandreas.hansson@arm.com // request 220711284Sandreas.hansson@arm.com pkt->setCacheResponding(); 220812349Snikos.nikoleris@arm.com if (!pkt->isClean() && blk->isWritable()) { 220911284Sandreas.hansson@arm.com // inform the cache hierarchy that this cache had the line 221011284Sandreas.hansson@arm.com // in the Modified state so that we avoid unnecessary 221111284Sandreas.hansson@arm.com // invalidations (see Packet::setResponderHadWritable) 221211284Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 221311284Sandreas.hansson@arm.com 221411081Sandreas.hansson@arm.com // in the case of an uncacheable request there is no point 221511284Sandreas.hansson@arm.com // in setting the responderHadWritable flag, but since the 221611284Sandreas.hansson@arm.com // recipient does not care there is no harm in doing so 221711284Sandreas.hansson@arm.com } else { 221811284Sandreas.hansson@arm.com // if the packet has needsWritable set we invalidate our 221911284Sandreas.hansson@arm.com // copy below and all other copies will be invalidates 222011284Sandreas.hansson@arm.com // through express snoops, and if needsWritable is not set 222111284Sandreas.hansson@arm.com // we already called setHasSharers above 222211051Sandreas.hansson@arm.com } 222311284Sandreas.hansson@arm.com 222411285Sandreas.hansson@arm.com // if we are returning a writable and dirty (Modified) line, 222511285Sandreas.hansson@arm.com // we should be invalidating the line 222611285Sandreas.hansson@arm.com panic_if(!invalidate && !pkt->hasSharers(), 222711744Snikos.nikoleris@arm.com "%s is passing a Modified line through %s, " 222811744Snikos.nikoleris@arm.com "but keeping the block", name(), pkt->print()); 222911285Sandreas.hansson@arm.com 223011051Sandreas.hansson@arm.com if (is_timing) { 223111051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval); 223211051Sandreas.hansson@arm.com } else { 223311051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 223411286Sandreas.hansson@arm.com // packets such as upgrades do not actually have any data 223511286Sandreas.hansson@arm.com // payload 223611286Sandreas.hansson@arm.com if (pkt->hasData()) 223711286Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 223811051Sandreas.hansson@arm.com } 223911051Sandreas.hansson@arm.com } 224011051Sandreas.hansson@arm.com 224111602Sandreas.hansson@arm.com if (!respond && is_deferred) { 224211051Sandreas.hansson@arm.com assert(pkt->needsResponse()); 224311602Sandreas.hansson@arm.com 224411602Sandreas.hansson@arm.com // if we copied the deferred packet with the intention to 224511602Sandreas.hansson@arm.com // respond, but are not responding, then a cache above us must 224611602Sandreas.hansson@arm.com // be, and we can use this as the indication of whether this 224711602Sandreas.hansson@arm.com // is a packet where we created a copy of the request or not 224811602Sandreas.hansson@arm.com if (!pkt->cacheResponding()) { 224911602Sandreas.hansson@arm.com delete pkt->req; 225011602Sandreas.hansson@arm.com } 225111602Sandreas.hansson@arm.com 225211051Sandreas.hansson@arm.com delete pkt; 225311051Sandreas.hansson@arm.com } 225411051Sandreas.hansson@arm.com 225511051Sandreas.hansson@arm.com // Do this last in case it deallocates block data or something 225611051Sandreas.hansson@arm.com // like that 225712349Snikos.nikoleris@arm.com if (blk_valid && invalidate) { 225811197Sandreas.hansson@arm.com invalidateBlock(blk); 225912349Snikos.nikoleris@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 226011051Sandreas.hansson@arm.com } 226111051Sandreas.hansson@arm.com 226211127Sandreas.hansson@arm.com return snoop_delay; 226311051Sandreas.hansson@arm.com} 226411051Sandreas.hansson@arm.com 226511051Sandreas.hansson@arm.com 226611051Sandreas.hansson@arm.comvoid 226711051Sandreas.hansson@arm.comCache::recvTimingSnoopReq(PacketPtr pkt) 226811051Sandreas.hansson@arm.com{ 226911744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 227011051Sandreas.hansson@arm.com 227111051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 227211051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 227311051Sandreas.hansson@arm.com 227411130Sali.jafri@arm.com // no need to snoop requests that are not in range 227511051Sandreas.hansson@arm.com if (!inRange(pkt->getAddr())) { 227611051Sandreas.hansson@arm.com return; 227711051Sandreas.hansson@arm.com } 227811051Sandreas.hansson@arm.com 227911051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 228011051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 228111051Sandreas.hansson@arm.com 228211892Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 228311051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 228411051Sandreas.hansson@arm.com 228511127Sandreas.hansson@arm.com // Update the latency cost of the snoop so that the crossbar can 228611127Sandreas.hansson@arm.com // account for it. Do not overwrite what other neighbouring caches 228711127Sandreas.hansson@arm.com // have already done, rather take the maximum. The update is 228811127Sandreas.hansson@arm.com // tentative, for cases where we return before an upward snoop 228911127Sandreas.hansson@arm.com // happens below. 229011127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, 229111127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 229211127Sandreas.hansson@arm.com 229311051Sandreas.hansson@arm.com // Inform request(Prefetch, CleanEvict or Writeback) from below of 229411051Sandreas.hansson@arm.com // MSHR hit, set setBlockCached. 229511051Sandreas.hansson@arm.com if (mshr && pkt->mustCheckAbove()) { 229611744Snikos.nikoleris@arm.com DPRINTF(Cache, "Setting block cached for %s from lower cache on " 229711744Snikos.nikoleris@arm.com "mshr hit\n", pkt->print()); 229811051Sandreas.hansson@arm.com pkt->setBlockCached(); 229911051Sandreas.hansson@arm.com return; 230011051Sandreas.hansson@arm.com } 230111051Sandreas.hansson@arm.com 230212349Snikos.nikoleris@arm.com // Bypass any existing cache maintenance requests if the request 230312349Snikos.nikoleris@arm.com // has been satisfied already (i.e., the dirty block has been 230412349Snikos.nikoleris@arm.com // found). 230512349Snikos.nikoleris@arm.com if (mshr && pkt->req->isCacheMaintenance() && pkt->satisfied()) { 230612349Snikos.nikoleris@arm.com return; 230712349Snikos.nikoleris@arm.com } 230812349Snikos.nikoleris@arm.com 230911051Sandreas.hansson@arm.com // Let the MSHR itself track the snoop and decide whether we want 231011051Sandreas.hansson@arm.com // to go ahead and do the regular cache snoop 231111051Sandreas.hansson@arm.com if (mshr && mshr->handleSnoop(pkt, order++)) { 231211051Sandreas.hansson@arm.com DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)." 231311051Sandreas.hansson@arm.com "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns", 231411051Sandreas.hansson@arm.com mshr->print()); 231511051Sandreas.hansson@arm.com 231611051Sandreas.hansson@arm.com if (mshr->getNumTargets() > numTarget) 231711051Sandreas.hansson@arm.com warn("allocating bonus target for snoop"); //handle later 231811051Sandreas.hansson@arm.com return; 231911051Sandreas.hansson@arm.com } 232011051Sandreas.hansson@arm.com 232111051Sandreas.hansson@arm.com //We also need to check the writeback buffers and handle those 232211375Sandreas.hansson@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(blk_addr, is_secure); 232311375Sandreas.hansson@arm.com if (wb_entry) { 232411051Sandreas.hansson@arm.com DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n", 232511051Sandreas.hansson@arm.com pkt->getAddr(), is_secure ? "s" : "ns"); 232611051Sandreas.hansson@arm.com // Expect to see only Writebacks and/or CleanEvicts here, both of 232711051Sandreas.hansson@arm.com // which should not be generated for uncacheable data. 232811051Sandreas.hansson@arm.com assert(!wb_entry->isUncacheable()); 232911051Sandreas.hansson@arm.com // There should only be a single request responsible for generating 233011051Sandreas.hansson@arm.com // Writebacks/CleanEvicts. 233111051Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 233211051Sandreas.hansson@arm.com PacketPtr wb_pkt = wb_entry->getTarget()->pkt; 233312345Snikos.nikoleris@arm.com assert(wb_pkt->isEviction() || wb_pkt->cmd == MemCmd::WriteClean); 233411051Sandreas.hansson@arm.com 233511199Sandreas.hansson@arm.com if (pkt->isEviction()) { 233611051Sandreas.hansson@arm.com // if the block is found in the write queue, set the BLOCK_CACHED 233711051Sandreas.hansson@arm.com // flag for Writeback/CleanEvict snoop. On return the snoop will 233811051Sandreas.hansson@arm.com // propagate the BLOCK_CACHED flag in Writeback packets and prevent 233911051Sandreas.hansson@arm.com // any CleanEvicts from travelling down the memory hierarchy. 234011051Sandreas.hansson@arm.com pkt->setBlockCached(); 234111744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Squashing %s from lower cache on writequeue " 234211744Snikos.nikoleris@arm.com "hit\n", __func__, pkt->print()); 234311051Sandreas.hansson@arm.com return; 234411051Sandreas.hansson@arm.com } 234511051Sandreas.hansson@arm.com 234611332Sandreas.hansson@arm.com // conceptually writebacks are no different to other blocks in 234711332Sandreas.hansson@arm.com // this cache, so the behaviour is modelled after handleSnoop, 234811332Sandreas.hansson@arm.com // the difference being that instead of querying the block 234911332Sandreas.hansson@arm.com // state to determine if it is dirty and writable, we use the 235011332Sandreas.hansson@arm.com // command and fields of the writeback packet 235111332Sandreas.hansson@arm.com bool respond = wb_pkt->cmd == MemCmd::WritebackDirty && 235211751Snikos.nikoleris@arm.com pkt->needsResponse(); 235311332Sandreas.hansson@arm.com bool have_writable = !wb_pkt->hasSharers(); 235411332Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 235511332Sandreas.hansson@arm.com 235611332Sandreas.hansson@arm.com if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) { 235711332Sandreas.hansson@arm.com assert(!pkt->needsWritable()); 235811332Sandreas.hansson@arm.com pkt->setHasSharers(); 235911332Sandreas.hansson@arm.com wb_pkt->setHasSharers(); 236011332Sandreas.hansson@arm.com } 236111332Sandreas.hansson@arm.com 236211332Sandreas.hansson@arm.com if (respond) { 236311284Sandreas.hansson@arm.com pkt->setCacheResponding(); 236411332Sandreas.hansson@arm.com 236511332Sandreas.hansson@arm.com if (have_writable) { 236611332Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 236711051Sandreas.hansson@arm.com } 236811332Sandreas.hansson@arm.com 236911051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(), 237011051Sandreas.hansson@arm.com false, false); 237111051Sandreas.hansson@arm.com } 237211051Sandreas.hansson@arm.com 237312349Snikos.nikoleris@arm.com if (invalidate && wb_pkt->cmd != MemCmd::WriteClean) { 237411051Sandreas.hansson@arm.com // Invalidation trumps our writeback... discard here 237511051Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 237611375Sandreas.hansson@arm.com markInService(wb_entry); 237711051Sandreas.hansson@arm.com delete wb_pkt; 237811051Sandreas.hansson@arm.com } 237911051Sandreas.hansson@arm.com } 238011051Sandreas.hansson@arm.com 238111051Sandreas.hansson@arm.com // If this was a shared writeback, there may still be 238211051Sandreas.hansson@arm.com // other shared copies above that require invalidation. 238311051Sandreas.hansson@arm.com // We could be more selective and return here if the 238411051Sandreas.hansson@arm.com // request is non-exclusive or if the writeback is 238511051Sandreas.hansson@arm.com // exclusive. 238611127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false); 238711127Sandreas.hansson@arm.com 238811127Sandreas.hansson@arm.com // Override what we did when we first saw the snoop, as we now 238911127Sandreas.hansson@arm.com // also have the cost of the upwards snoops to account for 239011127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay + 239111127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 239211051Sandreas.hansson@arm.com} 239311051Sandreas.hansson@arm.com 239411051Sandreas.hansson@arm.combool 239511051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 239611051Sandreas.hansson@arm.com{ 239711051Sandreas.hansson@arm.com // Express snoop responses from master to slave, e.g., from L1 to L2 239811051Sandreas.hansson@arm.com cache->recvTimingSnoopResp(pkt); 239911051Sandreas.hansson@arm.com return true; 240011051Sandreas.hansson@arm.com} 240111051Sandreas.hansson@arm.com 240211051Sandreas.hansson@arm.comTick 240311051Sandreas.hansson@arm.comCache::recvAtomicSnoop(PacketPtr pkt) 240411051Sandreas.hansson@arm.com{ 240511051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 240611051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 240711051Sandreas.hansson@arm.com 240811130Sali.jafri@arm.com // no need to snoop requests that are not in range. 240911130Sali.jafri@arm.com if (!inRange(pkt->getAddr())) { 241011051Sandreas.hansson@arm.com return 0; 241111051Sandreas.hansson@arm.com } 241211051Sandreas.hansson@arm.com 241311051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 241411127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false); 241511127Sandreas.hansson@arm.com return snoop_delay + lookupLatency * clockPeriod(); 241611051Sandreas.hansson@arm.com} 241711051Sandreas.hansson@arm.com 241811051Sandreas.hansson@arm.com 241911375Sandreas.hansson@arm.comQueueEntry* 242011375Sandreas.hansson@arm.comCache::getNextQueueEntry() 242111051Sandreas.hansson@arm.com{ 242211051Sandreas.hansson@arm.com // Check both MSHR queue and write buffer for potential requests, 242311051Sandreas.hansson@arm.com // note that null does not mean there is no request, it could 242411051Sandreas.hansson@arm.com // simply be that it is not ready 242511375Sandreas.hansson@arm.com MSHR *miss_mshr = mshrQueue.getNext(); 242611375Sandreas.hansson@arm.com WriteQueueEntry *wq_entry = writeBuffer.getNext(); 242711051Sandreas.hansson@arm.com 242811051Sandreas.hansson@arm.com // If we got a write buffer request ready, first priority is a 242911453Sandreas.hansson@arm.com // full write buffer, otherwise we favour the miss requests 243011453Sandreas.hansson@arm.com if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) { 243111051Sandreas.hansson@arm.com // need to search MSHR queue for conflicting earlier miss. 243211051Sandreas.hansson@arm.com MSHR *conflict_mshr = 243311375Sandreas.hansson@arm.com mshrQueue.findPending(wq_entry->blkAddr, 243411375Sandreas.hansson@arm.com wq_entry->isSecure); 243511375Sandreas.hansson@arm.com 243611375Sandreas.hansson@arm.com if (conflict_mshr && conflict_mshr->order < wq_entry->order) { 243711051Sandreas.hansson@arm.com // Service misses in order until conflict is cleared. 243811051Sandreas.hansson@arm.com return conflict_mshr; 243911051Sandreas.hansson@arm.com 244011051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 244111051Sandreas.hansson@arm.com } 244211051Sandreas.hansson@arm.com 244311051Sandreas.hansson@arm.com // No conflicts; issue write 244411375Sandreas.hansson@arm.com return wq_entry; 244511051Sandreas.hansson@arm.com } else if (miss_mshr) { 244611051Sandreas.hansson@arm.com // need to check for conflicting earlier writeback 244711375Sandreas.hansson@arm.com WriteQueueEntry *conflict_mshr = 244811051Sandreas.hansson@arm.com writeBuffer.findPending(miss_mshr->blkAddr, 244911051Sandreas.hansson@arm.com miss_mshr->isSecure); 245011051Sandreas.hansson@arm.com if (conflict_mshr) { 245111051Sandreas.hansson@arm.com // not sure why we don't check order here... it was in the 245211051Sandreas.hansson@arm.com // original code but commented out. 245311051Sandreas.hansson@arm.com 245411051Sandreas.hansson@arm.com // The only way this happens is if we are 245511051Sandreas.hansson@arm.com // doing a write and we didn't have permissions 245611051Sandreas.hansson@arm.com // then subsequently saw a writeback (owned got evicted) 245711051Sandreas.hansson@arm.com // We need to make sure to perform the writeback first 245811051Sandreas.hansson@arm.com // To preserve the dirty data, then we can issue the write 245911051Sandreas.hansson@arm.com 246011375Sandreas.hansson@arm.com // should we return wq_entry here instead? I.e. do we 246111051Sandreas.hansson@arm.com // have to flush writes in order? I don't think so... not 246211051Sandreas.hansson@arm.com // for Alpha anyway. Maybe for x86? 246311051Sandreas.hansson@arm.com return conflict_mshr; 246411051Sandreas.hansson@arm.com 246511051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 246611051Sandreas.hansson@arm.com } 246711051Sandreas.hansson@arm.com 246811051Sandreas.hansson@arm.com // No conflicts; issue read 246911051Sandreas.hansson@arm.com return miss_mshr; 247011051Sandreas.hansson@arm.com } 247111051Sandreas.hansson@arm.com 247211051Sandreas.hansson@arm.com // fall through... no pending requests. Try a prefetch. 247311375Sandreas.hansson@arm.com assert(!miss_mshr && !wq_entry); 247411051Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 247511051Sandreas.hansson@arm.com // If we have a miss queue slot, we can try a prefetch 247611051Sandreas.hansson@arm.com PacketPtr pkt = prefetcher->getPacket(); 247711051Sandreas.hansson@arm.com if (pkt) { 247811892Snikos.nikoleris@arm.com Addr pf_addr = pkt->getBlockAddr(blkSize); 247911051Sandreas.hansson@arm.com if (!tags->findBlock(pf_addr, pkt->isSecure()) && 248011051Sandreas.hansson@arm.com !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 248111051Sandreas.hansson@arm.com !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 248211051Sandreas.hansson@arm.com // Update statistic on number of prefetches issued 248311051Sandreas.hansson@arm.com // (hwpf_mshr_misses) 248411051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 248511051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 248611051Sandreas.hansson@arm.com 248711051Sandreas.hansson@arm.com // allocate an MSHR and return it, note 248811051Sandreas.hansson@arm.com // that we send the packet straight away, so do not 248911051Sandreas.hansson@arm.com // schedule the send 249011051Sandreas.hansson@arm.com return allocateMissBuffer(pkt, curTick(), false); 249111051Sandreas.hansson@arm.com } else { 249211051Sandreas.hansson@arm.com // free the request and packet 249311051Sandreas.hansson@arm.com delete pkt->req; 249411051Sandreas.hansson@arm.com delete pkt; 249511051Sandreas.hansson@arm.com } 249611051Sandreas.hansson@arm.com } 249711051Sandreas.hansson@arm.com } 249811051Sandreas.hansson@arm.com 249911375Sandreas.hansson@arm.com return nullptr; 250011051Sandreas.hansson@arm.com} 250111051Sandreas.hansson@arm.com 250211051Sandreas.hansson@arm.combool 250311130Sali.jafri@arm.comCache::isCachedAbove(PacketPtr pkt, bool is_timing) const 250411051Sandreas.hansson@arm.com{ 250511051Sandreas.hansson@arm.com if (!forwardSnoops) 250611051Sandreas.hansson@arm.com return false; 250711051Sandreas.hansson@arm.com // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and 250811051Sandreas.hansson@arm.com // Writeback snoops into upper level caches to check for copies of the 250911051Sandreas.hansson@arm.com // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict 251011051Sandreas.hansson@arm.com // packet, the cache can inform the crossbar below of presence or absence 251111051Sandreas.hansson@arm.com // of the block. 251211130Sali.jafri@arm.com if (is_timing) { 251311130Sali.jafri@arm.com Packet snoop_pkt(pkt, true, false); 251411130Sali.jafri@arm.com snoop_pkt.setExpressSnoop(); 251511130Sali.jafri@arm.com // Assert that packet is either Writeback or CleanEvict and not a 251611130Sali.jafri@arm.com // prefetch request because prefetch requests need an MSHR and may 251711130Sali.jafri@arm.com // generate a snoop response. 251812345Snikos.nikoleris@arm.com assert(pkt->isEviction() || pkt->cmd == MemCmd::WriteClean); 251911484Snikos.nikoleris@arm.com snoop_pkt.senderState = nullptr; 252011130Sali.jafri@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 252111130Sali.jafri@arm.com // Writeback/CleanEvict snoops do not generate a snoop response. 252211284Sandreas.hansson@arm.com assert(!(snoop_pkt.cacheResponding())); 252311130Sali.jafri@arm.com return snoop_pkt.isBlockCached(); 252411130Sali.jafri@arm.com } else { 252511130Sali.jafri@arm.com cpuSidePort->sendAtomicSnoop(pkt); 252611130Sali.jafri@arm.com return pkt->isBlockCached(); 252711130Sali.jafri@arm.com } 252811051Sandreas.hansson@arm.com} 252911051Sandreas.hansson@arm.com 253011375Sandreas.hansson@arm.comTick 253111375Sandreas.hansson@arm.comCache::nextQueueReadyTime() const 253211051Sandreas.hansson@arm.com{ 253311375Sandreas.hansson@arm.com Tick nextReady = std::min(mshrQueue.nextReadyTime(), 253411375Sandreas.hansson@arm.com writeBuffer.nextReadyTime()); 253511375Sandreas.hansson@arm.com 253611375Sandreas.hansson@arm.com // Don't signal prefetch ready time if no MSHRs available 253711375Sandreas.hansson@arm.com // Will signal once enoguh MSHRs are deallocated 253811375Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 253911375Sandreas.hansson@arm.com nextReady = std::min(nextReady, 254011375Sandreas.hansson@arm.com prefetcher->nextPrefetchReadyTime()); 254111051Sandreas.hansson@arm.com } 254211051Sandreas.hansson@arm.com 254311375Sandreas.hansson@arm.com return nextReady; 254411375Sandreas.hansson@arm.com} 254511375Sandreas.hansson@arm.com 254611375Sandreas.hansson@arm.combool 254711375Sandreas.hansson@arm.comCache::sendMSHRQueuePacket(MSHR* mshr) 254811375Sandreas.hansson@arm.com{ 254911375Sandreas.hansson@arm.com assert(mshr); 255011375Sandreas.hansson@arm.com 255111051Sandreas.hansson@arm.com // use request from 1st target 255211051Sandreas.hansson@arm.com PacketPtr tgt_pkt = mshr->getTarget()->pkt; 255311375Sandreas.hansson@arm.com 255411744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print()); 255511051Sandreas.hansson@arm.com 255611051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 255711051Sandreas.hansson@arm.com 255811051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) { 255911375Sandreas.hansson@arm.com // we should never have hardware prefetches to allocated 256011375Sandreas.hansson@arm.com // blocks 256111484Snikos.nikoleris@arm.com assert(blk == nullptr); 256211375Sandreas.hansson@arm.com 256311051Sandreas.hansson@arm.com // We need to check the caches above us to verify that 256411051Sandreas.hansson@arm.com // they don't have a copy of this block in the dirty state 256511051Sandreas.hansson@arm.com // at the moment. Without this check we could get a stale 256611051Sandreas.hansson@arm.com // copy from memory that might get used in place of the 256711051Sandreas.hansson@arm.com // dirty one. 256811051Sandreas.hansson@arm.com Packet snoop_pkt(tgt_pkt, true, false); 256911051Sandreas.hansson@arm.com snoop_pkt.setExpressSnoop(); 257011275Sandreas.hansson@arm.com // We are sending this packet upwards, but if it hits we will 257111275Sandreas.hansson@arm.com // get a snoop response that we end up treating just like a 257211275Sandreas.hansson@arm.com // normal response, hence it needs the MSHR as its sender 257311275Sandreas.hansson@arm.com // state 257411051Sandreas.hansson@arm.com snoop_pkt.senderState = mshr; 257511051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 257611051Sandreas.hansson@arm.com 257711051Sandreas.hansson@arm.com // Check to see if the prefetch was squashed by an upper cache (to 257811051Sandreas.hansson@arm.com // prevent us from grabbing the line) or if a Check to see if a 257911051Sandreas.hansson@arm.com // writeback arrived between the time the prefetch was placed in 258011051Sandreas.hansson@arm.com // the MSHRs and when it was selected to be sent or if the 258111051Sandreas.hansson@arm.com // prefetch was squashed by an upper cache. 258211051Sandreas.hansson@arm.com 258311284Sandreas.hansson@arm.com // It is important to check cacheResponding before 258411284Sandreas.hansson@arm.com // prefetchSquashed. If another cache has committed to 258511284Sandreas.hansson@arm.com // responding, it will be sending a dirty response which will 258611284Sandreas.hansson@arm.com // arrive at the MSHR allocated for this request. Checking the 258711284Sandreas.hansson@arm.com // prefetchSquash first may result in the MSHR being 258811284Sandreas.hansson@arm.com // prematurely deallocated. 258911284Sandreas.hansson@arm.com if (snoop_pkt.cacheResponding()) { 259011276Sandreas.hansson@arm.com auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req); 259111276Sandreas.hansson@arm.com assert(r.second); 259211284Sandreas.hansson@arm.com 259311284Sandreas.hansson@arm.com // if we are getting a snoop response with no sharers it 259411284Sandreas.hansson@arm.com // will be allocated as Modified 259511284Sandreas.hansson@arm.com bool pending_modified_resp = !snoop_pkt.hasSharers(); 259611284Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 259711284Sandreas.hansson@arm.com 259811051Sandreas.hansson@arm.com DPRINTF(Cache, "Upward snoop of prefetch for addr" 259911051Sandreas.hansson@arm.com " %#x (%s) hit\n", 260011051Sandreas.hansson@arm.com tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns"); 260111375Sandreas.hansson@arm.com return false; 260211051Sandreas.hansson@arm.com } 260311051Sandreas.hansson@arm.com 260411375Sandreas.hansson@arm.com if (snoop_pkt.isBlockCached()) { 260511051Sandreas.hansson@arm.com DPRINTF(Cache, "Block present, prefetch squashed by cache. " 260611051Sandreas.hansson@arm.com "Deallocating mshr target %#x.\n", 260711051Sandreas.hansson@arm.com mshr->blkAddr); 260811375Sandreas.hansson@arm.com 260911051Sandreas.hansson@arm.com // Deallocate the mshr target 261011375Sandreas.hansson@arm.com if (mshrQueue.forceDeallocateTarget(mshr)) { 261111277Sandreas.hansson@arm.com // Clear block if this deallocation resulted freed an 261211277Sandreas.hansson@arm.com // mshr when all had previously been utilized 261311375Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 261411051Sandreas.hansson@arm.com } 261512167Spau.cabre@metempsy.com 261612167Spau.cabre@metempsy.com // given that no response is expected, delete Request and Packet 261712167Spau.cabre@metempsy.com delete tgt_pkt->req; 261812167Spau.cabre@metempsy.com delete tgt_pkt; 261912167Spau.cabre@metempsy.com 262011375Sandreas.hansson@arm.com return false; 262111051Sandreas.hansson@arm.com } 262211051Sandreas.hansson@arm.com } 262311051Sandreas.hansson@arm.com 262411375Sandreas.hansson@arm.com // either a prefetch that is not present upstream, or a normal 262511375Sandreas.hansson@arm.com // MSHR request, proceed to get the packet to send downstream 262611452Sandreas.hansson@arm.com PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable()); 262711375Sandreas.hansson@arm.com 262811484Snikos.nikoleris@arm.com mshr->isForward = (pkt == nullptr); 262911375Sandreas.hansson@arm.com 263011375Sandreas.hansson@arm.com if (mshr->isForward) { 263111375Sandreas.hansson@arm.com // not a cache block request, but a response is expected 263211375Sandreas.hansson@arm.com // make copy of current packet to forward, keep current 263311375Sandreas.hansson@arm.com // copy for response handling 263411375Sandreas.hansson@arm.com pkt = new Packet(tgt_pkt, false, true); 263511375Sandreas.hansson@arm.com assert(!pkt->isWrite()); 263611375Sandreas.hansson@arm.com } 263711375Sandreas.hansson@arm.com 263811375Sandreas.hansson@arm.com // play it safe and append (rather than set) the sender state, 263911375Sandreas.hansson@arm.com // as forwarded packets may already have existing state 264011375Sandreas.hansson@arm.com pkt->pushSenderState(mshr); 264111375Sandreas.hansson@arm.com 264212349Snikos.nikoleris@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 264312349Snikos.nikoleris@arm.com // A cache clean opearation is looking for a dirty block. Mark 264412349Snikos.nikoleris@arm.com // the packet so that the destination xbar can determine that 264512349Snikos.nikoleris@arm.com // there will be a follow-up write packet as well. 264612349Snikos.nikoleris@arm.com pkt->setSatisfied(); 264712349Snikos.nikoleris@arm.com } 264812349Snikos.nikoleris@arm.com 264911375Sandreas.hansson@arm.com if (!memSidePort->sendTimingReq(pkt)) { 265011375Sandreas.hansson@arm.com // we are awaiting a retry, but we 265111375Sandreas.hansson@arm.com // delete the packet and will be creating a new packet 265211375Sandreas.hansson@arm.com // when we get the opportunity 265311375Sandreas.hansson@arm.com delete pkt; 265411375Sandreas.hansson@arm.com 265511375Sandreas.hansson@arm.com // note that we have now masked any requestBus and 265611375Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 265711375Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 265811375Sandreas.hansson@arm.com // care about this packet and might override it before 265911375Sandreas.hansson@arm.com // it gets retried 266011375Sandreas.hansson@arm.com return true; 266111375Sandreas.hansson@arm.com } else { 266211375Sandreas.hansson@arm.com // As part of the call to sendTimingReq the packet is 266311375Sandreas.hansson@arm.com // forwarded to all neighbouring caches (and any caches 266411375Sandreas.hansson@arm.com // above them) as a snoop. Thus at this point we know if 266511375Sandreas.hansson@arm.com // any of the neighbouring caches are responding, and if 266611375Sandreas.hansson@arm.com // so, we know it is dirty, and we can determine if it is 266711375Sandreas.hansson@arm.com // being passed as Modified, making our MSHR the ordering 266811375Sandreas.hansson@arm.com // point 266911375Sandreas.hansson@arm.com bool pending_modified_resp = !pkt->hasSharers() && 267011375Sandreas.hansson@arm.com pkt->cacheResponding(); 267111375Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 267212349Snikos.nikoleris@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 267312349Snikos.nikoleris@arm.com // A cache clean opearation is looking for a dirty 267412349Snikos.nikoleris@arm.com // block. If a dirty block is encountered a WriteClean 267512349Snikos.nikoleris@arm.com // will update any copies to the path to the memory 267612349Snikos.nikoleris@arm.com // until the point of reference. 267712349Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 267812349Snikos.nikoleris@arm.com __func__, pkt->print(), blk->print()); 267912351Snikos.nikoleris@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), 268012351Snikos.nikoleris@arm.com pkt->id); 268112349Snikos.nikoleris@arm.com PacketList writebacks; 268212349Snikos.nikoleris@arm.com writebacks.push_back(wb_pkt); 268312349Snikos.nikoleris@arm.com doWritebacks(writebacks, 0); 268412349Snikos.nikoleris@arm.com } 268512349Snikos.nikoleris@arm.com 268611375Sandreas.hansson@arm.com return false; 268711375Sandreas.hansson@arm.com } 268811375Sandreas.hansson@arm.com} 268911375Sandreas.hansson@arm.com 269011375Sandreas.hansson@arm.combool 269111375Sandreas.hansson@arm.comCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry) 269211375Sandreas.hansson@arm.com{ 269311375Sandreas.hansson@arm.com assert(wq_entry); 269411375Sandreas.hansson@arm.com 269511375Sandreas.hansson@arm.com // always a single target for write queue entries 269611375Sandreas.hansson@arm.com PacketPtr tgt_pkt = wq_entry->getTarget()->pkt; 269711375Sandreas.hansson@arm.com 269811744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print()); 269911375Sandreas.hansson@arm.com 270011453Sandreas.hansson@arm.com // forward as is, both for evictions and uncacheable writes 270111453Sandreas.hansson@arm.com if (!memSidePort->sendTimingReq(tgt_pkt)) { 270211375Sandreas.hansson@arm.com // note that we have now masked any requestBus and 270311375Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 270411375Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 270511375Sandreas.hansson@arm.com // care about this packet and might override it before 270611375Sandreas.hansson@arm.com // it gets retried 270711375Sandreas.hansson@arm.com return true; 270811375Sandreas.hansson@arm.com } else { 270911375Sandreas.hansson@arm.com markInService(wq_entry); 271011375Sandreas.hansson@arm.com return false; 271111051Sandreas.hansson@arm.com } 271211051Sandreas.hansson@arm.com} 271311051Sandreas.hansson@arm.com 271411051Sandreas.hansson@arm.comvoid 271511051Sandreas.hansson@arm.comCache::serialize(CheckpointOut &cp) const 271611051Sandreas.hansson@arm.com{ 271711051Sandreas.hansson@arm.com bool dirty(isDirty()); 271811051Sandreas.hansson@arm.com 271911051Sandreas.hansson@arm.com if (dirty) { 272011051Sandreas.hansson@arm.com warn("*** The cache still contains dirty data. ***\n"); 272111051Sandreas.hansson@arm.com warn(" Make sure to drain the system using the correct flags.\n"); 272211483Snikos.nikoleris@arm.com warn(" This checkpoint will not restore correctly and dirty data " 272311483Snikos.nikoleris@arm.com " in the cache will be lost!\n"); 272411051Sandreas.hansson@arm.com } 272511051Sandreas.hansson@arm.com 272611051Sandreas.hansson@arm.com // Since we don't checkpoint the data in the cache, any dirty data 272711051Sandreas.hansson@arm.com // will be lost when restoring from a checkpoint of a system that 272811051Sandreas.hansson@arm.com // wasn't drained properly. Flag the checkpoint as invalid if the 272911051Sandreas.hansson@arm.com // cache contains dirty data. 273011051Sandreas.hansson@arm.com bool bad_checkpoint(dirty); 273111051Sandreas.hansson@arm.com SERIALIZE_SCALAR(bad_checkpoint); 273211051Sandreas.hansson@arm.com} 273311051Sandreas.hansson@arm.com 273411051Sandreas.hansson@arm.comvoid 273511051Sandreas.hansson@arm.comCache::unserialize(CheckpointIn &cp) 273611051Sandreas.hansson@arm.com{ 273711051Sandreas.hansson@arm.com bool bad_checkpoint; 273811051Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(bad_checkpoint); 273911051Sandreas.hansson@arm.com if (bad_checkpoint) { 274011051Sandreas.hansson@arm.com fatal("Restoring from checkpoints with dirty caches is not supported " 274111051Sandreas.hansson@arm.com "in the classic memory system. Please remove any caches or " 274211051Sandreas.hansson@arm.com " drain them properly before taking checkpoints.\n"); 274311051Sandreas.hansson@arm.com } 274411051Sandreas.hansson@arm.com} 274511051Sandreas.hansson@arm.com 274611051Sandreas.hansson@arm.com/////////////// 274711051Sandreas.hansson@arm.com// 274811051Sandreas.hansson@arm.com// CpuSidePort 274911051Sandreas.hansson@arm.com// 275011051Sandreas.hansson@arm.com/////////////// 275111051Sandreas.hansson@arm.com 275211051Sandreas.hansson@arm.comAddrRangeList 275311051Sandreas.hansson@arm.comCache::CpuSidePort::getAddrRanges() const 275411051Sandreas.hansson@arm.com{ 275511051Sandreas.hansson@arm.com return cache->getAddrRanges(); 275611051Sandreas.hansson@arm.com} 275711051Sandreas.hansson@arm.com 275811051Sandreas.hansson@arm.combool 275912343Snikos.nikoleris@arm.comCache::CpuSidePort::tryTiming(PacketPtr pkt) 276012343Snikos.nikoleris@arm.com{ 276112343Snikos.nikoleris@arm.com assert(!cache->system->bypassCaches()); 276212343Snikos.nikoleris@arm.com 276312343Snikos.nikoleris@arm.com // always let express snoop packets through if even if blocked 276412343Snikos.nikoleris@arm.com if (pkt->isExpressSnoop()) { 276512343Snikos.nikoleris@arm.com return true; 276612343Snikos.nikoleris@arm.com } else if (isBlocked() || mustSendRetry) { 276712343Snikos.nikoleris@arm.com // either already committed to send a retry, or blocked 276812343Snikos.nikoleris@arm.com mustSendRetry = true; 276912343Snikos.nikoleris@arm.com return false; 277012343Snikos.nikoleris@arm.com } 277112343Snikos.nikoleris@arm.com mustSendRetry = false; 277212343Snikos.nikoleris@arm.com return true; 277312343Snikos.nikoleris@arm.com} 277412343Snikos.nikoleris@arm.com 277512343Snikos.nikoleris@arm.combool 277611051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingReq(PacketPtr pkt) 277711051Sandreas.hansson@arm.com{ 277811051Sandreas.hansson@arm.com assert(!cache->system->bypassCaches()); 277911051Sandreas.hansson@arm.com 278011334Sandreas.hansson@arm.com // always let express snoop packets through if even if blocked 278112630Snikos.nikoleris@arm.com if (pkt->isExpressSnoop() || tryTiming(pkt)) { 278212630Snikos.nikoleris@arm.com cache->recvTimingReq(pkt); 278311051Sandreas.hansson@arm.com return true; 278411051Sandreas.hansson@arm.com } 278512630Snikos.nikoleris@arm.com return false; 278611051Sandreas.hansson@arm.com} 278711051Sandreas.hansson@arm.com 278811051Sandreas.hansson@arm.comTick 278911051Sandreas.hansson@arm.comCache::CpuSidePort::recvAtomic(PacketPtr pkt) 279011051Sandreas.hansson@arm.com{ 279111051Sandreas.hansson@arm.com return cache->recvAtomic(pkt); 279211051Sandreas.hansson@arm.com} 279311051Sandreas.hansson@arm.com 279411051Sandreas.hansson@arm.comvoid 279511051Sandreas.hansson@arm.comCache::CpuSidePort::recvFunctional(PacketPtr pkt) 279611051Sandreas.hansson@arm.com{ 279711051Sandreas.hansson@arm.com // functional request 279811051Sandreas.hansson@arm.com cache->functionalAccess(pkt, true); 279911051Sandreas.hansson@arm.com} 280011051Sandreas.hansson@arm.com 280111051Sandreas.hansson@arm.comCache:: 280211051Sandreas.hansson@arm.comCpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache, 280311051Sandreas.hansson@arm.com const std::string &_label) 280411051Sandreas.hansson@arm.com : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache) 280511051Sandreas.hansson@arm.com{ 280611051Sandreas.hansson@arm.com} 280711051Sandreas.hansson@arm.com 280811053Sandreas.hansson@arm.comCache* 280911053Sandreas.hansson@arm.comCacheParams::create() 281011053Sandreas.hansson@arm.com{ 281111053Sandreas.hansson@arm.com assert(tags); 281212600Sodanrc@yahoo.com.br assert(replacement_policy); 281311053Sandreas.hansson@arm.com 281411053Sandreas.hansson@arm.com return new Cache(this); 281511053Sandreas.hansson@arm.com} 281611051Sandreas.hansson@arm.com/////////////// 281711051Sandreas.hansson@arm.com// 281811051Sandreas.hansson@arm.com// MemSidePort 281911051Sandreas.hansson@arm.com// 282011051Sandreas.hansson@arm.com/////////////// 282111051Sandreas.hansson@arm.com 282211051Sandreas.hansson@arm.combool 282311051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingResp(PacketPtr pkt) 282411051Sandreas.hansson@arm.com{ 282511051Sandreas.hansson@arm.com cache->recvTimingResp(pkt); 282611051Sandreas.hansson@arm.com return true; 282711051Sandreas.hansson@arm.com} 282811051Sandreas.hansson@arm.com 282911051Sandreas.hansson@arm.com// Express snooping requests to memside port 283011051Sandreas.hansson@arm.comvoid 283111051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 283211051Sandreas.hansson@arm.com{ 283311051Sandreas.hansson@arm.com // handle snooping requests 283411051Sandreas.hansson@arm.com cache->recvTimingSnoopReq(pkt); 283511051Sandreas.hansson@arm.com} 283611051Sandreas.hansson@arm.com 283711051Sandreas.hansson@arm.comTick 283811051Sandreas.hansson@arm.comCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 283911051Sandreas.hansson@arm.com{ 284011051Sandreas.hansson@arm.com return cache->recvAtomicSnoop(pkt); 284111051Sandreas.hansson@arm.com} 284211051Sandreas.hansson@arm.com 284311051Sandreas.hansson@arm.comvoid 284411051Sandreas.hansson@arm.comCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 284511051Sandreas.hansson@arm.com{ 284611051Sandreas.hansson@arm.com // functional snoop (note that in contrast to atomic we don't have 284711051Sandreas.hansson@arm.com // a specific functionalSnoop method, as they have the same 284811051Sandreas.hansson@arm.com // behaviour regardless) 284911051Sandreas.hansson@arm.com cache->functionalAccess(pkt, false); 285011051Sandreas.hansson@arm.com} 285111051Sandreas.hansson@arm.com 285211051Sandreas.hansson@arm.comvoid 285311051Sandreas.hansson@arm.comCache::CacheReqPacketQueue::sendDeferredPacket() 285411051Sandreas.hansson@arm.com{ 285511051Sandreas.hansson@arm.com // sanity check 285611051Sandreas.hansson@arm.com assert(!waitingOnRetry); 285711051Sandreas.hansson@arm.com 285811051Sandreas.hansson@arm.com // there should never be any deferred request packets in the 285911051Sandreas.hansson@arm.com // queue, instead we resly on the cache to provide the packets 286011051Sandreas.hansson@arm.com // from the MSHR queue or write queue 286111051Sandreas.hansson@arm.com assert(deferredPacketReadyTime() == MaxTick); 286211051Sandreas.hansson@arm.com 286311051Sandreas.hansson@arm.com // check for request packets (requests & writebacks) 286411375Sandreas.hansson@arm.com QueueEntry* entry = cache.getNextQueueEntry(); 286511375Sandreas.hansson@arm.com 286611375Sandreas.hansson@arm.com if (!entry) { 286711051Sandreas.hansson@arm.com // can happen if e.g. we attempt a writeback and fail, but 286811051Sandreas.hansson@arm.com // before the retry, the writeback is eliminated because 286911051Sandreas.hansson@arm.com // we snoop another cache's ReadEx. 287011051Sandreas.hansson@arm.com } else { 287111051Sandreas.hansson@arm.com // let our snoop responses go first if there are responses to 287211375Sandreas.hansson@arm.com // the same addresses 287311375Sandreas.hansson@arm.com if (checkConflictingSnoop(entry->blkAddr)) { 287411051Sandreas.hansson@arm.com return; 287511051Sandreas.hansson@arm.com } 287611375Sandreas.hansson@arm.com waitingOnRetry = entry->sendPacket(cache); 287711051Sandreas.hansson@arm.com } 287811051Sandreas.hansson@arm.com 287911051Sandreas.hansson@arm.com // if we succeeded and are not waiting for a retry, schedule the 288011375Sandreas.hansson@arm.com // next send considering when the next queue is ready, note that 288111051Sandreas.hansson@arm.com // snoop responses have their own packet queue and thus schedule 288211051Sandreas.hansson@arm.com // their own events 288311051Sandreas.hansson@arm.com if (!waitingOnRetry) { 288411375Sandreas.hansson@arm.com schedSendEvent(cache.nextQueueReadyTime()); 288511051Sandreas.hansson@arm.com } 288611051Sandreas.hansson@arm.com} 288711051Sandreas.hansson@arm.com 288811051Sandreas.hansson@arm.comCache:: 288911051Sandreas.hansson@arm.comMemSidePort::MemSidePort(const std::string &_name, Cache *_cache, 289011051Sandreas.hansson@arm.com const std::string &_label) 289111051Sandreas.hansson@arm.com : BaseCache::CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 289211051Sandreas.hansson@arm.com _reqQueue(*_cache, *this, _snoopRespQueue, _label), 289311051Sandreas.hansson@arm.com _snoopRespQueue(*_cache, *this, _label), cache(_cache) 289411051Sandreas.hansson@arm.com{ 289511051Sandreas.hansson@arm.com} 2896