cache.cc revision 12630
12810Srdreslin@umich.edu/* 211375Sandreas.hansson@arm.com * Copyright (c) 2010-2018 ARM Limited 311051Sandreas.hansson@arm.com * All rights reserved. 411051Sandreas.hansson@arm.com * 511051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911051Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311051Sandreas.hansson@arm.com * 1411051Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511051Sandreas.hansson@arm.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 162810Srdreslin@umich.edu * All rights reserved. 172810Srdreslin@umich.edu * 182810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 192810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 202810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 212810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 222810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 232810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 242810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 252810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 262810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 272810Srdreslin@umich.edu * this software without specific prior written permission. 282810Srdreslin@umich.edu * 292810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810Srdreslin@umich.edu * 412810Srdreslin@umich.edu * Authors: Erik Hallnor 4211051Sandreas.hansson@arm.com * Dave Greene 4311051Sandreas.hansson@arm.com * Nathan Binkert 442810Srdreslin@umich.edu * Steve Reinhardt 4511051Sandreas.hansson@arm.com * Ron Dreslinski 4611051Sandreas.hansson@arm.com * Andreas Sandberg 472810Srdreslin@umich.edu * Nikos Nikoleris 482810Srdreslin@umich.edu */ 492810Srdreslin@umich.edu 502810Srdreslin@umich.edu/** 5111051Sandreas.hansson@arm.com * @file 522810Srdreslin@umich.edu * Cache definitions. 532810Srdreslin@umich.edu */ 5411051Sandreas.hansson@arm.com 552810Srdreslin@umich.edu#include "mem/cache/cache.hh" 5611051Sandreas.hansson@arm.com 5711051Sandreas.hansson@arm.com#include "base/logging.hh" 5811051Sandreas.hansson@arm.com#include "base/types.hh" 5911051Sandreas.hansson@arm.com#include "debug/Cache.hh" 6011051Sandreas.hansson@arm.com#include "debug/CachePort.hh" 6111288Ssteve.reinhardt@amd.com#include "debug/CacheTags.hh" 6211051Sandreas.hansson@arm.com#include "debug/CacheVerbose.hh" 6311051Sandreas.hansson@arm.com#include "mem/cache/blk.hh" 6411051Sandreas.hansson@arm.com#include "mem/cache/mshr.hh" 6511051Sandreas.hansson@arm.com#include "mem/cache/prefetch/base.hh" 6611051Sandreas.hansson@arm.com#include "sim/sim_exit.hh" 6711053Sandreas.hansson@arm.com 6811053Sandreas.hansson@arm.comCache::Cache(const CacheParams *p) 6911051Sandreas.hansson@arm.com : BaseCache(p, p->system->cacheLineSize()), 7011051Sandreas.hansson@arm.com tags(p->tags), 7111051Sandreas.hansson@arm.com prefetcher(p->prefetcher), 7211197Sandreas.hansson@arm.com doFastWrites(true), 7311197Sandreas.hansson@arm.com prefetchOnAccess(p->prefetch_on_access), 7411199Sandreas.hansson@arm.com clusivity(p->clusivity), 7511197Sandreas.hansson@arm.com writebackClean(p->writeback_clean), 7611197Sandreas.hansson@arm.com tempBlockWriteback(nullptr), 7711197Sandreas.hansson@arm.com writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); }, 7811051Sandreas.hansson@arm.com name(), false, 7911051Sandreas.hansson@arm.com EventBase::Delayed_Writeback_Pri) 8011051Sandreas.hansson@arm.com{ 8111051Sandreas.hansson@arm.com tempBlock = new CacheBlk(); 8211051Sandreas.hansson@arm.com tempBlock->data = new uint8_t[blkSize]; 8311051Sandreas.hansson@arm.com 8411051Sandreas.hansson@arm.com cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this, 8511051Sandreas.hansson@arm.com "CpuSidePort"); 8611051Sandreas.hansson@arm.com memSidePort = new MemSidePort(p->name + ".mem_side", this, 8711051Sandreas.hansson@arm.com "MemSidePort"); 8811051Sandreas.hansson@arm.com 8911051Sandreas.hansson@arm.com tags->setCache(this); 9011051Sandreas.hansson@arm.com if (prefetcher) 9111051Sandreas.hansson@arm.com prefetcher->setCache(this); 9211051Sandreas.hansson@arm.com} 9311051Sandreas.hansson@arm.com 9411051Sandreas.hansson@arm.comCache::~Cache() 9511051Sandreas.hansson@arm.com{ 9611051Sandreas.hansson@arm.com delete [] tempBlock->data; 9711051Sandreas.hansson@arm.com delete tempBlock; 9811051Sandreas.hansson@arm.com 9911051Sandreas.hansson@arm.com delete cpuSidePort; 10011051Sandreas.hansson@arm.com delete memSidePort; 10111051Sandreas.hansson@arm.com} 10211051Sandreas.hansson@arm.com 10311051Sandreas.hansson@arm.comvoid 10411051Sandreas.hansson@arm.comCache::regStats() 10511051Sandreas.hansson@arm.com{ 10611051Sandreas.hansson@arm.com BaseCache::regStats(); 10711051Sandreas.hansson@arm.com} 10811051Sandreas.hansson@arm.com 10911051Sandreas.hansson@arm.comvoid 11011051Sandreas.hansson@arm.comCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 11111051Sandreas.hansson@arm.com{ 11211051Sandreas.hansson@arm.com assert(pkt->isRequest()); 11311051Sandreas.hansson@arm.com 11411051Sandreas.hansson@arm.com uint64_t overwrite_val; 11511051Sandreas.hansson@arm.com bool overwrite_mem; 11611051Sandreas.hansson@arm.com uint64_t condition_val64; 11711051Sandreas.hansson@arm.com uint32_t condition_val32; 11811051Sandreas.hansson@arm.com 11911051Sandreas.hansson@arm.com int offset = tags->extractBlkOffset(pkt->getAddr()); 12011051Sandreas.hansson@arm.com uint8_t *blk_data = blk->data + offset; 12111051Sandreas.hansson@arm.com 12211051Sandreas.hansson@arm.com assert(sizeof(uint64_t) >= pkt->getSize()); 12311051Sandreas.hansson@arm.com 12411051Sandreas.hansson@arm.com overwrite_mem = true; 12511051Sandreas.hansson@arm.com // keep a copy of our possible write value, and copy what is at the 12611051Sandreas.hansson@arm.com // memory address into the packet 12711051Sandreas.hansson@arm.com pkt->writeData((uint8_t *)&overwrite_val); 12811051Sandreas.hansson@arm.com pkt->setData(blk_data); 12911051Sandreas.hansson@arm.com 13011051Sandreas.hansson@arm.com if (pkt->req->isCondSwap()) { 13111051Sandreas.hansson@arm.com if (pkt->getSize() == sizeof(uint64_t)) { 13211051Sandreas.hansson@arm.com condition_val64 = pkt->req->getExtraData(); 13311051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val64, blk_data, 13411051Sandreas.hansson@arm.com sizeof(uint64_t)); 13511051Sandreas.hansson@arm.com } else if (pkt->getSize() == sizeof(uint32_t)) { 13611051Sandreas.hansson@arm.com condition_val32 = (uint32_t)pkt->req->getExtraData(); 13711051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val32, blk_data, 13811051Sandreas.hansson@arm.com sizeof(uint32_t)); 13911051Sandreas.hansson@arm.com } else 14011051Sandreas.hansson@arm.com panic("Invalid size for conditional read/write\n"); 14111051Sandreas.hansson@arm.com } 14211051Sandreas.hansson@arm.com 14311051Sandreas.hansson@arm.com if (overwrite_mem) { 14411051Sandreas.hansson@arm.com std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 14511051Sandreas.hansson@arm.com blk->status |= BlkDirty; 14611051Sandreas.hansson@arm.com } 14711051Sandreas.hansson@arm.com} 14811051Sandreas.hansson@arm.com 14911051Sandreas.hansson@arm.com 15011051Sandreas.hansson@arm.comvoid 15111051Sandreas.hansson@arm.comCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, 15211051Sandreas.hansson@arm.com bool deferred_response, bool pending_downgrade) 15311051Sandreas.hansson@arm.com{ 15411051Sandreas.hansson@arm.com assert(pkt->isRequest()); 15511051Sandreas.hansson@arm.com 15611051Sandreas.hansson@arm.com assert(blk && blk->isValid()); 15711051Sandreas.hansson@arm.com // Occasionally this is not true... if we are a lower-level cache 15811051Sandreas.hansson@arm.com // satisfying a string of Read and ReadEx requests from 15911051Sandreas.hansson@arm.com // upper-level caches, a Read will mark the block as shared but we 16011051Sandreas.hansson@arm.com // can satisfy a following ReadEx anyway since we can rely on the 16111284Sandreas.hansson@arm.com // Read requester(s) to have buffered the ReadEx snoop and to 16211051Sandreas.hansson@arm.com // invalidate their blocks after receiving them. 16311051Sandreas.hansson@arm.com // assert(!pkt->needsWritable() || blk->isWritable()); 16411051Sandreas.hansson@arm.com assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 16511051Sandreas.hansson@arm.com 16611051Sandreas.hansson@arm.com // Check RMW operations first since both isRead() and 16711051Sandreas.hansson@arm.com // isWrite() will be true for them 16811051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::SwapReq) { 16911284Sandreas.hansson@arm.com cmpAndSwap(blk, pkt); 17011284Sandreas.hansson@arm.com } else if (pkt->isWrite()) { 17111284Sandreas.hansson@arm.com // we have the block in a writable state and can go ahead, 17211284Sandreas.hansson@arm.com // note that the line may be also be considered writable in 17311051Sandreas.hansson@arm.com // downstream caches along the path to memory, but always 17411284Sandreas.hansson@arm.com // Exclusive, and never Modified 17511051Sandreas.hansson@arm.com assert(blk->isWritable()); 17611051Sandreas.hansson@arm.com // Write or WriteLine at the first cache with block in writable state 17711051Sandreas.hansson@arm.com if (blk->checkWrite(pkt)) { 17811284Sandreas.hansson@arm.com pkt->writeDataToBlock(blk->data, blkSize); 17911284Sandreas.hansson@arm.com } 18011284Sandreas.hansson@arm.com // Always mark the line as dirty (and thus transition to the 18111284Sandreas.hansson@arm.com // Modified state) even if we are a failed StoreCond so we 18211051Sandreas.hansson@arm.com // supply data to any snoops that have appended themselves to 18311288Ssteve.reinhardt@amd.com // this cache before knowing the store will fail. 18411288Ssteve.reinhardt@amd.com blk->status |= BlkDirty; 18511051Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s for %s (write)\n", __func__, pkt->print()); 18611051Sandreas.hansson@arm.com } else if (pkt->isRead()) { 18711051Sandreas.hansson@arm.com if (pkt->isLLSC()) { 18811051Sandreas.hansson@arm.com blk->trackLoadLocked(pkt); 18911286Sandreas.hansson@arm.com } 19011286Sandreas.hansson@arm.com 19111286Sandreas.hansson@arm.com // all read responses have a data payload 19211051Sandreas.hansson@arm.com assert(pkt->hasRespData()); 19311286Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 19411051Sandreas.hansson@arm.com 19511051Sandreas.hansson@arm.com // determine if this read is from a (coherent) cache or not 19611051Sandreas.hansson@arm.com if (pkt->fromCache()) { 19711051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 19811051Sandreas.hansson@arm.com // special handling for coherent block requests from 19911051Sandreas.hansson@arm.com // upper-level caches 20011051Sandreas.hansson@arm.com if (pkt->needsWritable()) { 20111051Sandreas.hansson@arm.com // sanity check 20211051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::ReadExReq || 20311051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq); 20411051Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 20511284Sandreas.hansson@arm.com 20611051Sandreas.hansson@arm.com // if we have a dirty copy, make sure the recipient 20711051Sandreas.hansson@arm.com // keeps it marked dirty (in the modified state) 20811051Sandreas.hansson@arm.com if (blk->isDirty()) { 20911051Sandreas.hansson@arm.com pkt->setCacheResponding(); 21011051Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 21111284Sandreas.hansson@arm.com } 21211051Sandreas.hansson@arm.com } else if (blk->isWritable() && !pending_downgrade && 21311284Sandreas.hansson@arm.com !pkt->hasSharers() && 21411051Sandreas.hansson@arm.com pkt->cmd != MemCmd::ReadCleanReq) { 21511197Sandreas.hansson@arm.com // we can give the requester a writable copy on a read 21611197Sandreas.hansson@arm.com // request if: 21711197Sandreas.hansson@arm.com // - we have a writable copy at this level (& below) 21811197Sandreas.hansson@arm.com // - we don't have a pending snoop from below 21911051Sandreas.hansson@arm.com // signaling another read request 22011284Sandreas.hansson@arm.com // - no other cache above has a copy (otherwise it 22111051Sandreas.hansson@arm.com // would have set hasSharers flag when 22211284Sandreas.hansson@arm.com // snooping the packet) 22311284Sandreas.hansson@arm.com // - the read has explicitly asked for a clean 22411284Sandreas.hansson@arm.com // copy of the line 22511051Sandreas.hansson@arm.com if (blk->isDirty()) { 22611051Sandreas.hansson@arm.com // special considerations if we're owner: 22711051Sandreas.hansson@arm.com if (!deferred_response) { 22811284Sandreas.hansson@arm.com // respond with the line in Modified state 22911284Sandreas.hansson@arm.com // (cacheResponding set, hasSharers not set) 23011284Sandreas.hansson@arm.com pkt->setCacheResponding(); 23111284Sandreas.hansson@arm.com 23211051Sandreas.hansson@arm.com // if this cache is mostly inclusive, we 23311051Sandreas.hansson@arm.com // keep the block in the Exclusive state, 23411051Sandreas.hansson@arm.com // and pass it upwards as Modified 23511284Sandreas.hansson@arm.com // (writable and dirty), hence we have 23611284Sandreas.hansson@arm.com // multiple caches, all on the same path 23711284Sandreas.hansson@arm.com // towards memory, all considering the 23811197Sandreas.hansson@arm.com // same block writable, but only one 23911284Sandreas.hansson@arm.com // considering it Modified 24011284Sandreas.hansson@arm.com 24111284Sandreas.hansson@arm.com // we get away with multiple caches (on 24211284Sandreas.hansson@arm.com // the same path to memory) considering 24311284Sandreas.hansson@arm.com // the block writeable as we always enter 24411284Sandreas.hansson@arm.com // the cache hierarchy through a cache, 24511284Sandreas.hansson@arm.com // and first snoop upwards in all other 24611284Sandreas.hansson@arm.com // branches 24711284Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 24811284Sandreas.hansson@arm.com } else { 24911284Sandreas.hansson@arm.com // if we're responding after our own miss, 25011284Sandreas.hansson@arm.com // there's a window where the recipient didn't 25111284Sandreas.hansson@arm.com // know it was getting ownership and may not 25211284Sandreas.hansson@arm.com // have responded to snoops correctly, so we 25311284Sandreas.hansson@arm.com // have to respond with a shared line 25411197Sandreas.hansson@arm.com pkt->setHasSharers(); 25511284Sandreas.hansson@arm.com } 25611284Sandreas.hansson@arm.com } 25711284Sandreas.hansson@arm.com } else { 25811284Sandreas.hansson@arm.com // otherwise only respond with a shared copy 25911284Sandreas.hansson@arm.com pkt->setHasSharers(); 26011284Sandreas.hansson@arm.com } 26111284Sandreas.hansson@arm.com } 26211197Sandreas.hansson@arm.com } else if (pkt->isUpgrade()) { 26311051Sandreas.hansson@arm.com // sanity check 26411051Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 26511051Sandreas.hansson@arm.com 26611051Sandreas.hansson@arm.com if (blk->isDirty()) { 26711051Sandreas.hansson@arm.com // we were in the Owned state, and a cache above us that 26811284Sandreas.hansson@arm.com // has the line in Shared state needs to be made aware 26911284Sandreas.hansson@arm.com // that the data it already has is in fact dirty 27011051Sandreas.hansson@arm.com pkt->setCacheResponding(); 27111051Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 27211051Sandreas.hansson@arm.com } 27311051Sandreas.hansson@arm.com } else { 27411284Sandreas.hansson@arm.com assert(pkt->isInvalidate()); 27511051Sandreas.hansson@arm.com invalidateBlock(blk); 27611051Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s for %s (invalidation)\n", __func__, 27711051Sandreas.hansson@arm.com pkt->print()); 27811284Sandreas.hansson@arm.com } 27911051Sandreas.hansson@arm.com} 28011197Sandreas.hansson@arm.com 28111197Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28211197Sandreas.hansson@arm.com// 28311197Sandreas.hansson@arm.com// Access path: requests coming in from the CPU side 28411288Ssteve.reinhardt@amd.com// 28511051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28611051Sandreas.hansson@arm.com 28711051Sandreas.hansson@arm.combool 28811051Sandreas.hansson@arm.comCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 28911051Sandreas.hansson@arm.com PacketList &writebacks) 29011051Sandreas.hansson@arm.com{ 29111051Sandreas.hansson@arm.com // sanity check 29211051Sandreas.hansson@arm.com assert(pkt->isRequest()); 29311051Sandreas.hansson@arm.com 29411051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 29511051Sandreas.hansson@arm.com "Should never see a write in a read-only cache %s\n", 29611051Sandreas.hansson@arm.com name()); 29711051Sandreas.hansson@arm.com 29811051Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s for %s\n", __func__, pkt->print()); 29911051Sandreas.hansson@arm.com 30011051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 30111051Sandreas.hansson@arm.com DPRINTF(Cache, "uncacheable: %s\n", pkt->print()); 30211051Sandreas.hansson@arm.com 30311051Sandreas.hansson@arm.com // flush and invalidate any existing block 30411051Sandreas.hansson@arm.com CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure())); 30511051Sandreas.hansson@arm.com if (old_blk && old_blk->isValid()) { 30611288Ssteve.reinhardt@amd.com if (old_blk->isDirty() || writebackClean) 30711051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(old_blk)); 30811051Sandreas.hansson@arm.com else 30911051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(old_blk)); 31011051Sandreas.hansson@arm.com invalidateBlock(old_blk); 31111051Sandreas.hansson@arm.com } 31211051Sandreas.hansson@arm.com 31311051Sandreas.hansson@arm.com blk = nullptr; 31411051Sandreas.hansson@arm.com // lookupLatency is the latency in case the request is uncacheable. 31511051Sandreas.hansson@arm.com lat = lookupLatency; 31611051Sandreas.hansson@arm.com return false; 31711199Sandreas.hansson@arm.com } 31811051Sandreas.hansson@arm.com 31911051Sandreas.hansson@arm.com // Here lat is the value passed as parameter to accessBlock() function 32011051Sandreas.hansson@arm.com // that can modify its value. 32111051Sandreas.hansson@arm.com blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat); 32211051Sandreas.hansson@arm.com 32311051Sandreas.hansson@arm.com DPRINTF(Cache, "%s %s\n", pkt->print(), 32411051Sandreas.hansson@arm.com blk ? "hit " + blk->print() : "miss"); 32511051Sandreas.hansson@arm.com 32611051Sandreas.hansson@arm.com if (pkt->req->isCacheMaintenance()) { 32711051Sandreas.hansson@arm.com // A cache maintenance operation is always forwarded to the 32811051Sandreas.hansson@arm.com // memory below even if the block is found in dirty state. 32911051Sandreas.hansson@arm.com 33011051Sandreas.hansson@arm.com // We defer any changes to the state of the block until we 33111051Sandreas.hansson@arm.com // create and mark as in service the mshr for the downstream 33211051Sandreas.hansson@arm.com // packet. 33311051Sandreas.hansson@arm.com return false; 33411051Sandreas.hansson@arm.com } 33511051Sandreas.hansson@arm.com 33611051Sandreas.hansson@arm.com if (pkt->isEviction()) { 33711051Sandreas.hansson@arm.com // We check for presence of block in above caches before issuing 33811051Sandreas.hansson@arm.com // Writeback or CleanEvict to write buffer. Therefore the only 33911051Sandreas.hansson@arm.com // possible cases can be of a CleanEvict packet coming from above 34011051Sandreas.hansson@arm.com // encountering a Writeback generated in this cache peer cache and 34111051Sandreas.hansson@arm.com // waiting in the write buffer. Cases of upper level peer caches 34211051Sandreas.hansson@arm.com // generating CleanEvict and Writeback or simply CleanEvict and 34311199Sandreas.hansson@arm.com // CleanEvict almost simultaneously will be caught by snoops sent out 34411051Sandreas.hansson@arm.com // by crossbar. 34511051Sandreas.hansson@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(), 34611051Sandreas.hansson@arm.com pkt->isSecure()); 34711051Sandreas.hansson@arm.com if (wb_entry) { 34811051Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 34911051Sandreas.hansson@arm.com PacketPtr wbPkt = wb_entry->getTarget()->pkt; 35011051Sandreas.hansson@arm.com assert(wbPkt->isWriteback()); 35111051Sandreas.hansson@arm.com 35211375Sandreas.hansson@arm.com if (pkt->isCleanEviction()) { 35311375Sandreas.hansson@arm.com // The CleanEvict and WritebackClean snoops into other 35411375Sandreas.hansson@arm.com // peer caches of the same level while traversing the 35511199Sandreas.hansson@arm.com // crossbar. If a copy of the block is found, the 35611199Sandreas.hansson@arm.com // packet is deleted in the crossbar. Hence, none of 35711199Sandreas.hansson@arm.com // the other upper level caches connected to this 35811199Sandreas.hansson@arm.com // cache have the block, so we can clear the 35911199Sandreas.hansson@arm.com // BLOCK_CACHED flag in the Writeback if set and 36011199Sandreas.hansson@arm.com // discard the CleanEvict by returning true. 36111199Sandreas.hansson@arm.com wbPkt->clearBlockCached(); 36211199Sandreas.hansson@arm.com return true; 36311199Sandreas.hansson@arm.com } else { 36411199Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::WritebackDirty); 36511199Sandreas.hansson@arm.com // Dirty writeback from above trumps our clean 36611199Sandreas.hansson@arm.com // writeback... discard here 36711199Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 36811199Sandreas.hansson@arm.com markInService(wb_entry); 36911199Sandreas.hansson@arm.com delete wbPkt; 37011199Sandreas.hansson@arm.com } 37111199Sandreas.hansson@arm.com } 37211199Sandreas.hansson@arm.com } 37311199Sandreas.hansson@arm.com 37411199Sandreas.hansson@arm.com // Writeback handling is special case. We can write the block into 37511375Sandreas.hansson@arm.com // the cache without having a writeable copy (or any copy at all). 37611199Sandreas.hansson@arm.com if (pkt->isWriteback()) { 37711199Sandreas.hansson@arm.com assert(blkSize == pkt->getSize()); 37811051Sandreas.hansson@arm.com 37911051Sandreas.hansson@arm.com // we could get a clean writeback while we are having 38011051Sandreas.hansson@arm.com // outstanding accesses to a block, do the simple thing for 38111051Sandreas.hansson@arm.com // now and drop the clean writeback so that we do not upset 38211051Sandreas.hansson@arm.com // any ordering/decisions about ownership already taken 38311199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackClean && 38411051Sandreas.hansson@arm.com mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) { 38511199Sandreas.hansson@arm.com DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, " 38611199Sandreas.hansson@arm.com "dropping\n", pkt->getAddr()); 38711199Sandreas.hansson@arm.com return true; 38811199Sandreas.hansson@arm.com } 38911199Sandreas.hansson@arm.com 39011199Sandreas.hansson@arm.com if (blk == nullptr) { 39111199Sandreas.hansson@arm.com // need to do a replacement 39211199Sandreas.hansson@arm.com blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks); 39311199Sandreas.hansson@arm.com if (blk == nullptr) { 39411199Sandreas.hansson@arm.com // no replaceable block available: give up, fwd to next level. 39511199Sandreas.hansson@arm.com incMissCount(pkt); 39611199Sandreas.hansson@arm.com return false; 39711051Sandreas.hansson@arm.com } 39811051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 39911051Sandreas.hansson@arm.com 40011051Sandreas.hansson@arm.com blk->status = (BlkValid | BlkReadable); 40111051Sandreas.hansson@arm.com if (pkt->isSecure()) { 40211051Sandreas.hansson@arm.com blk->status |= BlkSecure; 40311051Sandreas.hansson@arm.com } 40411051Sandreas.hansson@arm.com } 40511051Sandreas.hansson@arm.com // only mark the block dirty if we got a writeback command, 40611051Sandreas.hansson@arm.com // and leave it as is for a clean writeback 40711051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackDirty) { 40811051Sandreas.hansson@arm.com assert(!blk->isDirty()); 40911051Sandreas.hansson@arm.com blk->status |= BlkDirty; 41011051Sandreas.hansson@arm.com } 41111051Sandreas.hansson@arm.com // if the packet does not have sharers, it is passing 41211199Sandreas.hansson@arm.com // writable, and we got the writeback in Modified or Exclusive 41311199Sandreas.hansson@arm.com // state, if not we are in the Owned or Shared state 41411199Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 41511199Sandreas.hansson@arm.com blk->status |= BlkWritable; 41611199Sandreas.hansson@arm.com } 41711284Sandreas.hansson@arm.com // nothing else to do; writeback doesn't expect response 41811284Sandreas.hansson@arm.com assert(!pkt->needsResponse()); 41911284Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 42011284Sandreas.hansson@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 42111051Sandreas.hansson@arm.com incHitCount(pkt); 42211051Sandreas.hansson@arm.com // populate the time when the block will be ready to access. 42311051Sandreas.hansson@arm.com blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay + 42411051Sandreas.hansson@arm.com pkt->payloadDelay; 42511051Sandreas.hansson@arm.com return true; 42611051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::CleanEvict) { 42711051Sandreas.hansson@arm.com if (blk != nullptr) { 42811051Sandreas.hansson@arm.com // Found the block in the tags, need to stop CleanEvict from 42911051Sandreas.hansson@arm.com // propagating further down the hierarchy. Returning true will 43011051Sandreas.hansson@arm.com // treat the CleanEvict like a satisfied write request and delete 43111051Sandreas.hansson@arm.com // it. 43211051Sandreas.hansson@arm.com return true; 43311051Sandreas.hansson@arm.com } 43411051Sandreas.hansson@arm.com // We didn't find the block here, propagate the CleanEvict further 43511051Sandreas.hansson@arm.com // down the memory hierarchy. Returning false will treat the CleanEvict 43611051Sandreas.hansson@arm.com // like a Writeback which could not find a replaceable block so has to 43711051Sandreas.hansson@arm.com // go to next level. 43811051Sandreas.hansson@arm.com return false; 43911051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::WriteClean) { 44011051Sandreas.hansson@arm.com // WriteClean handling is a special case. We can allocate a 44111051Sandreas.hansson@arm.com // block directly if it doesn't exist and we can update the 44211051Sandreas.hansson@arm.com // block immediately. The WriteClean transfers the ownership 44311483Snikos.nikoleris@arm.com // of the block as well. 44411483Snikos.nikoleris@arm.com assert(blkSize == pkt->getSize()); 44511051Sandreas.hansson@arm.com 44611051Sandreas.hansson@arm.com if (!blk) { 44711051Sandreas.hansson@arm.com if (pkt->writeThrough()) { 44811051Sandreas.hansson@arm.com // if this is a write through packet, we don't try to 44911051Sandreas.hansson@arm.com // allocate if the block is not present 45011051Sandreas.hansson@arm.com return false; 45111051Sandreas.hansson@arm.com } else { 45211284Sandreas.hansson@arm.com // a writeback that misses needs to allocate a new block 45311051Sandreas.hansson@arm.com blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), 45411051Sandreas.hansson@arm.com writebacks); 45511051Sandreas.hansson@arm.com if (!blk) { 45611051Sandreas.hansson@arm.com // no replaceable block available: give up, fwd to 45711051Sandreas.hansson@arm.com // next level. 45811051Sandreas.hansson@arm.com incMissCount(pkt); 45911051Sandreas.hansson@arm.com return false; 46011051Sandreas.hansson@arm.com } 46111051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 46211051Sandreas.hansson@arm.com 46311051Sandreas.hansson@arm.com blk->status = (BlkValid | BlkReadable); 46411051Sandreas.hansson@arm.com if (pkt->isSecure()) { 46511051Sandreas.hansson@arm.com blk->status |= BlkSecure; 46611051Sandreas.hansson@arm.com } 46711051Sandreas.hansson@arm.com } 46811051Sandreas.hansson@arm.com } 46911051Sandreas.hansson@arm.com 47011051Sandreas.hansson@arm.com // at this point either this is a writeback or a write-through 47111051Sandreas.hansson@arm.com // write clean operation and the block is already in this 47211051Sandreas.hansson@arm.com // cache, we need to update the data and the block flags 47311051Sandreas.hansson@arm.com assert(blk); 47411051Sandreas.hansson@arm.com assert(!blk->isDirty()); 47511051Sandreas.hansson@arm.com if (!pkt->writeThrough()) { 47611051Sandreas.hansson@arm.com blk->status |= BlkDirty; 47711051Sandreas.hansson@arm.com } 47811051Sandreas.hansson@arm.com // nothing else to do; writeback doesn't expect response 47911051Sandreas.hansson@arm.com assert(!pkt->needsResponse()); 48011051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 48111199Sandreas.hansson@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 48211199Sandreas.hansson@arm.com 48311199Sandreas.hansson@arm.com incHitCount(pkt); 48411199Sandreas.hansson@arm.com // populate the time when the block will be ready to access. 48511199Sandreas.hansson@arm.com blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay + 48611051Sandreas.hansson@arm.com pkt->payloadDelay; 48711199Sandreas.hansson@arm.com // if this a write-through packet it will be sent to cache 48811051Sandreas.hansson@arm.com // below 48911051Sandreas.hansson@arm.com return !pkt->writeThrough(); 49011051Sandreas.hansson@arm.com } else if (blk && (pkt->needsWritable() ? blk->isWritable() : 49111051Sandreas.hansson@arm.com blk->isReadable())) { 49211051Sandreas.hansson@arm.com // OK to satisfy access 49311051Sandreas.hansson@arm.com incHitCount(pkt); 49411051Sandreas.hansson@arm.com satisfyRequest(pkt, blk); 49511051Sandreas.hansson@arm.com maintainClusivity(pkt->fromCache(), blk); 49611051Sandreas.hansson@arm.com 49711051Sandreas.hansson@arm.com return true; 49811051Sandreas.hansson@arm.com } 49911051Sandreas.hansson@arm.com 50011051Sandreas.hansson@arm.com // Can't satisfy access normally... either no block (blk == nullptr) 50111051Sandreas.hansson@arm.com // or have block but need writable 50211051Sandreas.hansson@arm.com 50311051Sandreas.hansson@arm.com incMissCount(pkt); 50411051Sandreas.hansson@arm.com 50511130Sali.jafri@arm.com if (blk == nullptr && pkt->isLLSC() && pkt->isWrite()) { 50611130Sali.jafri@arm.com // complete miss on store conditional... just give up now 50711130Sali.jafri@arm.com pkt->req->setExtraData(0); 50811130Sali.jafri@arm.com return true; 50911130Sali.jafri@arm.com } 51011130Sali.jafri@arm.com 51111130Sali.jafri@arm.com return false; 51211130Sali.jafri@arm.com} 51311130Sali.jafri@arm.com 51411199Sandreas.hansson@arm.comvoid 51511130Sali.jafri@arm.comCache::maintainClusivity(bool from_cache, CacheBlk *blk) 51611130Sali.jafri@arm.com{ 51711130Sali.jafri@arm.com if (from_cache && blk && blk->isValid() && !blk->isDirty() && 51811130Sali.jafri@arm.com clusivity == Enums::mostly_excl) { 51911130Sali.jafri@arm.com // if we have responded to a cache, and our block is still 52011130Sali.jafri@arm.com // valid, but not dirty, and this cache is mostly exclusive 52111130Sali.jafri@arm.com // with respect to the cache above, drop the block 52211130Sali.jafri@arm.com invalidateBlock(blk); 52311130Sali.jafri@arm.com } 52411130Sali.jafri@arm.com} 52511130Sali.jafri@arm.com 52611130Sali.jafri@arm.comvoid 52711130Sali.jafri@arm.comCache::doWritebacks(PacketList& writebacks, Tick forward_time) 52811130Sali.jafri@arm.com{ 52911130Sali.jafri@arm.com while (!writebacks.empty()) { 53011130Sali.jafri@arm.com PacketPtr wbPkt = writebacks.front(); 53111130Sali.jafri@arm.com // We use forwardLatency here because we are copying writebacks to 53211130Sali.jafri@arm.com // write buffer. 53311130Sali.jafri@arm.com 53411130Sali.jafri@arm.com // Call isCachedAbove for Writebacks, CleanEvicts and 53511130Sali.jafri@arm.com // WriteCleans to discover if the block is cached above. 53611130Sali.jafri@arm.com if (isCachedAbove(wbPkt)) { 53711130Sali.jafri@arm.com if (wbPkt->cmd == MemCmd::CleanEvict) { 53811051Sandreas.hansson@arm.com // Delete CleanEvict because cached copies exist above. The 53911051Sandreas.hansson@arm.com // packet destructor will delete the request object because 54011051Sandreas.hansson@arm.com // this is a non-snoop request packet which does not require a 54111051Sandreas.hansson@arm.com // response. 54211051Sandreas.hansson@arm.com delete wbPkt; 54311051Sandreas.hansson@arm.com } else if (wbPkt->cmd == MemCmd::WritebackClean) { 54411051Sandreas.hansson@arm.com // clean writeback, do not send since the block is 54511051Sandreas.hansson@arm.com // still cached above 54611051Sandreas.hansson@arm.com assert(writebackClean); 54711051Sandreas.hansson@arm.com delete wbPkt; 54811276Sandreas.hansson@arm.com } else { 54911276Sandreas.hansson@arm.com assert(wbPkt->cmd == MemCmd::WritebackDirty || 55011276Sandreas.hansson@arm.com wbPkt->cmd == MemCmd::WriteClean); 55111276Sandreas.hansson@arm.com // Set BLOCK_CACHED flag in Writeback and send below, so that 55211276Sandreas.hansson@arm.com // the Writeback does not reset the bit corresponding to this 55311276Sandreas.hansson@arm.com // address in the snoop filter below. 55411276Sandreas.hansson@arm.com wbPkt->setBlockCached(); 55511276Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 55611276Sandreas.hansson@arm.com } 55711051Sandreas.hansson@arm.com } else { 55811276Sandreas.hansson@arm.com // If the block is not cached above, send packet below. Both 55911276Sandreas.hansson@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 56011276Sandreas.hansson@arm.com // reset the bit corresponding to this address in the snoop filter 56111276Sandreas.hansson@arm.com // below. 56211276Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 56311051Sandreas.hansson@arm.com } 56411051Sandreas.hansson@arm.com writebacks.pop_front(); 56511051Sandreas.hansson@arm.com } 56611051Sandreas.hansson@arm.com} 56711051Sandreas.hansson@arm.com 56811051Sandreas.hansson@arm.comvoid 56911051Sandreas.hansson@arm.comCache::doWritebacksAtomic(PacketList& writebacks) 57011051Sandreas.hansson@arm.com{ 57111051Sandreas.hansson@arm.com while (!writebacks.empty()) { 57211051Sandreas.hansson@arm.com PacketPtr wbPkt = writebacks.front(); 57311051Sandreas.hansson@arm.com // Call isCachedAbove for both Writebacks and CleanEvicts. If 57411051Sandreas.hansson@arm.com // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks 57511051Sandreas.hansson@arm.com // and discard CleanEvicts. 57611051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt, false)) { 57711051Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::WritebackDirty || 57811051Sandreas.hansson@arm.com wbPkt->cmd == MemCmd::WriteClean) { 57911051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag in Writeback and send below, 58011051Sandreas.hansson@arm.com // so that the Writeback does not reset the bit 58111051Sandreas.hansson@arm.com // corresponding to this address in the snoop filter 58211051Sandreas.hansson@arm.com // below. We can discard CleanEvicts because cached 58311051Sandreas.hansson@arm.com // copies exist above. Atomic mode isCachedAbove 58411051Sandreas.hansson@arm.com // modifies packet to set BLOCK_CACHED flag 58511051Sandreas.hansson@arm.com memSidePort->sendAtomic(wbPkt); 58611051Sandreas.hansson@arm.com } 58711051Sandreas.hansson@arm.com } else { 58811051Sandreas.hansson@arm.com // If the block is not cached above, send packet below. Both 58911051Sandreas.hansson@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 59011051Sandreas.hansson@arm.com // reset the bit corresponding to this address in the snoop filter 59111051Sandreas.hansson@arm.com // below. 59211051Sandreas.hansson@arm.com memSidePort->sendAtomic(wbPkt); 59311051Sandreas.hansson@arm.com } 59411051Sandreas.hansson@arm.com writebacks.pop_front(); 59511051Sandreas.hansson@arm.com // In case of CleanEvicts, the packet destructor will delete the 59611051Sandreas.hansson@arm.com // request object because this is a non-snoop request packet which 59711051Sandreas.hansson@arm.com // does not require a response. 59811051Sandreas.hansson@arm.com delete wbPkt; 59911051Sandreas.hansson@arm.com } 60011051Sandreas.hansson@arm.com} 60111051Sandreas.hansson@arm.com 60211051Sandreas.hansson@arm.com 60311051Sandreas.hansson@arm.comvoid 60411051Sandreas.hansson@arm.comCache::recvTimingSnoopResp(PacketPtr pkt) 60511284Sandreas.hansson@arm.com{ 60611051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s\n", __func__, pkt->print()); 60711284Sandreas.hansson@arm.com 60811284Sandreas.hansson@arm.com assert(pkt->isResponse()); 60911284Sandreas.hansson@arm.com assert(!system->bypassCaches()); 61011284Sandreas.hansson@arm.com 61111051Sandreas.hansson@arm.com // determine if the response is from a snoop request we created 61211051Sandreas.hansson@arm.com // (in which case it should be in the outstandingSnoop), or if we 61311284Sandreas.hansson@arm.com // merely forwarded someone else's snoop request 61411284Sandreas.hansson@arm.com const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) == 61511284Sandreas.hansson@arm.com outstandingSnoop.end(); 61611284Sandreas.hansson@arm.com 61711284Sandreas.hansson@arm.com if (!forwardAsSnoop) { 61811334Sandreas.hansson@arm.com // the packet came from this cache, so sink it here and do not 61911284Sandreas.hansson@arm.com // forward it 62011334Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::HardPFResp); 62111334Sandreas.hansson@arm.com 62211334Sandreas.hansson@arm.com outstandingSnoop.erase(pkt->req); 62311334Sandreas.hansson@arm.com 62411284Sandreas.hansson@arm.com DPRINTF(Cache, "Got prefetch response from above for addr " 62511334Sandreas.hansson@arm.com "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 62611334Sandreas.hansson@arm.com recvTimingResp(pkt); 62711334Sandreas.hansson@arm.com return; 62811334Sandreas.hansson@arm.com } 62911334Sandreas.hansson@arm.com 63011334Sandreas.hansson@arm.com // forwardLatency is set here because there is a response from an 63111051Sandreas.hansson@arm.com // upper level cache. 63211334Sandreas.hansson@arm.com // To pay the delay that occurs if the packet comes from the bus, 63311334Sandreas.hansson@arm.com // we charge also headerDelay. 63411334Sandreas.hansson@arm.com Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay; 63511334Sandreas.hansson@arm.com // Reset the timing of the packet. 63611051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 63711334Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, snoop_resp_time); 63811334Sandreas.hansson@arm.com} 63911334Sandreas.hansson@arm.com 64011051Sandreas.hansson@arm.comvoid 64111334Sandreas.hansson@arm.comCache::promoteWholeLineWrites(PacketPtr pkt) 64211334Sandreas.hansson@arm.com{ 64311334Sandreas.hansson@arm.com // Cache line clearing instructions 64411334Sandreas.hansson@arm.com if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) && 64511334Sandreas.hansson@arm.com (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) { 64611334Sandreas.hansson@arm.com pkt->cmd = MemCmd::WriteLineReq; 64711334Sandreas.hansson@arm.com DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n"); 64811051Sandreas.hansson@arm.com } 64911334Sandreas.hansson@arm.com} 65011334Sandreas.hansson@arm.com 65111334Sandreas.hansson@arm.comvoid 65211334Sandreas.hansson@arm.comCache::recvTimingReq(PacketPtr pkt) 65311334Sandreas.hansson@arm.com{ 65411334Sandreas.hansson@arm.com DPRINTF(CacheTags, "%s tags:\n%s\n", __func__, tags->print()); 65511334Sandreas.hansson@arm.com 65611334Sandreas.hansson@arm.com assert(pkt->isRequest()); 65711051Sandreas.hansson@arm.com 65811284Sandreas.hansson@arm.com // Just forward the packet if caches are disabled. 65911284Sandreas.hansson@arm.com if (system->bypassCaches()) { 66011190Sandreas.hansson@arm.com // @todo This should really enqueue the packet rather 66111051Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt); 66211334Sandreas.hansson@arm.com assert(success); 66311334Sandreas.hansson@arm.com return; 66411334Sandreas.hansson@arm.com } 66511334Sandreas.hansson@arm.com 66611334Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 66711051Sandreas.hansson@arm.com 66811051Sandreas.hansson@arm.com // Cache maintenance operations have to visit all the caches down 66911051Sandreas.hansson@arm.com // to the specified xbar (PoC, PoU, etc.). Even if a cache above 67011051Sandreas.hansson@arm.com // is responding we forward the packet to the memory below rather 67111051Sandreas.hansson@arm.com // than creating an express snoop. 67211051Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 67311051Sandreas.hansson@arm.com // a cache above us (but not where the packet came from) is 67411051Sandreas.hansson@arm.com // responding to the request, in other words it has the line 67511051Sandreas.hansson@arm.com // in Modified or Owned state 67611051Sandreas.hansson@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 67711051Sandreas.hansson@arm.com pkt->print()); 67811051Sandreas.hansson@arm.com 67911051Sandreas.hansson@arm.com // if the packet needs the block to be writable, and the cache 68011051Sandreas.hansson@arm.com // that has promised to respond (setting the cache responding 68111051Sandreas.hansson@arm.com // flag) is not providing writable (it is in Owned rather than 68211051Sandreas.hansson@arm.com // the Modified state), we know that there may be other Shared 68311051Sandreas.hansson@arm.com // copies in the system; go out and invalidate them all 68411051Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 68511051Sandreas.hansson@arm.com 68611051Sandreas.hansson@arm.com // an upstream cache that had the line in Owned state 68711051Sandreas.hansson@arm.com // (dirty, but not writable), is responding and thus 68811051Sandreas.hansson@arm.com // transferring the dirty line from one branch of the 68911051Sandreas.hansson@arm.com // cache hierarchy to another 69011051Sandreas.hansson@arm.com 69111051Sandreas.hansson@arm.com // send out an express snoop and invalidate all other 69211051Sandreas.hansson@arm.com // copies (snooping a packet that needs writable is the 69311051Sandreas.hansson@arm.com // same as an invalidation), thus turning the Owned line 69411051Sandreas.hansson@arm.com // into a Modified line, note that we don't invalidate the 69511051Sandreas.hansson@arm.com // block in the current cache or any other cache on the 69611051Sandreas.hansson@arm.com // path to memory 69711051Sandreas.hansson@arm.com 69811051Sandreas.hansson@arm.com // create a downstream express snoop with cleared packet 69911051Sandreas.hansson@arm.com // flags, there is no need to allocate any data as the 70011051Sandreas.hansson@arm.com // packet is merely used to co-ordinate state transitions 70111051Sandreas.hansson@arm.com Packet *snoop_pkt = new Packet(pkt, true, false); 70211051Sandreas.hansson@arm.com 70311051Sandreas.hansson@arm.com // also reset the bus time that the original packet has 70411051Sandreas.hansson@arm.com // not yet paid for 70511051Sandreas.hansson@arm.com snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0; 70611051Sandreas.hansson@arm.com 70711051Sandreas.hansson@arm.com // make this an instantaneous express snoop, and let the 70811051Sandreas.hansson@arm.com // other caches in the system know that the another cache 70911051Sandreas.hansson@arm.com // is responding, because we have found the authorative 71011051Sandreas.hansson@arm.com // copy (Modified or Owned) that will supply the right 71111051Sandreas.hansson@arm.com // data 71211051Sandreas.hansson@arm.com snoop_pkt->setExpressSnoop(); 71311483Snikos.nikoleris@arm.com snoop_pkt->setCacheResponding(); 71411483Snikos.nikoleris@arm.com 71511051Sandreas.hansson@arm.com // this express snoop travels towards the memory, and at 71611051Sandreas.hansson@arm.com // every crossbar it is snooped upwards thus reaching 71711051Sandreas.hansson@arm.com // every cache in the system 71811051Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(snoop_pkt); 71911051Sandreas.hansson@arm.com // express snoops always succeed 72011051Sandreas.hansson@arm.com assert(success); 72111051Sandreas.hansson@arm.com 72211051Sandreas.hansson@arm.com // main memory will delete the snoop packet 72311051Sandreas.hansson@arm.com 72411051Sandreas.hansson@arm.com // queue for deletion, as opposed to immediate deletion, as 72511051Sandreas.hansson@arm.com // the sending cache is still relying on the packet 72611051Sandreas.hansson@arm.com pendingDelete.reset(pkt); 72711051Sandreas.hansson@arm.com 72811051Sandreas.hansson@arm.com // no need to take any further action in this particular cache 72911051Sandreas.hansson@arm.com // as an upstram cache has already committed to responding, 73011051Sandreas.hansson@arm.com // and we have already sent out any express snoops in the 73111051Sandreas.hansson@arm.com // section above to ensure all other copies in the system are 73211051Sandreas.hansson@arm.com // invalidated 73311194Sali.jafri@arm.com return; 73411051Sandreas.hansson@arm.com } 73511199Sandreas.hansson@arm.com 73611199Sandreas.hansson@arm.com // anything that is merely forwarded pays for the forward latency and 73711199Sandreas.hansson@arm.com // the delay provided by the crossbar 73811199Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 73911190Sandreas.hansson@arm.com 74011190Sandreas.hansson@arm.com // We use lookupLatency here because it is used to specify the latency 74111190Sandreas.hansson@arm.com // to access. 74211190Sandreas.hansson@arm.com Cycles lat = lookupLatency; 74311190Sandreas.hansson@arm.com CacheBlk *blk = nullptr; 74411051Sandreas.hansson@arm.com bool satisfied = false; 74511051Sandreas.hansson@arm.com { 74611051Sandreas.hansson@arm.com PacketList writebacks; 74711051Sandreas.hansson@arm.com // Note that lat is passed by reference here. The function 74811051Sandreas.hansson@arm.com // access() calls accessBlock() which can modify lat value. 74911051Sandreas.hansson@arm.com satisfied = access(pkt, blk, lat, writebacks); 75011051Sandreas.hansson@arm.com 75111051Sandreas.hansson@arm.com // copy writebacks to write buffer here to ensure they logically 75211051Sandreas.hansson@arm.com // proceed anything happening below 75311051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 75411051Sandreas.hansson@arm.com } 75511051Sandreas.hansson@arm.com 75611051Sandreas.hansson@arm.com // Here we charge the headerDelay that takes into account the latencies 75711051Sandreas.hansson@arm.com // of the bus, if the packet comes from it. 75811051Sandreas.hansson@arm.com // The latency charged it is just lat that is the value of lookupLatency 75911051Sandreas.hansson@arm.com // modified by access() function, or if not just lookupLatency. 76011051Sandreas.hansson@arm.com // In case of a hit we are neglecting response latency. 76111051Sandreas.hansson@arm.com // In case of a miss we are neglecting forward latency. 76211051Sandreas.hansson@arm.com Tick request_time = clockEdge(lat) + pkt->headerDelay; 76311051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 76411051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 76511051Sandreas.hansson@arm.com 76611051Sandreas.hansson@arm.com // track time of availability of next prefetch, if any 76711051Sandreas.hansson@arm.com Tick next_pf_time = MaxTick; 76811051Sandreas.hansson@arm.com 76911051Sandreas.hansson@arm.com bool needsResponse = pkt->needsResponse(); 77011051Sandreas.hansson@arm.com 77111051Sandreas.hansson@arm.com if (satisfied) { 77211051Sandreas.hansson@arm.com // should never be satisfying an uncacheable access as we 77311051Sandreas.hansson@arm.com // flush and invalidate any existing block as part of the 77411051Sandreas.hansson@arm.com // lookup 77511051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 77611051Sandreas.hansson@arm.com 77711051Sandreas.hansson@arm.com // hit (for all other request types) 77811051Sandreas.hansson@arm.com 77911051Sandreas.hansson@arm.com if (prefetcher && (prefetchOnAccess || 78011051Sandreas.hansson@arm.com (blk && blk->wasPrefetched()))) { 78111051Sandreas.hansson@arm.com if (blk) 78211051Sandreas.hansson@arm.com blk->status &= ~BlkHWPrefetched; 78311051Sandreas.hansson@arm.com 78411051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 78511051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) { 78611051Sandreas.hansson@arm.com assert(!pkt->req->isCacheMaintenance()); 78711051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 78811286Sandreas.hansson@arm.com } 78911051Sandreas.hansson@arm.com } 79011051Sandreas.hansson@arm.com 79111194Sali.jafri@arm.com if (needsResponse) { 79211051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 79311051Sandreas.hansson@arm.com // @todo: Make someone pay for this 79411051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 79511051Sandreas.hansson@arm.com 79611051Sandreas.hansson@arm.com // In this case we are considering request_time that takes 79711051Sandreas.hansson@arm.com // into account the delay of the xbar, if any, and just 79811051Sandreas.hansson@arm.com // lat, neglecting responseLatency, modelling hit latency 79911051Sandreas.hansson@arm.com // just as lookupLatency or or the value of lat overriden 80011051Sandreas.hansson@arm.com // by access(), that calls accessBlock() function. 80111051Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 80211051Sandreas.hansson@arm.com } else { 80311051Sandreas.hansson@arm.com DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__, 80411051Sandreas.hansson@arm.com pkt->print()); 80511051Sandreas.hansson@arm.com 80611051Sandreas.hansson@arm.com // queue the packet for deletion, as the sending cache is 80711199Sandreas.hansson@arm.com // still relying on it; if the block is found in access(), 80811199Sandreas.hansson@arm.com // CleanEvict and Writeback messages will be deleted 80911199Sandreas.hansson@arm.com // here as well 81011051Sandreas.hansson@arm.com pendingDelete.reset(pkt); 81111190Sandreas.hansson@arm.com } 81211051Sandreas.hansson@arm.com } else { 81311483Snikos.nikoleris@arm.com // miss 81411483Snikos.nikoleris@arm.com 81511483Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 81611051Sandreas.hansson@arm.com 81711051Sandreas.hansson@arm.com // ignore any existing MSHR if we are dealing with an 81811051Sandreas.hansson@arm.com // uncacheable request 81911051Sandreas.hansson@arm.com MSHR *mshr = pkt->req->isUncacheable() ? nullptr : 82011051Sandreas.hansson@arm.com mshrQueue.findMatch(blk_addr, pkt->isSecure()); 82111051Sandreas.hansson@arm.com 82211051Sandreas.hansson@arm.com // Software prefetch handling: 82311051Sandreas.hansson@arm.com // To keep the core from waiting on data it won't look at 82411051Sandreas.hansson@arm.com // anyway, send back a response with dummy data. Miss handling 82511051Sandreas.hansson@arm.com // will continue asynchronously. Unfortunately, the core will 82611197Sandreas.hansson@arm.com // insist upon freeing original Packet/Request, so we have to 82711197Sandreas.hansson@arm.com // create a new pair with a different lifecycle. Note that this 82811051Sandreas.hansson@arm.com // processing happens before any MSHR munging on the behalf of 82911051Sandreas.hansson@arm.com // this request because this new Request will be the one stored 83011051Sandreas.hansson@arm.com // into the MSHRs, not the original. 83111051Sandreas.hansson@arm.com if (pkt->cmd.isSWPrefetch()) { 83211051Sandreas.hansson@arm.com assert(needsResponse); 83311051Sandreas.hansson@arm.com assert(pkt->req->hasPaddr()); 83411051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 83511051Sandreas.hansson@arm.com 83611051Sandreas.hansson@arm.com // There's no reason to add a prefetch as an additional target 83711051Sandreas.hansson@arm.com // to an existing MSHR. If an outstanding request is already 83811483Snikos.nikoleris@arm.com // in progress, there is nothing for the prefetch to do. 83911483Snikos.nikoleris@arm.com // If this is the case, we don't even create a request at all. 84011051Sandreas.hansson@arm.com PacketPtr pf = nullptr; 84111051Sandreas.hansson@arm.com 84211483Snikos.nikoleris@arm.com if (!mshr) { 84311483Snikos.nikoleris@arm.com // copy the request and create a new SoftPFReq packet 84411051Sandreas.hansson@arm.com RequestPtr req = new Request(pkt->req->getPaddr(), 84511051Sandreas.hansson@arm.com pkt->req->getSize(), 84611051Sandreas.hansson@arm.com pkt->req->getFlags(), 84711051Sandreas.hansson@arm.com pkt->req->masterId()); 84811051Sandreas.hansson@arm.com pf = new Packet(req, pkt->cmd); 84911051Sandreas.hansson@arm.com pf->allocate(); 85011051Sandreas.hansson@arm.com assert(pf->getAddr() == pkt->getAddr()); 85111051Sandreas.hansson@arm.com assert(pf->getSize() == pkt->getSize()); 85211051Sandreas.hansson@arm.com } 85311051Sandreas.hansson@arm.com 85411051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 85511051Sandreas.hansson@arm.com 85611051Sandreas.hansson@arm.com // request_time is used here, taking into account lat and the delay 85711051Sandreas.hansson@arm.com // charged if the packet comes from the xbar. 85811051Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 85911199Sandreas.hansson@arm.com 86011051Sandreas.hansson@arm.com // If an outstanding request is in progress (we found an 86111051Sandreas.hansson@arm.com // MSHR) this is set to null 86211051Sandreas.hansson@arm.com pkt = pf; 86311051Sandreas.hansson@arm.com } 86411051Sandreas.hansson@arm.com 86511051Sandreas.hansson@arm.com if (mshr) { 86611051Sandreas.hansson@arm.com /// MSHR hit 86711051Sandreas.hansson@arm.com /// @note writebacks will be checked in getNextMSHR() 86811051Sandreas.hansson@arm.com /// for any conflicting requests to the same block 86911051Sandreas.hansson@arm.com 87011051Sandreas.hansson@arm.com //@todo remove hw_pf here 87111051Sandreas.hansson@arm.com 87211051Sandreas.hansson@arm.com // Coalesce unless it was a software prefetch (see above). 87311051Sandreas.hansson@arm.com if (pkt) { 87411051Sandreas.hansson@arm.com assert(!pkt->isWriteback()); 87511051Sandreas.hansson@arm.com // CleanEvicts corresponding to blocks which have 87611051Sandreas.hansson@arm.com // outstanding requests in MSHRs are simply sunk here 87711051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::CleanEvict) { 87811051Sandreas.hansson@arm.com pendingDelete.reset(pkt); 87911051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::WriteClean) { 88011051Sandreas.hansson@arm.com // A WriteClean should never coalesce with any 88111051Sandreas.hansson@arm.com // outstanding cache maintenance requests. 88211051Sandreas.hansson@arm.com 88311051Sandreas.hansson@arm.com // We use forward_time here because there is an 88411284Sandreas.hansson@arm.com // uncached memory write, forwarded to WriteBuffer. 88511051Sandreas.hansson@arm.com allocateWriteBuffer(pkt, forward_time); 88611051Sandreas.hansson@arm.com } else { 88711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s coalescing MSHR for %s\n", __func__, 88811051Sandreas.hansson@arm.com pkt->print()); 88911051Sandreas.hansson@arm.com 89011051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 89111051Sandreas.hansson@arm.com mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 89211051Sandreas.hansson@arm.com // We use forward_time here because it is the same 89311051Sandreas.hansson@arm.com // considering new targets. We have multiple 89411051Sandreas.hansson@arm.com // requests for the same address here. It 89511051Sandreas.hansson@arm.com // specifies the latency to allocate an internal 89611051Sandreas.hansson@arm.com // buffer and to schedule an event to the queued 89711051Sandreas.hansson@arm.com // port and also takes into account the additional 89811051Sandreas.hansson@arm.com // delay of the xbar. 89911051Sandreas.hansson@arm.com mshr->allocateTarget(pkt, forward_time, order++, 90011051Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 90111051Sandreas.hansson@arm.com if (mshr->getNumTargets() == numTarget) { 90211051Sandreas.hansson@arm.com noTargetMSHR = mshr; 90311051Sandreas.hansson@arm.com setBlocked(Blocked_NoTargets); 90411051Sandreas.hansson@arm.com // need to be careful with this... if this mshr isn't 90511051Sandreas.hansson@arm.com // ready yet (i.e. time > curTick()), we don't want to 90611051Sandreas.hansson@arm.com // move it ahead of mshrs that are ready 90711051Sandreas.hansson@arm.com // mshrQueue.moveToFront(mshr); 90811051Sandreas.hansson@arm.com } 90911452Sandreas.hansson@arm.com } 91011452Sandreas.hansson@arm.com // We should call the prefetcher reguardless if the request is 91111051Sandreas.hansson@arm.com // satisfied or not, reguardless if the request is in the MSHR 91211452Sandreas.hansson@arm.com // or not. The request could be a ReadReq hit, but still not 91311452Sandreas.hansson@arm.com // satisfied (potentially because of a prior write to the same 91411452Sandreas.hansson@arm.com // cache line. So, even when not satisfied, tehre is an MSHR 91511051Sandreas.hansson@arm.com // already allocated for this, we need to let the prefetcher 91611051Sandreas.hansson@arm.com // know about the request 91711452Sandreas.hansson@arm.com if (prefetcher) { 91811452Sandreas.hansson@arm.com // Don't notify on SWPrefetch 91911452Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch() && 92011452Sandreas.hansson@arm.com !pkt->req->isCacheMaintenance()) 92111452Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 92211051Sandreas.hansson@arm.com } 92311051Sandreas.hansson@arm.com } 92411051Sandreas.hansson@arm.com } else { 92511051Sandreas.hansson@arm.com // no MSHR 92611051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 92711051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 92811051Sandreas.hansson@arm.com mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++; 92911051Sandreas.hansson@arm.com } else { 93011051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 93111051Sandreas.hansson@arm.com } 93211051Sandreas.hansson@arm.com 93311284Sandreas.hansson@arm.com if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean || 93411284Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 93511284Sandreas.hansson@arm.com // We use forward_time here because there is an 93611051Sandreas.hansson@arm.com // uncached memory write, forwarded to WriteBuffer. 93711051Sandreas.hansson@arm.com allocateWriteBuffer(pkt, forward_time); 93811051Sandreas.hansson@arm.com } else { 93911051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 94011051Sandreas.hansson@arm.com // should have flushed and have no valid block 94111051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 94211051Sandreas.hansson@arm.com 94311051Sandreas.hansson@arm.com // If we have a write miss to a valid block, we 94411051Sandreas.hansson@arm.com // need to mark the block non-readable. Otherwise 94511352Sandreas.hansson@arm.com // if we allow reads while there's an outstanding 94611352Sandreas.hansson@arm.com // write miss, the read could return stale data 94711051Sandreas.hansson@arm.com // out of the cache block... a more aggressive 94811284Sandreas.hansson@arm.com // system could detect the overlap (if any) and 94911051Sandreas.hansson@arm.com // forward data out of the MSHRs, but we don't do 95011051Sandreas.hansson@arm.com // that yet. Note that we do need to leave the 95111051Sandreas.hansson@arm.com // block valid so that it stays in the cache, in 95211051Sandreas.hansson@arm.com // case we get an upgrade response (and hence no 95311284Sandreas.hansson@arm.com // new data) when the write miss completes. 95411051Sandreas.hansson@arm.com // As long as CPUs do proper store/load forwarding 95511051Sandreas.hansson@arm.com // internally, and have a sufficiently weak memory 95611051Sandreas.hansson@arm.com // model, this is probably unnecessary, but at some 95711051Sandreas.hansson@arm.com // point it must have seemed like we needed it... 95811284Sandreas.hansson@arm.com assert((pkt->needsWritable() && !blk->isWritable()) || 95911284Sandreas.hansson@arm.com pkt->req->isCacheMaintenance()); 96011284Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 96111284Sandreas.hansson@arm.com } 96211051Sandreas.hansson@arm.com // Here we are using forward_time, modelling the latency of 96311051Sandreas.hansson@arm.com // a miss (outbound) just as forwardLatency, neglecting the 96411051Sandreas.hansson@arm.com // lookupLatency component. 96511284Sandreas.hansson@arm.com allocateMissBuffer(pkt, forward_time); 96611284Sandreas.hansson@arm.com } 96711284Sandreas.hansson@arm.com 96811284Sandreas.hansson@arm.com if (prefetcher) { 96911051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 97011051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch() && 97111051Sandreas.hansson@arm.com !pkt->req->isCacheMaintenance()) 97211051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 97311051Sandreas.hansson@arm.com } 97411051Sandreas.hansson@arm.com } 97511051Sandreas.hansson@arm.com } 97611051Sandreas.hansson@arm.com 97711051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 97811051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 97911051Sandreas.hansson@arm.com} 98011051Sandreas.hansson@arm.com 98111051Sandreas.hansson@arm.comPacketPtr 98211051Sandreas.hansson@arm.comCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 98311051Sandreas.hansson@arm.com bool needsWritable) const 98411051Sandreas.hansson@arm.com{ 98511051Sandreas.hansson@arm.com // should never see evictions here 98611051Sandreas.hansson@arm.com assert(!cpu_pkt->isEviction()); 98711051Sandreas.hansson@arm.com 98811051Sandreas.hansson@arm.com bool blkValid = blk && blk->isValid(); 98911051Sandreas.hansson@arm.com 99011051Sandreas.hansson@arm.com if (cpu_pkt->req->isUncacheable() || 99111051Sandreas.hansson@arm.com (!blkValid && cpu_pkt->isUpgrade()) || 99211051Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::InvalidateReq || cpu_pkt->isClean()) { 99311051Sandreas.hansson@arm.com // uncacheable requests and upgrades from upper-level caches 99411051Sandreas.hansson@arm.com // that missed completely just go through as is 99511051Sandreas.hansson@arm.com return nullptr; 99611333Sandreas.hansson@arm.com } 99711333Sandreas.hansson@arm.com 99811284Sandreas.hansson@arm.com assert(cpu_pkt->needsResponse()); 99911333Sandreas.hansson@arm.com 100011333Sandreas.hansson@arm.com MemCmd cmd; 100111333Sandreas.hansson@arm.com // @TODO make useUpgrades a parameter. 100211333Sandreas.hansson@arm.com // Note that ownership protocols require upgrade, otherwise a 100311333Sandreas.hansson@arm.com // write miss on a shared owned block will generate a ReadExcl, 100411333Sandreas.hansson@arm.com // which will clobber the owned copy. 100511333Sandreas.hansson@arm.com const bool useUpgrades = true; 100611334Sandreas.hansson@arm.com if (cpu_pkt->cmd == MemCmd::WriteLineReq) { 100711334Sandreas.hansson@arm.com assert(!blkValid || !blk->isWritable()); 100811051Sandreas.hansson@arm.com // forward as invalidate to all other caches, this gives us 100911051Sandreas.hansson@arm.com // the line in Exclusive state, and invalidates all other 101011051Sandreas.hansson@arm.com // copies 101111051Sandreas.hansson@arm.com cmd = MemCmd::InvalidateReq; 101211051Sandreas.hansson@arm.com } else if (blkValid && useUpgrades) { 101311051Sandreas.hansson@arm.com // only reason to be here is that blk is read only and we need 101411051Sandreas.hansson@arm.com // it to be writable 101511051Sandreas.hansson@arm.com assert(needsWritable); 101611051Sandreas.hansson@arm.com assert(!blk->isWritable()); 101711051Sandreas.hansson@arm.com cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq; 101811051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq || 101911051Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::StoreCondFailReq) { 102011051Sandreas.hansson@arm.com // Even though this SC will fail, we still need to send out the 102111051Sandreas.hansson@arm.com // request and get the data to supply it to other snoopers in the case 102211130Sali.jafri@arm.com // where the determination the StoreCond fails is delayed due to 102311051Sandreas.hansson@arm.com // all caches not being on the same local bus. 102411051Sandreas.hansson@arm.com cmd = MemCmd::SCUpgradeFailReq; 102511051Sandreas.hansson@arm.com } else { 102611051Sandreas.hansson@arm.com // block is invalid 102711452Sandreas.hansson@arm.com 102811452Sandreas.hansson@arm.com // If the request does not need a writable there are two cases 102911452Sandreas.hansson@arm.com // where we need to ensure the response will not fetch the 103011452Sandreas.hansson@arm.com // block in dirty state: 103111452Sandreas.hansson@arm.com // * this cache is read only and it does not perform 103211452Sandreas.hansson@arm.com // writebacks, 103311452Sandreas.hansson@arm.com // * this cache is mostly exclusive and will not fill (since 103411452Sandreas.hansson@arm.com // it does not fill it will have to writeback the dirty data 103511452Sandreas.hansson@arm.com // immediately which generates uneccesary writebacks). 103611452Sandreas.hansson@arm.com bool force_clean_rsp = isReadOnly || clusivity == Enums::mostly_excl; 103711051Sandreas.hansson@arm.com cmd = needsWritable ? MemCmd::ReadExReq : 103811051Sandreas.hansson@arm.com (force_clean_rsp ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq); 103911051Sandreas.hansson@arm.com } 104011051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize); 104111051Sandreas.hansson@arm.com 104211051Sandreas.hansson@arm.com // if there are upstream caches that have already marked the 104311051Sandreas.hansson@arm.com // packet as having sharers (not passing writable), pass that info 104411051Sandreas.hansson@arm.com // downstream 104511051Sandreas.hansson@arm.com if (cpu_pkt->hasSharers() && !needsWritable) { 104611051Sandreas.hansson@arm.com // note that cpu_pkt may have spent a considerable time in the 104711051Sandreas.hansson@arm.com // MSHR queue and that the information could possibly be out 104811051Sandreas.hansson@arm.com // of date, however, there is no harm in conservatively 104911051Sandreas.hansson@arm.com // assuming the block has sharers 105011051Sandreas.hansson@arm.com pkt->setHasSharers(); 105111051Sandreas.hansson@arm.com DPRINTF(Cache, "%s: passing hasSharers from %s to %s\n", 105211051Sandreas.hansson@arm.com __func__, cpu_pkt->print(), pkt->print()); 105311051Sandreas.hansson@arm.com } 105411051Sandreas.hansson@arm.com 105511051Sandreas.hansson@arm.com // the packet should be block aligned 105611452Sandreas.hansson@arm.com assert(pkt->getAddr() == pkt->getBlockAddr(blkSize)); 105711452Sandreas.hansson@arm.com 105811051Sandreas.hansson@arm.com pkt->allocate(); 105911483Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: created %s from %s\n", __func__, pkt->print(), 106011483Snikos.nikoleris@arm.com cpu_pkt->print()); 106111051Sandreas.hansson@arm.com return pkt; 106211051Sandreas.hansson@arm.com} 106311051Sandreas.hansson@arm.com 106411051Sandreas.hansson@arm.com 106511051Sandreas.hansson@arm.comTick 106611051Sandreas.hansson@arm.comCache::recvAtomic(PacketPtr pkt) 106711051Sandreas.hansson@arm.com{ 106811051Sandreas.hansson@arm.com // We are in atomic mode so we pay just for lookupLatency here. 106911051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 107011051Sandreas.hansson@arm.com 107111051Sandreas.hansson@arm.com // Forward the request if the system is in cache bypass mode. 107211051Sandreas.hansson@arm.com if (system->bypassCaches()) 107311051Sandreas.hansson@arm.com return ticksToCycles(memSidePort->sendAtomic(pkt)); 107411051Sandreas.hansson@arm.com 107511051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 107611051Sandreas.hansson@arm.com 107711051Sandreas.hansson@arm.com // follow the same flow as in recvTimingReq, and check if a cache 107811051Sandreas.hansson@arm.com // above us is responding 107911197Sandreas.hansson@arm.com if (pkt->cacheResponding() && !pkt->isClean()) { 108011197Sandreas.hansson@arm.com assert(!pkt->req->isCacheInvalidate()); 108111452Sandreas.hansson@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 108211452Sandreas.hansson@arm.com pkt->print()); 108311051Sandreas.hansson@arm.com 108411051Sandreas.hansson@arm.com // if a cache is responding, and it had the line in Owned 108511051Sandreas.hansson@arm.com // rather than Modified state, we need to invalidate any 108611051Sandreas.hansson@arm.com // copies that are not on the same path to memory 108711051Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 108811197Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 108911197Sandreas.hansson@arm.com 109011051Sandreas.hansson@arm.com return lat * clockPeriod(); 109111051Sandreas.hansson@arm.com } 109211051Sandreas.hansson@arm.com 109311051Sandreas.hansson@arm.com // should assert here that there are no outstanding MSHRs or 109411051Sandreas.hansson@arm.com // writebacks... that would mean that someone used an atomic 109511051Sandreas.hansson@arm.com // access in timing mode 109611051Sandreas.hansson@arm.com 109711051Sandreas.hansson@arm.com CacheBlk *blk = nullptr; 109811051Sandreas.hansson@arm.com PacketList writebacks; 109911452Sandreas.hansson@arm.com bool satisfied = access(pkt, blk, lat, writebacks); 110011452Sandreas.hansson@arm.com 110111452Sandreas.hansson@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 110211452Sandreas.hansson@arm.com // A cache clean opearation is looking for a dirty 110311051Sandreas.hansson@arm.com // block. If a dirty block is encountered a WriteClean 110411051Sandreas.hansson@arm.com // will update any copies to the path to the memory 110511051Sandreas.hansson@arm.com // until the point of reference. 110611051Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 110711051Sandreas.hansson@arm.com __func__, pkt->print(), blk->print()); 110811051Sandreas.hansson@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id); 110911051Sandreas.hansson@arm.com writebacks.push_back(wb_pkt); 111011051Sandreas.hansson@arm.com pkt->setSatisfied(); 111111051Sandreas.hansson@arm.com } 111211051Sandreas.hansson@arm.com 111311051Sandreas.hansson@arm.com // handle writebacks resulting from the access here to ensure they 111411051Sandreas.hansson@arm.com // logically proceed anything happening below 111511051Sandreas.hansson@arm.com doWritebacksAtomic(writebacks); 111611197Sandreas.hansson@arm.com 111711130Sali.jafri@arm.com if (!satisfied) { 111811051Sandreas.hansson@arm.com // MISS 111911197Sandreas.hansson@arm.com 112011197Sandreas.hansson@arm.com // deal with the packets that go through the write path of 112111197Sandreas.hansson@arm.com // the cache, i.e. any evictions and writes 112211197Sandreas.hansson@arm.com if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean || 112311197Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 112411197Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 112511197Sandreas.hansson@arm.com return lat * clockPeriod(); 112611197Sandreas.hansson@arm.com } 112711197Sandreas.hansson@arm.com // only misses left 112811197Sandreas.hansson@arm.com 112911197Sandreas.hansson@arm.com PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable()); 113011197Sandreas.hansson@arm.com 113111197Sandreas.hansson@arm.com bool is_forward = (bus_pkt == nullptr); 113211197Sandreas.hansson@arm.com 113311197Sandreas.hansson@arm.com if (is_forward) { 113411197Sandreas.hansson@arm.com // just forwarding the same request to the next level 113511197Sandreas.hansson@arm.com // no local cache operation involved 113611197Sandreas.hansson@arm.com bus_pkt = pkt; 113711197Sandreas.hansson@arm.com } 113811197Sandreas.hansson@arm.com 113911199Sandreas.hansson@arm.com DPRINTF(Cache, "%s: Sending an atomic %s\n", __func__, 114011199Sandreas.hansson@arm.com bus_pkt->print()); 114111197Sandreas.hansson@arm.com 114211197Sandreas.hansson@arm.com#if TRACING_ON 114311197Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 114411051Sandreas.hansson@arm.com#endif 114511051Sandreas.hansson@arm.com 114611051Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt)); 114711051Sandreas.hansson@arm.com 114811051Sandreas.hansson@arm.com bool is_invalidate = bus_pkt->isInvalidate(); 114911051Sandreas.hansson@arm.com 115011051Sandreas.hansson@arm.com // We are now dealing with the response handling 115111051Sandreas.hansson@arm.com DPRINTF(Cache, "%s: Receive response: %s in state %i\n", __func__, 115211051Sandreas.hansson@arm.com bus_pkt->print(), old_state); 115311051Sandreas.hansson@arm.com 115411051Sandreas.hansson@arm.com // If packet was a forward, the response (if any) is already 115511051Sandreas.hansson@arm.com // in place in the bus_pkt == pkt structure, so we don't need 115611051Sandreas.hansson@arm.com // to do anything. Otherwise, use the separate bus_pkt to 115711051Sandreas.hansson@arm.com // generate response to pkt and then delete it. 115811051Sandreas.hansson@arm.com if (!is_forward) { 115911051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 116011051Sandreas.hansson@arm.com assert(bus_pkt->isResponse()); 116111051Sandreas.hansson@arm.com if (bus_pkt->isError()) { 116211051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 116311051Sandreas.hansson@arm.com pkt->copyError(bus_pkt); 116411051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::WriteLineReq) { 116511051Sandreas.hansson@arm.com // note the use of pkt, not bus_pkt here. 116611051Sandreas.hansson@arm.com 116711051Sandreas.hansson@arm.com // write-line request to the cache that promoted 116811051Sandreas.hansson@arm.com // the write to a whole line 116911051Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks, 117011051Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 117111051Sandreas.hansson@arm.com assert(blk != NULL); 117211051Sandreas.hansson@arm.com is_invalidate = false; 117311051Sandreas.hansson@arm.com satisfyRequest(pkt, blk); 117411051Sandreas.hansson@arm.com } else if (bus_pkt->isRead() || 117511051Sandreas.hansson@arm.com bus_pkt->cmd == MemCmd::UpgradeResp) { 117611051Sandreas.hansson@arm.com // we're updating cache state to allow us to 117711051Sandreas.hansson@arm.com // satisfy the upstream request from the cache 117811051Sandreas.hansson@arm.com blk = handleFill(bus_pkt, blk, writebacks, 117911051Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 118011051Sandreas.hansson@arm.com satisfyRequest(pkt, blk); 118111051Sandreas.hansson@arm.com maintainClusivity(pkt->fromCache(), blk); 118211051Sandreas.hansson@arm.com } else { 118311051Sandreas.hansson@arm.com // we're satisfying the upstream request without 118411051Sandreas.hansson@arm.com // modifying cache state, e.g., a write-through 118511284Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 118611284Sandreas.hansson@arm.com } 118711051Sandreas.hansson@arm.com } 118811051Sandreas.hansson@arm.com delete bus_pkt; 118911284Sandreas.hansson@arm.com } 119011051Sandreas.hansson@arm.com 119111051Sandreas.hansson@arm.com if (is_invalidate && blk && blk->isValid()) { 119211051Sandreas.hansson@arm.com invalidateBlock(blk); 119311051Sandreas.hansson@arm.com } 119411051Sandreas.hansson@arm.com } 119511051Sandreas.hansson@arm.com 119611051Sandreas.hansson@arm.com // Note that we don't invoke the prefetcher at all in atomic mode. 119711288Ssteve.reinhardt@amd.com // It's not clear how to do it properly, particularly for 119811051Sandreas.hansson@arm.com // prefetchers that aggressively generate prefetch candidates and 119911051Sandreas.hansson@arm.com // rely on bandwidth contention to throttle them; these will tend 120011051Sandreas.hansson@arm.com // to pollute the cache in atomic mode since there is no bandwidth 120111051Sandreas.hansson@arm.com // contention. If we ever do want to enable prefetching in atomic 120211051Sandreas.hansson@arm.com // mode, though, this is the place to do it... see timingAccess() 120311051Sandreas.hansson@arm.com // for an example (though we'd want to issue the prefetch(es) 120411051Sandreas.hansson@arm.com // immediately rather than calling requestMemSideBus() as we do 120511051Sandreas.hansson@arm.com // there). 120611051Sandreas.hansson@arm.com 120711051Sandreas.hansson@arm.com // do any writebacks resulting from the response handling 120811051Sandreas.hansson@arm.com doWritebacksAtomic(writebacks); 120911051Sandreas.hansson@arm.com 121011051Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and if so 121111051Sandreas.hansson@arm.com // clear it out, but only do so after the call to recvAtomic is 121211051Sandreas.hansson@arm.com // finished so that any downstream observers (such as a snoop 121311051Sandreas.hansson@arm.com // filter), first see the fill, and only then see the eviction 121411051Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 121511051Sandreas.hansson@arm.com // the atomic CPU calls recvAtomic for fetch and load/store 121611051Sandreas.hansson@arm.com // sequentuially, and we may already have a tempBlock 121711051Sandreas.hansson@arm.com // writeback from the fetch that we have not yet sent 121811051Sandreas.hansson@arm.com if (tempBlockWriteback) { 121911051Sandreas.hansson@arm.com // if that is the case, write the prevoius one back, and 122011051Sandreas.hansson@arm.com // do not schedule any new event 122111051Sandreas.hansson@arm.com writebackTempBlockAtomic(); 122211051Sandreas.hansson@arm.com } else { 122311051Sandreas.hansson@arm.com // the writeback/clean eviction happens after the call to 122411051Sandreas.hansson@arm.com // recvAtomic has finished (but before any successive 122511051Sandreas.hansson@arm.com // calls), so that the response handling from the fill is 122611051Sandreas.hansson@arm.com // allowed to happen first 122711051Sandreas.hansson@arm.com schedule(writebackTempBlockAtomicEvent, curTick()); 122811051Sandreas.hansson@arm.com } 122911375Sandreas.hansson@arm.com 123011375Sandreas.hansson@arm.com tempBlockWriteback = (blk->isDirty() || writebackClean) ? 123111375Sandreas.hansson@arm.com writebackBlk(blk) : cleanEvictBlk(blk); 123211375Sandreas.hansson@arm.com invalidateBlock(blk); 123311375Sandreas.hansson@arm.com } 123411453Sandreas.hansson@arm.com 123511453Sandreas.hansson@arm.com if (pkt->needsResponse()) { 123611375Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 123711453Sandreas.hansson@arm.com } 123811375Sandreas.hansson@arm.com 123911375Sandreas.hansson@arm.com return lat * clockPeriod(); 124011375Sandreas.hansson@arm.com} 124111051Sandreas.hansson@arm.com 124211051Sandreas.hansson@arm.com 124311051Sandreas.hansson@arm.comvoid 124411051Sandreas.hansson@arm.comCache::functionalAccess(PacketPtr pkt, bool fromCpuSide) 124511051Sandreas.hansson@arm.com{ 124611051Sandreas.hansson@arm.com if (system->bypassCaches()) { 124711051Sandreas.hansson@arm.com // Packets from the memory side are snoop request and 124811051Sandreas.hansson@arm.com // shouldn't happen in bypass mode. 124911051Sandreas.hansson@arm.com assert(fromCpuSide); 125011051Sandreas.hansson@arm.com 125111051Sandreas.hansson@arm.com // The cache should be flushed if we are in cache bypass mode, 125211051Sandreas.hansson@arm.com // so we don't need to check if we need to update anything. 125311051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 125411051Sandreas.hansson@arm.com return; 125511051Sandreas.hansson@arm.com } 125611051Sandreas.hansson@arm.com 125711051Sandreas.hansson@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 125811051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 125911051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 126011051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 126111051Sandreas.hansson@arm.com 126211375Sandreas.hansson@arm.com pkt->pushLabel(name()); 126311375Sandreas.hansson@arm.com 126411375Sandreas.hansson@arm.com CacheBlkPrintWrapper cbpw(blk); 126511375Sandreas.hansson@arm.com 126611375Sandreas.hansson@arm.com // Note that just because an L2/L3 has valid data doesn't mean an 126711375Sandreas.hansson@arm.com // L1 doesn't have a more up-to-date modified copy that still 126811375Sandreas.hansson@arm.com // needs to be found. As a result we always update the request if 126911375Sandreas.hansson@arm.com // we have it, but only declare it satisfied if we are the owner. 127011375Sandreas.hansson@arm.com 127111375Sandreas.hansson@arm.com // see if we have data at all (owned or otherwise) 127211453Sandreas.hansson@arm.com bool have_data = blk && blk->isValid() 127311375Sandreas.hansson@arm.com && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize, 127411051Sandreas.hansson@arm.com blk->data); 127511051Sandreas.hansson@arm.com 127611051Sandreas.hansson@arm.com // data we have is dirty if marked as such or if we have an 127711051Sandreas.hansson@arm.com // in-service MSHR that is pending a modified line 127811051Sandreas.hansson@arm.com bool have_dirty = 127911051Sandreas.hansson@arm.com have_data && (blk->isDirty() || 128011051Sandreas.hansson@arm.com (mshr && mshr->inService && mshr->isPendingModified())); 128111051Sandreas.hansson@arm.com 128211051Sandreas.hansson@arm.com bool done = have_dirty 128311051Sandreas.hansson@arm.com || cpuSidePort->checkFunctional(pkt) 128411051Sandreas.hansson@arm.com || mshrQueue.checkFunctional(pkt, blk_addr) 128511051Sandreas.hansson@arm.com || writeBuffer.checkFunctional(pkt, blk_addr) 128611051Sandreas.hansson@arm.com || memSidePort->checkFunctional(pkt); 128711051Sandreas.hansson@arm.com 128811051Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s: %s %s%s%s\n", __func__, pkt->print(), 128911051Sandreas.hansson@arm.com (blk && blk->isValid()) ? "valid " : "", 129011051Sandreas.hansson@arm.com have_data ? "data " : "", done ? "done " : ""); 129111051Sandreas.hansson@arm.com 129211051Sandreas.hansson@arm.com // We're leaving the cache, so pop cache->name() label 129311051Sandreas.hansson@arm.com pkt->popLabel(); 129411051Sandreas.hansson@arm.com 129511051Sandreas.hansson@arm.com if (done) { 129611375Sandreas.hansson@arm.com pkt->makeResponse(); 129711375Sandreas.hansson@arm.com } else { 129811375Sandreas.hansson@arm.com // if it came as a request from the CPU side then make sure it 129911375Sandreas.hansson@arm.com // continues towards the memory side 130011375Sandreas.hansson@arm.com if (fromCpuSide) { 130111375Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 130211284Sandreas.hansson@arm.com } else if (cpuSidePort->isSnooping()) { 130311284Sandreas.hansson@arm.com // if it came from the memory side, it must be a snoop request 130411284Sandreas.hansson@arm.com // and we should only forward it if we are forwarding snoops 130511284Sandreas.hansson@arm.com cpuSidePort->sendFunctionalSnoop(pkt); 130611177Sandreas.hansson@arm.com } 130711177Sandreas.hansson@arm.com } 130811051Sandreas.hansson@arm.com} 130911051Sandreas.hansson@arm.com 131011051Sandreas.hansson@arm.com 131111177Sandreas.hansson@arm.com///////////////////////////////////////////////////// 131211177Sandreas.hansson@arm.com// 131311051Sandreas.hansson@arm.com// Response handling: responses from the memory side 131411051Sandreas.hansson@arm.com// 131511051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 131611051Sandreas.hansson@arm.com 131711197Sandreas.hansson@arm.com 131811051Sandreas.hansson@arm.comvoid 131911051Sandreas.hansson@arm.comCache::handleUncacheableWriteResp(PacketPtr pkt) 132011051Sandreas.hansson@arm.com{ 132111051Sandreas.hansson@arm.com Tick completion_time = clockEdge(responseLatency) + 132211051Sandreas.hansson@arm.com pkt->headerDelay + pkt->payloadDelay; 132311136Sandreas.hansson@arm.com 132411051Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 132511051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 132611051Sandreas.hansson@arm.com 132711051Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(pkt, completion_time, true); 132811051Sandreas.hansson@arm.com} 132911051Sandreas.hansson@arm.com 133011051Sandreas.hansson@arm.comvoid 133111051Sandreas.hansson@arm.comCache::recvTimingResp(PacketPtr pkt) 133211051Sandreas.hansson@arm.com{ 133311051Sandreas.hansson@arm.com assert(pkt->isResponse()); 133411051Sandreas.hansson@arm.com 133511051Sandreas.hansson@arm.com // all header delay should be paid for by the crossbar, unless 133611051Sandreas.hansson@arm.com // this is a prefetch response from above 133711051Sandreas.hansson@arm.com panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 133811051Sandreas.hansson@arm.com "%s saw a non-zero packet delay\n", name()); 133911051Sandreas.hansson@arm.com 134011051Sandreas.hansson@arm.com bool is_error = pkt->isError(); 134111483Snikos.nikoleris@arm.com 134211483Snikos.nikoleris@arm.com if (is_error) { 134311483Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Cache received %s with error\n", __func__, 134411483Snikos.nikoleris@arm.com pkt->print()); 134511051Sandreas.hansson@arm.com } 134611051Sandreas.hansson@arm.com 134711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s: Handling response %s\n", __func__, 134811051Sandreas.hansson@arm.com pkt->print()); 134911051Sandreas.hansson@arm.com 135011051Sandreas.hansson@arm.com // if this is a write, we should be looking at an uncacheable 135111051Sandreas.hansson@arm.com // write 135211051Sandreas.hansson@arm.com if (pkt->isWrite()) { 135311051Sandreas.hansson@arm.com assert(pkt->req->isUncacheable()); 135411051Sandreas.hansson@arm.com handleUncacheableWriteResp(pkt); 135511051Sandreas.hansson@arm.com return; 135611051Sandreas.hansson@arm.com } 135711051Sandreas.hansson@arm.com 135811284Sandreas.hansson@arm.com // we have dealt with any (uncacheable) writes above, from here on 135911284Sandreas.hansson@arm.com // we know we are dealing with an MSHR due to a miss or a prefetch 136011284Sandreas.hansson@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState()); 136111051Sandreas.hansson@arm.com assert(mshr); 136211197Sandreas.hansson@arm.com 136311051Sandreas.hansson@arm.com if (mshr == noTargetMSHR) { 136411051Sandreas.hansson@arm.com // we always clear at least one target 136511051Sandreas.hansson@arm.com clearBlocked(Blocked_NoTargets); 136611051Sandreas.hansson@arm.com noTargetMSHR = nullptr; 136711051Sandreas.hansson@arm.com } 136811136Sandreas.hansson@arm.com 136911051Sandreas.hansson@arm.com // Initial target is used just for stats 137011051Sandreas.hansson@arm.com MSHR::Target *initial_tgt = mshr->getTarget(); 137111051Sandreas.hansson@arm.com int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 137211051Sandreas.hansson@arm.com Tick miss_latency = curTick() - initial_tgt->recvTime; 137311051Sandreas.hansson@arm.com 137411051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 137511051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 137611051Sandreas.hansson@arm.com mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 137711051Sandreas.hansson@arm.com miss_latency; 137811051Sandreas.hansson@arm.com } else { 137911051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 138011051Sandreas.hansson@arm.com mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 138111051Sandreas.hansson@arm.com miss_latency; 138211051Sandreas.hansson@arm.com } 138311051Sandreas.hansson@arm.com 138411051Sandreas.hansson@arm.com bool wasFull = mshrQueue.isFull(); 138511051Sandreas.hansson@arm.com 138611051Sandreas.hansson@arm.com PacketList writebacks; 138711051Sandreas.hansson@arm.com 138811051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 138911051Sandreas.hansson@arm.com 139011051Sandreas.hansson@arm.com bool is_fill = !mshr->isForward && 139111051Sandreas.hansson@arm.com (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp); 139211051Sandreas.hansson@arm.com 139311051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 139411051Sandreas.hansson@arm.com const bool valid_blk = blk && blk->isValid(); 139511051Sandreas.hansson@arm.com // If the response indicates that there are no sharers and we 139611051Sandreas.hansson@arm.com // either had the block already or the response is filling we can 139711051Sandreas.hansson@arm.com // promote our copy to writable 139811051Sandreas.hansson@arm.com if (!pkt->hasSharers() && 139911051Sandreas.hansson@arm.com (is_fill || (valid_blk && !pkt->req->isCacheInvalidate()))) { 140011051Sandreas.hansson@arm.com mshr->promoteWritable(); 140111051Sandreas.hansson@arm.com } 140211051Sandreas.hansson@arm.com 140311051Sandreas.hansson@arm.com if (is_fill && !is_error) { 140411051Sandreas.hansson@arm.com DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 140511051Sandreas.hansson@arm.com pkt->getAddr()); 140611051Sandreas.hansson@arm.com 140711051Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill()); 140811051Sandreas.hansson@arm.com assert(blk != nullptr); 140911051Sandreas.hansson@arm.com } 141011051Sandreas.hansson@arm.com 141111051Sandreas.hansson@arm.com // allow invalidation responses originating from write-line 141211051Sandreas.hansson@arm.com // requests to be discarded 141311051Sandreas.hansson@arm.com bool is_invalidate = pkt->isInvalidate(); 141411051Sandreas.hansson@arm.com 141511051Sandreas.hansson@arm.com // The block was marked as not readable while there was a pending 141611051Sandreas.hansson@arm.com // cache maintenance operation, restore its flag. 141711051Sandreas.hansson@arm.com if (pkt->isClean() && !is_invalidate && valid_blk) { 141811051Sandreas.hansson@arm.com blk->status |= BlkReadable; 141911051Sandreas.hansson@arm.com } 142011051Sandreas.hansson@arm.com 142111051Sandreas.hansson@arm.com // First offset for critical word first calculations 142211051Sandreas.hansson@arm.com int initial_offset = initial_tgt->pkt->getOffset(blkSize); 142311051Sandreas.hansson@arm.com 142411136Sandreas.hansson@arm.com bool from_cache = false; 142511051Sandreas.hansson@arm.com MSHR::TargetList targets = mshr->extractServiceableTargets(pkt); 142611051Sandreas.hansson@arm.com for (auto &target: targets) { 142711051Sandreas.hansson@arm.com Packet *tgt_pkt = target.pkt; 142811051Sandreas.hansson@arm.com switch (target.source) { 142911051Sandreas.hansson@arm.com case MSHR::Target::FromCPU: 143011051Sandreas.hansson@arm.com Tick completion_time; 143111051Sandreas.hansson@arm.com // Here we charge on completion_time the delay of the xbar if the 143211051Sandreas.hansson@arm.com // packet comes from it, charged on headerDelay. 143311051Sandreas.hansson@arm.com completion_time = pkt->headerDelay; 143411194Sali.jafri@arm.com 143511051Sandreas.hansson@arm.com // Software prefetch handling for cache closest to core 143611051Sandreas.hansson@arm.com if (tgt_pkt->cmd.isSWPrefetch()) { 143711051Sandreas.hansson@arm.com // a software prefetch would have already been ack'd 143811051Sandreas.hansson@arm.com // immediately with dummy data so the core would be able to 143911051Sandreas.hansson@arm.com // retire it. This request completes right here, so we 144011051Sandreas.hansson@arm.com // deallocate it. 144111051Sandreas.hansson@arm.com delete tgt_pkt->req; 144211051Sandreas.hansson@arm.com delete tgt_pkt; 144311051Sandreas.hansson@arm.com break; // skip response 144411051Sandreas.hansson@arm.com } 144511051Sandreas.hansson@arm.com 144611051Sandreas.hansson@arm.com // keep track of whether we have responded to another 144711051Sandreas.hansson@arm.com // cache 144811051Sandreas.hansson@arm.com from_cache = from_cache || tgt_pkt->fromCache(); 144911051Sandreas.hansson@arm.com 145011136Sandreas.hansson@arm.com // unlike the other packet flows, where data is found in other 145111051Sandreas.hansson@arm.com // caches or memory and brought back, write-line requests always 145211051Sandreas.hansson@arm.com // have the data right away, so the above check for "is fill?" 145311051Sandreas.hansson@arm.com // cannot actually be determined until examining the stored MSHR 145411051Sandreas.hansson@arm.com // state. We "catch up" with that logic here, which is duplicated 145511051Sandreas.hansson@arm.com // from above. 145611051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::WriteLineReq) { 145711051Sandreas.hansson@arm.com assert(!is_error); 145811051Sandreas.hansson@arm.com // we got the block in a writable state, so promote 145911051Sandreas.hansson@arm.com // any deferred targets if possible 146011051Sandreas.hansson@arm.com mshr->promoteWritable(); 146111051Sandreas.hansson@arm.com // NB: we use the original packet here and not the response! 146211051Sandreas.hansson@arm.com blk = handleFill(tgt_pkt, blk, writebacks, 146311051Sandreas.hansson@arm.com targets.allocOnFill); 146411051Sandreas.hansson@arm.com assert(blk != nullptr); 146511136Sandreas.hansson@arm.com 146611197Sandreas.hansson@arm.com // treat as a fill, and discard the invalidation 146711051Sandreas.hansson@arm.com // response 146811051Sandreas.hansson@arm.com is_fill = true; 146911051Sandreas.hansson@arm.com is_invalidate = false; 147011051Sandreas.hansson@arm.com } 147111051Sandreas.hansson@arm.com 147211051Sandreas.hansson@arm.com if (is_fill) { 147311051Sandreas.hansson@arm.com satisfyRequest(tgt_pkt, blk, true, mshr->hasPostDowngrade()); 147411051Sandreas.hansson@arm.com 147511051Sandreas.hansson@arm.com // How many bytes past the first request is this one 147611051Sandreas.hansson@arm.com int transfer_offset = 147711051Sandreas.hansson@arm.com tgt_pkt->getOffset(blkSize) - initial_offset; 147811375Sandreas.hansson@arm.com if (transfer_offset < 0) { 147911051Sandreas.hansson@arm.com transfer_offset += blkSize; 148011051Sandreas.hansson@arm.com } 148111375Sandreas.hansson@arm.com 148211375Sandreas.hansson@arm.com // If not critical word (offset) return payloadDelay. 148311375Sandreas.hansson@arm.com // responseLatency is the latency of the return path 148411051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 148511051Sandreas.hansson@arm.com // the core. 148611051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 148711051Sandreas.hansson@arm.com (transfer_offset ? pkt->payloadDelay : 0); 148811375Sandreas.hansson@arm.com 148911051Sandreas.hansson@arm.com assert(!tgt_pkt->req->isUncacheable()); 149011051Sandreas.hansson@arm.com 149111051Sandreas.hansson@arm.com assert(tgt_pkt->req->masterId() < system->maxMasters()); 149211051Sandreas.hansson@arm.com missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] += 149311051Sandreas.hansson@arm.com completion_time - target.recvTime; 149411051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::UpgradeFailResp) { 149511051Sandreas.hansson@arm.com // failed StoreCond upgrade 149611051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::StoreCondReq || 149711051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::StoreCondFailReq || 149811051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::SCUpgradeFailReq); 149911051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 150011051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 150111051Sandreas.hansson@arm.com // the core. 150211051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 150311051Sandreas.hansson@arm.com pkt->payloadDelay; 150411051Sandreas.hansson@arm.com tgt_pkt->req->setExtraData(0); 150511051Sandreas.hansson@arm.com } else { 150611051Sandreas.hansson@arm.com // We are about to send a response to a cache above 150711199Sandreas.hansson@arm.com // that asked for an invalidation; we need to 150811051Sandreas.hansson@arm.com // invalidate our copy immediately as the most 150911051Sandreas.hansson@arm.com // up-to-date copy of the block will now be in the 151011051Sandreas.hansson@arm.com // cache above. It will also prevent this cache from 151111051Sandreas.hansson@arm.com // responding (if the block was previously dirty) to 151211051Sandreas.hansson@arm.com // snoops as they should snoop the caches above where 151311051Sandreas.hansson@arm.com // they will get the response from. 151411051Sandreas.hansson@arm.com if (is_invalidate && blk && blk->isValid()) { 151511051Sandreas.hansson@arm.com invalidateBlock(blk); 151611051Sandreas.hansson@arm.com } 151711051Sandreas.hansson@arm.com // not a cache fill, just forwarding response 151811051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 151911051Sandreas.hansson@arm.com // from lower level cahces/memory to the core. 152011051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 152111051Sandreas.hansson@arm.com pkt->payloadDelay; 152211051Sandreas.hansson@arm.com if (pkt->isRead() && !is_error) { 152311051Sandreas.hansson@arm.com // sanity check 152411051Sandreas.hansson@arm.com assert(pkt->getAddr() == tgt_pkt->getAddr()); 152511288Ssteve.reinhardt@amd.com assert(pkt->getSize() >= tgt_pkt->getSize()); 152611051Sandreas.hansson@arm.com 152711051Sandreas.hansson@arm.com tgt_pkt->setData(pkt->getConstPtr<uint8_t>()); 152811051Sandreas.hansson@arm.com } 152911051Sandreas.hansson@arm.com } 153011051Sandreas.hansson@arm.com tgt_pkt->makeTimingResponse(); 153111051Sandreas.hansson@arm.com // if this packet is an error copy that to the new packet 153211051Sandreas.hansson@arm.com if (is_error) 153311199Sandreas.hansson@arm.com tgt_pkt->copyError(pkt); 153411199Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::ReadResp && 153511199Sandreas.hansson@arm.com (is_invalidate || mshr->hasPostInvalidate())) { 153611051Sandreas.hansson@arm.com // If intermediate cache got ReadRespWithInvalidate, 153711051Sandreas.hansson@arm.com // propagate that. Response should not have 153811051Sandreas.hansson@arm.com // isInvalidate() set otherwise. 153911199Sandreas.hansson@arm.com tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate; 154011199Sandreas.hansson@arm.com DPRINTF(Cache, "%s: updated cmd to %s\n", __func__, 154111051Sandreas.hansson@arm.com tgt_pkt->print()); 154211199Sandreas.hansson@arm.com } 154311051Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 154411199Sandreas.hansson@arm.com tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; 154511051Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true); 154611051Sandreas.hansson@arm.com break; 154711051Sandreas.hansson@arm.com 154811199Sandreas.hansson@arm.com case MSHR::Target::FromPrefetcher: 154911199Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::HardPFReq); 155011199Sandreas.hansson@arm.com if (blk) 155111199Sandreas.hansson@arm.com blk->status |= BlkHWPrefetched; 155211199Sandreas.hansson@arm.com delete tgt_pkt->req; 155311199Sandreas.hansson@arm.com delete tgt_pkt; 155411199Sandreas.hansson@arm.com break; 155511051Sandreas.hansson@arm.com 155611051Sandreas.hansson@arm.com case MSHR::Target::FromSnoop: 155711051Sandreas.hansson@arm.com // I don't believe that a snoop can be in an error state 155811051Sandreas.hansson@arm.com assert(!is_error); 155911051Sandreas.hansson@arm.com // response to snoop request 156011284Sandreas.hansson@arm.com DPRINTF(Cache, "processing deferred snoop...\n"); 156111284Sandreas.hansson@arm.com // If the response is invalidating, a snooping target can 156211051Sandreas.hansson@arm.com // be satisfied if it is also invalidating. If the reponse is, not 156311051Sandreas.hansson@arm.com // only invalidating, but more specifically an InvalidateResp and 156411199Sandreas.hansson@arm.com // the MSHR was created due to an InvalidateReq then a cache above 156511199Sandreas.hansson@arm.com // is waiting to satisfy a WriteLineReq. In this case even an 156611051Sandreas.hansson@arm.com // non-invalidating snoop is added as a target here since this is 156711199Sandreas.hansson@arm.com // the ordering point. When the InvalidateResp reaches this cache, 156811199Sandreas.hansson@arm.com // the snooping target will snoop further the cache above with the 156911199Sandreas.hansson@arm.com // WriteLineReq. 157011199Sandreas.hansson@arm.com assert(!is_invalidate || pkt->cmd == MemCmd::InvalidateResp || 157111051Sandreas.hansson@arm.com pkt->req->isCacheMaintenance() || 157211051Sandreas.hansson@arm.com mshr->hasPostInvalidate()); 157311051Sandreas.hansson@arm.com handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate()); 157411051Sandreas.hansson@arm.com break; 157511051Sandreas.hansson@arm.com 157611199Sandreas.hansson@arm.com default: 157711051Sandreas.hansson@arm.com panic("Illegal target->source enum %d\n", target.source); 157811051Sandreas.hansson@arm.com } 157911051Sandreas.hansson@arm.com } 158011051Sandreas.hansson@arm.com 158111051Sandreas.hansson@arm.com maintainClusivity(from_cache, blk); 158211051Sandreas.hansson@arm.com 158311051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 158411051Sandreas.hansson@arm.com // an invalidate response stemming from a write line request 158511051Sandreas.hansson@arm.com // should not invalidate the block, so check if the 158611051Sandreas.hansson@arm.com // invalidation should be discarded 158711051Sandreas.hansson@arm.com if (is_invalidate || mshr->hasPostInvalidate()) { 158811051Sandreas.hansson@arm.com invalidateBlock(blk); 158911051Sandreas.hansson@arm.com } else if (mshr->hasPostDowngrade()) { 159011051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 159111051Sandreas.hansson@arm.com } 159211051Sandreas.hansson@arm.com } 159311051Sandreas.hansson@arm.com 159411051Sandreas.hansson@arm.com if (mshr->promoteDeferredTargets()) { 159511051Sandreas.hansson@arm.com // avoid later read getting stale data while write miss is 159611051Sandreas.hansson@arm.com // outstanding.. see comment in timingAccess() 159711051Sandreas.hansson@arm.com if (blk) { 159811051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 159911051Sandreas.hansson@arm.com } 160011051Sandreas.hansson@arm.com mshrQueue.markPending(mshr); 160111051Sandreas.hansson@arm.com schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 160211051Sandreas.hansson@arm.com } else { 160311051Sandreas.hansson@arm.com mshrQueue.deallocate(mshr); 160411051Sandreas.hansson@arm.com if (wasFull && !mshrQueue.isFull()) { 160511051Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 160611051Sandreas.hansson@arm.com } 160711051Sandreas.hansson@arm.com 160811051Sandreas.hansson@arm.com // Request the bus for a prefetch if this deallocation freed enough 160911051Sandreas.hansson@arm.com // MSHRs for a prefetch to take place 161011051Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 161111051Sandreas.hansson@arm.com Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 161211051Sandreas.hansson@arm.com clockEdge()); 161311051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 161411051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 161511051Sandreas.hansson@arm.com } 161611051Sandreas.hansson@arm.com } 161711051Sandreas.hansson@arm.com // reset the xbar additional timinig as it is now accounted for 161811051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 161911051Sandreas.hansson@arm.com 162011051Sandreas.hansson@arm.com // copy writebacks to write buffer 162111051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 162211051Sandreas.hansson@arm.com 162311051Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and then clear it out 162411051Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 162511051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying 162611051Sandreas.hansson@arm.com // Writebacks/CleanEvicts to write buffer. It specifies the latency to 162711051Sandreas.hansson@arm.com // allocate an internal buffer and to schedule an event to the 162811051Sandreas.hansson@arm.com // queued port. 162911051Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 163011051Sandreas.hansson@arm.com PacketPtr wbPkt = writebackBlk(blk); 163111051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 163211051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag if cached above. 163311051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) 163411051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 163511051Sandreas.hansson@arm.com } else { 163611051Sandreas.hansson@arm.com PacketPtr wcPkt = cleanEvictBlk(blk); 163711051Sandreas.hansson@arm.com // Check to see if block is cached above. If not allocate 163811051Sandreas.hansson@arm.com // write buffer 163911051Sandreas.hansson@arm.com if (isCachedAbove(wcPkt)) 164011051Sandreas.hansson@arm.com delete wcPkt; 164111051Sandreas.hansson@arm.com else 164211051Sandreas.hansson@arm.com allocateWriteBuffer(wcPkt, forward_time); 164311051Sandreas.hansson@arm.com } 164411051Sandreas.hansson@arm.com invalidateBlock(blk); 164511051Sandreas.hansson@arm.com } 164611051Sandreas.hansson@arm.com 164711051Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print()); 164811051Sandreas.hansson@arm.com delete pkt; 164911051Sandreas.hansson@arm.com} 165011051Sandreas.hansson@arm.com 165111051Sandreas.hansson@arm.comPacketPtr 165211051Sandreas.hansson@arm.comCache::writebackBlk(CacheBlk *blk) 165311051Sandreas.hansson@arm.com{ 165411051Sandreas.hansson@arm.com chatty_assert(!isReadOnly || writebackClean, 165511051Sandreas.hansson@arm.com "Writeback from read-only cache"); 165611051Sandreas.hansson@arm.com assert(blk && blk->isValid() && (blk->isDirty() || writebackClean)); 165711051Sandreas.hansson@arm.com 165811051Sandreas.hansson@arm.com writebacks[Request::wbMasterId]++; 165911051Sandreas.hansson@arm.com 166011051Sandreas.hansson@arm.com Request *req = new Request(tags->regenerateBlkAddr(blk), blkSize, 0, 166111051Sandreas.hansson@arm.com Request::wbMasterId); 166211051Sandreas.hansson@arm.com if (blk->isSecure()) 166311051Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 166411051Sandreas.hansson@arm.com 166511051Sandreas.hansson@arm.com req->taskId(blk->task_id); 166611051Sandreas.hansson@arm.com 166711051Sandreas.hansson@arm.com PacketPtr pkt = 166811051Sandreas.hansson@arm.com new Packet(req, blk->isDirty() ? 166911051Sandreas.hansson@arm.com MemCmd::WritebackDirty : MemCmd::WritebackClean); 167011051Sandreas.hansson@arm.com 167111051Sandreas.hansson@arm.com DPRINTF(Cache, "Create Writeback %s writable: %d, dirty: %d\n", 167211051Sandreas.hansson@arm.com pkt->print(), blk->isWritable(), blk->isDirty()); 167311051Sandreas.hansson@arm.com 167411284Sandreas.hansson@arm.com if (blk->isWritable()) { 167511051Sandreas.hansson@arm.com // not asserting shared means we pass the block in modified 167611051Sandreas.hansson@arm.com // state, mark our own block non-writeable 167711051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 167811051Sandreas.hansson@arm.com } else { 167911483Snikos.nikoleris@arm.com // we are in the Owned state, tell the receiver 168011483Snikos.nikoleris@arm.com pkt->setHasSharers(); 168111051Sandreas.hansson@arm.com } 168211051Sandreas.hansson@arm.com 168311051Sandreas.hansson@arm.com // make sure the block is not marked dirty 168411436SRekai.GonzalezAlberquilla@arm.com blk->status &= ~BlkDirty; 168511436SRekai.GonzalezAlberquilla@arm.com 168611436SRekai.GonzalezAlberquilla@arm.com pkt->allocate(); 168711051Sandreas.hansson@arm.com std::memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize); 168811051Sandreas.hansson@arm.com 168911199Sandreas.hansson@arm.com return pkt; 169011051Sandreas.hansson@arm.com} 169111051Sandreas.hansson@arm.com 169211051Sandreas.hansson@arm.comPacketPtr 169311051Sandreas.hansson@arm.comCache::writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id) 169411051Sandreas.hansson@arm.com{ 169511051Sandreas.hansson@arm.com Request *req = new Request(tags->regenerateBlkAddr(blk), blkSize, 0, 169611051Sandreas.hansson@arm.com Request::wbMasterId); 169711051Sandreas.hansson@arm.com if (blk->isSecure()) { 169811051Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 169911051Sandreas.hansson@arm.com } 170011051Sandreas.hansson@arm.com req->taskId(blk->task_id); 170111197Sandreas.hansson@arm.com 170211197Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::WriteClean, blkSize, id); 170311197Sandreas.hansson@arm.com 170411197Sandreas.hansson@arm.com if (dest) { 170511197Sandreas.hansson@arm.com req->setFlags(dest); 170611197Sandreas.hansson@arm.com pkt->setWriteThrough(); 170711197Sandreas.hansson@arm.com } 170811051Sandreas.hansson@arm.com 170911051Sandreas.hansson@arm.com DPRINTF(Cache, "Create %s writable: %d, dirty: %d\n", pkt->print(), 171011051Sandreas.hansson@arm.com blk->isWritable(), blk->isDirty()); 171111051Sandreas.hansson@arm.com 171211051Sandreas.hansson@arm.com if (blk->isWritable()) { 171311051Sandreas.hansson@arm.com // not asserting shared means we pass the block in modified 171411051Sandreas.hansson@arm.com // state, mark our own block non-writeable 171511197Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 171611197Sandreas.hansson@arm.com } else { 171711051Sandreas.hansson@arm.com // we are in the Owned state, tell the receiver 171811051Sandreas.hansson@arm.com pkt->setHasSharers(); 171911051Sandreas.hansson@arm.com } 172011051Sandreas.hansson@arm.com 172111051Sandreas.hansson@arm.com // make sure the block is not marked dirty 172211051Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 172311051Sandreas.hansson@arm.com 172411051Sandreas.hansson@arm.com pkt->allocate(); 172511375Sandreas.hansson@arm.com std::memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize); 172611375Sandreas.hansson@arm.com 172711375Sandreas.hansson@arm.com return pkt; 172811051Sandreas.hansson@arm.com} 172911051Sandreas.hansson@arm.com 173011051Sandreas.hansson@arm.com 173111051Sandreas.hansson@arm.comPacketPtr 173211051Sandreas.hansson@arm.comCache::cleanEvictBlk(CacheBlk *blk) 173311051Sandreas.hansson@arm.com{ 173411051Sandreas.hansson@arm.com assert(!writebackClean); 173511051Sandreas.hansson@arm.com assert(blk && blk->isValid() && !blk->isDirty()); 173611051Sandreas.hansson@arm.com // Creating a zero sized write, a message to the snoop filter 173711051Sandreas.hansson@arm.com Request *req = 173811197Sandreas.hansson@arm.com new Request(tags->regenerateBlkAddr(blk), blkSize, 0, 173911197Sandreas.hansson@arm.com Request::wbMasterId); 174011197Sandreas.hansson@arm.com if (blk->isSecure()) 174111197Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 174211051Sandreas.hansson@arm.com 174311197Sandreas.hansson@arm.com req->taskId(blk->task_id); 174411197Sandreas.hansson@arm.com 174511197Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::CleanEvict); 174611051Sandreas.hansson@arm.com pkt->allocate(); 174711051Sandreas.hansson@arm.com DPRINTF(Cache, "Create CleanEvict %s\n", pkt->print()); 174811051Sandreas.hansson@arm.com 174911051Sandreas.hansson@arm.com return pkt; 175011051Sandreas.hansson@arm.com} 175111051Sandreas.hansson@arm.com 175211051Sandreas.hansson@arm.comvoid 175311051Sandreas.hansson@arm.comCache::memWriteback() 175411051Sandreas.hansson@arm.com{ 175511051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::writebackVisitor); 175611051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 175711051Sandreas.hansson@arm.com} 175811051Sandreas.hansson@arm.com 175911051Sandreas.hansson@arm.comvoid 176011051Sandreas.hansson@arm.comCache::memInvalidate() 176111051Sandreas.hansson@arm.com{ 176211051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::invalidateVisitor); 176311051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 176411051Sandreas.hansson@arm.com} 176511051Sandreas.hansson@arm.com 176611051Sandreas.hansson@arm.combool 176711051Sandreas.hansson@arm.comCache::isDirty() const 176811051Sandreas.hansson@arm.com{ 176911051Sandreas.hansson@arm.com CacheBlkIsDirtyVisitor visitor; 177011051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 177111051Sandreas.hansson@arm.com 177211137Sandreas.hansson@arm.com return visitor.isDirty(); 177311137Sandreas.hansson@arm.com} 177411137Sandreas.hansson@arm.com 177511137Sandreas.hansson@arm.combool 177611284Sandreas.hansson@arm.comCache::writebackVisitor(CacheBlk &blk) 177711137Sandreas.hansson@arm.com{ 177811137Sandreas.hansson@arm.com if (blk.isDirty()) { 177911284Sandreas.hansson@arm.com assert(blk.isValid()); 178011137Sandreas.hansson@arm.com 178111137Sandreas.hansson@arm.com Request request(tags->regenerateBlkAddr(&blk), blkSize, 0, 178211284Sandreas.hansson@arm.com Request::funcMasterId); 178311284Sandreas.hansson@arm.com request.taskId(blk.task_id); 178411284Sandreas.hansson@arm.com if (blk.isSecure()) { 178511284Sandreas.hansson@arm.com request.setFlags(Request::SECURE); 178611284Sandreas.hansson@arm.com } 178711284Sandreas.hansson@arm.com 178811284Sandreas.hansson@arm.com Packet packet(&request, MemCmd::WriteReq); 178911284Sandreas.hansson@arm.com packet.dataStatic(blk.data); 179011284Sandreas.hansson@arm.com 179111284Sandreas.hansson@arm.com memSidePort->sendFunctional(&packet); 179211284Sandreas.hansson@arm.com 179311051Sandreas.hansson@arm.com blk.status &= ~BlkDirty; 179411051Sandreas.hansson@arm.com } 179511284Sandreas.hansson@arm.com 179611284Sandreas.hansson@arm.com return true; 179711284Sandreas.hansson@arm.com} 179811284Sandreas.hansson@arm.com 179911284Sandreas.hansson@arm.combool 180011051Sandreas.hansson@arm.comCache::invalidateVisitor(CacheBlk &blk) 180111051Sandreas.hansson@arm.com{ 180211051Sandreas.hansson@arm.com 180311051Sandreas.hansson@arm.com if (blk.isDirty()) 180411051Sandreas.hansson@arm.com warn_once("Invalidating dirty cache lines. Expect things to break.\n"); 180511051Sandreas.hansson@arm.com 180611051Sandreas.hansson@arm.com if (blk.isValid()) { 180711051Sandreas.hansson@arm.com assert(!blk.isDirty()); 180811051Sandreas.hansson@arm.com invalidateBlock(&blk); 180911051Sandreas.hansson@arm.com } 181011051Sandreas.hansson@arm.com 181111051Sandreas.hansson@arm.com return true; 181211051Sandreas.hansson@arm.com} 181311051Sandreas.hansson@arm.com 181411051Sandreas.hansson@arm.comCacheBlk* 181511051Sandreas.hansson@arm.comCache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks) 181611051Sandreas.hansson@arm.com{ 181711051Sandreas.hansson@arm.com // Find replacement victim 181811051Sandreas.hansson@arm.com CacheBlk *blk = tags->findVictim(addr); 181911051Sandreas.hansson@arm.com 182011051Sandreas.hansson@arm.com // It is valid to return nullptr if there is no victim 182111051Sandreas.hansson@arm.com if (!blk) 182211051Sandreas.hansson@arm.com return nullptr; 182311051Sandreas.hansson@arm.com 182411051Sandreas.hansson@arm.com if (blk->isValid()) { 182511051Sandreas.hansson@arm.com Addr repl_addr = tags->regenerateBlkAddr(blk); 182611051Sandreas.hansson@arm.com MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure()); 182711051Sandreas.hansson@arm.com if (repl_mshr) { 182811051Sandreas.hansson@arm.com // must be an outstanding upgrade or clean request 182911051Sandreas.hansson@arm.com // on a block we're about to replace... 183011051Sandreas.hansson@arm.com assert((!blk->isWritable() && repl_mshr->needsWritable()) || 183111051Sandreas.hansson@arm.com repl_mshr->isCleaning()); 183211051Sandreas.hansson@arm.com // too hard to replace block with transient state 183311051Sandreas.hansson@arm.com // allocation failed, block not inserted 183411051Sandreas.hansson@arm.com return nullptr; 183511051Sandreas.hansson@arm.com } else { 183611051Sandreas.hansson@arm.com DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx " 183711051Sandreas.hansson@arm.com "(%s): %s\n", repl_addr, blk->isSecure() ? "s" : "ns", 183811051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", 183911051Sandreas.hansson@arm.com blk->isDirty() ? "writeback" : "clean"); 184011051Sandreas.hansson@arm.com 184111051Sandreas.hansson@arm.com if (blk->wasPrefetched()) { 184211051Sandreas.hansson@arm.com unusedPrefetches++; 184311051Sandreas.hansson@arm.com } 184411051Sandreas.hansson@arm.com // Will send up Writeback/CleanEvict snoops via isCachedAbove 184511051Sandreas.hansson@arm.com // when pushing this writeback list into the write buffer. 184611051Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 184711051Sandreas.hansson@arm.com // Save writeback packet for handling by caller 184811051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(blk)); 184911051Sandreas.hansson@arm.com } else { 185011051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(blk)); 185111051Sandreas.hansson@arm.com } 185211051Sandreas.hansson@arm.com } 185311284Sandreas.hansson@arm.com } 185411051Sandreas.hansson@arm.com 185511051Sandreas.hansson@arm.com return blk; 185611051Sandreas.hansson@arm.com} 185711051Sandreas.hansson@arm.com 185811051Sandreas.hansson@arm.comvoid 185911051Sandreas.hansson@arm.comCache::invalidateBlock(CacheBlk *blk) 186011051Sandreas.hansson@arm.com{ 186111284Sandreas.hansson@arm.com if (blk != tempBlock) 186211284Sandreas.hansson@arm.com tags->invalidate(blk); 186311284Sandreas.hansson@arm.com blk->invalidate(); 186411284Sandreas.hansson@arm.com} 186511284Sandreas.hansson@arm.com 186611051Sandreas.hansson@arm.com// Note that the reason we return a list of writebacks rather than 186711051Sandreas.hansson@arm.com// inserting them directly in the write buffer is that this function 186811051Sandreas.hansson@arm.com// is called by both atomic and timing-mode accesses, and in atomic 186911051Sandreas.hansson@arm.com// mode we don't mess with the write buffer (we just perform the 187011051Sandreas.hansson@arm.com// writebacks atomically once the original request is complete). 187111051Sandreas.hansson@arm.comCacheBlk* 187211051Sandreas.hansson@arm.comCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, 187311051Sandreas.hansson@arm.com bool allocate) 187411288Ssteve.reinhardt@amd.com{ 187511288Ssteve.reinhardt@amd.com assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq); 187611051Sandreas.hansson@arm.com Addr addr = pkt->getAddr(); 187711051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 187811051Sandreas.hansson@arm.com#if TRACING_ON 187911051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 188011051Sandreas.hansson@arm.com#endif 188111127Sandreas.hansson@arm.com 188211051Sandreas.hansson@arm.com // When handling a fill, we should have no writes to this line. 188311051Sandreas.hansson@arm.com assert(addr == pkt->getBlockAddr(blkSize)); 188411051Sandreas.hansson@arm.com assert(!writeBuffer.findMatch(addr, is_secure)); 188511288Ssteve.reinhardt@amd.com 188611051Sandreas.hansson@arm.com if (blk == nullptr) { 188711051Sandreas.hansson@arm.com // better have read new data... 188811051Sandreas.hansson@arm.com assert(pkt->hasData()); 188911051Sandreas.hansson@arm.com 189011051Sandreas.hansson@arm.com // only read responses and write-line requests have data; 189111051Sandreas.hansson@arm.com // note that we don't write the data here for write-line - that 189211051Sandreas.hansson@arm.com // happens in the subsequent call to satisfyRequest 189311051Sandreas.hansson@arm.com assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq); 189411051Sandreas.hansson@arm.com 189511051Sandreas.hansson@arm.com // need to do a replacement if allocating, otherwise we stick 189611051Sandreas.hansson@arm.com // with the temporary storage 189711284Sandreas.hansson@arm.com blk = allocate ? allocateBlock(addr, is_secure, writebacks) : nullptr; 189811051Sandreas.hansson@arm.com 189911285Sandreas.hansson@arm.com if (blk == nullptr) { 190011285Sandreas.hansson@arm.com // No replaceable block or a mostly exclusive 190111285Sandreas.hansson@arm.com // cache... just use temporary storage to complete the 190211285Sandreas.hansson@arm.com // current request and then get rid of it 190311285Sandreas.hansson@arm.com assert(!tempBlock->isValid()); 190411285Sandreas.hansson@arm.com blk = tempBlock; 190511285Sandreas.hansson@arm.com tempBlock->set = tags->extractSet(addr); 190611127Sandreas.hansson@arm.com tempBlock->tag = tags->extractTag(addr); 190711127Sandreas.hansson@arm.com if (is_secure) { 190811051Sandreas.hansson@arm.com tempBlock->status |= BlkSecure; 190911051Sandreas.hansson@arm.com } 191011051Sandreas.hansson@arm.com DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr, 191111051Sandreas.hansson@arm.com is_secure ? "s" : "ns"); 191211284Sandreas.hansson@arm.com } else { 191311051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 191411051Sandreas.hansson@arm.com } 191511051Sandreas.hansson@arm.com 191611051Sandreas.hansson@arm.com // we should never be overwriting a valid block 191711051Sandreas.hansson@arm.com assert(!blk->isValid()); 191811051Sandreas.hansson@arm.com } else { 191911051Sandreas.hansson@arm.com // existing block... probably an upgrade 192011051Sandreas.hansson@arm.com assert(blk->tag == tags->extractTag(addr)); 192111051Sandreas.hansson@arm.com // either we're getting new data or the block should already be valid 192211051Sandreas.hansson@arm.com assert(pkt->hasData() || blk->isValid()); 192311051Sandreas.hansson@arm.com // don't clear block status... if block is already dirty we 192411127Sandreas.hansson@arm.com // don't want to lose that 192511127Sandreas.hansson@arm.com } 192611127Sandreas.hansson@arm.com 192711127Sandreas.hansson@arm.com if (is_secure) 192811127Sandreas.hansson@arm.com blk->status |= BlkSecure; 192911127Sandreas.hansson@arm.com blk->status |= BlkValid | BlkReadable; 193011284Sandreas.hansson@arm.com 193111051Sandreas.hansson@arm.com // sanity check for whole-line writes, which should always be 193211051Sandreas.hansson@arm.com // marked as writable as part of the fill, and then later marked 193311284Sandreas.hansson@arm.com // dirty as part of satisfyRequest 193411051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WriteLineReq) { 193511284Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 193611284Sandreas.hansson@arm.com } 193711284Sandreas.hansson@arm.com 193811284Sandreas.hansson@arm.com // here we deal with setting the appropriate state of the line, 193911051Sandreas.hansson@arm.com // and we start by looking at the hasSharers flag, and ignore the 194011051Sandreas.hansson@arm.com // cacheResponding flag (normally signalling dirty data) if the 194111051Sandreas.hansson@arm.com // packet has sharers, thus the line is never allocated as Owned 194211051Sandreas.hansson@arm.com // (dirty but not writable), and always ends up being either 194311051Sandreas.hansson@arm.com // Shared, Exclusive or Modified, see Packet::setCacheResponding 194411051Sandreas.hansson@arm.com // for more details 194511051Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 194611051Sandreas.hansson@arm.com // we could get a writable line from memory (rather than a 194711051Sandreas.hansson@arm.com // cache) even in a read-only cache, note that we set this bit 194811284Sandreas.hansson@arm.com // even for a read-only cache, possibly revisit this decision 194911051Sandreas.hansson@arm.com blk->status |= BlkWritable; 195011051Sandreas.hansson@arm.com 195111051Sandreas.hansson@arm.com // check if we got this via cache-to-cache transfer (i.e., from a 195211051Sandreas.hansson@arm.com // cache that had the block in Modified or Owned state) 195311051Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 195411051Sandreas.hansson@arm.com // we got the block in Modified state, and invalidated the 195511051Sandreas.hansson@arm.com // owners copy 195611051Sandreas.hansson@arm.com blk->status |= BlkDirty; 195711288Ssteve.reinhardt@amd.com 195811051Sandreas.hansson@arm.com chatty_assert(!isReadOnly, "Should never see dirty snoop response " 195911127Sandreas.hansson@arm.com "in read-only cache %s\n", name()); 196011051Sandreas.hansson@arm.com } 196111288Ssteve.reinhardt@amd.com } 196211288Ssteve.reinhardt@amd.com 196311288Ssteve.reinhardt@amd.com DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n", 196411051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", old_state, blk->print()); 196511051Sandreas.hansson@arm.com 196611051Sandreas.hansson@arm.com // if we got new data, copy it in (checking for a read response 196711051Sandreas.hansson@arm.com // and a response that has data is the same in the end) 196811051Sandreas.hansson@arm.com if (pkt->isRead()) { 196911051Sandreas.hansson@arm.com // sanity checks 197011051Sandreas.hansson@arm.com assert(pkt->hasData()); 197111051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 197211051Sandreas.hansson@arm.com 197311051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 197411051Sandreas.hansson@arm.com } 197511051Sandreas.hansson@arm.com // We pay for fillLatency here. 197611051Sandreas.hansson@arm.com blk->whenReady = clockEdge() + fillLatency * clockPeriod() + 197711284Sandreas.hansson@arm.com pkt->payloadDelay; 197811051Sandreas.hansson@arm.com 197911051Sandreas.hansson@arm.com return blk; 198011051Sandreas.hansson@arm.com} 198111051Sandreas.hansson@arm.com 198211051Sandreas.hansson@arm.com 198311051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 198411483Snikos.nikoleris@arm.com// 198511483Snikos.nikoleris@arm.com// Snoop path: requests coming in from the memory side 198611051Sandreas.hansson@arm.com// 198711127Sandreas.hansson@arm.com///////////////////////////////////////////////////// 198811051Sandreas.hansson@arm.com 198911051Sandreas.hansson@arm.comvoid 199011285Sandreas.hansson@arm.comCache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 199111285Sandreas.hansson@arm.com bool already_copied, bool pending_inval) 199211284Sandreas.hansson@arm.com{ 199311284Sandreas.hansson@arm.com // sanity check 199411285Sandreas.hansson@arm.com assert(req_pkt->isRequest()); 199511285Sandreas.hansson@arm.com assert(req_pkt->needsResponse()); 199611285Sandreas.hansson@arm.com 199711285Sandreas.hansson@arm.com DPRINTF(Cache, "%s: for %s\n", __func__, req_pkt->print()); 199811285Sandreas.hansson@arm.com // timing-mode snoop responses require a new packet, unless we 199911285Sandreas.hansson@arm.com // already made a copy... 200011285Sandreas.hansson@arm.com PacketPtr pkt = req_pkt; 200111285Sandreas.hansson@arm.com if (!already_copied) 200211051Sandreas.hansson@arm.com // do not clear flags, and allocate space for data if the 200311051Sandreas.hansson@arm.com // packet needs it (the only packets that carry data are read 200411051Sandreas.hansson@arm.com // responses) 200511051Sandreas.hansson@arm.com pkt = new Packet(req_pkt, false, req_pkt->isRead()); 200611051Sandreas.hansson@arm.com 200711284Sandreas.hansson@arm.com assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() || 200811284Sandreas.hansson@arm.com pkt->hasSharers()); 200911284Sandreas.hansson@arm.com pkt->makeTimingResponse(); 201011284Sandreas.hansson@arm.com if (pkt->isRead()) { 201111284Sandreas.hansson@arm.com pkt->setDataFromBlock(blk_data, blkSize); 201211284Sandreas.hansson@arm.com } 201311284Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadResp && pending_inval) { 201411284Sandreas.hansson@arm.com // Assume we defer a response to a read from a far-away cache 201511081Sandreas.hansson@arm.com // A, then later defer a ReadExcl from a cache B on the same 201611284Sandreas.hansson@arm.com // bus as us. We'll assert cacheResponding in both cases, but 201711284Sandreas.hansson@arm.com // in the latter case cacheResponding will keep the 201811284Sandreas.hansson@arm.com // invalidation from reaching cache A. This special response 201911284Sandreas.hansson@arm.com // tells cache A that it gets the block to satisfy its read, 202011284Sandreas.hansson@arm.com // but must immediately invalidate it. 202111284Sandreas.hansson@arm.com pkt->cmd = MemCmd::ReadRespWithInvalidate; 202211284Sandreas.hansson@arm.com } 202311051Sandreas.hansson@arm.com // Here we consider forward_time, paying for just forward latency and 202411284Sandreas.hansson@arm.com // also charging the delay provided by the xbar. 202511285Sandreas.hansson@arm.com // forward_time is used as send_time in next allocateWriteBuffer(). 202611285Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 202711285Sandreas.hansson@arm.com // Here we reset the timing of the packet. 202811285Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 202911285Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s: created response: %s tick: %lu\n", __func__, 203011285Sandreas.hansson@arm.com pkt->print(), forward_time); 203111285Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, forward_time, true); 203211051Sandreas.hansson@arm.com} 203311051Sandreas.hansson@arm.com 203411051Sandreas.hansson@arm.comuint32_t 203511051Sandreas.hansson@arm.comCache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, 203611286Sandreas.hansson@arm.com bool is_deferred, bool pending_inval) 203711286Sandreas.hansson@arm.com{ 203811286Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 203911286Sandreas.hansson@arm.com // deferred snoops can only happen in timing mode 204011051Sandreas.hansson@arm.com assert(!(is_deferred && !is_timing)); 204111051Sandreas.hansson@arm.com // pending_inval only makes sense on deferred snoops 204211051Sandreas.hansson@arm.com assert(!(pending_inval && !is_deferred)); 204311051Sandreas.hansson@arm.com assert(pkt->isRequest()); 204411271Sandreas.hansson@arm.com 204511271Sandreas.hansson@arm.com // the packet may get modified if we or a forwarded snooper 204611271Sandreas.hansson@arm.com // responds in atomic mode, so remember a few things about the 204711051Sandreas.hansson@arm.com // original packet up front 204811051Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 204911051Sandreas.hansson@arm.com bool M5_VAR_USED needs_writable = pkt->needsWritable(); 205011051Sandreas.hansson@arm.com 205111051Sandreas.hansson@arm.com // at the moment we could get an uncacheable write which does not 205211051Sandreas.hansson@arm.com // have the invalidate flag, and we need a suitable way of dealing 205311051Sandreas.hansson@arm.com // with this case 205411051Sandreas.hansson@arm.com panic_if(invalidate && pkt->req->isUncacheable(), 205511197Sandreas.hansson@arm.com "%s got an invalidating uncacheable snoop request %s", 205611051Sandreas.hansson@arm.com name(), pkt->print()); 205711051Sandreas.hansson@arm.com 205811051Sandreas.hansson@arm.com uint32_t snoop_delay = 0; 205911127Sandreas.hansson@arm.com 206011127Sandreas.hansson@arm.com if (forwardSnoops) { 206111051Sandreas.hansson@arm.com // first propagate snoop upward to see if anyone above us wants to 206211051Sandreas.hansson@arm.com // handle it. save & restore packet src since it will get 206311051Sandreas.hansson@arm.com // rewritten to be relative to cpu-side bus (if any) 206411051Sandreas.hansson@arm.com bool alreadyResponded = pkt->cacheResponding(); 206511051Sandreas.hansson@arm.com if (is_timing) { 206611051Sandreas.hansson@arm.com // copy the packet so that we can clear any flags before 206711288Ssteve.reinhardt@amd.com // forwarding it upwards, we also allocate data (passing 206811051Sandreas.hansson@arm.com // the pointer along in case of static data), in case 206911051Sandreas.hansson@arm.com // there is a snoop hit in upper levels 207011051Sandreas.hansson@arm.com Packet snoopPkt(pkt, true, true); 207111051Sandreas.hansson@arm.com snoopPkt.setExpressSnoop(); 207211051Sandreas.hansson@arm.com // the snoop packet does not need to wait any additional 207311130Sali.jafri@arm.com // time 207411051Sandreas.hansson@arm.com snoopPkt.headerDelay = snoopPkt.payloadDelay = 0; 207511051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoopPkt); 207611051Sandreas.hansson@arm.com 207711051Sandreas.hansson@arm.com // add the header delay (including crossbar and snoop 207811051Sandreas.hansson@arm.com // delays) of the upward snoop to the snoop delay for this 207911051Sandreas.hansson@arm.com // cache 208011051Sandreas.hansson@arm.com snoop_delay += snoopPkt.headerDelay; 208111051Sandreas.hansson@arm.com 208211051Sandreas.hansson@arm.com if (snoopPkt.cacheResponding()) { 208311051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache 208411127Sandreas.hansson@arm.com assert(!alreadyResponded); 208511127Sandreas.hansson@arm.com pkt->setCacheResponding(); 208611127Sandreas.hansson@arm.com } 208711127Sandreas.hansson@arm.com // upstream cache has the block, or has an outstanding 208811127Sandreas.hansson@arm.com // MSHR, pass the flag on 208911127Sandreas.hansson@arm.com if (snoopPkt.hasSharers()) { 209011127Sandreas.hansson@arm.com pkt->setHasSharers(); 209111127Sandreas.hansson@arm.com } 209211051Sandreas.hansson@arm.com // If this request is a prefetch or clean evict and an upper level 209311051Sandreas.hansson@arm.com // signals block present, make sure to propagate the block 209411051Sandreas.hansson@arm.com // presence to the requester. 209511051Sandreas.hansson@arm.com if (snoopPkt.isBlockCached()) { 209611051Sandreas.hansson@arm.com pkt->setBlockCached(); 209711051Sandreas.hansson@arm.com } 209811051Sandreas.hansson@arm.com // If the request was satisfied by snooping the cache 209911051Sandreas.hansson@arm.com // above, mark the original packet as satisfied too. 210011051Sandreas.hansson@arm.com if (snoopPkt.satisfied()) { 210111051Sandreas.hansson@arm.com pkt->setSatisfied(); 210211051Sandreas.hansson@arm.com } 210311051Sandreas.hansson@arm.com } else { 210411051Sandreas.hansson@arm.com cpuSidePort->sendAtomicSnoop(pkt); 210511051Sandreas.hansson@arm.com if (!alreadyResponded && pkt->cacheResponding()) { 210611051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache: 210711051Sandreas.hansson@arm.com // forward response to original requester 210811051Sandreas.hansson@arm.com assert(pkt->isResponse()); 210911051Sandreas.hansson@arm.com } 211011051Sandreas.hansson@arm.com } 211111051Sandreas.hansson@arm.com } 211211051Sandreas.hansson@arm.com 211311051Sandreas.hansson@arm.com bool respond = false; 211411051Sandreas.hansson@arm.com bool blk_valid = blk && blk->isValid(); 211511375Sandreas.hansson@arm.com if (pkt->isClean()) { 211611375Sandreas.hansson@arm.com if (blk_valid && blk->isDirty()) { 211711051Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s: packet (snoop) %s found block: %s\n", 211811051Sandreas.hansson@arm.com __func__, pkt->print(), blk->print()); 211911051Sandreas.hansson@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id); 212011051Sandreas.hansson@arm.com PacketList writebacks; 212111051Sandreas.hansson@arm.com writebacks.push_back(wb_pkt); 212211051Sandreas.hansson@arm.com 212311051Sandreas.hansson@arm.com if (is_timing) { 212411051Sandreas.hansson@arm.com // anything that is merely forwarded pays for the forward 212511051Sandreas.hansson@arm.com // latency and the delay provided by the crossbar 212611199Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + 212711051Sandreas.hansson@arm.com pkt->headerDelay; 212811199Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 212911051Sandreas.hansson@arm.com } else { 213011051Sandreas.hansson@arm.com doWritebacksAtomic(writebacks); 213111051Sandreas.hansson@arm.com } 213211051Sandreas.hansson@arm.com pkt->setSatisfied(); 213311051Sandreas.hansson@arm.com } 213411051Sandreas.hansson@arm.com } else if (!blk_valid) { 213511051Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s: snoop miss for %s\n", __func__, 213611051Sandreas.hansson@arm.com pkt->print()); 213711051Sandreas.hansson@arm.com if (is_deferred) { 213811051Sandreas.hansson@arm.com // we no longer have the block, and will not respond, but a 213911332Sandreas.hansson@arm.com // packet was allocated in MSHR::handleSnoop and we have 214011332Sandreas.hansson@arm.com // to delete it 214111332Sandreas.hansson@arm.com assert(pkt->needsResponse()); 214211332Sandreas.hansson@arm.com 214311332Sandreas.hansson@arm.com // we have passed the block to a cache upstream, that 214411332Sandreas.hansson@arm.com // cache should be responding 214511332Sandreas.hansson@arm.com assert(pkt->cacheResponding()); 214611332Sandreas.hansson@arm.com 214711332Sandreas.hansson@arm.com delete pkt; 214811332Sandreas.hansson@arm.com } 214911332Sandreas.hansson@arm.com return snoop_delay; 215011332Sandreas.hansson@arm.com } else { 215111332Sandreas.hansson@arm.com DPRINTF(Cache, "%s: snoop hit for %s, old state is %s\n", __func__, 215211332Sandreas.hansson@arm.com pkt->print(), blk->print()); 215311332Sandreas.hansson@arm.com 215411332Sandreas.hansson@arm.com // We may end up modifying both the block state and the packet (if 215511332Sandreas.hansson@arm.com // we respond in atomic mode), so just figure out what to do now 215611284Sandreas.hansson@arm.com // and then do it later. We respond to all snoops that need 215711332Sandreas.hansson@arm.com // responses provided we have the block in dirty state. The 215811332Sandreas.hansson@arm.com // invalidation itself is taken care of below. We don't respond to 215911332Sandreas.hansson@arm.com // cache maintenance operations as this is done by the destination 216011051Sandreas.hansson@arm.com // xbar. 216111332Sandreas.hansson@arm.com respond = blk->isDirty() && pkt->needsResponse(); 216211051Sandreas.hansson@arm.com 216311051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && blk->isDirty()), "Should never have " 216411051Sandreas.hansson@arm.com "a dirty block in a read-only cache %s\n", name()); 216511051Sandreas.hansson@arm.com } 216611332Sandreas.hansson@arm.com 216711051Sandreas.hansson@arm.com // Invalidate any prefetch's from below that would strip write permissions 216811051Sandreas.hansson@arm.com // MemCmd::HardPFReq is only observed by upstream caches. After missing 216911375Sandreas.hansson@arm.com // above and in it's own cache, a new MemCmd::ReadReq is created that 217011051Sandreas.hansson@arm.com // downstream caches observe. 217111051Sandreas.hansson@arm.com if (pkt->mustCheckAbove()) { 217211051Sandreas.hansson@arm.com DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s " 217311051Sandreas.hansson@arm.com "from lower cache\n", pkt->getAddr(), pkt->print()); 217411051Sandreas.hansson@arm.com pkt->setBlockCached(); 217511051Sandreas.hansson@arm.com return snoop_delay; 217611051Sandreas.hansson@arm.com } 217711051Sandreas.hansson@arm.com 217811051Sandreas.hansson@arm.com if (pkt->isRead() && !invalidate) { 217911127Sandreas.hansson@arm.com // reading without requiring the line in a writable state 218011127Sandreas.hansson@arm.com assert(!needs_writable); 218111127Sandreas.hansson@arm.com pkt->setHasSharers(); 218211127Sandreas.hansson@arm.com 218311127Sandreas.hansson@arm.com // if the requesting packet is uncacheable, retain the line in 218411127Sandreas.hansson@arm.com // the current state, otherwhise unset the writable flag, 218511051Sandreas.hansson@arm.com // which means we go from Modified to Owned (and will respond 218611051Sandreas.hansson@arm.com // below), remain in Owned (and will respond below), from 218711051Sandreas.hansson@arm.com // Exclusive to Shared, or remain in Shared 218811051Sandreas.hansson@arm.com if (!pkt->req->isUncacheable()) 218911051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 219011051Sandreas.hansson@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 219111051Sandreas.hansson@arm.com } 219211051Sandreas.hansson@arm.com 219311051Sandreas.hansson@arm.com if (respond) { 219411051Sandreas.hansson@arm.com // prevent anyone else from responding, cache as well as 219511051Sandreas.hansson@arm.com // memory, and also prevent any memory from even seeing the 219611051Sandreas.hansson@arm.com // request 219711051Sandreas.hansson@arm.com pkt->setCacheResponding(); 219811051Sandreas.hansson@arm.com if (!pkt->isClean() && blk->isWritable()) { 219911051Sandreas.hansson@arm.com // inform the cache hierarchy that this cache had the line 220011051Sandreas.hansson@arm.com // in the Modified state so that we avoid unnecessary 220111130Sali.jafri@arm.com // invalidations (see Packet::setResponderHadWritable) 220211130Sali.jafri@arm.com pkt->setResponderHadWritable(); 220311051Sandreas.hansson@arm.com 220411051Sandreas.hansson@arm.com // in the case of an uncacheable request there is no point 220511051Sandreas.hansson@arm.com // in setting the responderHadWritable flag, but since the 220611051Sandreas.hansson@arm.com // recipient does not care there is no harm in doing so 220711127Sandreas.hansson@arm.com } else { 220811127Sandreas.hansson@arm.com // if the packet has needsWritable set we invalidate our 220911051Sandreas.hansson@arm.com // copy below and all other copies will be invalidates 221011051Sandreas.hansson@arm.com // through express snoops, and if needsWritable is not set 221111051Sandreas.hansson@arm.com // we already called setHasSharers above 221211375Sandreas.hansson@arm.com } 221311375Sandreas.hansson@arm.com 221411051Sandreas.hansson@arm.com // if we are returning a writable and dirty (Modified) line, 221511051Sandreas.hansson@arm.com // we should be invalidating the line 221611051Sandreas.hansson@arm.com panic_if(!invalidate && !pkt->hasSharers(), 221711051Sandreas.hansson@arm.com "%s is passing a Modified line through %s, " 221811375Sandreas.hansson@arm.com "but keeping the block", name(), pkt->print()); 221911375Sandreas.hansson@arm.com 222011051Sandreas.hansson@arm.com if (is_timing) { 222111051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval); 222211453Sandreas.hansson@arm.com } else { 222311453Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 222411051Sandreas.hansson@arm.com // packets such as upgrades do not actually have any data 222511051Sandreas.hansson@arm.com // payload 222611375Sandreas.hansson@arm.com if (pkt->hasData()) 222711375Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 222811375Sandreas.hansson@arm.com } 222911375Sandreas.hansson@arm.com } 223011051Sandreas.hansson@arm.com 223111051Sandreas.hansson@arm.com if (!respond && is_deferred) { 223211051Sandreas.hansson@arm.com assert(pkt->needsResponse()); 223311051Sandreas.hansson@arm.com 223411051Sandreas.hansson@arm.com // if we copied the deferred packet with the intention to 223511051Sandreas.hansson@arm.com // respond, but are not responding, then a cache above us must 223611051Sandreas.hansson@arm.com // be, and we can use this as the indication of whether this 223711375Sandreas.hansson@arm.com // is a packet where we created a copy of the request or not 223811051Sandreas.hansson@arm.com if (!pkt->cacheResponding()) { 223911051Sandreas.hansson@arm.com delete pkt->req; 224011375Sandreas.hansson@arm.com } 224111051Sandreas.hansson@arm.com 224211051Sandreas.hansson@arm.com delete pkt; 224311051Sandreas.hansson@arm.com } 224411051Sandreas.hansson@arm.com 224511051Sandreas.hansson@arm.com // Do this last in case it deallocates block data or something 224611051Sandreas.hansson@arm.com // like that 224711051Sandreas.hansson@arm.com if (blk_valid && invalidate) { 224811051Sandreas.hansson@arm.com invalidateBlock(blk); 224911051Sandreas.hansson@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 225011051Sandreas.hansson@arm.com } 225111051Sandreas.hansson@arm.com 225211051Sandreas.hansson@arm.com return snoop_delay; 225311375Sandreas.hansson@arm.com} 225411051Sandreas.hansson@arm.com 225511051Sandreas.hansson@arm.com 225611051Sandreas.hansson@arm.comvoid 225711051Sandreas.hansson@arm.comCache::recvTimingSnoopReq(PacketPtr pkt) 225811051Sandreas.hansson@arm.com{ 225911051Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 226011051Sandreas.hansson@arm.com 226111051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 226211051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 226311051Sandreas.hansson@arm.com 226411051Sandreas.hansson@arm.com // no need to snoop requests that are not in range 226511051Sandreas.hansson@arm.com if (!inRange(pkt->getAddr())) { 226611375Sandreas.hansson@arm.com return; 226711051Sandreas.hansson@arm.com } 226811051Sandreas.hansson@arm.com 226911051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 227011051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 227111051Sandreas.hansson@arm.com 227211051Sandreas.hansson@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 227311051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 227411051Sandreas.hansson@arm.com 227511051Sandreas.hansson@arm.com // Update the latency cost of the snoop so that the crossbar can 227611051Sandreas.hansson@arm.com // account for it. Do not overwrite what other neighbouring caches 227711051Sandreas.hansson@arm.com // have already done, rather take the maximum. The update is 227811051Sandreas.hansson@arm.com // tentative, for cases where we return before an upward snoop 227911051Sandreas.hansson@arm.com // happens below. 228011051Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, 228111051Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 228211051Sandreas.hansson@arm.com 228311051Sandreas.hansson@arm.com // Inform request(Prefetch, CleanEvict or Writeback) from below of 228411051Sandreas.hansson@arm.com // MSHR hit, set setBlockCached. 228511051Sandreas.hansson@arm.com if (mshr && pkt->mustCheckAbove()) { 228611051Sandreas.hansson@arm.com DPRINTF(Cache, "Setting block cached for %s from lower cache on " 228711051Sandreas.hansson@arm.com "mshr hit\n", pkt->print()); 228811051Sandreas.hansson@arm.com pkt->setBlockCached(); 228911051Sandreas.hansson@arm.com return; 229011051Sandreas.hansson@arm.com } 229111051Sandreas.hansson@arm.com 229211375Sandreas.hansson@arm.com // Bypass any existing cache maintenance requests if the request 229311051Sandreas.hansson@arm.com // has been satisfied already (i.e., the dirty block has been 229411051Sandreas.hansson@arm.com // found). 229511051Sandreas.hansson@arm.com if (mshr && pkt->req->isCacheMaintenance() && pkt->satisfied()) { 229611130Sali.jafri@arm.com return; 229711051Sandreas.hansson@arm.com } 229811051Sandreas.hansson@arm.com 229911051Sandreas.hansson@arm.com // Let the MSHR itself track the snoop and decide whether we want 230011051Sandreas.hansson@arm.com // to go ahead and do the regular cache snoop 230111051Sandreas.hansson@arm.com if (mshr && mshr->handleSnoop(pkt, order++)) { 230211051Sandreas.hansson@arm.com DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)." 230311051Sandreas.hansson@arm.com "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns", 230411051Sandreas.hansson@arm.com mshr->print()); 230511130Sali.jafri@arm.com 230611130Sali.jafri@arm.com if (mshr->getNumTargets() > numTarget) 230711130Sali.jafri@arm.com warn("allocating bonus target for snoop"); //handle later 230811130Sali.jafri@arm.com return; 230911130Sali.jafri@arm.com } 231011130Sali.jafri@arm.com 231111199Sandreas.hansson@arm.com //We also need to check the writeback buffers and handle those 231211130Sali.jafri@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(blk_addr, is_secure); 231311130Sali.jafri@arm.com if (wb_entry) { 231411130Sali.jafri@arm.com DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n", 231511284Sandreas.hansson@arm.com pkt->getAddr(), is_secure ? "s" : "ns"); 231611130Sali.jafri@arm.com // Expect to see only Writebacks and/or CleanEvicts here, both of 231711130Sali.jafri@arm.com // which should not be generated for uncacheable data. 231811130Sali.jafri@arm.com assert(!wb_entry->isUncacheable()); 231911130Sali.jafri@arm.com // There should only be a single request responsible for generating 232011130Sali.jafri@arm.com // Writebacks/CleanEvicts. 232111051Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 232211051Sandreas.hansson@arm.com PacketPtr wb_pkt = wb_entry->getTarget()->pkt; 232311375Sandreas.hansson@arm.com assert(wb_pkt->isEviction() || wb_pkt->cmd == MemCmd::WriteClean); 232411375Sandreas.hansson@arm.com 232511051Sandreas.hansson@arm.com if (pkt->isEviction()) { 232611375Sandreas.hansson@arm.com // if the block is found in the write queue, set the BLOCK_CACHED 232711375Sandreas.hansson@arm.com // flag for Writeback/CleanEvict snoop. On return the snoop will 232811375Sandreas.hansson@arm.com // propagate the BLOCK_CACHED flag in Writeback packets and prevent 232911375Sandreas.hansson@arm.com // any CleanEvicts from travelling down the memory hierarchy. 233011375Sandreas.hansson@arm.com pkt->setBlockCached(); 233111375Sandreas.hansson@arm.com DPRINTF(Cache, "%s: Squashing %s from lower cache on writequeue " 233211375Sandreas.hansson@arm.com "hit\n", __func__, pkt->print()); 233311375Sandreas.hansson@arm.com return; 233411051Sandreas.hansson@arm.com } 233511051Sandreas.hansson@arm.com 233611375Sandreas.hansson@arm.com // conceptually writebacks are no different to other blocks in 233711375Sandreas.hansson@arm.com // this cache, so the behaviour is modelled after handleSnoop, 233811375Sandreas.hansson@arm.com // the difference being that instead of querying the block 233911375Sandreas.hansson@arm.com // state to determine if it is dirty and writable, we use the 234011375Sandreas.hansson@arm.com // command and fields of the writeback packet 234111375Sandreas.hansson@arm.com bool respond = wb_pkt->cmd == MemCmd::WritebackDirty && 234211375Sandreas.hansson@arm.com pkt->needsResponse(); 234311375Sandreas.hansson@arm.com bool have_writable = !wb_pkt->hasSharers(); 234411051Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 234511051Sandreas.hansson@arm.com 234611375Sandreas.hansson@arm.com if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) { 234711375Sandreas.hansson@arm.com assert(!pkt->needsWritable()); 234811375Sandreas.hansson@arm.com pkt->setHasSharers(); 234911375Sandreas.hansson@arm.com wb_pkt->setHasSharers(); 235011051Sandreas.hansson@arm.com } 235111051Sandreas.hansson@arm.com 235211051Sandreas.hansson@arm.com if (respond) { 235311051Sandreas.hansson@arm.com pkt->setCacheResponding(); 235411375Sandreas.hansson@arm.com 235511375Sandreas.hansson@arm.com if (have_writable) { 235611375Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 235711375Sandreas.hansson@arm.com } 235811051Sandreas.hansson@arm.com 235911051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(), 236011051Sandreas.hansson@arm.com false, false); 236111051Sandreas.hansson@arm.com } 236211051Sandreas.hansson@arm.com 236311051Sandreas.hansson@arm.com if (invalidate && wb_pkt->cmd != MemCmd::WriteClean) { 236411051Sandreas.hansson@arm.com // Invalidation trumps our writeback... discard here 236511275Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 236611275Sandreas.hansson@arm.com markInService(wb_entry); 236711275Sandreas.hansson@arm.com delete wb_pkt; 236811275Sandreas.hansson@arm.com } 236911051Sandreas.hansson@arm.com } 237011051Sandreas.hansson@arm.com 237111051Sandreas.hansson@arm.com // If this was a shared writeback, there may still be 237211051Sandreas.hansson@arm.com // other shared copies above that require invalidation. 237311051Sandreas.hansson@arm.com // We could be more selective and return here if the 237411051Sandreas.hansson@arm.com // request is non-exclusive or if the writeback is 237511051Sandreas.hansson@arm.com // exclusive. 237611051Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false); 237711051Sandreas.hansson@arm.com 237811284Sandreas.hansson@arm.com // Override what we did when we first saw the snoop, as we now 237911284Sandreas.hansson@arm.com // also have the cost of the upwards snoops to account for 238011284Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay + 238111284Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 238211284Sandreas.hansson@arm.com} 238311284Sandreas.hansson@arm.com 238411284Sandreas.hansson@arm.combool 238511276Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 238611276Sandreas.hansson@arm.com{ 238711284Sandreas.hansson@arm.com // Express snoop responses from master to slave, e.g., from L1 to L2 238811284Sandreas.hansson@arm.com cache->recvTimingSnoopResp(pkt); 238911284Sandreas.hansson@arm.com return true; 239011284Sandreas.hansson@arm.com} 239111284Sandreas.hansson@arm.com 239211284Sandreas.hansson@arm.comTick 239311051Sandreas.hansson@arm.comCache::recvAtomicSnoop(PacketPtr pkt) 239411051Sandreas.hansson@arm.com{ 239511051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 239611375Sandreas.hansson@arm.com assert(!system->bypassCaches()); 239711051Sandreas.hansson@arm.com 239811051Sandreas.hansson@arm.com // no need to snoop requests that are not in range. 239911375Sandreas.hansson@arm.com if (!inRange(pkt->getAddr())) { 240011051Sandreas.hansson@arm.com return 0; 240111051Sandreas.hansson@arm.com } 240211051Sandreas.hansson@arm.com 240311375Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 240411051Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false); 240511375Sandreas.hansson@arm.com return snoop_delay + lookupLatency * clockPeriod(); 240611277Sandreas.hansson@arm.com} 240711277Sandreas.hansson@arm.com 240811375Sandreas.hansson@arm.com 240911051Sandreas.hansson@arm.comQueueEntry* 241011375Sandreas.hansson@arm.comCache::getNextQueueEntry() 241111051Sandreas.hansson@arm.com{ 241211051Sandreas.hansson@arm.com // Check both MSHR queue and write buffer for potential requests, 241311051Sandreas.hansson@arm.com // note that null does not mean there is no request, it could 241411375Sandreas.hansson@arm.com // simply be that it is not ready 241511375Sandreas.hansson@arm.com MSHR *miss_mshr = mshrQueue.getNext(); 241611452Sandreas.hansson@arm.com WriteQueueEntry *wq_entry = writeBuffer.getNext(); 241711375Sandreas.hansson@arm.com 241811375Sandreas.hansson@arm.com // If we got a write buffer request ready, first priority is a 241911375Sandreas.hansson@arm.com // full write buffer, otherwise we favour the miss requests 242011375Sandreas.hansson@arm.com if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) { 242111375Sandreas.hansson@arm.com // need to search MSHR queue for conflicting earlier miss. 242211375Sandreas.hansson@arm.com MSHR *conflict_mshr = 242311375Sandreas.hansson@arm.com mshrQueue.findPending(wq_entry->blkAddr, 242411375Sandreas.hansson@arm.com wq_entry->isSecure); 242511375Sandreas.hansson@arm.com 242611375Sandreas.hansson@arm.com if (conflict_mshr && conflict_mshr->order < wq_entry->order) { 242711375Sandreas.hansson@arm.com // Service misses in order until conflict is cleared. 242811375Sandreas.hansson@arm.com return conflict_mshr; 242911375Sandreas.hansson@arm.com 243011375Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 243111375Sandreas.hansson@arm.com } 243211375Sandreas.hansson@arm.com 243311375Sandreas.hansson@arm.com // No conflicts; issue write 243411375Sandreas.hansson@arm.com return wq_entry; 243511375Sandreas.hansson@arm.com } else if (miss_mshr) { 243611375Sandreas.hansson@arm.com // need to check for conflicting earlier writeback 243711375Sandreas.hansson@arm.com WriteQueueEntry *conflict_mshr = 243811375Sandreas.hansson@arm.com writeBuffer.findPending(miss_mshr->blkAddr, 243911375Sandreas.hansson@arm.com miss_mshr->isSecure); 244011375Sandreas.hansson@arm.com if (conflict_mshr) { 244111375Sandreas.hansson@arm.com // not sure why we don't check order here... it was in the 244211375Sandreas.hansson@arm.com // original code but commented out. 244311375Sandreas.hansson@arm.com 244411375Sandreas.hansson@arm.com // The only way this happens is if we are 244511375Sandreas.hansson@arm.com // doing a write and we didn't have permissions 244611375Sandreas.hansson@arm.com // then subsequently saw a writeback (owned got evicted) 244711375Sandreas.hansson@arm.com // We need to make sure to perform the writeback first 244811375Sandreas.hansson@arm.com // To preserve the dirty data, then we can issue the write 244911375Sandreas.hansson@arm.com 245011375Sandreas.hansson@arm.com // should we return wq_entry here instead? I.e. do we 245111375Sandreas.hansson@arm.com // have to flush writes in order? I don't think so... not 245211375Sandreas.hansson@arm.com // for Alpha anyway. Maybe for x86? 245311375Sandreas.hansson@arm.com return conflict_mshr; 245411375Sandreas.hansson@arm.com 245511375Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 245611375Sandreas.hansson@arm.com } 245711375Sandreas.hansson@arm.com 245811375Sandreas.hansson@arm.com // No conflicts; issue read 245911375Sandreas.hansson@arm.com return miss_mshr; 246011375Sandreas.hansson@arm.com } 246111375Sandreas.hansson@arm.com 246211375Sandreas.hansson@arm.com // fall through... no pending requests. Try a prefetch. 246311375Sandreas.hansson@arm.com assert(!miss_mshr && !wq_entry); 246411375Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 246511375Sandreas.hansson@arm.com // If we have a miss queue slot, we can try a prefetch 246611375Sandreas.hansson@arm.com PacketPtr pkt = prefetcher->getPacket(); 246711375Sandreas.hansson@arm.com if (pkt) { 246811375Sandreas.hansson@arm.com Addr pf_addr = pkt->getBlockAddr(blkSize); 246911375Sandreas.hansson@arm.com if (!tags->findBlock(pf_addr, pkt->isSecure()) && 247011375Sandreas.hansson@arm.com !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 247111453Sandreas.hansson@arm.com !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 247211453Sandreas.hansson@arm.com // Update statistic on number of prefetches issued 247311375Sandreas.hansson@arm.com // (hwpf_mshr_misses) 247411375Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 247511375Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 247611375Sandreas.hansson@arm.com 247711375Sandreas.hansson@arm.com // allocate an MSHR and return it, note 247811375Sandreas.hansson@arm.com // that we send the packet straight away, so do not 247911375Sandreas.hansson@arm.com // schedule the send 248011375Sandreas.hansson@arm.com return allocateMissBuffer(pkt, curTick(), false); 248111375Sandreas.hansson@arm.com } else { 248211051Sandreas.hansson@arm.com // free the request and packet 248311051Sandreas.hansson@arm.com delete pkt->req; 248411051Sandreas.hansson@arm.com delete pkt; 248511051Sandreas.hansson@arm.com } 248611051Sandreas.hansson@arm.com } 248711051Sandreas.hansson@arm.com } 248811051Sandreas.hansson@arm.com 248911051Sandreas.hansson@arm.com return nullptr; 249011051Sandreas.hansson@arm.com} 249111051Sandreas.hansson@arm.com 249211051Sandreas.hansson@arm.combool 249311483Snikos.nikoleris@arm.comCache::isCachedAbove(PacketPtr pkt, bool is_timing) const 249411483Snikos.nikoleris@arm.com{ 249511051Sandreas.hansson@arm.com if (!forwardSnoops) 249611051Sandreas.hansson@arm.com return false; 249711051Sandreas.hansson@arm.com // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and 249811051Sandreas.hansson@arm.com // Writeback snoops into upper level caches to check for copies of the 249911051Sandreas.hansson@arm.com // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict 250011051Sandreas.hansson@arm.com // packet, the cache can inform the crossbar below of presence or absence 250111051Sandreas.hansson@arm.com // of the block. 250211051Sandreas.hansson@arm.com if (is_timing) { 250311051Sandreas.hansson@arm.com Packet snoop_pkt(pkt, true, false); 250411051Sandreas.hansson@arm.com snoop_pkt.setExpressSnoop(); 250511051Sandreas.hansson@arm.com // Assert that packet is either Writeback or CleanEvict and not a 250611051Sandreas.hansson@arm.com // prefetch request because prefetch requests need an MSHR and may 250711051Sandreas.hansson@arm.com // generate a snoop response. 250811051Sandreas.hansson@arm.com assert(pkt->isEviction() || pkt->cmd == MemCmd::WriteClean); 250911051Sandreas.hansson@arm.com snoop_pkt.senderState = nullptr; 251011051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 251111051Sandreas.hansson@arm.com // Writeback/CleanEvict snoops do not generate a snoop response. 251211051Sandreas.hansson@arm.com assert(!(snoop_pkt.cacheResponding())); 251311051Sandreas.hansson@arm.com return snoop_pkt.isBlockCached(); 251411051Sandreas.hansson@arm.com } else { 251511051Sandreas.hansson@arm.com cpuSidePort->sendAtomicSnoop(pkt); 251611051Sandreas.hansson@arm.com return pkt->isBlockCached(); 251711051Sandreas.hansson@arm.com } 251811051Sandreas.hansson@arm.com} 251911051Sandreas.hansson@arm.com 252011051Sandreas.hansson@arm.comTick 252111051Sandreas.hansson@arm.comCache::nextQueueReadyTime() const 252211051Sandreas.hansson@arm.com{ 252311051Sandreas.hansson@arm.com Tick nextReady = std::min(mshrQueue.nextReadyTime(), 252411051Sandreas.hansson@arm.com writeBuffer.nextReadyTime()); 252511051Sandreas.hansson@arm.com 252611051Sandreas.hansson@arm.com // Don't signal prefetch ready time if no MSHRs available 252711051Sandreas.hansson@arm.com // Will signal once enoguh MSHRs are deallocated 252811051Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 252911051Sandreas.hansson@arm.com nextReady = std::min(nextReady, 253011051Sandreas.hansson@arm.com prefetcher->nextPrefetchReadyTime()); 253111051Sandreas.hansson@arm.com } 253211051Sandreas.hansson@arm.com 253311051Sandreas.hansson@arm.com return nextReady; 253411051Sandreas.hansson@arm.com} 253511051Sandreas.hansson@arm.com 253611334Sandreas.hansson@arm.combool 253711334Sandreas.hansson@arm.comCache::sendMSHRQueuePacket(MSHR* mshr) 253811051Sandreas.hansson@arm.com{ 253911051Sandreas.hansson@arm.com assert(mshr); 254011051Sandreas.hansson@arm.com 254111051Sandreas.hansson@arm.com // use request from 1st target 254211051Sandreas.hansson@arm.com PacketPtr tgt_pkt = mshr->getTarget()->pkt; 254311051Sandreas.hansson@arm.com 254411051Sandreas.hansson@arm.com DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print()); 254511051Sandreas.hansson@arm.com 254611051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 254711051Sandreas.hansson@arm.com 254811051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) { 254911051Sandreas.hansson@arm.com // we should never have hardware prefetches to allocated 255011051Sandreas.hansson@arm.com // blocks 255111051Sandreas.hansson@arm.com assert(blk == nullptr); 255211051Sandreas.hansson@arm.com 255311051Sandreas.hansson@arm.com // We need to check the caches above us to verify that 255411051Sandreas.hansson@arm.com // they don't have a copy of this block in the dirty state 255511051Sandreas.hansson@arm.com // at the moment. Without this check we could get a stale 255611051Sandreas.hansson@arm.com // copy from memory that might get used in place of the 255711051Sandreas.hansson@arm.com // dirty one. 255811051Sandreas.hansson@arm.com Packet snoop_pkt(tgt_pkt, true, false); 255911051Sandreas.hansson@arm.com snoop_pkt.setExpressSnoop(); 256011051Sandreas.hansson@arm.com // We are sending this packet upwards, but if it hits we will 256111051Sandreas.hansson@arm.com // get a snoop response that we end up treating just like a 256211051Sandreas.hansson@arm.com // normal response, hence it needs the MSHR as its sender 256311051Sandreas.hansson@arm.com // state 256411051Sandreas.hansson@arm.com snoop_pkt.senderState = mshr; 256511051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 256611051Sandreas.hansson@arm.com 256711051Sandreas.hansson@arm.com // Check to see if the prefetch was squashed by an upper cache (to 256811051Sandreas.hansson@arm.com // prevent us from grabbing the line) or if a Check to see if a 256911051Sandreas.hansson@arm.com // writeback arrived between the time the prefetch was placed in 257011051Sandreas.hansson@arm.com // the MSHRs and when it was selected to be sent or if the 257111051Sandreas.hansson@arm.com // prefetch was squashed by an upper cache. 257211051Sandreas.hansson@arm.com 257311051Sandreas.hansson@arm.com // It is important to check cacheResponding before 257411051Sandreas.hansson@arm.com // prefetchSquashed. If another cache has committed to 257511051Sandreas.hansson@arm.com // responding, it will be sending a dirty response which will 257611053Sandreas.hansson@arm.com // arrive at the MSHR allocated for this request. Checking the 257711053Sandreas.hansson@arm.com // prefetchSquash first may result in the MSHR being 257811053Sandreas.hansson@arm.com // prematurely deallocated. 257911053Sandreas.hansson@arm.com if (snoop_pkt.cacheResponding()) { 258011053Sandreas.hansson@arm.com auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req); 258111053Sandreas.hansson@arm.com assert(r.second); 258211053Sandreas.hansson@arm.com 258311051Sandreas.hansson@arm.com // if we are getting a snoop response with no sharers it 258411051Sandreas.hansson@arm.com // will be allocated as Modified 258511051Sandreas.hansson@arm.com bool pending_modified_resp = !snoop_pkt.hasSharers(); 258611051Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 258711051Sandreas.hansson@arm.com 258811051Sandreas.hansson@arm.com DPRINTF(Cache, "Upward snoop of prefetch for addr" 258911051Sandreas.hansson@arm.com " %#x (%s) hit\n", 259011051Sandreas.hansson@arm.com tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns"); 259111051Sandreas.hansson@arm.com return false; 259211051Sandreas.hansson@arm.com } 259311051Sandreas.hansson@arm.com 259411051Sandreas.hansson@arm.com if (snoop_pkt.isBlockCached()) { 259511051Sandreas.hansson@arm.com DPRINTF(Cache, "Block present, prefetch squashed by cache. " 259611051Sandreas.hansson@arm.com "Deallocating mshr target %#x.\n", 259711051Sandreas.hansson@arm.com mshr->blkAddr); 259811051Sandreas.hansson@arm.com 259911051Sandreas.hansson@arm.com // Deallocate the mshr target 260011051Sandreas.hansson@arm.com if (mshrQueue.forceDeallocateTarget(mshr)) { 260111051Sandreas.hansson@arm.com // Clear block if this deallocation resulted freed an 260211051Sandreas.hansson@arm.com // mshr when all had previously been utilized 260311051Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 260411051Sandreas.hansson@arm.com } 260511051Sandreas.hansson@arm.com 260611051Sandreas.hansson@arm.com // given that no response is expected, delete Request and Packet 260711051Sandreas.hansson@arm.com delete tgt_pkt->req; 260811051Sandreas.hansson@arm.com delete tgt_pkt; 260911051Sandreas.hansson@arm.com 261011051Sandreas.hansson@arm.com return false; 261111051Sandreas.hansson@arm.com } 261211051Sandreas.hansson@arm.com } 261311051Sandreas.hansson@arm.com 261411051Sandreas.hansson@arm.com // either a prefetch that is not present upstream, or a normal 261511051Sandreas.hansson@arm.com // MSHR request, proceed to get the packet to send downstream 261611051Sandreas.hansson@arm.com PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable()); 261711051Sandreas.hansson@arm.com 261811051Sandreas.hansson@arm.com mshr->isForward = (pkt == nullptr); 261911051Sandreas.hansson@arm.com 262011051Sandreas.hansson@arm.com if (mshr->isForward) { 262111051Sandreas.hansson@arm.com // not a cache block request, but a response is expected 262211051Sandreas.hansson@arm.com // make copy of current packet to forward, keep current 262311051Sandreas.hansson@arm.com // copy for response handling 262411051Sandreas.hansson@arm.com pkt = new Packet(tgt_pkt, false, true); 262511051Sandreas.hansson@arm.com assert(!pkt->isWrite()); 262611051Sandreas.hansson@arm.com } 262711051Sandreas.hansson@arm.com 262811051Sandreas.hansson@arm.com // play it safe and append (rather than set) the sender state, 262911051Sandreas.hansson@arm.com // as forwarded packets may already have existing state 263011051Sandreas.hansson@arm.com pkt->pushSenderState(mshr); 263111375Sandreas.hansson@arm.com 263211375Sandreas.hansson@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 263311375Sandreas.hansson@arm.com // A cache clean opearation is looking for a dirty block. Mark 263411051Sandreas.hansson@arm.com // the packet so that the destination xbar can determine that 263511051Sandreas.hansson@arm.com // there will be a follow-up write packet as well. 263611051Sandreas.hansson@arm.com pkt->setSatisfied(); 263711051Sandreas.hansson@arm.com } 263811051Sandreas.hansson@arm.com 263911375Sandreas.hansson@arm.com if (!memSidePort->sendTimingReq(pkt)) { 264011375Sandreas.hansson@arm.com // we are awaiting a retry, but we 264111051Sandreas.hansson@arm.com // delete the packet and will be creating a new packet 264211051Sandreas.hansson@arm.com // when we get the opportunity 264311375Sandreas.hansson@arm.com delete pkt; 264411051Sandreas.hansson@arm.com 264511051Sandreas.hansson@arm.com // note that we have now masked any requestBus and 264611051Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 264711375Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 264811051Sandreas.hansson@arm.com // care about this packet and might override it before 264911051Sandreas.hansson@arm.com // it gets retried 265011051Sandreas.hansson@arm.com return true; 265111375Sandreas.hansson@arm.com } else { 265211051Sandreas.hansson@arm.com // As part of the call to sendTimingReq the packet is 265311051Sandreas.hansson@arm.com // forwarded to all neighbouring caches (and any caches 265411051Sandreas.hansson@arm.com // above them) as a snoop. Thus at this point we know if 265511051Sandreas.hansson@arm.com // any of the neighbouring caches are responding, and if 265611051Sandreas.hansson@arm.com // so, we know it is dirty, and we can determine if it is 265711051Sandreas.hansson@arm.com // being passed as Modified, making our MSHR the ordering 265811051Sandreas.hansson@arm.com // point 265911051Sandreas.hansson@arm.com bool pending_modified_resp = !pkt->hasSharers() && 266011051Sandreas.hansson@arm.com pkt->cacheResponding(); 266111051Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 266211051Sandreas.hansson@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 2663 // A cache clean opearation is looking for a dirty 2664 // block. If a dirty block is encountered a WriteClean 2665 // will update any copies to the path to the memory 2666 // until the point of reference. 2667 DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 2668 __func__, pkt->print(), blk->print()); 2669 PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), 2670 pkt->id); 2671 PacketList writebacks; 2672 writebacks.push_back(wb_pkt); 2673 doWritebacks(writebacks, 0); 2674 } 2675 2676 return false; 2677 } 2678} 2679 2680bool 2681Cache::sendWriteQueuePacket(WriteQueueEntry* wq_entry) 2682{ 2683 assert(wq_entry); 2684 2685 // always a single target for write queue entries 2686 PacketPtr tgt_pkt = wq_entry->getTarget()->pkt; 2687 2688 DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print()); 2689 2690 // forward as is, both for evictions and uncacheable writes 2691 if (!memSidePort->sendTimingReq(tgt_pkt)) { 2692 // note that we have now masked any requestBus and 2693 // schedSendEvent (we will wait for a retry before 2694 // doing anything), and this is so even if we do not 2695 // care about this packet and might override it before 2696 // it gets retried 2697 return true; 2698 } else { 2699 markInService(wq_entry); 2700 return false; 2701 } 2702} 2703 2704void 2705Cache::serialize(CheckpointOut &cp) const 2706{ 2707 bool dirty(isDirty()); 2708 2709 if (dirty) { 2710 warn("*** The cache still contains dirty data. ***\n"); 2711 warn(" Make sure to drain the system using the correct flags.\n"); 2712 warn(" This checkpoint will not restore correctly and dirty data " 2713 " in the cache will be lost!\n"); 2714 } 2715 2716 // Since we don't checkpoint the data in the cache, any dirty data 2717 // will be lost when restoring from a checkpoint of a system that 2718 // wasn't drained properly. Flag the checkpoint as invalid if the 2719 // cache contains dirty data. 2720 bool bad_checkpoint(dirty); 2721 SERIALIZE_SCALAR(bad_checkpoint); 2722} 2723 2724void 2725Cache::unserialize(CheckpointIn &cp) 2726{ 2727 bool bad_checkpoint; 2728 UNSERIALIZE_SCALAR(bad_checkpoint); 2729 if (bad_checkpoint) { 2730 fatal("Restoring from checkpoints with dirty caches is not supported " 2731 "in the classic memory system. Please remove any caches or " 2732 " drain them properly before taking checkpoints.\n"); 2733 } 2734} 2735 2736/////////////// 2737// 2738// CpuSidePort 2739// 2740/////////////// 2741 2742AddrRangeList 2743Cache::CpuSidePort::getAddrRanges() const 2744{ 2745 return cache->getAddrRanges(); 2746} 2747 2748bool 2749Cache::CpuSidePort::tryTiming(PacketPtr pkt) 2750{ 2751 assert(!cache->system->bypassCaches()); 2752 2753 // always let express snoop packets through if even if blocked 2754 if (pkt->isExpressSnoop()) { 2755 return true; 2756 } else if (isBlocked() || mustSendRetry) { 2757 // either already committed to send a retry, or blocked 2758 mustSendRetry = true; 2759 return false; 2760 } 2761 mustSendRetry = false; 2762 return true; 2763} 2764 2765bool 2766Cache::CpuSidePort::recvTimingReq(PacketPtr pkt) 2767{ 2768 assert(!cache->system->bypassCaches()); 2769 2770 // always let express snoop packets through if even if blocked 2771 if (pkt->isExpressSnoop() || tryTiming(pkt)) { 2772 cache->recvTimingReq(pkt); 2773 return true; 2774 } 2775 return false; 2776} 2777 2778Tick 2779Cache::CpuSidePort::recvAtomic(PacketPtr pkt) 2780{ 2781 return cache->recvAtomic(pkt); 2782} 2783 2784void 2785Cache::CpuSidePort::recvFunctional(PacketPtr pkt) 2786{ 2787 // functional request 2788 cache->functionalAccess(pkt, true); 2789} 2790 2791Cache:: 2792CpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache, 2793 const std::string &_label) 2794 : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache) 2795{ 2796} 2797 2798Cache* 2799CacheParams::create() 2800{ 2801 assert(tags); 2802 assert(replacement_policy); 2803 2804 return new Cache(this); 2805} 2806/////////////// 2807// 2808// MemSidePort 2809// 2810/////////////// 2811 2812bool 2813Cache::MemSidePort::recvTimingResp(PacketPtr pkt) 2814{ 2815 cache->recvTimingResp(pkt); 2816 return true; 2817} 2818 2819// Express snooping requests to memside port 2820void 2821Cache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 2822{ 2823 // handle snooping requests 2824 cache->recvTimingSnoopReq(pkt); 2825} 2826 2827Tick 2828Cache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 2829{ 2830 return cache->recvAtomicSnoop(pkt); 2831} 2832 2833void 2834Cache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 2835{ 2836 // functional snoop (note that in contrast to atomic we don't have 2837 // a specific functionalSnoop method, as they have the same 2838 // behaviour regardless) 2839 cache->functionalAccess(pkt, false); 2840} 2841 2842void 2843Cache::CacheReqPacketQueue::sendDeferredPacket() 2844{ 2845 // sanity check 2846 assert(!waitingOnRetry); 2847 2848 // there should never be any deferred request packets in the 2849 // queue, instead we resly on the cache to provide the packets 2850 // from the MSHR queue or write queue 2851 assert(deferredPacketReadyTime() == MaxTick); 2852 2853 // check for request packets (requests & writebacks) 2854 QueueEntry* entry = cache.getNextQueueEntry(); 2855 2856 if (!entry) { 2857 // can happen if e.g. we attempt a writeback and fail, but 2858 // before the retry, the writeback is eliminated because 2859 // we snoop another cache's ReadEx. 2860 } else { 2861 // let our snoop responses go first if there are responses to 2862 // the same addresses 2863 if (checkConflictingSnoop(entry->blkAddr)) { 2864 return; 2865 } 2866 waitingOnRetry = entry->sendPacket(cache); 2867 } 2868 2869 // if we succeeded and are not waiting for a retry, schedule the 2870 // next send considering when the next queue is ready, note that 2871 // snoop responses have their own packet queue and thus schedule 2872 // their own events 2873 if (!waitingOnRetry) { 2874 schedSendEvent(cache.nextQueueReadyTime()); 2875 } 2876} 2877 2878Cache:: 2879MemSidePort::MemSidePort(const std::string &_name, Cache *_cache, 2880 const std::string &_label) 2881 : BaseCache::CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 2882 _reqQueue(*_cache, *this, _snoopRespQueue, _label), 2883 _snoopRespQueue(*_cache, *this, _label), cache(_cache) 2884{ 2885} 2886