cache.cc revision 12600
12810Srdreslin@umich.edu/* 212500Snikos.nikoleris@arm.com * Copyright (c) 2010-2018 ARM Limited 311051Sandreas.hansson@arm.com * All rights reserved. 411051Sandreas.hansson@arm.com * 511051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911051Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311051Sandreas.hansson@arm.com * 1411051Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511051Sandreas.hansson@arm.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 162810Srdreslin@umich.edu * All rights reserved. 172810Srdreslin@umich.edu * 182810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 192810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 202810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 212810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 222810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 232810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 242810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 252810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 262810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 272810Srdreslin@umich.edu * this software without specific prior written permission. 282810Srdreslin@umich.edu * 292810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810Srdreslin@umich.edu * 412810Srdreslin@umich.edu * Authors: Erik Hallnor 4211051Sandreas.hansson@arm.com * Dave Greene 4311051Sandreas.hansson@arm.com * Nathan Binkert 442810Srdreslin@umich.edu * Steve Reinhardt 4511051Sandreas.hansson@arm.com * Ron Dreslinski 4611051Sandreas.hansson@arm.com * Andreas Sandberg 4712349Snikos.nikoleris@arm.com * Nikos Nikoleris 482810Srdreslin@umich.edu */ 492810Srdreslin@umich.edu 502810Srdreslin@umich.edu/** 512810Srdreslin@umich.edu * @file 5211051Sandreas.hansson@arm.com * Cache definitions. 532810Srdreslin@umich.edu */ 542810Srdreslin@umich.edu 5511051Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 562810Srdreslin@umich.edu 5712724Snikos.nikoleris@arm.com#include "base/logging.hh" 5812724Snikos.nikoleris@arm.com#include "base/types.hh" 5912724Snikos.nikoleris@arm.com#include "debug/Cache.hh" 6012334Sgabeblack@google.com#include "debug/CachePort.hh" 6112724Snikos.nikoleris@arm.com#include "debug/CacheTags.hh" 6211051Sandreas.hansson@arm.com#include "debug/CacheVerbose.hh" 6311051Sandreas.hansson@arm.com#include "mem/cache/blk.hh" 6411051Sandreas.hansson@arm.com#include "mem/cache/mshr.hh" 6511288Ssteve.reinhardt@amd.com#include "mem/cache/prefetch/base.hh" 6612724Snikos.nikoleris@arm.com#include "sim/sim_exit.hh" 6711051Sandreas.hansson@arm.com 6811051Sandreas.hansson@arm.comCache::Cache(const CacheParams *p) 6912724Snikos.nikoleris@arm.com : BaseCache(p, p->system->cacheLineSize()), 7012724Snikos.nikoleris@arm.com tags(p->tags), 7112724Snikos.nikoleris@arm.com prefetcher(p->prefetcher), 7212724Snikos.nikoleris@arm.com doFastWrites(true), 7311051Sandreas.hansson@arm.com prefetchOnAccess(p->prefetch_on_access), 7411053Sandreas.hansson@arm.com clusivity(p->clusivity), 7511053Sandreas.hansson@arm.com writebackClean(p->writeback_clean), 7612724Snikos.nikoleris@arm.com tempBlockWriteback(nullptr), 7711051Sandreas.hansson@arm.com writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); }, 7811051Sandreas.hansson@arm.com name(), false, 7911051Sandreas.hansson@arm.com EventBase::Delayed_Writeback_Pri) 8011051Sandreas.hansson@arm.com{ 8111601Sandreas.hansson@arm.com tempBlock = new CacheBlk(); 8211601Sandreas.hansson@arm.com tempBlock->data = new uint8_t[blkSize]; 8311051Sandreas.hansson@arm.com 8412724Snikos.nikoleris@arm.com cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this, 8511051Sandreas.hansson@arm.com "CpuSidePort"); 8612724Snikos.nikoleris@arm.com memSidePort = new MemSidePort(p->name + ".mem_side", this, 8711600Sandreas.hansson@arm.com "MemSidePort"); 8811600Sandreas.hansson@arm.com 8911051Sandreas.hansson@arm.com tags->setCache(this); 9011051Sandreas.hansson@arm.com if (prefetcher) 9111051Sandreas.hansson@arm.com prefetcher->setCache(this); 9211284Sandreas.hansson@arm.com} 9311051Sandreas.hansson@arm.com 9411051Sandreas.hansson@arm.comCache::~Cache() 9511051Sandreas.hansson@arm.com{ 9611602Sandreas.hansson@arm.com delete [] tempBlock->data; 9711051Sandreas.hansson@arm.com delete tempBlock; 9811051Sandreas.hansson@arm.com 9911284Sandreas.hansson@arm.com delete cpuSidePort; 10011051Sandreas.hansson@arm.com delete memSidePort; 10111284Sandreas.hansson@arm.com} 10211602Sandreas.hansson@arm.com 10311051Sandreas.hansson@arm.comvoid 10411051Sandreas.hansson@arm.comCache::regStats() 10511284Sandreas.hansson@arm.com{ 10611051Sandreas.hansson@arm.com BaseCache::regStats(); 10711284Sandreas.hansson@arm.com} 10811284Sandreas.hansson@arm.com 10911284Sandreas.hansson@arm.comvoid 11011051Sandreas.hansson@arm.comCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 11111051Sandreas.hansson@arm.com{ 11211051Sandreas.hansson@arm.com assert(pkt->isRequest()); 11311284Sandreas.hansson@arm.com 11411284Sandreas.hansson@arm.com uint64_t overwrite_val; 11511284Sandreas.hansson@arm.com bool overwrite_mem; 11611284Sandreas.hansson@arm.com uint64_t condition_val64; 11711051Sandreas.hansson@arm.com uint32_t condition_val32; 11811051Sandreas.hansson@arm.com 11911051Sandreas.hansson@arm.com int offset = tags->extractBlkOffset(pkt->getAddr()); 12011284Sandreas.hansson@arm.com uint8_t *blk_data = blk->data + offset; 12111284Sandreas.hansson@arm.com 12211284Sandreas.hansson@arm.com assert(sizeof(uint64_t) >= pkt->getSize()); 12311197Sandreas.hansson@arm.com 12411601Sandreas.hansson@arm.com overwrite_mem = true; 12511601Sandreas.hansson@arm.com // keep a copy of our possible write value, and copy what is at the 12611601Sandreas.hansson@arm.com // memory address into the packet 12711601Sandreas.hansson@arm.com pkt->writeData((uint8_t *)&overwrite_val); 12811601Sandreas.hansson@arm.com pkt->setData(blk_data); 12911601Sandreas.hansson@arm.com 13011601Sandreas.hansson@arm.com if (pkt->req->isCondSwap()) { 13111601Sandreas.hansson@arm.com if (pkt->getSize() == sizeof(uint64_t)) { 13211197Sandreas.hansson@arm.com condition_val64 = pkt->req->getExtraData(); 13311601Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val64, blk_data, 13411601Sandreas.hansson@arm.com sizeof(uint64_t)); 13511601Sandreas.hansson@arm.com } else if (pkt->getSize() == sizeof(uint32_t)) { 13611601Sandreas.hansson@arm.com condition_val32 = (uint32_t)pkt->req->getExtraData(); 13711601Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val32, blk_data, 13811601Sandreas.hansson@arm.com sizeof(uint32_t)); 13911601Sandreas.hansson@arm.com } else 14011051Sandreas.hansson@arm.com panic("Invalid size for conditional read/write\n"); 14111051Sandreas.hansson@arm.com } 14211051Sandreas.hansson@arm.com 14311051Sandreas.hansson@arm.com if (overwrite_mem) { 14411051Sandreas.hansson@arm.com std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 14511284Sandreas.hansson@arm.com blk->status |= BlkDirty; 14611284Sandreas.hansson@arm.com } 14711051Sandreas.hansson@arm.com} 14811051Sandreas.hansson@arm.com 14911051Sandreas.hansson@arm.com 15011051Sandreas.hansson@arm.comvoid 15111284Sandreas.hansson@arm.comCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, 15211051Sandreas.hansson@arm.com bool deferred_response, bool pending_downgrade) 15311051Sandreas.hansson@arm.com{ 15411051Sandreas.hansson@arm.com assert(pkt->isRequest()); 15511051Sandreas.hansson@arm.com 15611051Sandreas.hansson@arm.com assert(blk && blk->isValid()); 15711051Sandreas.hansson@arm.com // Occasionally this is not true... if we are a lower-level cache 15811051Sandreas.hansson@arm.com // satisfying a string of Read and ReadEx requests from 15911051Sandreas.hansson@arm.com // upper-level caches, a Read will mark the block as shared but we 16011051Sandreas.hansson@arm.com // can satisfy a following ReadEx anyway since we can rely on the 16111051Sandreas.hansson@arm.com // Read requester(s) to have buffered the ReadEx snoop and to 16211051Sandreas.hansson@arm.com // invalidate their blocks after receiving them. 16311051Sandreas.hansson@arm.com // assert(!pkt->needsWritable() || blk->isWritable()); 16411051Sandreas.hansson@arm.com assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 16511051Sandreas.hansson@arm.com 16611051Sandreas.hansson@arm.com // Check RMW operations first since both isRead() and 16711051Sandreas.hansson@arm.com // isWrite() will be true for them 16811051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::SwapReq) { 16912724Snikos.nikoleris@arm.com cmpAndSwap(blk, pkt); 17012724Snikos.nikoleris@arm.com } else if (pkt->isWrite()) { 17112724Snikos.nikoleris@arm.com // we have the block in a writable state and can go ahead, 17212724Snikos.nikoleris@arm.com // note that the line may be also be considered writable in 17312724Snikos.nikoleris@arm.com // downstream caches along the path to memory, but always 17412724Snikos.nikoleris@arm.com // Exclusive, and never Modified 17512724Snikos.nikoleris@arm.com assert(blk->isWritable()); 17611051Sandreas.hansson@arm.com // Write or WriteLine at the first cache with block in writable state 17711051Sandreas.hansson@arm.com if (blk->checkWrite(pkt)) { 17811051Sandreas.hansson@arm.com pkt->writeDataToBlock(blk->data, blkSize); 17911051Sandreas.hansson@arm.com } 18012723Snikos.nikoleris@arm.com // Always mark the line as dirty (and thus transition to the 18111051Sandreas.hansson@arm.com // Modified state) even if we are a failed StoreCond so we 18211051Sandreas.hansson@arm.com // supply data to any snoops that have appended themselves to 18311484Snikos.nikoleris@arm.com // this cache before knowing the store will fail. 18411051Sandreas.hansson@arm.com blk->status |= BlkDirty; 18511051Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s for %s (write)\n", __func__, pkt->print()); 18611051Sandreas.hansson@arm.com } else if (pkt->isRead()) { 18711051Sandreas.hansson@arm.com if (pkt->isLLSC()) { 18811051Sandreas.hansson@arm.com blk->trackLoadLocked(pkt); 18912724Snikos.nikoleris@arm.com } 19011601Sandreas.hansson@arm.com 19111601Sandreas.hansson@arm.com // all read responses have a data payload 19211601Sandreas.hansson@arm.com assert(pkt->hasRespData()); 19311051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 19411051Sandreas.hansson@arm.com 19511051Sandreas.hansson@arm.com // determine if this read is from a (coherent) cache or not 19611051Sandreas.hansson@arm.com if (pkt->fromCache()) { 19711051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 19812345Snikos.nikoleris@arm.com // special handling for coherent block requests from 19912345Snikos.nikoleris@arm.com // upper-level caches 20012345Snikos.nikoleris@arm.com if (pkt->needsWritable()) { 20112345Snikos.nikoleris@arm.com // sanity check 20211051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::ReadExReq || 20311051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq); 20411051Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 20511051Sandreas.hansson@arm.com 20611051Sandreas.hansson@arm.com // if we have a dirty copy, make sure the recipient 20711051Sandreas.hansson@arm.com // keeps it marked dirty (in the modified state) 20811051Sandreas.hansson@arm.com if (blk->isDirty()) { 20911199Sandreas.hansson@arm.com pkt->setCacheResponding(); 21011199Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 21111199Sandreas.hansson@arm.com } 21211199Sandreas.hansson@arm.com } else if (blk->isWritable() && !pending_downgrade && 21311199Sandreas.hansson@arm.com !pkt->hasSharers() && 21411051Sandreas.hansson@arm.com pkt->cmd != MemCmd::ReadCleanReq) { 21512345Snikos.nikoleris@arm.com // we can give the requester a writable copy on a read 21612345Snikos.nikoleris@arm.com // request if: 21711051Sandreas.hansson@arm.com // - we have a writable copy at this level (& below) 21811051Sandreas.hansson@arm.com // - we don't have a pending snoop from below 21911051Sandreas.hansson@arm.com // signaling another read request 22011051Sandreas.hansson@arm.com // - no other cache above has a copy (otherwise it 22111051Sandreas.hansson@arm.com // would have set hasSharers flag when 22211051Sandreas.hansson@arm.com // snooping the packet) 22311051Sandreas.hansson@arm.com // - the read has explicitly asked for a clean 22411051Sandreas.hansson@arm.com // copy of the line 22511051Sandreas.hansson@arm.com if (blk->isDirty()) { 22611051Sandreas.hansson@arm.com // special considerations if we're owner: 22711051Sandreas.hansson@arm.com if (!deferred_response) { 22811051Sandreas.hansson@arm.com // respond with the line in Modified state 22911051Sandreas.hansson@arm.com // (cacheResponding set, hasSharers not set) 23011051Sandreas.hansson@arm.com pkt->setCacheResponding(); 23111051Sandreas.hansson@arm.com 23211051Sandreas.hansson@arm.com // if this cache is mostly inclusive, we 23311051Sandreas.hansson@arm.com // keep the block in the Exclusive state, 23411130Sali.jafri@arm.com // and pass it upwards as Modified 23511130Sali.jafri@arm.com // (writable and dirty), hence we have 23611130Sali.jafri@arm.com // multiple caches, all on the same path 23711130Sali.jafri@arm.com // towards memory, all considering the 23811130Sali.jafri@arm.com // same block writable, but only one 23911130Sali.jafri@arm.com // considering it Modified 24011130Sali.jafri@arm.com 24111130Sali.jafri@arm.com // we get away with multiple caches (on 24211130Sali.jafri@arm.com // the same path to memory) considering 24312345Snikos.nikoleris@arm.com // the block writeable as we always enter 24412345Snikos.nikoleris@arm.com // the cache hierarchy through a cache, 24511130Sali.jafri@arm.com // and first snoop upwards in all other 24611130Sali.jafri@arm.com // branches 24711130Sali.jafri@arm.com blk->status &= ~BlkDirty; 24811130Sali.jafri@arm.com } else { 24911130Sali.jafri@arm.com // if we're responding after our own miss, 25011130Sali.jafri@arm.com // there's a window where the recipient didn't 25112724Snikos.nikoleris@arm.com // know it was getting ownership and may not 25211130Sali.jafri@arm.com // have responded to snoops correctly, so we 25311130Sali.jafri@arm.com // have to respond with a shared line 25411130Sali.jafri@arm.com pkt->setHasSharers(); 25511130Sali.jafri@arm.com } 25611130Sali.jafri@arm.com } 25711130Sali.jafri@arm.com } else { 25812724Snikos.nikoleris@arm.com // otherwise only respond with a shared copy 25911130Sali.jafri@arm.com pkt->setHasSharers(); 26011130Sali.jafri@arm.com } 26111130Sali.jafri@arm.com } 26211130Sali.jafri@arm.com } else if (pkt->isUpgrade()) { 26311130Sali.jafri@arm.com // sanity check 26411130Sali.jafri@arm.com assert(!pkt->hasSharers()); 26511130Sali.jafri@arm.com 26611130Sali.jafri@arm.com if (blk->isDirty()) { 26711130Sali.jafri@arm.com // we were in the Owned state, and a cache above us that 26811051Sandreas.hansson@arm.com // has the line in Shared state needs to be made aware 26911051Sandreas.hansson@arm.com // that the data it already has is in fact dirty 27011051Sandreas.hansson@arm.com pkt->setCacheResponding(); 27111051Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 27211744Snikos.nikoleris@arm.com } 27311051Sandreas.hansson@arm.com } else { 27411276Sandreas.hansson@arm.com assert(pkt->isInvalidate()); 27511276Sandreas.hansson@arm.com invalidateBlock(blk); 27611276Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s for %s (invalidation)\n", __func__, 27711276Sandreas.hansson@arm.com pkt->print()); 27811276Sandreas.hansson@arm.com } 27911276Sandreas.hansson@arm.com} 28011276Sandreas.hansson@arm.com 28111276Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28211276Sandreas.hansson@arm.com// 28311051Sandreas.hansson@arm.com// Access path: requests coming in from the CPU side 28411276Sandreas.hansson@arm.com// 28511276Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28611276Sandreas.hansson@arm.com 28711276Sandreas.hansson@arm.combool 28811276Sandreas.hansson@arm.comCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 28911051Sandreas.hansson@arm.com PacketList &writebacks) 29011051Sandreas.hansson@arm.com{ 29111051Sandreas.hansson@arm.com // sanity check 29211051Sandreas.hansson@arm.com assert(pkt->isRequest()); 29311051Sandreas.hansson@arm.com 29411051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 29511051Sandreas.hansson@arm.com "Should never see a write in a read-only cache %s\n", 29611051Sandreas.hansson@arm.com name()); 29711051Sandreas.hansson@arm.com 29811051Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s for %s\n", __func__, pkt->print()); 29911051Sandreas.hansson@arm.com 30012724Snikos.nikoleris@arm.com if (pkt->req->isUncacheable()) { 30111051Sandreas.hansson@arm.com DPRINTF(Cache, "uncacheable: %s\n", pkt->print()); 30211051Sandreas.hansson@arm.com 30311051Sandreas.hansson@arm.com // flush and invalidate any existing block 30411051Sandreas.hansson@arm.com CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure())); 30511051Sandreas.hansson@arm.com if (old_blk && old_blk->isValid()) { 30611051Sandreas.hansson@arm.com if (old_blk->isDirty() || writebackClean) 30711051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(old_blk)); 30811051Sandreas.hansson@arm.com else 30911051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(old_blk)); 31011051Sandreas.hansson@arm.com invalidateBlock(old_blk); 31111051Sandreas.hansson@arm.com } 31211051Sandreas.hansson@arm.com 31311051Sandreas.hansson@arm.com blk = nullptr; 31412630Snikos.nikoleris@arm.com // lookupLatency is the latency in case the request is uncacheable. 31512720Snikos.nikoleris@arm.com lat = lookupLatency; 31612720Snikos.nikoleris@arm.com return false; 31712720Snikos.nikoleris@arm.com } 31812720Snikos.nikoleris@arm.com 31912720Snikos.nikoleris@arm.com // Here lat is the value passed as parameter to accessBlock() function 32012720Snikos.nikoleris@arm.com // that can modify its value. 32112720Snikos.nikoleris@arm.com blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat); 32212724Snikos.nikoleris@arm.com 32312720Snikos.nikoleris@arm.com DPRINTF(Cache, "%s %s\n", pkt->print(), 32412720Snikos.nikoleris@arm.com blk ? "hit " + blk->print() : "miss"); 32512720Snikos.nikoleris@arm.com 32612720Snikos.nikoleris@arm.com if (pkt->req->isCacheMaintenance()) { 32712720Snikos.nikoleris@arm.com // A cache maintenance operation is always forwarded to the 32812720Snikos.nikoleris@arm.com // memory below even if the block is found in dirty state. 32912724Snikos.nikoleris@arm.com 33012724Snikos.nikoleris@arm.com // We defer any changes to the state of the block until we 33112724Snikos.nikoleris@arm.com // create and mark as in service the mshr for the downstream 33212724Snikos.nikoleris@arm.com // packet. 33312724Snikos.nikoleris@arm.com return false; 33412724Snikos.nikoleris@arm.com } 33512724Snikos.nikoleris@arm.com 33612724Snikos.nikoleris@arm.com if (pkt->isEviction()) { 33712724Snikos.nikoleris@arm.com // We check for presence of block in above caches before issuing 33812724Snikos.nikoleris@arm.com // Writeback or CleanEvict to write buffer. Therefore the only 33912724Snikos.nikoleris@arm.com // possible cases can be of a CleanEvict packet coming from above 34012724Snikos.nikoleris@arm.com // encountering a Writeback generated in this cache peer cache and 34112724Snikos.nikoleris@arm.com // waiting in the write buffer. Cases of upper level peer caches 34212724Snikos.nikoleris@arm.com // generating CleanEvict and Writeback or simply CleanEvict and 34312724Snikos.nikoleris@arm.com // CleanEvict almost simultaneously will be caught by snoops sent out 34412724Snikos.nikoleris@arm.com // by crossbar. 34512724Snikos.nikoleris@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(), 34612724Snikos.nikoleris@arm.com pkt->isSecure()); 34712724Snikos.nikoleris@arm.com if (wb_entry) { 34812724Snikos.nikoleris@arm.com assert(wb_entry->getNumTargets() == 1); 34912724Snikos.nikoleris@arm.com PacketPtr wbPkt = wb_entry->getTarget()->pkt; 35012724Snikos.nikoleris@arm.com assert(wbPkt->isWriteback()); 35112724Snikos.nikoleris@arm.com 35212724Snikos.nikoleris@arm.com if (pkt->isCleanEviction()) { 35312724Snikos.nikoleris@arm.com // The CleanEvict and WritebackClean snoops into other 35412720Snikos.nikoleris@arm.com // peer caches of the same level while traversing the 35512720Snikos.nikoleris@arm.com // crossbar. If a copy of the block is found, the 35612724Snikos.nikoleris@arm.com // packet is deleted in the crossbar. Hence, none of 35712720Snikos.nikoleris@arm.com // the other upper level caches connected to this 35812720Snikos.nikoleris@arm.com // cache have the block, so we can clear the 35912720Snikos.nikoleris@arm.com // BLOCK_CACHED flag in the Writeback if set and 36012720Snikos.nikoleris@arm.com // discard the CleanEvict by returning true. 36112720Snikos.nikoleris@arm.com wbPkt->clearBlockCached(); 36212720Snikos.nikoleris@arm.com return true; 36312720Snikos.nikoleris@arm.com } else { 36412720Snikos.nikoleris@arm.com assert(pkt->cmd == MemCmd::WritebackDirty); 36512720Snikos.nikoleris@arm.com // Dirty writeback from above trumps our clean 36612720Snikos.nikoleris@arm.com // writeback... discard here 36712720Snikos.nikoleris@arm.com // Note: markInService will remove entry from writeback buffer. 36812720Snikos.nikoleris@arm.com markInService(wb_entry); 36912720Snikos.nikoleris@arm.com delete wbPkt; 37012720Snikos.nikoleris@arm.com } 37112720Snikos.nikoleris@arm.com } 37212720Snikos.nikoleris@arm.com } 37312720Snikos.nikoleris@arm.com 37412720Snikos.nikoleris@arm.com // Writeback handling is special case. We can write the block into 37512720Snikos.nikoleris@arm.com // the cache without having a writeable copy (or any copy at all). 37612720Snikos.nikoleris@arm.com if (pkt->isWriteback()) { 37712720Snikos.nikoleris@arm.com assert(blkSize == pkt->getSize()); 37812720Snikos.nikoleris@arm.com 37912720Snikos.nikoleris@arm.com // we could get a clean writeback while we are having 38012749Sgiacomo.travaglini@arm.com // outstanding accesses to a block, do the simple thing for 38112749Sgiacomo.travaglini@arm.com // now and drop the clean writeback so that we do not upset 38212749Sgiacomo.travaglini@arm.com // any ordering/decisions about ownership already taken 38312749Sgiacomo.travaglini@arm.com if (pkt->cmd == MemCmd::WritebackClean && 38412720Snikos.nikoleris@arm.com mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) { 38512720Snikos.nikoleris@arm.com DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, " 38612720Snikos.nikoleris@arm.com "dropping\n", pkt->getAddr()); 38712720Snikos.nikoleris@arm.com return true; 38812720Snikos.nikoleris@arm.com } 38912720Snikos.nikoleris@arm.com 39012720Snikos.nikoleris@arm.com if (blk == nullptr) { 39112720Snikos.nikoleris@arm.com // need to do a replacement 39212720Snikos.nikoleris@arm.com blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks); 39312720Snikos.nikoleris@arm.com if (blk == nullptr) { 39412724Snikos.nikoleris@arm.com // no replaceable block available: give up, fwd to next level. 39512720Snikos.nikoleris@arm.com incMissCount(pkt); 39612720Snikos.nikoleris@arm.com return false; 39712720Snikos.nikoleris@arm.com } 39812720Snikos.nikoleris@arm.com tags->insertBlock(pkt, blk); 39912720Snikos.nikoleris@arm.com 40012720Snikos.nikoleris@arm.com blk->status = (BlkValid | BlkReadable); 40112724Snikos.nikoleris@arm.com if (pkt->isSecure()) { 40212720Snikos.nikoleris@arm.com blk->status |= BlkSecure; 40312720Snikos.nikoleris@arm.com } 40412720Snikos.nikoleris@arm.com } 40511051Sandreas.hansson@arm.com // only mark the block dirty if we got a writeback command, 40611051Sandreas.hansson@arm.com // and leave it as is for a clean writeback 40711830Sbaz21@cam.ac.uk if (pkt->cmd == MemCmd::WritebackDirty) { 40811051Sandreas.hansson@arm.com assert(!blk->isDirty()); 40911051Sandreas.hansson@arm.com blk->status |= BlkDirty; 41011051Sandreas.hansson@arm.com } 41111284Sandreas.hansson@arm.com // if the packet does not have sharers, it is passing 41211051Sandreas.hansson@arm.com // writable, and we got the writeback in Modified or Exclusive 41311284Sandreas.hansson@arm.com // state, if not we are in the Owned or Shared state 41411284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 41511744Snikos.nikoleris@arm.com blk->status |= BlkWritable; 41611744Snikos.nikoleris@arm.com } 41711051Sandreas.hansson@arm.com // nothing else to do; writeback doesn't expect response 41811284Sandreas.hansson@arm.com assert(!pkt->needsResponse()); 41911284Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 42011284Sandreas.hansson@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 42111284Sandreas.hansson@arm.com incHitCount(pkt); 42211284Sandreas.hansson@arm.com // populate the time when the block will be ready to access. 42311334Sandreas.hansson@arm.com blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay + 42411284Sandreas.hansson@arm.com pkt->payloadDelay; 42511334Sandreas.hansson@arm.com return true; 42611334Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::CleanEvict) { 42711334Sandreas.hansson@arm.com if (blk != nullptr) { 42811334Sandreas.hansson@arm.com // Found the block in the tags, need to stop CleanEvict from 42911284Sandreas.hansson@arm.com // propagating further down the hierarchy. Returning true will 43011334Sandreas.hansson@arm.com // treat the CleanEvict like a satisfied write request and delete 43111334Sandreas.hansson@arm.com // it. 43211334Sandreas.hansson@arm.com return true; 43311334Sandreas.hansson@arm.com } 43411334Sandreas.hansson@arm.com // We didn't find the block here, propagate the CleanEvict further 43511334Sandreas.hansson@arm.com // down the memory hierarchy. Returning false will treat the CleanEvict 43611051Sandreas.hansson@arm.com // like a Writeback which could not find a replaceable block so has to 43711334Sandreas.hansson@arm.com // go to next level. 43811334Sandreas.hansson@arm.com return false; 43911334Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::WriteClean) { 44011334Sandreas.hansson@arm.com // WriteClean handling is a special case. We can allocate a 44111051Sandreas.hansson@arm.com // block directly if it doesn't exist and we can update the 44211334Sandreas.hansson@arm.com // block immediately. The WriteClean transfers the ownership 44311334Sandreas.hansson@arm.com // of the block as well. 44411334Sandreas.hansson@arm.com assert(blkSize == pkt->getSize()); 44511051Sandreas.hansson@arm.com 44611334Sandreas.hansson@arm.com if (!blk) { 44711334Sandreas.hansson@arm.com if (pkt->writeThrough()) { 44811334Sandreas.hansson@arm.com // if this is a write through packet, we don't try to 44911334Sandreas.hansson@arm.com // allocate if the block is not present 45011334Sandreas.hansson@arm.com return false; 45111334Sandreas.hansson@arm.com } else { 45211334Sandreas.hansson@arm.com // a writeback that misses needs to allocate a new block 45311051Sandreas.hansson@arm.com blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), 45411334Sandreas.hansson@arm.com writebacks); 45511334Sandreas.hansson@arm.com if (!blk) { 45611334Sandreas.hansson@arm.com // no replaceable block available: give up, fwd to 45712724Snikos.nikoleris@arm.com // next level. 45811334Sandreas.hansson@arm.com incMissCount(pkt); 45911334Sandreas.hansson@arm.com return false; 46011334Sandreas.hansson@arm.com } 46111334Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 46211051Sandreas.hansson@arm.com 46311284Sandreas.hansson@arm.com blk->status = (BlkValid | BlkReadable); 46411284Sandreas.hansson@arm.com if (pkt->isSecure()) { 46511190Sandreas.hansson@arm.com blk->status |= BlkSecure; 46611051Sandreas.hansson@arm.com } 46711334Sandreas.hansson@arm.com } 46811334Sandreas.hansson@arm.com } 46911334Sandreas.hansson@arm.com 47011334Sandreas.hansson@arm.com // at this point either this is a writeback or a write-through 47111334Sandreas.hansson@arm.com // write clean operation and the block is already in this 47212630Snikos.nikoleris@arm.com // cache, we need to update the data and the block flags 47311051Sandreas.hansson@arm.com assert(blk); 47411051Sandreas.hansson@arm.com assert(!blk->isDirty()); 47512724Snikos.nikoleris@arm.com if (!pkt->writeThrough()) { 47611051Sandreas.hansson@arm.com blk->status |= BlkDirty; 47711051Sandreas.hansson@arm.com } 47811051Sandreas.hansson@arm.com // nothing else to do; writeback doesn't expect response 47911452Sandreas.hansson@arm.com assert(!pkt->needsResponse()); 48011452Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 48111051Sandreas.hansson@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 48211452Sandreas.hansson@arm.com 48311452Sandreas.hansson@arm.com incHitCount(pkt); 48411452Sandreas.hansson@arm.com // populate the time when the block will be ready to access. 48511051Sandreas.hansson@arm.com blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay + 48611051Sandreas.hansson@arm.com pkt->payloadDelay; 48711452Sandreas.hansson@arm.com // if this a write-through packet it will be sent to cache 48811745Sandreas.hansson@arm.com // below 48912349Snikos.nikoleris@arm.com return !pkt->writeThrough(); 49011452Sandreas.hansson@arm.com } else if (blk && (pkt->needsWritable() ? blk->isWritable() : 49111452Sandreas.hansson@arm.com blk->isReadable())) { 49211452Sandreas.hansson@arm.com // OK to satisfy access 49311051Sandreas.hansson@arm.com incHitCount(pkt); 49411051Sandreas.hansson@arm.com satisfyRequest(pkt, blk); 49511051Sandreas.hansson@arm.com maintainClusivity(pkt->fromCache(), blk); 49611051Sandreas.hansson@arm.com 49711051Sandreas.hansson@arm.com return true; 49811051Sandreas.hansson@arm.com } 49911051Sandreas.hansson@arm.com 50011051Sandreas.hansson@arm.com // Can't satisfy access normally... either no block (blk == nullptr) 50111051Sandreas.hansson@arm.com // or have block but need writable 50211051Sandreas.hansson@arm.com 50311747Snikos.nikoleris@arm.com incMissCount(pkt); 50411747Snikos.nikoleris@arm.com 50511747Snikos.nikoleris@arm.com if (blk == nullptr && pkt->isLLSC() && pkt->isWrite()) { 50611747Snikos.nikoleris@arm.com // complete miss on store conditional... just give up now 50711747Snikos.nikoleris@arm.com pkt->req->setExtraData(0); 50811747Snikos.nikoleris@arm.com return true; 50911747Snikos.nikoleris@arm.com } 51011284Sandreas.hansson@arm.com 51111284Sandreas.hansson@arm.com return false; 51211284Sandreas.hansson@arm.com} 51311051Sandreas.hansson@arm.com 51411051Sandreas.hansson@arm.comvoid 51511051Sandreas.hansson@arm.comCache::maintainClusivity(bool from_cache, CacheBlk *blk) 51611051Sandreas.hansson@arm.com{ 51711051Sandreas.hansson@arm.com if (from_cache && blk && blk->isValid() && !blk->isDirty() && 51811051Sandreas.hansson@arm.com clusivity == Enums::mostly_excl) { 51911051Sandreas.hansson@arm.com // if we have responded to a cache, and our block is still 52011051Sandreas.hansson@arm.com // valid, but not dirty, and this cache is mostly exclusive 52111051Sandreas.hansson@arm.com // with respect to the cache above, drop the block 52211051Sandreas.hansson@arm.com invalidateBlock(blk); 52311051Sandreas.hansson@arm.com } 52412425Snikos.nikoleris@arm.com} 52512425Snikos.nikoleris@arm.com 52612425Snikos.nikoleris@arm.comvoid 52712425Snikos.nikoleris@arm.comCache::doWritebacks(PacketList& writebacks, Tick forward_time) 52812425Snikos.nikoleris@arm.com{ 52912425Snikos.nikoleris@arm.com while (!writebacks.empty()) { 53012425Snikos.nikoleris@arm.com PacketPtr wbPkt = writebacks.front(); 53112425Snikos.nikoleris@arm.com // We use forwardLatency here because we are copying writebacks to 53212425Snikos.nikoleris@arm.com // write buffer. 53312425Snikos.nikoleris@arm.com 53411284Sandreas.hansson@arm.com // Call isCachedAbove for Writebacks, CleanEvicts and 53512425Snikos.nikoleris@arm.com // WriteCleans to discover if the block is cached above. 53611051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) { 53711051Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::CleanEvict) { 53811051Sandreas.hansson@arm.com // Delete CleanEvict because cached copies exist above. The 53911284Sandreas.hansson@arm.com // packet destructor will delete the request object because 54011284Sandreas.hansson@arm.com // this is a non-snoop request packet which does not require a 54111284Sandreas.hansson@arm.com // response. 54211602Sandreas.hansson@arm.com delete wbPkt; 54311051Sandreas.hansson@arm.com } else if (wbPkt->cmd == MemCmd::WritebackClean) { 54411051Sandreas.hansson@arm.com // clean writeback, do not send since the block is 54511051Sandreas.hansson@arm.com // still cached above 54611284Sandreas.hansson@arm.com assert(writebackClean); 54711284Sandreas.hansson@arm.com delete wbPkt; 54811744Snikos.nikoleris@arm.com } else { 54911744Snikos.nikoleris@arm.com assert(wbPkt->cmd == MemCmd::WritebackDirty || 55011051Sandreas.hansson@arm.com wbPkt->cmd == MemCmd::WriteClean); 55111051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag in Writeback and send below, so that 55211051Sandreas.hansson@arm.com // the Writeback does not reset the bit corresponding to this 55311892Snikos.nikoleris@arm.com // address in the snoop filter below. 55411051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 55511051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 55611744Snikos.nikoleris@arm.com } 55711744Snikos.nikoleris@arm.com } else { 55811051Sandreas.hansson@arm.com // If the block is not cached above, send packet below. Both 55911051Sandreas.hansson@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 56011051Sandreas.hansson@arm.com // reset the bit corresponding to this address in the snoop filter 56111051Sandreas.hansson@arm.com // below. 56212721Snikos.nikoleris@arm.com allocateWriteBuffer(wbPkt, forward_time); 56312721Snikos.nikoleris@arm.com } 56412721Snikos.nikoleris@arm.com writebacks.pop_front(); 56512721Snikos.nikoleris@arm.com } 56612721Snikos.nikoleris@arm.com} 56712721Snikos.nikoleris@arm.com 56812721Snikos.nikoleris@arm.comvoid 56912721Snikos.nikoleris@arm.comCache::doWritebacksAtomic(PacketList& writebacks) 57012724Snikos.nikoleris@arm.com{ 57112721Snikos.nikoleris@arm.com while (!writebacks.empty()) { 57212721Snikos.nikoleris@arm.com PacketPtr wbPkt = writebacks.front(); 57312721Snikos.nikoleris@arm.com // Call isCachedAbove for both Writebacks and CleanEvicts. If 57412721Snikos.nikoleris@arm.com // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks 57512721Snikos.nikoleris@arm.com // and discard CleanEvicts. 57612721Snikos.nikoleris@arm.com if (isCachedAbove(wbPkt, false)) { 57712721Snikos.nikoleris@arm.com if (wbPkt->cmd == MemCmd::WritebackDirty || 57812721Snikos.nikoleris@arm.com wbPkt->cmd == MemCmd::WriteClean) { 57912721Snikos.nikoleris@arm.com // Set BLOCK_CACHED flag in Writeback and send below, 58012721Snikos.nikoleris@arm.com // so that the Writeback does not reset the bit 58112721Snikos.nikoleris@arm.com // corresponding to this address in the snoop filter 58212721Snikos.nikoleris@arm.com // below. We can discard CleanEvicts because cached 58312721Snikos.nikoleris@arm.com // copies exist above. Atomic mode isCachedAbove 58412721Snikos.nikoleris@arm.com // modifies packet to set BLOCK_CACHED flag 58512721Snikos.nikoleris@arm.com memSidePort->sendAtomic(wbPkt); 58612721Snikos.nikoleris@arm.com } 58712721Snikos.nikoleris@arm.com } else { 58812721Snikos.nikoleris@arm.com // If the block is not cached above, send packet below. Both 58912721Snikos.nikoleris@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 59012721Snikos.nikoleris@arm.com // reset the bit corresponding to this address in the snoop filter 59112721Snikos.nikoleris@arm.com // below. 59212721Snikos.nikoleris@arm.com memSidePort->sendAtomic(wbPkt); 59312721Snikos.nikoleris@arm.com } 59412721Snikos.nikoleris@arm.com writebacks.pop_front(); 59512721Snikos.nikoleris@arm.com // In case of CleanEvicts, the packet destructor will delete the 59612721Snikos.nikoleris@arm.com // request object because this is a non-snoop request packet which 59712721Snikos.nikoleris@arm.com // does not require a response. 59812721Snikos.nikoleris@arm.com delete wbPkt; 59912721Snikos.nikoleris@arm.com } 60012724Snikos.nikoleris@arm.com} 60112721Snikos.nikoleris@arm.com 60212721Snikos.nikoleris@arm.com 60312721Snikos.nikoleris@arm.comvoid 60412721Snikos.nikoleris@arm.comCache::recvTimingSnoopResp(PacketPtr pkt) 60512721Snikos.nikoleris@arm.com{ 60612721Snikos.nikoleris@arm.com DPRINTF(Cache, "%s for %s\n", __func__, pkt->print()); 60712721Snikos.nikoleris@arm.com 60812721Snikos.nikoleris@arm.com assert(pkt->isResponse()); 60912721Snikos.nikoleris@arm.com assert(!system->bypassCaches()); 61012721Snikos.nikoleris@arm.com 61112721Snikos.nikoleris@arm.com // determine if the response is from a snoop request we created 61212721Snikos.nikoleris@arm.com // (in which case it should be in the outstandingSnoop), or if we 61312721Snikos.nikoleris@arm.com // merely forwarded someone else's snoop request 61412721Snikos.nikoleris@arm.com const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) == 61512721Snikos.nikoleris@arm.com outstandingSnoop.end(); 61612721Snikos.nikoleris@arm.com 61712721Snikos.nikoleris@arm.com if (!forwardAsSnoop) { 61812721Snikos.nikoleris@arm.com // the packet came from this cache, so sink it here and do not 61912721Snikos.nikoleris@arm.com // forward it 62012721Snikos.nikoleris@arm.com assert(pkt->cmd == MemCmd::HardPFResp); 62112721Snikos.nikoleris@arm.com 62212721Snikos.nikoleris@arm.com outstandingSnoop.erase(pkt->req); 62312721Snikos.nikoleris@arm.com 62412721Snikos.nikoleris@arm.com DPRINTF(Cache, "Got prefetch response from above for addr " 62512721Snikos.nikoleris@arm.com "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 62612721Snikos.nikoleris@arm.com recvTimingResp(pkt); 62712721Snikos.nikoleris@arm.com return; 62812721Snikos.nikoleris@arm.com } 62912721Snikos.nikoleris@arm.com 63012721Snikos.nikoleris@arm.com // forwardLatency is set here because there is a response from an 63112721Snikos.nikoleris@arm.com // upper level cache. 63212721Snikos.nikoleris@arm.com // To pay the delay that occurs if the packet comes from the bus, 63312721Snikos.nikoleris@arm.com // we charge also headerDelay. 63412721Snikos.nikoleris@arm.com Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay; 63512721Snikos.nikoleris@arm.com // Reset the timing of the packet. 63612721Snikos.nikoleris@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 63712721Snikos.nikoleris@arm.com memSidePort->schedTimingSnoopResp(pkt, snoop_resp_time); 63812721Snikos.nikoleris@arm.com} 63912721Snikos.nikoleris@arm.com 64012721Snikos.nikoleris@arm.comvoid 64112721Snikos.nikoleris@arm.comCache::promoteWholeLineWrites(PacketPtr pkt) 64212721Snikos.nikoleris@arm.com{ 64312721Snikos.nikoleris@arm.com // Cache line clearing instructions 64412721Snikos.nikoleris@arm.com if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) && 64512721Snikos.nikoleris@arm.com (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) { 64612721Snikos.nikoleris@arm.com pkt->cmd = MemCmd::WriteLineReq; 64712721Snikos.nikoleris@arm.com DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n"); 64812721Snikos.nikoleris@arm.com } 64912721Snikos.nikoleris@arm.com} 65012721Snikos.nikoleris@arm.com 65112721Snikos.nikoleris@arm.combool 65211051Sandreas.hansson@arm.comCache::recvTimingReq(PacketPtr pkt) 65311051Sandreas.hansson@arm.com{ 65411051Sandreas.hansson@arm.com DPRINTF(CacheTags, "%s tags:\n%s\n", __func__, tags->print()); 65511051Sandreas.hansson@arm.com 65611051Sandreas.hansson@arm.com assert(pkt->isRequest()); 65712724Snikos.nikoleris@arm.com 65811051Sandreas.hansson@arm.com // Just forward the packet if caches are disabled. 65911051Sandreas.hansson@arm.com if (system->bypassCaches()) { 66011051Sandreas.hansson@arm.com // @todo This should really enqueue the packet rather 66111051Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt); 66211051Sandreas.hansson@arm.com assert(success); 66311051Sandreas.hansson@arm.com return true; 66411051Sandreas.hansson@arm.com } 66511051Sandreas.hansson@arm.com 66611051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 66711051Sandreas.hansson@arm.com 66811051Sandreas.hansson@arm.com // Cache maintenance operations have to visit all the caches down 66912719Snikos.nikoleris@arm.com // to the specified xbar (PoC, PoU, etc.). Even if a cache above 67012719Snikos.nikoleris@arm.com // is responding we forward the packet to the memory below rather 67111051Sandreas.hansson@arm.com // than creating an express snoop. 67211051Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 67312719Snikos.nikoleris@arm.com // a cache above us (but not where the packet came from) is 67412719Snikos.nikoleris@arm.com // responding to the request, in other words it has the line 67512719Snikos.nikoleris@arm.com // in Modified or Owned state 67612719Snikos.nikoleris@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 67711051Sandreas.hansson@arm.com pkt->print()); 67811051Sandreas.hansson@arm.com 67911136Sandreas.hansson@arm.com // if the packet needs the block to be writable, and the cache 68011051Sandreas.hansson@arm.com // that has promised to respond (setting the cache responding 68111742Snikos.nikoleris@arm.com // flag) is not providing writable (it is in Owned rather than 68211742Snikos.nikoleris@arm.com // the Modified state), we know that there may be other Shared 68311742Snikos.nikoleris@arm.com // copies in the system; go out and invalidate them all 68411742Snikos.nikoleris@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 68511051Sandreas.hansson@arm.com 68611051Sandreas.hansson@arm.com // an upstream cache that had the line in Owned state 68711051Sandreas.hansson@arm.com // (dirty, but not writable), is responding and thus 68811051Sandreas.hansson@arm.com // transferring the dirty line from one branch of the 68911051Sandreas.hansson@arm.com // cache hierarchy to another 69011051Sandreas.hansson@arm.com 69111051Sandreas.hansson@arm.com // send out an express snoop and invalidate all other 69211051Sandreas.hansson@arm.com // copies (snooping a packet that needs writable is the 69311483Snikos.nikoleris@arm.com // same as an invalidation), thus turning the Owned line 69411483Snikos.nikoleris@arm.com // into a Modified line, note that we don't invalidate the 69511483Snikos.nikoleris@arm.com // block in the current cache or any other cache on the 69611483Snikos.nikoleris@arm.com // path to memory 69711051Sandreas.hansson@arm.com 69811051Sandreas.hansson@arm.com // create a downstream express snoop with cleared packet 69911051Sandreas.hansson@arm.com // flags, there is no need to allocate any data as the 70011051Sandreas.hansson@arm.com // packet is merely used to co-ordinate state transitions 70111051Sandreas.hansson@arm.com Packet *snoop_pkt = new Packet(pkt, true, false); 70211051Sandreas.hansson@arm.com 70311051Sandreas.hansson@arm.com // also reset the bus time that the original packet has 70411051Sandreas.hansson@arm.com // not yet paid for 70511051Sandreas.hansson@arm.com snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0; 70611051Sandreas.hansson@arm.com 70711051Sandreas.hansson@arm.com // make this an instantaneous express snoop, and let the 70811051Sandreas.hansson@arm.com // other caches in the system know that the another cache 70911284Sandreas.hansson@arm.com // is responding, because we have found the authorative 71011284Sandreas.hansson@arm.com // copy (Modified or Owned) that will supply the right 71111284Sandreas.hansson@arm.com // data 71211051Sandreas.hansson@arm.com snoop_pkt->setExpressSnoop(); 71311741Snikos.nikoleris@arm.com snoop_pkt->setCacheResponding(); 71411742Snikos.nikoleris@arm.com 71512719Snikos.nikoleris@arm.com // this express snoop travels towards the memory, and at 71611051Sandreas.hansson@arm.com // every crossbar it is snooped upwards thus reaching 71712794Snikos.nikoleris@arm.com // every cache in the system 71811136Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(snoop_pkt); 71911051Sandreas.hansson@arm.com // express snoops always succeed 72011051Sandreas.hansson@arm.com assert(success); 72112794Snikos.nikoleris@arm.com 72211601Sandreas.hansson@arm.com // main memory will delete the snoop packet 72311051Sandreas.hansson@arm.com 72411051Sandreas.hansson@arm.com // queue for deletion, as opposed to immediate deletion, as 72511051Sandreas.hansson@arm.com // the sending cache is still relying on the packet 72611051Sandreas.hansson@arm.com pendingDelete.reset(pkt); 72711051Sandreas.hansson@arm.com 72811051Sandreas.hansson@arm.com // no need to take any further action in this particular cache 72911051Sandreas.hansson@arm.com // as an upstram cache has already committed to responding, 73011051Sandreas.hansson@arm.com // and we have already sent out any express snoops in the 73111051Sandreas.hansson@arm.com // section above to ensure all other copies in the system are 73211051Sandreas.hansson@arm.com // invalidated 73311051Sandreas.hansson@arm.com return true; 73411051Sandreas.hansson@arm.com } 73511051Sandreas.hansson@arm.com 73611051Sandreas.hansson@arm.com // anything that is merely forwarded pays for the forward latency and 73711051Sandreas.hansson@arm.com // the delay provided by the crossbar 73811051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 73911051Sandreas.hansson@arm.com 74011051Sandreas.hansson@arm.com // We use lookupLatency here because it is used to specify the latency 74111051Sandreas.hansson@arm.com // to access. 74211742Snikos.nikoleris@arm.com Cycles lat = lookupLatency; 74311051Sandreas.hansson@arm.com CacheBlk *blk = nullptr; 74411051Sandreas.hansson@arm.com bool satisfied = false; 74511051Sandreas.hansson@arm.com { 74611051Sandreas.hansson@arm.com PacketList writebacks; 74711051Sandreas.hansson@arm.com // Note that lat is passed by reference here. The function 74811051Sandreas.hansson@arm.com // access() calls accessBlock() which can modify lat value. 74911051Sandreas.hansson@arm.com satisfied = access(pkt, blk, lat, writebacks); 75011051Sandreas.hansson@arm.com 75111051Sandreas.hansson@arm.com // copy writebacks to write buffer here to ensure they logically 75211051Sandreas.hansson@arm.com // proceed anything happening below 75311051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 75411051Sandreas.hansson@arm.com } 75511750Snikos.nikoleris@arm.com 75611750Snikos.nikoleris@arm.com // Here we charge the headerDelay that takes into account the latencies 75711750Snikos.nikoleris@arm.com // of the bus, if the packet comes from it. 75811750Snikos.nikoleris@arm.com // The latency charged it is just lat that is the value of lookupLatency 75911750Snikos.nikoleris@arm.com // modified by access() function, or if not just lookupLatency. 76011750Snikos.nikoleris@arm.com // In case of a hit we are neglecting response latency. 76111750Snikos.nikoleris@arm.com // In case of a miss we are neglecting forward latency. 76211750Snikos.nikoleris@arm.com Tick request_time = clockEdge(lat) + pkt->headerDelay; 76311750Snikos.nikoleris@arm.com // Here we reset the timing of the packet. 76411750Snikos.nikoleris@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 76511750Snikos.nikoleris@arm.com 76611051Sandreas.hansson@arm.com // track time of availability of next prefetch, if any 76711051Sandreas.hansson@arm.com Tick next_pf_time = MaxTick; 76811051Sandreas.hansson@arm.com 76911051Sandreas.hansson@arm.com bool needsResponse = pkt->needsResponse(); 77011051Sandreas.hansson@arm.com 77111051Sandreas.hansson@arm.com if (satisfied) { 77211051Sandreas.hansson@arm.com // should never be satisfying an uncacheable access as we 77311051Sandreas.hansson@arm.com // flush and invalidate any existing block as part of the 77411051Sandreas.hansson@arm.com // lookup 77511051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 77611051Sandreas.hansson@arm.com 77711051Sandreas.hansson@arm.com // hit (for all other request types) 77811051Sandreas.hansson@arm.com 77911051Sandreas.hansson@arm.com if (prefetcher && (prefetchOnAccess || 78011051Sandreas.hansson@arm.com (blk && blk->wasPrefetched()))) { 78111051Sandreas.hansson@arm.com if (blk) 78211051Sandreas.hansson@arm.com blk->status &= ~BlkHWPrefetched; 78311051Sandreas.hansson@arm.com 78411136Sandreas.hansson@arm.com // Don't notify on SWPrefetch 78511051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) { 78611051Sandreas.hansson@arm.com assert(!pkt->req->isCacheMaintenance()); 78711051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 78811051Sandreas.hansson@arm.com } 78911744Snikos.nikoleris@arm.com } 79011744Snikos.nikoleris@arm.com 79111051Sandreas.hansson@arm.com if (needsResponse) { 79211051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 79311051Sandreas.hansson@arm.com // @todo: Make someone pay for this 79412724Snikos.nikoleris@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 79511051Sandreas.hansson@arm.com 79611051Sandreas.hansson@arm.com // In this case we are considering request_time that takes 79711051Sandreas.hansson@arm.com // into account the delay of the xbar, if any, and just 79811051Sandreas.hansson@arm.com // lat, neglecting responseLatency, modelling hit latency 79911051Sandreas.hansson@arm.com // just as lookupLatency or or the value of lat overriden 80011051Sandreas.hansson@arm.com // by access(), that calls accessBlock() function. 80111051Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 80211051Sandreas.hansson@arm.com } else { 80311051Sandreas.hansson@arm.com DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__, 80411051Sandreas.hansson@arm.com pkt->print()); 80511051Sandreas.hansson@arm.com 80611051Sandreas.hansson@arm.com // queue the packet for deletion, as the sending cache is 80711051Sandreas.hansson@arm.com // still relying on it; if the block is found in access(), 80811051Sandreas.hansson@arm.com // CleanEvict and Writeback messages will be deleted 80911749Snikos.nikoleris@arm.com // here as well 81011749Snikos.nikoleris@arm.com pendingDelete.reset(pkt); 81112349Snikos.nikoleris@arm.com } 81212349Snikos.nikoleris@arm.com } else { 81312349Snikos.nikoleris@arm.com // miss 81411749Snikos.nikoleris@arm.com 81511749Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 81611749Snikos.nikoleris@arm.com 81711749Snikos.nikoleris@arm.com // ignore any existing MSHR if we are dealing with an 81812349Snikos.nikoleris@arm.com // uncacheable request 81912349Snikos.nikoleris@arm.com MSHR *mshr = pkt->req->isUncacheable() ? nullptr : 82012349Snikos.nikoleris@arm.com mshrQueue.findMatch(blk_addr, pkt->isSecure()); 82111051Sandreas.hansson@arm.com 82211051Sandreas.hansson@arm.com // Software prefetch handling: 82311051Sandreas.hansson@arm.com // To keep the core from waiting on data it won't look at 82411051Sandreas.hansson@arm.com // anyway, send back a response with dummy data. Miss handling 82511742Snikos.nikoleris@arm.com // will continue asynchronously. Unfortunately, the core will 82611051Sandreas.hansson@arm.com // insist upon freeing original Packet/Request, so we have to 82711051Sandreas.hansson@arm.com // create a new pair with a different lifecycle. Note that this 82811051Sandreas.hansson@arm.com // processing happens before any MSHR munging on the behalf of 82912715Snikos.nikoleris@arm.com // this request because this new Request will be the one stored 83011601Sandreas.hansson@arm.com // into the MSHRs, not the original. 83111051Sandreas.hansson@arm.com if (pkt->cmd.isSWPrefetch()) { 83211051Sandreas.hansson@arm.com assert(needsResponse); 83311051Sandreas.hansson@arm.com assert(pkt->req->hasPaddr()); 83411051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 83511136Sandreas.hansson@arm.com 83611197Sandreas.hansson@arm.com // There's no reason to add a prefetch as an additional target 83711051Sandreas.hansson@arm.com // to an existing MSHR. If an outstanding request is already 83811051Sandreas.hansson@arm.com // in progress, there is nothing for the prefetch to do. 83911051Sandreas.hansson@arm.com // If this is the case, we don't even create a request at all. 84011051Sandreas.hansson@arm.com PacketPtr pf = nullptr; 84112719Snikos.nikoleris@arm.com 84212719Snikos.nikoleris@arm.com if (!mshr) { 84311051Sandreas.hansson@arm.com // copy the request and create a new SoftPFReq packet 84412723Snikos.nikoleris@arm.com RequestPtr req = new Request(pkt->req->getPaddr(), 84512723Snikos.nikoleris@arm.com pkt->req->getSize(), 84612723Snikos.nikoleris@arm.com pkt->req->getFlags(), 84712723Snikos.nikoleris@arm.com pkt->req->masterId()); 84812723Snikos.nikoleris@arm.com pf = new Packet(req, pkt->cmd); 84912723Snikos.nikoleris@arm.com pf->allocate(); 85012723Snikos.nikoleris@arm.com assert(pf->getAddr() == pkt->getAddr()); 85112723Snikos.nikoleris@arm.com assert(pf->getSize() == pkt->getSize()); 85212723Snikos.nikoleris@arm.com } 85312723Snikos.nikoleris@arm.com 85412723Snikos.nikoleris@arm.com pkt->makeTimingResponse(); 85512723Snikos.nikoleris@arm.com 85612723Snikos.nikoleris@arm.com // request_time is used here, taking into account lat and the delay 85712723Snikos.nikoleris@arm.com // charged if the packet comes from the xbar. 85812723Snikos.nikoleris@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 85912723Snikos.nikoleris@arm.com 86012723Snikos.nikoleris@arm.com // If an outstanding request is in progress (we found an 86112723Snikos.nikoleris@arm.com // MSHR) this is set to null 86212723Snikos.nikoleris@arm.com pkt = pf; 86312723Snikos.nikoleris@arm.com } 86411051Sandreas.hansson@arm.com 86511051Sandreas.hansson@arm.com if (mshr) { 86611199Sandreas.hansson@arm.com /// MSHR hit 86711051Sandreas.hansson@arm.com /// @note writebacks will be checked in getNextMSHR() 86812749Sgiacomo.travaglini@arm.com /// for any conflicting requests to the same block 86911051Sandreas.hansson@arm.com 87012749Sgiacomo.travaglini@arm.com //@todo remove hw_pf here 87112749Sgiacomo.travaglini@arm.com 87212748Sgiacomo.travaglini@arm.com // Coalesce unless it was a software prefetch (see above). 87311051Sandreas.hansson@arm.com if (pkt) { 87411051Sandreas.hansson@arm.com assert(!pkt->isWriteback()); 87511051Sandreas.hansson@arm.com // CleanEvicts corresponding to blocks which have 87611051Sandreas.hansson@arm.com // outstanding requests in MSHRs are simply sunk here 87711051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::CleanEvict) { 87811051Sandreas.hansson@arm.com pendingDelete.reset(pkt); 87911051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::WriteClean) { 88011744Snikos.nikoleris@arm.com // A WriteClean should never coalesce with any 88111051Sandreas.hansson@arm.com // outstanding cache maintenance requests. 88211051Sandreas.hansson@arm.com 88311051Sandreas.hansson@arm.com // We use forward_time here because there is an 88411051Sandreas.hansson@arm.com // uncached memory write, forwarded to WriteBuffer. 88511051Sandreas.hansson@arm.com allocateWriteBuffer(pkt, forward_time); 88611051Sandreas.hansson@arm.com } else { 88711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s coalescing MSHR for %s\n", __func__, 88811051Sandreas.hansson@arm.com pkt->print()); 88911051Sandreas.hansson@arm.com 89011051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 89111051Sandreas.hansson@arm.com mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 89211051Sandreas.hansson@arm.com // We use forward_time here because it is the same 89311051Sandreas.hansson@arm.com // considering new targets. We have multiple 89411051Sandreas.hansson@arm.com // requests for the same address here. It 89511051Sandreas.hansson@arm.com // specifies the latency to allocate an internal 89611051Sandreas.hansson@arm.com // buffer and to schedule an event to the queued 89711051Sandreas.hansson@arm.com // port and also takes into account the additional 89811051Sandreas.hansson@arm.com // delay of the xbar. 89911744Snikos.nikoleris@arm.com mshr->allocateTarget(pkt, forward_time, order++, 90011051Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 90111051Sandreas.hansson@arm.com if (mshr->getNumTargets() == numTarget) { 90211051Sandreas.hansson@arm.com noTargetMSHR = mshr; 90311051Sandreas.hansson@arm.com setBlocked(Blocked_NoTargets); 90411051Sandreas.hansson@arm.com // need to be careful with this... if this mshr isn't 90511051Sandreas.hansson@arm.com // ready yet (i.e. time > curTick()), we don't want to 90611051Sandreas.hansson@arm.com // move it ahead of mshrs that are ready 90711051Sandreas.hansson@arm.com // mshrQueue.moveToFront(mshr); 90811051Sandreas.hansson@arm.com } 90911051Sandreas.hansson@arm.com } 91011284Sandreas.hansson@arm.com // We should call the prefetcher reguardless if the request is 91111051Sandreas.hansson@arm.com // satisfied or not, reguardless if the request is in the MSHR 91211051Sandreas.hansson@arm.com // or not. The request could be a ReadReq hit, but still not 91311051Sandreas.hansson@arm.com // satisfied (potentially because of a prior write to the same 91411051Sandreas.hansson@arm.com // cache line. So, even when not satisfied, tehre is an MSHR 91511051Sandreas.hansson@arm.com // already allocated for this, we need to let the prefetcher 91611051Sandreas.hansson@arm.com // know about the request 91711051Sandreas.hansson@arm.com if (prefetcher) { 91811284Sandreas.hansson@arm.com // Don't notify on SWPrefetch 91911284Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch() && 92011284Sandreas.hansson@arm.com !pkt->req->isCacheMaintenance()) 92111284Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 92211284Sandreas.hansson@arm.com } 92311051Sandreas.hansson@arm.com } 92411051Sandreas.hansson@arm.com } else { 92511051Sandreas.hansson@arm.com // no MSHR 92611051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 92711051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 92811051Sandreas.hansson@arm.com mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++; 92911051Sandreas.hansson@arm.com } else { 93011051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 93111744Snikos.nikoleris@arm.com } 93211744Snikos.nikoleris@arm.com 93312724Snikos.nikoleris@arm.com if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean || 93411051Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 93511051Sandreas.hansson@arm.com // We use forward_time here because there is an 93611127Sandreas.hansson@arm.com // uncached memory write, forwarded to WriteBuffer. 93711051Sandreas.hansson@arm.com allocateWriteBuffer(pkt, forward_time); 93811051Sandreas.hansson@arm.com } else { 93911051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 94011744Snikos.nikoleris@arm.com // should have flushed and have no valid block 94111051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 94211051Sandreas.hansson@arm.com 94311051Sandreas.hansson@arm.com // If we have a write miss to a valid block, we 94411051Sandreas.hansson@arm.com // need to mark the block non-readable. Otherwise 94511051Sandreas.hansson@arm.com // if we allow reads while there's an outstanding 94611051Sandreas.hansson@arm.com // write miss, the read could return stale data 94711051Sandreas.hansson@arm.com // out of the cache block... a more aggressive 94811051Sandreas.hansson@arm.com // system could detect the overlap (if any) and 94911051Sandreas.hansson@arm.com // forward data out of the MSHRs, but we don't do 95011051Sandreas.hansson@arm.com // that yet. Note that we do need to leave the 95111284Sandreas.hansson@arm.com // block valid so that it stays in the cache, in 95211051Sandreas.hansson@arm.com // case we get an upgrade response (and hence no 95311285Sandreas.hansson@arm.com // new data) when the write miss completes. 95411285Sandreas.hansson@arm.com // As long as CPUs do proper store/load forwarding 95511285Sandreas.hansson@arm.com // internally, and have a sufficiently weak memory 95611285Sandreas.hansson@arm.com // model, this is probably unnecessary, but at some 95711744Snikos.nikoleris@arm.com // point it must have seemed like we needed it... 95811744Snikos.nikoleris@arm.com assert((pkt->needsWritable() && !blk->isWritable()) || 95911285Sandreas.hansson@arm.com pkt->req->isCacheMaintenance()); 96011127Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 96111127Sandreas.hansson@arm.com } 96211051Sandreas.hansson@arm.com // Here we are using forward_time, modelling the latency of 96311051Sandreas.hansson@arm.com // a miss (outbound) just as forwardLatency, neglecting the 96411051Sandreas.hansson@arm.com // lookupLatency component. 96511051Sandreas.hansson@arm.com allocateMissBuffer(pkt, forward_time); 96611284Sandreas.hansson@arm.com } 96711051Sandreas.hansson@arm.com 96811051Sandreas.hansson@arm.com if (prefetcher) { 96911051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 97011051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch() && 97111051Sandreas.hansson@arm.com !pkt->req->isCacheMaintenance()) 97211051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 97311051Sandreas.hansson@arm.com } 97411051Sandreas.hansson@arm.com } 97511051Sandreas.hansson@arm.com } 97611051Sandreas.hansson@arm.com 97712724Snikos.nikoleris@arm.com if (next_pf_time != MaxTick) 97811127Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 97911127Sandreas.hansson@arm.com 98011127Sandreas.hansson@arm.com return true; 98111127Sandreas.hansson@arm.com} 98211127Sandreas.hansson@arm.com 98311127Sandreas.hansson@arm.comPacketPtr 98411284Sandreas.hansson@arm.comCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 98511051Sandreas.hansson@arm.com bool needsWritable) const 98611051Sandreas.hansson@arm.com{ 98711284Sandreas.hansson@arm.com // should never see evictions here 98811051Sandreas.hansson@arm.com assert(!cpu_pkt->isEviction()); 98911284Sandreas.hansson@arm.com 99011284Sandreas.hansson@arm.com bool blkValid = blk && blk->isValid(); 99111284Sandreas.hansson@arm.com 99211284Sandreas.hansson@arm.com if (cpu_pkt->req->isUncacheable() || 99311051Sandreas.hansson@arm.com (!blkValid && cpu_pkt->isUpgrade()) || 99411051Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::InvalidateReq || cpu_pkt->isClean()) { 99511051Sandreas.hansson@arm.com // uncacheable requests and upgrades from upper-level caches 99611051Sandreas.hansson@arm.com // that missed completely just go through as is 99711051Sandreas.hansson@arm.com return nullptr; 99811051Sandreas.hansson@arm.com } 99911051Sandreas.hansson@arm.com 100012349Snikos.nikoleris@arm.com assert(cpu_pkt->needsResponse()); 100112349Snikos.nikoleris@arm.com 100212349Snikos.nikoleris@arm.com MemCmd cmd; 100312349Snikos.nikoleris@arm.com // @TODO make useUpgrades a parameter. 100412349Snikos.nikoleris@arm.com // Note that ownership protocols require upgrade, otherwise a 100511051Sandreas.hansson@arm.com // write miss on a shared owned block will generate a ReadExcl, 100612724Snikos.nikoleris@arm.com // which will clobber the owned copy. 100711284Sandreas.hansson@arm.com const bool useUpgrades = true; 100811051Sandreas.hansson@arm.com if (cpu_pkt->cmd == MemCmd::WriteLineReq) { 100911051Sandreas.hansson@arm.com assert(!blkValid || !blk->isWritable()); 101011051Sandreas.hansson@arm.com // forward as invalidate to all other caches, this gives us 101111051Sandreas.hansson@arm.com // the line in Exclusive state, and invalidates all other 101211051Sandreas.hansson@arm.com // copies 101311051Sandreas.hansson@arm.com cmd = MemCmd::InvalidateReq; 101411051Sandreas.hansson@arm.com } else if (blkValid && useUpgrades) { 101512349Snikos.nikoleris@arm.com // only reason to be here is that blk is read only and we need 101612349Snikos.nikoleris@arm.com // it to be writable 101712349Snikos.nikoleris@arm.com assert(needsWritable); 101812349Snikos.nikoleris@arm.com assert(!blk->isWritable()); 101912349Snikos.nikoleris@arm.com cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq; 102012349Snikos.nikoleris@arm.com } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq || 102112351Snikos.nikoleris@arm.com cpu_pkt->cmd == MemCmd::StoreCondFailReq) { 102212349Snikos.nikoleris@arm.com // Even though this SC will fail, we still need to send out the 102312349Snikos.nikoleris@arm.com // request and get the data to supply it to other snoopers in the case 102412349Snikos.nikoleris@arm.com // where the determination the StoreCond fails is delayed due to 102512349Snikos.nikoleris@arm.com // all caches not being on the same local bus. 102612349Snikos.nikoleris@arm.com cmd = MemCmd::SCUpgradeFailReq; 102712349Snikos.nikoleris@arm.com } else { 102812349Snikos.nikoleris@arm.com // block is invalid 102912349Snikos.nikoleris@arm.com 103012349Snikos.nikoleris@arm.com // If the request does not need a writable there are two cases 103112349Snikos.nikoleris@arm.com // where we need to ensure the response will not fetch the 103212349Snikos.nikoleris@arm.com // block in dirty state: 103312349Snikos.nikoleris@arm.com // * this cache is read only and it does not perform 103412349Snikos.nikoleris@arm.com // writebacks, 103512349Snikos.nikoleris@arm.com // * this cache is mostly exclusive and will not fill (since 103612349Snikos.nikoleris@arm.com // it does not fill it will have to writeback the dirty data 103711744Snikos.nikoleris@arm.com // immediately which generates uneccesary writebacks). 103811744Snikos.nikoleris@arm.com bool force_clean_rsp = isReadOnly || clusivity == Enums::mostly_excl; 103911493Sandreas.hansson@arm.com cmd = needsWritable ? MemCmd::ReadExReq : 104011493Sandreas.hansson@arm.com (force_clean_rsp ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq); 104111493Sandreas.hansson@arm.com } 104211493Sandreas.hansson@arm.com PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize); 104311493Sandreas.hansson@arm.com 104411493Sandreas.hansson@arm.com // if there are upstream caches that have already marked the 104511493Sandreas.hansson@arm.com // packet as having sharers (not passing writable), pass that info 104611493Sandreas.hansson@arm.com // downstream 104711493Sandreas.hansson@arm.com if (cpu_pkt->hasSharers() && !needsWritable) { 104811493Sandreas.hansson@arm.com // note that cpu_pkt may have spent a considerable time in the 104911493Sandreas.hansson@arm.com // MSHR queue and that the information could possibly be out 105011493Sandreas.hansson@arm.com // of date, however, there is no harm in conservatively 105111127Sandreas.hansson@arm.com // assuming the block has sharers 105211051Sandreas.hansson@arm.com pkt->setHasSharers(); 105311744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: passing hasSharers from %s to %s\n", 105411744Snikos.nikoleris@arm.com __func__, cpu_pkt->print(), pkt->print()); 105512349Snikos.nikoleris@arm.com } 105612349Snikos.nikoleris@arm.com 105712349Snikos.nikoleris@arm.com // the packet should be block aligned 105812349Snikos.nikoleris@arm.com assert(pkt->getAddr() == pkt->getBlockAddr(blkSize)); 105912349Snikos.nikoleris@arm.com 106012349Snikos.nikoleris@arm.com pkt->allocate(); 106112349Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: created %s from %s\n", __func__, pkt->print(), 106212349Snikos.nikoleris@arm.com cpu_pkt->print()); 106312349Snikos.nikoleris@arm.com return pkt; 106412349Snikos.nikoleris@arm.com} 106512349Snikos.nikoleris@arm.com 106612349Snikos.nikoleris@arm.com 106711051Sandreas.hansson@arm.comTick 106811051Sandreas.hansson@arm.comCache::recvAtomic(PacketPtr pkt) 106911051Sandreas.hansson@arm.com{ 107011051Sandreas.hansson@arm.com // We are in atomic mode so we pay just for lookupLatency here. 107111051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 107211051Sandreas.hansson@arm.com 107311051Sandreas.hansson@arm.com // Forward the request if the system is in cache bypass mode. 107411483Snikos.nikoleris@arm.com if (system->bypassCaches()) 107511744Snikos.nikoleris@arm.com return ticksToCycles(memSidePort->sendAtomic(pkt)); 107611051Sandreas.hansson@arm.com 107711127Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 107811051Sandreas.hansson@arm.com 107911051Sandreas.hansson@arm.com // follow the same flow as in recvTimingReq, and check if a cache 108011285Sandreas.hansson@arm.com // above us is responding 108111285Sandreas.hansson@arm.com if (pkt->cacheResponding() && !pkt->isClean()) { 108211284Sandreas.hansson@arm.com assert(!pkt->req->isCacheInvalidate()); 108311284Sandreas.hansson@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 108411285Sandreas.hansson@arm.com pkt->print()); 108511285Sandreas.hansson@arm.com 108611285Sandreas.hansson@arm.com // if a cache is responding, and it had the line in Owned 108711285Sandreas.hansson@arm.com // rather than Modified state, we need to invalidate any 108811285Sandreas.hansson@arm.com // copies that are not on the same path to memory 108911285Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 109011285Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 109111285Sandreas.hansson@arm.com 109212349Snikos.nikoleris@arm.com return lat * clockPeriod(); 109311051Sandreas.hansson@arm.com } 109411051Sandreas.hansson@arm.com 109511051Sandreas.hansson@arm.com // should assert here that there are no outstanding MSHRs or 109611051Sandreas.hansson@arm.com // writebacks... that would mean that someone used an atomic 109711051Sandreas.hansson@arm.com // access in timing mode 109811284Sandreas.hansson@arm.com 109911284Sandreas.hansson@arm.com CacheBlk *blk = nullptr; 110012349Snikos.nikoleris@arm.com PacketList writebacks; 110111284Sandreas.hansson@arm.com bool satisfied = access(pkt, blk, lat, writebacks); 110211284Sandreas.hansson@arm.com 110311284Sandreas.hansson@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 110411284Sandreas.hansson@arm.com // A cache clean opearation is looking for a dirty 110511284Sandreas.hansson@arm.com // block. If a dirty block is encountered a WriteClean 110611081Sandreas.hansson@arm.com // will update any copies to the path to the memory 110711284Sandreas.hansson@arm.com // until the point of reference. 110811284Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 110911284Sandreas.hansson@arm.com __func__, pkt->print(), blk->print()); 111011284Sandreas.hansson@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id); 111111284Sandreas.hansson@arm.com writebacks.push_back(wb_pkt); 111211284Sandreas.hansson@arm.com pkt->setSatisfied(); 111311284Sandreas.hansson@arm.com } 111411051Sandreas.hansson@arm.com 111511284Sandreas.hansson@arm.com // handle writebacks resulting from the access here to ensure they 111611285Sandreas.hansson@arm.com // logically proceed anything happening below 111711285Sandreas.hansson@arm.com doWritebacksAtomic(writebacks); 111811285Sandreas.hansson@arm.com 111911744Snikos.nikoleris@arm.com if (!satisfied) { 112011744Snikos.nikoleris@arm.com // MISS 112111285Sandreas.hansson@arm.com 112211051Sandreas.hansson@arm.com // deal with the packets that go through the write path of 112311051Sandreas.hansson@arm.com // the cache, i.e. any evictions and writes 112411051Sandreas.hansson@arm.com if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean || 112511051Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 112611286Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 112711286Sandreas.hansson@arm.com return lat * clockPeriod(); 112811286Sandreas.hansson@arm.com } 112911286Sandreas.hansson@arm.com // only misses left 113011051Sandreas.hansson@arm.com 113111051Sandreas.hansson@arm.com PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable()); 113211051Sandreas.hansson@arm.com 113311602Sandreas.hansson@arm.com bool is_forward = (bus_pkt == nullptr); 113411051Sandreas.hansson@arm.com 113511051Sandreas.hansson@arm.com if (is_forward) { 113611051Sandreas.hansson@arm.com // just forwarding the same request to the next level 113711051Sandreas.hansson@arm.com // no local cache operation involved 113811051Sandreas.hansson@arm.com bus_pkt = pkt; 113911051Sandreas.hansson@arm.com } 114012349Snikos.nikoleris@arm.com 114111197Sandreas.hansson@arm.com DPRINTF(Cache, "%s: Sending an atomic %s\n", __func__, 114212349Snikos.nikoleris@arm.com bus_pkt->print()); 114311051Sandreas.hansson@arm.com 114411051Sandreas.hansson@arm.com#if TRACING_ON 114511127Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 114611051Sandreas.hansson@arm.com#endif 114711051Sandreas.hansson@arm.com 114811051Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt)); 114911051Sandreas.hansson@arm.com 115011051Sandreas.hansson@arm.com bool is_invalidate = bus_pkt->isInvalidate(); 115111051Sandreas.hansson@arm.com 115211744Snikos.nikoleris@arm.com // We are now dealing with the response handling 115311051Sandreas.hansson@arm.com DPRINTF(Cache, "%s: Receive response: %s in state %i\n", __func__, 115411130Sali.jafri@arm.com bus_pkt->print(), old_state); 115511051Sandreas.hansson@arm.com 115611051Sandreas.hansson@arm.com // If packet was a forward, the response (if any) is already 115711051Sandreas.hansson@arm.com // in place in the bus_pkt == pkt structure, so we don't need 115811051Sandreas.hansson@arm.com // to do anything. Otherwise, use the separate bus_pkt to 115911051Sandreas.hansson@arm.com // generate response to pkt and then delete it. 116011051Sandreas.hansson@arm.com if (!is_forward) { 116111051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 116211892Snikos.nikoleris@arm.com assert(bus_pkt->isResponse()); 116311051Sandreas.hansson@arm.com if (bus_pkt->isError()) { 116411051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 116511127Sandreas.hansson@arm.com pkt->copyError(bus_pkt); 116611127Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::WriteLineReq) { 116711127Sandreas.hansson@arm.com // note the use of pkt, not bus_pkt here. 116811127Sandreas.hansson@arm.com 116911127Sandreas.hansson@arm.com // write-line request to the cache that promoted 117011127Sandreas.hansson@arm.com // the write to a whole line 117111127Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks, 117211127Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 117311051Sandreas.hansson@arm.com assert(blk != NULL); 117411051Sandreas.hansson@arm.com is_invalidate = false; 117511051Sandreas.hansson@arm.com satisfyRequest(pkt, blk); 117611744Snikos.nikoleris@arm.com } else if (bus_pkt->isRead() || 117711744Snikos.nikoleris@arm.com bus_pkt->cmd == MemCmd::UpgradeResp) { 117811051Sandreas.hansson@arm.com // we're updating cache state to allow us to 117911051Sandreas.hansson@arm.com // satisfy the upstream request from the cache 118011051Sandreas.hansson@arm.com blk = handleFill(bus_pkt, blk, writebacks, 118111051Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 118212349Snikos.nikoleris@arm.com satisfyRequest(pkt, blk); 118312349Snikos.nikoleris@arm.com maintainClusivity(pkt->fromCache(), blk); 118412349Snikos.nikoleris@arm.com } else { 118512349Snikos.nikoleris@arm.com // we're satisfying the upstream request without 118612349Snikos.nikoleris@arm.com // modifying cache state, e.g., a write-through 118712349Snikos.nikoleris@arm.com pkt->makeAtomicResponse(); 118812349Snikos.nikoleris@arm.com } 118911051Sandreas.hansson@arm.com } 119011051Sandreas.hansson@arm.com delete bus_pkt; 119111051Sandreas.hansson@arm.com } 119211051Sandreas.hansson@arm.com 119311051Sandreas.hansson@arm.com if (is_invalidate && blk && blk->isValid()) { 119411051Sandreas.hansson@arm.com invalidateBlock(blk); 119511051Sandreas.hansson@arm.com } 119611051Sandreas.hansson@arm.com } 119711051Sandreas.hansson@arm.com 119811051Sandreas.hansson@arm.com // Note that we don't invoke the prefetcher at all in atomic mode. 119911051Sandreas.hansson@arm.com // It's not clear how to do it properly, particularly for 120011051Sandreas.hansson@arm.com // prefetchers that aggressively generate prefetch candidates and 120111051Sandreas.hansson@arm.com // rely on bandwidth contention to throttle them; these will tend 120211375Sandreas.hansson@arm.com // to pollute the cache in atomic mode since there is no bandwidth 120311375Sandreas.hansson@arm.com // contention. If we ever do want to enable prefetching in atomic 120411051Sandreas.hansson@arm.com // mode, though, this is the place to do it... see timingAccess() 120511051Sandreas.hansson@arm.com // for an example (though we'd want to issue the prefetch(es) 120611051Sandreas.hansson@arm.com // immediately rather than calling requestMemSideBus() as we do 120711051Sandreas.hansson@arm.com // there). 120811051Sandreas.hansson@arm.com 120911051Sandreas.hansson@arm.com // do any writebacks resulting from the response handling 121011051Sandreas.hansson@arm.com doWritebacksAtomic(writebacks); 121111051Sandreas.hansson@arm.com 121211051Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and if so 121312345Snikos.nikoleris@arm.com // clear it out, but only do so after the call to recvAtomic is 121411051Sandreas.hansson@arm.com // finished so that any downstream observers (such as a snoop 121511199Sandreas.hansson@arm.com // filter), first see the fill, and only then see the eviction 121611051Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 121711051Sandreas.hansson@arm.com // the atomic CPU calls recvAtomic for fetch and load/store 121811051Sandreas.hansson@arm.com // sequentuially, and we may already have a tempBlock 121911051Sandreas.hansson@arm.com // writeback from the fetch that we have not yet sent 122011051Sandreas.hansson@arm.com if (tempBlockWriteback) { 122111744Snikos.nikoleris@arm.com // if that is the case, write the prevoius one back, and 122211744Snikos.nikoleris@arm.com // do not schedule any new event 122311051Sandreas.hansson@arm.com writebackTempBlockAtomic(); 122411051Sandreas.hansson@arm.com } else { 122511051Sandreas.hansson@arm.com // the writeback/clean eviction happens after the call to 122611332Sandreas.hansson@arm.com // recvAtomic has finished (but before any successive 122711332Sandreas.hansson@arm.com // calls), so that the response handling from the fill is 122811332Sandreas.hansson@arm.com // allowed to happen first 122911332Sandreas.hansson@arm.com schedule(writebackTempBlockAtomicEvent, curTick()); 123011332Sandreas.hansson@arm.com } 123111332Sandreas.hansson@arm.com 123211751Snikos.nikoleris@arm.com tempBlockWriteback = (blk->isDirty() || writebackClean) ? 123311332Sandreas.hansson@arm.com writebackBlk(blk) : cleanEvictBlk(blk); 123411332Sandreas.hansson@arm.com invalidateBlock(blk); 123511332Sandreas.hansson@arm.com } 123611332Sandreas.hansson@arm.com 123711332Sandreas.hansson@arm.com if (pkt->needsResponse()) { 123811332Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 123911332Sandreas.hansson@arm.com } 124011332Sandreas.hansson@arm.com 124111332Sandreas.hansson@arm.com return lat * clockPeriod(); 124211332Sandreas.hansson@arm.com} 124311284Sandreas.hansson@arm.com 124411332Sandreas.hansson@arm.com 124511332Sandreas.hansson@arm.comvoid 124611332Sandreas.hansson@arm.comCache::functionalAccess(PacketPtr pkt, bool fromCpuSide) 124711051Sandreas.hansson@arm.com{ 124811332Sandreas.hansson@arm.com if (system->bypassCaches()) { 124911051Sandreas.hansson@arm.com // Packets from the memory side are snoop request and 125011051Sandreas.hansson@arm.com // shouldn't happen in bypass mode. 125111051Sandreas.hansson@arm.com assert(fromCpuSide); 125211051Sandreas.hansson@arm.com 125312349Snikos.nikoleris@arm.com // The cache should be flushed if we are in cache bypass mode, 125411051Sandreas.hansson@arm.com // so we don't need to check if we need to update anything. 125511051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 125611375Sandreas.hansson@arm.com return; 125711051Sandreas.hansson@arm.com } 125811051Sandreas.hansson@arm.com 125911051Sandreas.hansson@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 126011051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 126111051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 126211051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 126311051Sandreas.hansson@arm.com 126411051Sandreas.hansson@arm.com pkt->pushLabel(name()); 126511051Sandreas.hansson@arm.com 126611127Sandreas.hansson@arm.com CacheBlkPrintWrapper cbpw(blk); 126711127Sandreas.hansson@arm.com 126811127Sandreas.hansson@arm.com // Note that just because an L2/L3 has valid data doesn't mean an 126911127Sandreas.hansson@arm.com // L1 doesn't have a more up-to-date modified copy that still 127011127Sandreas.hansson@arm.com // needs to be found. As a result we always update the request if 127111127Sandreas.hansson@arm.com // we have it, but only declare it satisfied if we are the owner. 127211051Sandreas.hansson@arm.com 127311051Sandreas.hansson@arm.com // see if we have data at all (owned or otherwise) 127411051Sandreas.hansson@arm.com bool have_data = blk && blk->isValid() 127511051Sandreas.hansson@arm.com && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize, 127611051Sandreas.hansson@arm.com blk->data); 127711130Sali.jafri@arm.com 127811130Sali.jafri@arm.com // data we have is dirty if marked as such or if we have an 127911051Sandreas.hansson@arm.com // in-service MSHR that is pending a modified line 128011051Sandreas.hansson@arm.com bool have_dirty = 128111051Sandreas.hansson@arm.com have_data && (blk->isDirty() || 128211051Sandreas.hansson@arm.com (mshr && mshr->inService && mshr->isPendingModified())); 128311127Sandreas.hansson@arm.com 128411127Sandreas.hansson@arm.com bool done = have_dirty 128511051Sandreas.hansson@arm.com || cpuSidePort->checkFunctional(pkt) 128611051Sandreas.hansson@arm.com || mshrQueue.checkFunctional(pkt, blk_addr) 128711051Sandreas.hansson@arm.com || writeBuffer.checkFunctional(pkt, blk_addr) 128812724Snikos.nikoleris@arm.com || memSidePort->checkFunctional(pkt); 128911051Sandreas.hansson@arm.com 129011051Sandreas.hansson@arm.com DPRINTF(CacheVerbose, "%s: %s %s%s%s\n", __func__, pkt->print(), 129111051Sandreas.hansson@arm.com (blk && blk->isValid()) ? "valid " : "", 129211051Sandreas.hansson@arm.com have_data ? "data " : "", done ? "done " : ""); 129311051Sandreas.hansson@arm.com 129411051Sandreas.hansson@arm.com // We're leaving the cache, so pop cache->name() label 129511051Sandreas.hansson@arm.com pkt->popLabel(); 129611051Sandreas.hansson@arm.com 129711130Sali.jafri@arm.com if (done) { 129811130Sali.jafri@arm.com pkt->makeResponse(); 129911130Sali.jafri@arm.com } else { 130011130Sali.jafri@arm.com // if it came as a request from the CPU side then make sure it 130111130Sali.jafri@arm.com // continues towards the memory side 130211130Sali.jafri@arm.com if (fromCpuSide) { 130312345Snikos.nikoleris@arm.com memSidePort->sendFunctional(pkt); 130411484Snikos.nikoleris@arm.com } else if (cpuSidePort->isSnooping()) { 130512724Snikos.nikoleris@arm.com // if it came from the memory side, it must be a snoop request 130611130Sali.jafri@arm.com // and we should only forward it if we are forwarding snoops 130711284Sandreas.hansson@arm.com cpuSidePort->sendFunctionalSnoop(pkt); 130811130Sali.jafri@arm.com } 130911130Sali.jafri@arm.com } 131012724Snikos.nikoleris@arm.com} 131111130Sali.jafri@arm.com 131211130Sali.jafri@arm.com 131311051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 131411051Sandreas.hansson@arm.com// 131511375Sandreas.hansson@arm.com// Response handling: responses from the memory side 131611375Sandreas.hansson@arm.com// 131711375Sandreas.hansson@arm.com///////////////////////////////////////////////////// 131811375Sandreas.hansson@arm.com 131911375Sandreas.hansson@arm.com 132011051Sandreas.hansson@arm.comvoid 132111051Sandreas.hansson@arm.comCache::handleUncacheableWriteResp(PacketPtr pkt) 132211375Sandreas.hansson@arm.com{ 132312724Snikos.nikoleris@arm.com Tick completion_time = clockEdge(responseLatency) + 132412724Snikos.nikoleris@arm.com pkt->headerDelay + pkt->payloadDelay; 132511051Sandreas.hansson@arm.com 132611375Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 132711375Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 132812724Snikos.nikoleris@arm.com 132911375Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(pkt, completion_time, true); 133011051Sandreas.hansson@arm.com} 133111051Sandreas.hansson@arm.com 133211051Sandreas.hansson@arm.comvoid 133311051Sandreas.hansson@arm.comCache::recvTimingResp(PacketPtr pkt) 133411051Sandreas.hansson@arm.com{ 133511051Sandreas.hansson@arm.com assert(pkt->isResponse()); 133611051Sandreas.hansson@arm.com 133711275Sandreas.hansson@arm.com // all header delay should be paid for by the crossbar, unless 133811275Sandreas.hansson@arm.com // this is a prefetch response from above 133911275Sandreas.hansson@arm.com panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 134011275Sandreas.hansson@arm.com "%s saw a non-zero packet delay\n", name()); 134111051Sandreas.hansson@arm.com 134212724Snikos.nikoleris@arm.com bool is_error = pkt->isError(); 134311051Sandreas.hansson@arm.com 134411051Sandreas.hansson@arm.com if (is_error) { 134511051Sandreas.hansson@arm.com DPRINTF(Cache, "%s: Cache received %s with error\n", __func__, 134611051Sandreas.hansson@arm.com pkt->print()); 134711051Sandreas.hansson@arm.com } 134811051Sandreas.hansson@arm.com 134911051Sandreas.hansson@arm.com DPRINTF(Cache, "%s: Handling response %s\n", __func__, 135011284Sandreas.hansson@arm.com pkt->print()); 135111284Sandreas.hansson@arm.com 135211284Sandreas.hansson@arm.com // if this is a write, we should be looking at an uncacheable 135311284Sandreas.hansson@arm.com // write 135411284Sandreas.hansson@arm.com if (pkt->isWrite()) { 135511284Sandreas.hansson@arm.com assert(pkt->req->isUncacheable()); 135611284Sandreas.hansson@arm.com handleUncacheableWriteResp(pkt); 135711276Sandreas.hansson@arm.com return; 135811276Sandreas.hansson@arm.com } 135911284Sandreas.hansson@arm.com 136011284Sandreas.hansson@arm.com // we have dealt with any (uncacheable) writes above, from here on 136111284Sandreas.hansson@arm.com // we know we are dealing with an MSHR due to a miss or a prefetch 136211284Sandreas.hansson@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState()); 136311284Sandreas.hansson@arm.com assert(mshr); 136411284Sandreas.hansson@arm.com 136511051Sandreas.hansson@arm.com if (mshr == noTargetMSHR) { 136611051Sandreas.hansson@arm.com // we always clear at least one target 136711051Sandreas.hansson@arm.com clearBlocked(Blocked_NoTargets); 136811375Sandreas.hansson@arm.com noTargetMSHR = nullptr; 136911051Sandreas.hansson@arm.com } 137011051Sandreas.hansson@arm.com 137111375Sandreas.hansson@arm.com // Initial target is used just for stats 137211051Sandreas.hansson@arm.com MSHR::Target *initial_tgt = mshr->getTarget(); 137311051Sandreas.hansson@arm.com int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 137411051Sandreas.hansson@arm.com Tick miss_latency = curTick() - initial_tgt->recvTime; 137511375Sandreas.hansson@arm.com 137611051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 137711375Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 137811277Sandreas.hansson@arm.com mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 137911277Sandreas.hansson@arm.com miss_latency; 138011375Sandreas.hansson@arm.com } else { 138111051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 138212167Spau.cabre@metempsy.com mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 138312167Spau.cabre@metempsy.com miss_latency; 138412167Spau.cabre@metempsy.com } 138512167Spau.cabre@metempsy.com 138611375Sandreas.hansson@arm.com bool wasFull = mshrQueue.isFull(); 138711051Sandreas.hansson@arm.com 138811051Sandreas.hansson@arm.com PacketList writebacks; 138911051Sandreas.hansson@arm.com 139012724Snikos.nikoleris@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 139111051Sandreas.hansson@arm.com 139211051Sandreas.hansson@arm.com bool is_fill = !mshr->isForward && 139311053Sandreas.hansson@arm.com (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp); 139411053Sandreas.hansson@arm.com 139511053Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 139611053Sandreas.hansson@arm.com const bool valid_blk = blk && blk->isValid(); 139712600Sodanrc@yahoo.com.br // If the response indicates that there are no sharers and we 139811053Sandreas.hansson@arm.com // either had the block already or the response is filling we can 139911053Sandreas.hansson@arm.com // promote our copy to writable 140011053Sandreas.hansson@arm.com if (!pkt->hasSharers() && 1401 (is_fill || (valid_blk && !pkt->req->isCacheInvalidate()))) { 1402 mshr->promoteWritable(); 1403 } 1404 1405 if (is_fill && !is_error) { 1406 DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 1407 pkt->getAddr()); 1408 1409 blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill()); 1410 assert(blk != nullptr); 1411 } 1412 1413 // allow invalidation responses originating from write-line 1414 // requests to be discarded 1415 bool is_invalidate = pkt->isInvalidate(); 1416 1417 // The block was marked as not readable while there was a pending 1418 // cache maintenance operation, restore its flag. 1419 if (pkt->isClean() && !is_invalidate && valid_blk) { 1420 blk->status |= BlkReadable; 1421 } 1422 1423 // First offset for critical word first calculations 1424 int initial_offset = initial_tgt->pkt->getOffset(blkSize); 1425 1426 bool from_cache = false; 1427 MSHR::TargetList targets = mshr->extractServiceableTargets(pkt); 1428 for (auto &target: targets) { 1429 Packet *tgt_pkt = target.pkt; 1430 switch (target.source) { 1431 case MSHR::Target::FromCPU: 1432 Tick completion_time; 1433 // Here we charge on completion_time the delay of the xbar if the 1434 // packet comes from it, charged on headerDelay. 1435 completion_time = pkt->headerDelay; 1436 1437 // Software prefetch handling for cache closest to core 1438 if (tgt_pkt->cmd.isSWPrefetch()) { 1439 // a software prefetch would have already been ack'd 1440 // immediately with dummy data so the core would be able to 1441 // retire it. This request completes right here, so we 1442 // deallocate it. 1443 delete tgt_pkt->req; 1444 delete tgt_pkt; 1445 break; // skip response 1446 } 1447 1448 // keep track of whether we have responded to another 1449 // cache 1450 from_cache = from_cache || tgt_pkt->fromCache(); 1451 1452 // unlike the other packet flows, where data is found in other 1453 // caches or memory and brought back, write-line requests always 1454 // have the data right away, so the above check for "is fill?" 1455 // cannot actually be determined until examining the stored MSHR 1456 // state. We "catch up" with that logic here, which is duplicated 1457 // from above. 1458 if (tgt_pkt->cmd == MemCmd::WriteLineReq) { 1459 assert(!is_error); 1460 // we got the block in a writable state, so promote 1461 // any deferred targets if possible 1462 mshr->promoteWritable(); 1463 // NB: we use the original packet here and not the response! 1464 blk = handleFill(tgt_pkt, blk, writebacks, 1465 targets.allocOnFill); 1466 assert(blk != nullptr); 1467 1468 // treat as a fill, and discard the invalidation 1469 // response 1470 is_fill = true; 1471 is_invalidate = false; 1472 } 1473 1474 if (is_fill) { 1475 satisfyRequest(tgt_pkt, blk, true, mshr->hasPostDowngrade()); 1476 1477 // How many bytes past the first request is this one 1478 int transfer_offset = 1479 tgt_pkt->getOffset(blkSize) - initial_offset; 1480 if (transfer_offset < 0) { 1481 transfer_offset += blkSize; 1482 } 1483 1484 // If not critical word (offset) return payloadDelay. 1485 // responseLatency is the latency of the return path 1486 // from lower level caches/memory to an upper level cache or 1487 // the core. 1488 completion_time += clockEdge(responseLatency) + 1489 (transfer_offset ? pkt->payloadDelay : 0); 1490 1491 assert(!tgt_pkt->req->isUncacheable()); 1492 1493 assert(tgt_pkt->req->masterId() < system->maxMasters()); 1494 missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] += 1495 completion_time - target.recvTime; 1496 } else if (pkt->cmd == MemCmd::UpgradeFailResp) { 1497 // failed StoreCond upgrade 1498 assert(tgt_pkt->cmd == MemCmd::StoreCondReq || 1499 tgt_pkt->cmd == MemCmd::StoreCondFailReq || 1500 tgt_pkt->cmd == MemCmd::SCUpgradeFailReq); 1501 // responseLatency is the latency of the return path 1502 // from lower level caches/memory to an upper level cache or 1503 // the core. 1504 completion_time += clockEdge(responseLatency) + 1505 pkt->payloadDelay; 1506 tgt_pkt->req->setExtraData(0); 1507 } else { 1508 // We are about to send a response to a cache above 1509 // that asked for an invalidation; we need to 1510 // invalidate our copy immediately as the most 1511 // up-to-date copy of the block will now be in the 1512 // cache above. It will also prevent this cache from 1513 // responding (if the block was previously dirty) to 1514 // snoops as they should snoop the caches above where 1515 // they will get the response from. 1516 if (is_invalidate && blk && blk->isValid()) { 1517 invalidateBlock(blk); 1518 } 1519 // not a cache fill, just forwarding response 1520 // responseLatency is the latency of the return path 1521 // from lower level cahces/memory to the core. 1522 completion_time += clockEdge(responseLatency) + 1523 pkt->payloadDelay; 1524 if (pkt->isRead() && !is_error) { 1525 // sanity check 1526 assert(pkt->getAddr() == tgt_pkt->getAddr()); 1527 assert(pkt->getSize() >= tgt_pkt->getSize()); 1528 1529 tgt_pkt->setData(pkt->getConstPtr<uint8_t>()); 1530 } 1531 } 1532 tgt_pkt->makeTimingResponse(); 1533 // if this packet is an error copy that to the new packet 1534 if (is_error) 1535 tgt_pkt->copyError(pkt); 1536 if (tgt_pkt->cmd == MemCmd::ReadResp && 1537 (is_invalidate || mshr->hasPostInvalidate())) { 1538 // If intermediate cache got ReadRespWithInvalidate, 1539 // propagate that. Response should not have 1540 // isInvalidate() set otherwise. 1541 tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate; 1542 DPRINTF(Cache, "%s: updated cmd to %s\n", __func__, 1543 tgt_pkt->print()); 1544 } 1545 // Reset the bus additional time as it is now accounted for 1546 tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; 1547 cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true); 1548 break; 1549 1550 case MSHR::Target::FromPrefetcher: 1551 assert(tgt_pkt->cmd == MemCmd::HardPFReq); 1552 if (blk) 1553 blk->status |= BlkHWPrefetched; 1554 delete tgt_pkt->req; 1555 delete tgt_pkt; 1556 break; 1557 1558 case MSHR::Target::FromSnoop: 1559 // I don't believe that a snoop can be in an error state 1560 assert(!is_error); 1561 // response to snoop request 1562 DPRINTF(Cache, "processing deferred snoop...\n"); 1563 // If the response is invalidating, a snooping target can 1564 // be satisfied if it is also invalidating. If the reponse is, not 1565 // only invalidating, but more specifically an InvalidateResp and 1566 // the MSHR was created due to an InvalidateReq then a cache above 1567 // is waiting to satisfy a WriteLineReq. In this case even an 1568 // non-invalidating snoop is added as a target here since this is 1569 // the ordering point. When the InvalidateResp reaches this cache, 1570 // the snooping target will snoop further the cache above with the 1571 // WriteLineReq. 1572 assert(!is_invalidate || pkt->cmd == MemCmd::InvalidateResp || 1573 pkt->req->isCacheMaintenance() || 1574 mshr->hasPostInvalidate()); 1575 handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate()); 1576 break; 1577 1578 default: 1579 panic("Illegal target->source enum %d\n", target.source); 1580 } 1581 } 1582 1583 maintainClusivity(from_cache, blk); 1584 1585 if (blk && blk->isValid()) { 1586 // an invalidate response stemming from a write line request 1587 // should not invalidate the block, so check if the 1588 // invalidation should be discarded 1589 if (is_invalidate || mshr->hasPostInvalidate()) { 1590 invalidateBlock(blk); 1591 } else if (mshr->hasPostDowngrade()) { 1592 blk->status &= ~BlkWritable; 1593 } 1594 } 1595 1596 if (mshr->promoteDeferredTargets()) { 1597 // avoid later read getting stale data while write miss is 1598 // outstanding.. see comment in timingAccess() 1599 if (blk) { 1600 blk->status &= ~BlkReadable; 1601 } 1602 mshrQueue.markPending(mshr); 1603 schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 1604 } else { 1605 mshrQueue.deallocate(mshr); 1606 if (wasFull && !mshrQueue.isFull()) { 1607 clearBlocked(Blocked_NoMSHRs); 1608 } 1609 1610 // Request the bus for a prefetch if this deallocation freed enough 1611 // MSHRs for a prefetch to take place 1612 if (prefetcher && mshrQueue.canPrefetch()) { 1613 Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 1614 clockEdge()); 1615 if (next_pf_time != MaxTick) 1616 schedMemSideSendEvent(next_pf_time); 1617 } 1618 } 1619 // reset the xbar additional timinig as it is now accounted for 1620 pkt->headerDelay = pkt->payloadDelay = 0; 1621 1622 // copy writebacks to write buffer 1623 doWritebacks(writebacks, forward_time); 1624 1625 // if we used temp block, check to see if its valid and then clear it out 1626 if (blk == tempBlock && tempBlock->isValid()) { 1627 // We use forwardLatency here because we are copying 1628 // Writebacks/CleanEvicts to write buffer. It specifies the latency to 1629 // allocate an internal buffer and to schedule an event to the 1630 // queued port. 1631 if (blk->isDirty() || writebackClean) { 1632 PacketPtr wbPkt = writebackBlk(blk); 1633 allocateWriteBuffer(wbPkt, forward_time); 1634 // Set BLOCK_CACHED flag if cached above. 1635 if (isCachedAbove(wbPkt)) 1636 wbPkt->setBlockCached(); 1637 } else { 1638 PacketPtr wcPkt = cleanEvictBlk(blk); 1639 // Check to see if block is cached above. If not allocate 1640 // write buffer 1641 if (isCachedAbove(wcPkt)) 1642 delete wcPkt; 1643 else 1644 allocateWriteBuffer(wcPkt, forward_time); 1645 } 1646 invalidateBlock(blk); 1647 } 1648 1649 DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print()); 1650 delete pkt; 1651} 1652 1653PacketPtr 1654Cache::writebackBlk(CacheBlk *blk) 1655{ 1656 chatty_assert(!isReadOnly || writebackClean, 1657 "Writeback from read-only cache"); 1658 assert(blk && blk->isValid() && (blk->isDirty() || writebackClean)); 1659 1660 writebacks[Request::wbMasterId]++; 1661 1662 Request *req = new Request(tags->regenerateBlkAddr(blk), blkSize, 0, 1663 Request::wbMasterId); 1664 if (blk->isSecure()) 1665 req->setFlags(Request::SECURE); 1666 1667 req->taskId(blk->task_id); 1668 1669 PacketPtr pkt = 1670 new Packet(req, blk->isDirty() ? 1671 MemCmd::WritebackDirty : MemCmd::WritebackClean); 1672 1673 DPRINTF(Cache, "Create Writeback %s writable: %d, dirty: %d\n", 1674 pkt->print(), blk->isWritable(), blk->isDirty()); 1675 1676 if (blk->isWritable()) { 1677 // not asserting shared means we pass the block in modified 1678 // state, mark our own block non-writeable 1679 blk->status &= ~BlkWritable; 1680 } else { 1681 // we are in the Owned state, tell the receiver 1682 pkt->setHasSharers(); 1683 } 1684 1685 // make sure the block is not marked dirty 1686 blk->status &= ~BlkDirty; 1687 1688 pkt->allocate(); 1689 std::memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize); 1690 1691 return pkt; 1692} 1693 1694PacketPtr 1695Cache::writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id) 1696{ 1697 Request *req = new Request(tags->regenerateBlkAddr(blk), blkSize, 0, 1698 Request::wbMasterId); 1699 if (blk->isSecure()) { 1700 req->setFlags(Request::SECURE); 1701 } 1702 req->taskId(blk->task_id); 1703 1704 PacketPtr pkt = new Packet(req, MemCmd::WriteClean, blkSize, id); 1705 1706 if (dest) { 1707 req->setFlags(dest); 1708 pkt->setWriteThrough(); 1709 } 1710 1711 DPRINTF(Cache, "Create %s writable: %d, dirty: %d\n", pkt->print(), 1712 blk->isWritable(), blk->isDirty()); 1713 1714 if (blk->isWritable()) { 1715 // not asserting shared means we pass the block in modified 1716 // state, mark our own block non-writeable 1717 blk->status &= ~BlkWritable; 1718 } else { 1719 // we are in the Owned state, tell the receiver 1720 pkt->setHasSharers(); 1721 } 1722 1723 // make sure the block is not marked dirty 1724 blk->status &= ~BlkDirty; 1725 1726 pkt->allocate(); 1727 std::memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize); 1728 1729 return pkt; 1730} 1731 1732 1733PacketPtr 1734Cache::cleanEvictBlk(CacheBlk *blk) 1735{ 1736 assert(!writebackClean); 1737 assert(blk && blk->isValid() && !blk->isDirty()); 1738 // Creating a zero sized write, a message to the snoop filter 1739 Request *req = 1740 new Request(tags->regenerateBlkAddr(blk), blkSize, 0, 1741 Request::wbMasterId); 1742 if (blk->isSecure()) 1743 req->setFlags(Request::SECURE); 1744 1745 req->taskId(blk->task_id); 1746 1747 PacketPtr pkt = new Packet(req, MemCmd::CleanEvict); 1748 pkt->allocate(); 1749 DPRINTF(Cache, "Create CleanEvict %s\n", pkt->print()); 1750 1751 return pkt; 1752} 1753 1754void 1755Cache::memWriteback() 1756{ 1757 CacheBlkVisitorWrapper visitor(*this, &Cache::writebackVisitor); 1758 tags->forEachBlk(visitor); 1759} 1760 1761void 1762Cache::memInvalidate() 1763{ 1764 CacheBlkVisitorWrapper visitor(*this, &Cache::invalidateVisitor); 1765 tags->forEachBlk(visitor); 1766} 1767 1768bool 1769Cache::isDirty() const 1770{ 1771 CacheBlkIsDirtyVisitor visitor; 1772 tags->forEachBlk(visitor); 1773 1774 return visitor.isDirty(); 1775} 1776 1777bool 1778Cache::writebackVisitor(CacheBlk &blk) 1779{ 1780 if (blk.isDirty()) { 1781 assert(blk.isValid()); 1782 1783 Request request(tags->regenerateBlkAddr(&blk), blkSize, 0, 1784 Request::funcMasterId); 1785 request.taskId(blk.task_id); 1786 if (blk.isSecure()) { 1787 request.setFlags(Request::SECURE); 1788 } 1789 1790 Packet packet(&request, MemCmd::WriteReq); 1791 packet.dataStatic(blk.data); 1792 1793 memSidePort->sendFunctional(&packet); 1794 1795 blk.status &= ~BlkDirty; 1796 } 1797 1798 return true; 1799} 1800 1801bool 1802Cache::invalidateVisitor(CacheBlk &blk) 1803{ 1804 1805 if (blk.isDirty()) 1806 warn_once("Invalidating dirty cache lines. Expect things to break.\n"); 1807 1808 if (blk.isValid()) { 1809 assert(!blk.isDirty()); 1810 invalidateBlock(&blk); 1811 } 1812 1813 return true; 1814} 1815 1816CacheBlk* 1817Cache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks) 1818{ 1819 // Find replacement victim 1820 CacheBlk *blk = tags->findVictim(addr); 1821 1822 // It is valid to return nullptr if there is no victim 1823 if (!blk) 1824 return nullptr; 1825 1826 if (blk->isValid()) { 1827 Addr repl_addr = tags->regenerateBlkAddr(blk); 1828 MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure()); 1829 if (repl_mshr) { 1830 // must be an outstanding upgrade or clean request 1831 // on a block we're about to replace... 1832 assert((!blk->isWritable() && repl_mshr->needsWritable()) || 1833 repl_mshr->isCleaning()); 1834 // too hard to replace block with transient state 1835 // allocation failed, block not inserted 1836 return nullptr; 1837 } else { 1838 DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx " 1839 "(%s): %s\n", repl_addr, blk->isSecure() ? "s" : "ns", 1840 addr, is_secure ? "s" : "ns", 1841 blk->isDirty() ? "writeback" : "clean"); 1842 1843 if (blk->wasPrefetched()) { 1844 unusedPrefetches++; 1845 } 1846 // Will send up Writeback/CleanEvict snoops via isCachedAbove 1847 // when pushing this writeback list into the write buffer. 1848 if (blk->isDirty() || writebackClean) { 1849 // Save writeback packet for handling by caller 1850 writebacks.push_back(writebackBlk(blk)); 1851 } else { 1852 writebacks.push_back(cleanEvictBlk(blk)); 1853 } 1854 } 1855 } 1856 1857 return blk; 1858} 1859 1860void 1861Cache::invalidateBlock(CacheBlk *blk) 1862{ 1863 if (blk != tempBlock) 1864 tags->invalidate(blk); 1865 blk->invalidate(); 1866} 1867 1868// Note that the reason we return a list of writebacks rather than 1869// inserting them directly in the write buffer is that this function 1870// is called by both atomic and timing-mode accesses, and in atomic 1871// mode we don't mess with the write buffer (we just perform the 1872// writebacks atomically once the original request is complete). 1873CacheBlk* 1874Cache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, 1875 bool allocate) 1876{ 1877 assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq); 1878 Addr addr = pkt->getAddr(); 1879 bool is_secure = pkt->isSecure(); 1880#if TRACING_ON 1881 CacheBlk::State old_state = blk ? blk->status : 0; 1882#endif 1883 1884 // When handling a fill, we should have no writes to this line. 1885 assert(addr == pkt->getBlockAddr(blkSize)); 1886 assert(!writeBuffer.findMatch(addr, is_secure)); 1887 1888 if (blk == nullptr) { 1889 // better have read new data... 1890 assert(pkt->hasData()); 1891 1892 // only read responses and write-line requests have data; 1893 // note that we don't write the data here for write-line - that 1894 // happens in the subsequent call to satisfyRequest 1895 assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq); 1896 1897 // need to do a replacement if allocating, otherwise we stick 1898 // with the temporary storage 1899 blk = allocate ? allocateBlock(addr, is_secure, writebacks) : nullptr; 1900 1901 if (blk == nullptr) { 1902 // No replaceable block or a mostly exclusive 1903 // cache... just use temporary storage to complete the 1904 // current request and then get rid of it 1905 assert(!tempBlock->isValid()); 1906 blk = tempBlock; 1907 tempBlock->set = tags->extractSet(addr); 1908 tempBlock->tag = tags->extractTag(addr); 1909 if (is_secure) { 1910 tempBlock->status |= BlkSecure; 1911 } 1912 DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr, 1913 is_secure ? "s" : "ns"); 1914 } else { 1915 tags->insertBlock(pkt, blk); 1916 } 1917 1918 // we should never be overwriting a valid block 1919 assert(!blk->isValid()); 1920 } else { 1921 // existing block... probably an upgrade 1922 assert(blk->tag == tags->extractTag(addr)); 1923 // either we're getting new data or the block should already be valid 1924 assert(pkt->hasData() || blk->isValid()); 1925 // don't clear block status... if block is already dirty we 1926 // don't want to lose that 1927 } 1928 1929 if (is_secure) 1930 blk->status |= BlkSecure; 1931 blk->status |= BlkValid | BlkReadable; 1932 1933 // sanity check for whole-line writes, which should always be 1934 // marked as writable as part of the fill, and then later marked 1935 // dirty as part of satisfyRequest 1936 if (pkt->cmd == MemCmd::WriteLineReq) { 1937 assert(!pkt->hasSharers()); 1938 } 1939 1940 // here we deal with setting the appropriate state of the line, 1941 // and we start by looking at the hasSharers flag, and ignore the 1942 // cacheResponding flag (normally signalling dirty data) if the 1943 // packet has sharers, thus the line is never allocated as Owned 1944 // (dirty but not writable), and always ends up being either 1945 // Shared, Exclusive or Modified, see Packet::setCacheResponding 1946 // for more details 1947 if (!pkt->hasSharers()) { 1948 // we could get a writable line from memory (rather than a 1949 // cache) even in a read-only cache, note that we set this bit 1950 // even for a read-only cache, possibly revisit this decision 1951 blk->status |= BlkWritable; 1952 1953 // check if we got this via cache-to-cache transfer (i.e., from a 1954 // cache that had the block in Modified or Owned state) 1955 if (pkt->cacheResponding()) { 1956 // we got the block in Modified state, and invalidated the 1957 // owners copy 1958 blk->status |= BlkDirty; 1959 1960 chatty_assert(!isReadOnly, "Should never see dirty snoop response " 1961 "in read-only cache %s\n", name()); 1962 } 1963 } 1964 1965 DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n", 1966 addr, is_secure ? "s" : "ns", old_state, blk->print()); 1967 1968 // if we got new data, copy it in (checking for a read response 1969 // and a response that has data is the same in the end) 1970 if (pkt->isRead()) { 1971 // sanity checks 1972 assert(pkt->hasData()); 1973 assert(pkt->getSize() == blkSize); 1974 1975 std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 1976 } 1977 // We pay for fillLatency here. 1978 blk->whenReady = clockEdge() + fillLatency * clockPeriod() + 1979 pkt->payloadDelay; 1980 1981 return blk; 1982} 1983 1984 1985///////////////////////////////////////////////////// 1986// 1987// Snoop path: requests coming in from the memory side 1988// 1989///////////////////////////////////////////////////// 1990 1991void 1992Cache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 1993 bool already_copied, bool pending_inval) 1994{ 1995 // sanity check 1996 assert(req_pkt->isRequest()); 1997 assert(req_pkt->needsResponse()); 1998 1999 DPRINTF(Cache, "%s: for %s\n", __func__, req_pkt->print()); 2000 // timing-mode snoop responses require a new packet, unless we 2001 // already made a copy... 2002 PacketPtr pkt = req_pkt; 2003 if (!already_copied) 2004 // do not clear flags, and allocate space for data if the 2005 // packet needs it (the only packets that carry data are read 2006 // responses) 2007 pkt = new Packet(req_pkt, false, req_pkt->isRead()); 2008 2009 assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() || 2010 pkt->hasSharers()); 2011 pkt->makeTimingResponse(); 2012 if (pkt->isRead()) { 2013 pkt->setDataFromBlock(blk_data, blkSize); 2014 } 2015 if (pkt->cmd == MemCmd::ReadResp && pending_inval) { 2016 // Assume we defer a response to a read from a far-away cache 2017 // A, then later defer a ReadExcl from a cache B on the same 2018 // bus as us. We'll assert cacheResponding in both cases, but 2019 // in the latter case cacheResponding will keep the 2020 // invalidation from reaching cache A. This special response 2021 // tells cache A that it gets the block to satisfy its read, 2022 // but must immediately invalidate it. 2023 pkt->cmd = MemCmd::ReadRespWithInvalidate; 2024 } 2025 // Here we consider forward_time, paying for just forward latency and 2026 // also charging the delay provided by the xbar. 2027 // forward_time is used as send_time in next allocateWriteBuffer(). 2028 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 2029 // Here we reset the timing of the packet. 2030 pkt->headerDelay = pkt->payloadDelay = 0; 2031 DPRINTF(CacheVerbose, "%s: created response: %s tick: %lu\n", __func__, 2032 pkt->print(), forward_time); 2033 memSidePort->schedTimingSnoopResp(pkt, forward_time, true); 2034} 2035 2036uint32_t 2037Cache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, 2038 bool is_deferred, bool pending_inval) 2039{ 2040 DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 2041 // deferred snoops can only happen in timing mode 2042 assert(!(is_deferred && !is_timing)); 2043 // pending_inval only makes sense on deferred snoops 2044 assert(!(pending_inval && !is_deferred)); 2045 assert(pkt->isRequest()); 2046 2047 // the packet may get modified if we or a forwarded snooper 2048 // responds in atomic mode, so remember a few things about the 2049 // original packet up front 2050 bool invalidate = pkt->isInvalidate(); 2051 bool M5_VAR_USED needs_writable = pkt->needsWritable(); 2052 2053 // at the moment we could get an uncacheable write which does not 2054 // have the invalidate flag, and we need a suitable way of dealing 2055 // with this case 2056 panic_if(invalidate && pkt->req->isUncacheable(), 2057 "%s got an invalidating uncacheable snoop request %s", 2058 name(), pkt->print()); 2059 2060 uint32_t snoop_delay = 0; 2061 2062 if (forwardSnoops) { 2063 // first propagate snoop upward to see if anyone above us wants to 2064 // handle it. save & restore packet src since it will get 2065 // rewritten to be relative to cpu-side bus (if any) 2066 bool alreadyResponded = pkt->cacheResponding(); 2067 if (is_timing) { 2068 // copy the packet so that we can clear any flags before 2069 // forwarding it upwards, we also allocate data (passing 2070 // the pointer along in case of static data), in case 2071 // there is a snoop hit in upper levels 2072 Packet snoopPkt(pkt, true, true); 2073 snoopPkt.setExpressSnoop(); 2074 // the snoop packet does not need to wait any additional 2075 // time 2076 snoopPkt.headerDelay = snoopPkt.payloadDelay = 0; 2077 cpuSidePort->sendTimingSnoopReq(&snoopPkt); 2078 2079 // add the header delay (including crossbar and snoop 2080 // delays) of the upward snoop to the snoop delay for this 2081 // cache 2082 snoop_delay += snoopPkt.headerDelay; 2083 2084 if (snoopPkt.cacheResponding()) { 2085 // cache-to-cache response from some upper cache 2086 assert(!alreadyResponded); 2087 pkt->setCacheResponding(); 2088 } 2089 // upstream cache has the block, or has an outstanding 2090 // MSHR, pass the flag on 2091 if (snoopPkt.hasSharers()) { 2092 pkt->setHasSharers(); 2093 } 2094 // If this request is a prefetch or clean evict and an upper level 2095 // signals block present, make sure to propagate the block 2096 // presence to the requester. 2097 if (snoopPkt.isBlockCached()) { 2098 pkt->setBlockCached(); 2099 } 2100 // If the request was satisfied by snooping the cache 2101 // above, mark the original packet as satisfied too. 2102 if (snoopPkt.satisfied()) { 2103 pkt->setSatisfied(); 2104 } 2105 } else { 2106 cpuSidePort->sendAtomicSnoop(pkt); 2107 if (!alreadyResponded && pkt->cacheResponding()) { 2108 // cache-to-cache response from some upper cache: 2109 // forward response to original requester 2110 assert(pkt->isResponse()); 2111 } 2112 } 2113 } 2114 2115 bool respond = false; 2116 bool blk_valid = blk && blk->isValid(); 2117 if (pkt->isClean()) { 2118 if (blk_valid && blk->isDirty()) { 2119 DPRINTF(CacheVerbose, "%s: packet (snoop) %s found block: %s\n", 2120 __func__, pkt->print(), blk->print()); 2121 PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id); 2122 PacketList writebacks; 2123 writebacks.push_back(wb_pkt); 2124 2125 if (is_timing) { 2126 // anything that is merely forwarded pays for the forward 2127 // latency and the delay provided by the crossbar 2128 Tick forward_time = clockEdge(forwardLatency) + 2129 pkt->headerDelay; 2130 doWritebacks(writebacks, forward_time); 2131 } else { 2132 doWritebacksAtomic(writebacks); 2133 } 2134 pkt->setSatisfied(); 2135 } 2136 } else if (!blk_valid) { 2137 DPRINTF(CacheVerbose, "%s: snoop miss for %s\n", __func__, 2138 pkt->print()); 2139 if (is_deferred) { 2140 // we no longer have the block, and will not respond, but a 2141 // packet was allocated in MSHR::handleSnoop and we have 2142 // to delete it 2143 assert(pkt->needsResponse()); 2144 2145 // we have passed the block to a cache upstream, that 2146 // cache should be responding 2147 assert(pkt->cacheResponding()); 2148 2149 delete pkt; 2150 } 2151 return snoop_delay; 2152 } else { 2153 DPRINTF(Cache, "%s: snoop hit for %s, old state is %s\n", __func__, 2154 pkt->print(), blk->print()); 2155 2156 // We may end up modifying both the block state and the packet (if 2157 // we respond in atomic mode), so just figure out what to do now 2158 // and then do it later. We respond to all snoops that need 2159 // responses provided we have the block in dirty state. The 2160 // invalidation itself is taken care of below. We don't respond to 2161 // cache maintenance operations as this is done by the destination 2162 // xbar. 2163 respond = blk->isDirty() && pkt->needsResponse(); 2164 2165 chatty_assert(!(isReadOnly && blk->isDirty()), "Should never have " 2166 "a dirty block in a read-only cache %s\n", name()); 2167 } 2168 2169 // Invalidate any prefetch's from below that would strip write permissions 2170 // MemCmd::HardPFReq is only observed by upstream caches. After missing 2171 // above and in it's own cache, a new MemCmd::ReadReq is created that 2172 // downstream caches observe. 2173 if (pkt->mustCheckAbove()) { 2174 DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s " 2175 "from lower cache\n", pkt->getAddr(), pkt->print()); 2176 pkt->setBlockCached(); 2177 return snoop_delay; 2178 } 2179 2180 if (pkt->isRead() && !invalidate) { 2181 // reading without requiring the line in a writable state 2182 assert(!needs_writable); 2183 pkt->setHasSharers(); 2184 2185 // if the requesting packet is uncacheable, retain the line in 2186 // the current state, otherwhise unset the writable flag, 2187 // which means we go from Modified to Owned (and will respond 2188 // below), remain in Owned (and will respond below), from 2189 // Exclusive to Shared, or remain in Shared 2190 if (!pkt->req->isUncacheable()) 2191 blk->status &= ~BlkWritable; 2192 DPRINTF(Cache, "new state is %s\n", blk->print()); 2193 } 2194 2195 if (respond) { 2196 // prevent anyone else from responding, cache as well as 2197 // memory, and also prevent any memory from even seeing the 2198 // request 2199 pkt->setCacheResponding(); 2200 if (!pkt->isClean() && blk->isWritable()) { 2201 // inform the cache hierarchy that this cache had the line 2202 // in the Modified state so that we avoid unnecessary 2203 // invalidations (see Packet::setResponderHadWritable) 2204 pkt->setResponderHadWritable(); 2205 2206 // in the case of an uncacheable request there is no point 2207 // in setting the responderHadWritable flag, but since the 2208 // recipient does not care there is no harm in doing so 2209 } else { 2210 // if the packet has needsWritable set we invalidate our 2211 // copy below and all other copies will be invalidates 2212 // through express snoops, and if needsWritable is not set 2213 // we already called setHasSharers above 2214 } 2215 2216 // if we are returning a writable and dirty (Modified) line, 2217 // we should be invalidating the line 2218 panic_if(!invalidate && !pkt->hasSharers(), 2219 "%s is passing a Modified line through %s, " 2220 "but keeping the block", name(), pkt->print()); 2221 2222 if (is_timing) { 2223 doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval); 2224 } else { 2225 pkt->makeAtomicResponse(); 2226 // packets such as upgrades do not actually have any data 2227 // payload 2228 if (pkt->hasData()) 2229 pkt->setDataFromBlock(blk->data, blkSize); 2230 } 2231 } 2232 2233 if (!respond && is_deferred) { 2234 assert(pkt->needsResponse()); 2235 2236 // if we copied the deferred packet with the intention to 2237 // respond, but are not responding, then a cache above us must 2238 // be, and we can use this as the indication of whether this 2239 // is a packet where we created a copy of the request or not 2240 if (!pkt->cacheResponding()) { 2241 delete pkt->req; 2242 } 2243 2244 delete pkt; 2245 } 2246 2247 // Do this last in case it deallocates block data or something 2248 // like that 2249 if (blk_valid && invalidate) { 2250 invalidateBlock(blk); 2251 DPRINTF(Cache, "new state is %s\n", blk->print()); 2252 } 2253 2254 return snoop_delay; 2255} 2256 2257 2258void 2259Cache::recvTimingSnoopReq(PacketPtr pkt) 2260{ 2261 DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 2262 2263 // Snoops shouldn't happen when bypassing caches 2264 assert(!system->bypassCaches()); 2265 2266 // no need to snoop requests that are not in range 2267 if (!inRange(pkt->getAddr())) { 2268 return; 2269 } 2270 2271 bool is_secure = pkt->isSecure(); 2272 CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 2273 2274 Addr blk_addr = pkt->getBlockAddr(blkSize); 2275 MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 2276 2277 // Update the latency cost of the snoop so that the crossbar can 2278 // account for it. Do not overwrite what other neighbouring caches 2279 // have already done, rather take the maximum. The update is 2280 // tentative, for cases where we return before an upward snoop 2281 // happens below. 2282 pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, 2283 lookupLatency * clockPeriod()); 2284 2285 // Inform request(Prefetch, CleanEvict or Writeback) from below of 2286 // MSHR hit, set setBlockCached. 2287 if (mshr && pkt->mustCheckAbove()) { 2288 DPRINTF(Cache, "Setting block cached for %s from lower cache on " 2289 "mshr hit\n", pkt->print()); 2290 pkt->setBlockCached(); 2291 return; 2292 } 2293 2294 // Bypass any existing cache maintenance requests if the request 2295 // has been satisfied already (i.e., the dirty block has been 2296 // found). 2297 if (mshr && pkt->req->isCacheMaintenance() && pkt->satisfied()) { 2298 return; 2299 } 2300 2301 // Let the MSHR itself track the snoop and decide whether we want 2302 // to go ahead and do the regular cache snoop 2303 if (mshr && mshr->handleSnoop(pkt, order++)) { 2304 DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)." 2305 "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns", 2306 mshr->print()); 2307 2308 if (mshr->getNumTargets() > numTarget) 2309 warn("allocating bonus target for snoop"); //handle later 2310 return; 2311 } 2312 2313 //We also need to check the writeback buffers and handle those 2314 WriteQueueEntry *wb_entry = writeBuffer.findMatch(blk_addr, is_secure); 2315 if (wb_entry) { 2316 DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n", 2317 pkt->getAddr(), is_secure ? "s" : "ns"); 2318 // Expect to see only Writebacks and/or CleanEvicts here, both of 2319 // which should not be generated for uncacheable data. 2320 assert(!wb_entry->isUncacheable()); 2321 // There should only be a single request responsible for generating 2322 // Writebacks/CleanEvicts. 2323 assert(wb_entry->getNumTargets() == 1); 2324 PacketPtr wb_pkt = wb_entry->getTarget()->pkt; 2325 assert(wb_pkt->isEviction() || wb_pkt->cmd == MemCmd::WriteClean); 2326 2327 if (pkt->isEviction()) { 2328 // if the block is found in the write queue, set the BLOCK_CACHED 2329 // flag for Writeback/CleanEvict snoop. On return the snoop will 2330 // propagate the BLOCK_CACHED flag in Writeback packets and prevent 2331 // any CleanEvicts from travelling down the memory hierarchy. 2332 pkt->setBlockCached(); 2333 DPRINTF(Cache, "%s: Squashing %s from lower cache on writequeue " 2334 "hit\n", __func__, pkt->print()); 2335 return; 2336 } 2337 2338 // conceptually writebacks are no different to other blocks in 2339 // this cache, so the behaviour is modelled after handleSnoop, 2340 // the difference being that instead of querying the block 2341 // state to determine if it is dirty and writable, we use the 2342 // command and fields of the writeback packet 2343 bool respond = wb_pkt->cmd == MemCmd::WritebackDirty && 2344 pkt->needsResponse(); 2345 bool have_writable = !wb_pkt->hasSharers(); 2346 bool invalidate = pkt->isInvalidate(); 2347 2348 if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) { 2349 assert(!pkt->needsWritable()); 2350 pkt->setHasSharers(); 2351 wb_pkt->setHasSharers(); 2352 } 2353 2354 if (respond) { 2355 pkt->setCacheResponding(); 2356 2357 if (have_writable) { 2358 pkt->setResponderHadWritable(); 2359 } 2360 2361 doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(), 2362 false, false); 2363 } 2364 2365 if (invalidate && wb_pkt->cmd != MemCmd::WriteClean) { 2366 // Invalidation trumps our writeback... discard here 2367 // Note: markInService will remove entry from writeback buffer. 2368 markInService(wb_entry); 2369 delete wb_pkt; 2370 } 2371 } 2372 2373 // If this was a shared writeback, there may still be 2374 // other shared copies above that require invalidation. 2375 // We could be more selective and return here if the 2376 // request is non-exclusive or if the writeback is 2377 // exclusive. 2378 uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false); 2379 2380 // Override what we did when we first saw the snoop, as we now 2381 // also have the cost of the upwards snoops to account for 2382 pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay + 2383 lookupLatency * clockPeriod()); 2384} 2385 2386bool 2387Cache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 2388{ 2389 // Express snoop responses from master to slave, e.g., from L1 to L2 2390 cache->recvTimingSnoopResp(pkt); 2391 return true; 2392} 2393 2394Tick 2395Cache::recvAtomicSnoop(PacketPtr pkt) 2396{ 2397 // Snoops shouldn't happen when bypassing caches 2398 assert(!system->bypassCaches()); 2399 2400 // no need to snoop requests that are not in range. 2401 if (!inRange(pkt->getAddr())) { 2402 return 0; 2403 } 2404 2405 CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 2406 uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false); 2407 return snoop_delay + lookupLatency * clockPeriod(); 2408} 2409 2410 2411QueueEntry* 2412Cache::getNextQueueEntry() 2413{ 2414 // Check both MSHR queue and write buffer for potential requests, 2415 // note that null does not mean there is no request, it could 2416 // simply be that it is not ready 2417 MSHR *miss_mshr = mshrQueue.getNext(); 2418 WriteQueueEntry *wq_entry = writeBuffer.getNext(); 2419 2420 // If we got a write buffer request ready, first priority is a 2421 // full write buffer, otherwise we favour the miss requests 2422 if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) { 2423 // need to search MSHR queue for conflicting earlier miss. 2424 MSHR *conflict_mshr = 2425 mshrQueue.findPending(wq_entry->blkAddr, 2426 wq_entry->isSecure); 2427 2428 if (conflict_mshr && conflict_mshr->order < wq_entry->order) { 2429 // Service misses in order until conflict is cleared. 2430 return conflict_mshr; 2431 2432 // @todo Note that we ignore the ready time of the conflict here 2433 } 2434 2435 // No conflicts; issue write 2436 return wq_entry; 2437 } else if (miss_mshr) { 2438 // need to check for conflicting earlier writeback 2439 WriteQueueEntry *conflict_mshr = 2440 writeBuffer.findPending(miss_mshr->blkAddr, 2441 miss_mshr->isSecure); 2442 if (conflict_mshr) { 2443 // not sure why we don't check order here... it was in the 2444 // original code but commented out. 2445 2446 // The only way this happens is if we are 2447 // doing a write and we didn't have permissions 2448 // then subsequently saw a writeback (owned got evicted) 2449 // We need to make sure to perform the writeback first 2450 // To preserve the dirty data, then we can issue the write 2451 2452 // should we return wq_entry here instead? I.e. do we 2453 // have to flush writes in order? I don't think so... not 2454 // for Alpha anyway. Maybe for x86? 2455 return conflict_mshr; 2456 2457 // @todo Note that we ignore the ready time of the conflict here 2458 } 2459 2460 // No conflicts; issue read 2461 return miss_mshr; 2462 } 2463 2464 // fall through... no pending requests. Try a prefetch. 2465 assert(!miss_mshr && !wq_entry); 2466 if (prefetcher && mshrQueue.canPrefetch()) { 2467 // If we have a miss queue slot, we can try a prefetch 2468 PacketPtr pkt = prefetcher->getPacket(); 2469 if (pkt) { 2470 Addr pf_addr = pkt->getBlockAddr(blkSize); 2471 if (!tags->findBlock(pf_addr, pkt->isSecure()) && 2472 !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 2473 !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 2474 // Update statistic on number of prefetches issued 2475 // (hwpf_mshr_misses) 2476 assert(pkt->req->masterId() < system->maxMasters()); 2477 mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 2478 2479 // allocate an MSHR and return it, note 2480 // that we send the packet straight away, so do not 2481 // schedule the send 2482 return allocateMissBuffer(pkt, curTick(), false); 2483 } else { 2484 // free the request and packet 2485 delete pkt->req; 2486 delete pkt; 2487 } 2488 } 2489 } 2490 2491 return nullptr; 2492} 2493 2494bool 2495Cache::isCachedAbove(PacketPtr pkt, bool is_timing) const 2496{ 2497 if (!forwardSnoops) 2498 return false; 2499 // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and 2500 // Writeback snoops into upper level caches to check for copies of the 2501 // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict 2502 // packet, the cache can inform the crossbar below of presence or absence 2503 // of the block. 2504 if (is_timing) { 2505 Packet snoop_pkt(pkt, true, false); 2506 snoop_pkt.setExpressSnoop(); 2507 // Assert that packet is either Writeback or CleanEvict and not a 2508 // prefetch request because prefetch requests need an MSHR and may 2509 // generate a snoop response. 2510 assert(pkt->isEviction() || pkt->cmd == MemCmd::WriteClean); 2511 snoop_pkt.senderState = nullptr; 2512 cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 2513 // Writeback/CleanEvict snoops do not generate a snoop response. 2514 assert(!(snoop_pkt.cacheResponding())); 2515 return snoop_pkt.isBlockCached(); 2516 } else { 2517 cpuSidePort->sendAtomicSnoop(pkt); 2518 return pkt->isBlockCached(); 2519 } 2520} 2521 2522Tick 2523Cache::nextQueueReadyTime() const 2524{ 2525 Tick nextReady = std::min(mshrQueue.nextReadyTime(), 2526 writeBuffer.nextReadyTime()); 2527 2528 // Don't signal prefetch ready time if no MSHRs available 2529 // Will signal once enoguh MSHRs are deallocated 2530 if (prefetcher && mshrQueue.canPrefetch()) { 2531 nextReady = std::min(nextReady, 2532 prefetcher->nextPrefetchReadyTime()); 2533 } 2534 2535 return nextReady; 2536} 2537 2538bool 2539Cache::sendMSHRQueuePacket(MSHR* mshr) 2540{ 2541 assert(mshr); 2542 2543 // use request from 1st target 2544 PacketPtr tgt_pkt = mshr->getTarget()->pkt; 2545 2546 DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print()); 2547 2548 CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 2549 2550 if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) { 2551 // we should never have hardware prefetches to allocated 2552 // blocks 2553 assert(blk == nullptr); 2554 2555 // We need to check the caches above us to verify that 2556 // they don't have a copy of this block in the dirty state 2557 // at the moment. Without this check we could get a stale 2558 // copy from memory that might get used in place of the 2559 // dirty one. 2560 Packet snoop_pkt(tgt_pkt, true, false); 2561 snoop_pkt.setExpressSnoop(); 2562 // We are sending this packet upwards, but if it hits we will 2563 // get a snoop response that we end up treating just like a 2564 // normal response, hence it needs the MSHR as its sender 2565 // state 2566 snoop_pkt.senderState = mshr; 2567 cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 2568 2569 // Check to see if the prefetch was squashed by an upper cache (to 2570 // prevent us from grabbing the line) or if a Check to see if a 2571 // writeback arrived between the time the prefetch was placed in 2572 // the MSHRs and when it was selected to be sent or if the 2573 // prefetch was squashed by an upper cache. 2574 2575 // It is important to check cacheResponding before 2576 // prefetchSquashed. If another cache has committed to 2577 // responding, it will be sending a dirty response which will 2578 // arrive at the MSHR allocated for this request. Checking the 2579 // prefetchSquash first may result in the MSHR being 2580 // prematurely deallocated. 2581 if (snoop_pkt.cacheResponding()) { 2582 auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req); 2583 assert(r.second); 2584 2585 // if we are getting a snoop response with no sharers it 2586 // will be allocated as Modified 2587 bool pending_modified_resp = !snoop_pkt.hasSharers(); 2588 markInService(mshr, pending_modified_resp); 2589 2590 DPRINTF(Cache, "Upward snoop of prefetch for addr" 2591 " %#x (%s) hit\n", 2592 tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns"); 2593 return false; 2594 } 2595 2596 if (snoop_pkt.isBlockCached()) { 2597 DPRINTF(Cache, "Block present, prefetch squashed by cache. " 2598 "Deallocating mshr target %#x.\n", 2599 mshr->blkAddr); 2600 2601 // Deallocate the mshr target 2602 if (mshrQueue.forceDeallocateTarget(mshr)) { 2603 // Clear block if this deallocation resulted freed an 2604 // mshr when all had previously been utilized 2605 clearBlocked(Blocked_NoMSHRs); 2606 } 2607 2608 // given that no response is expected, delete Request and Packet 2609 delete tgt_pkt->req; 2610 delete tgt_pkt; 2611 2612 return false; 2613 } 2614 } 2615 2616 // either a prefetch that is not present upstream, or a normal 2617 // MSHR request, proceed to get the packet to send downstream 2618 PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable()); 2619 2620 mshr->isForward = (pkt == nullptr); 2621 2622 if (mshr->isForward) { 2623 // not a cache block request, but a response is expected 2624 // make copy of current packet to forward, keep current 2625 // copy for response handling 2626 pkt = new Packet(tgt_pkt, false, true); 2627 assert(!pkt->isWrite()); 2628 } 2629 2630 // play it safe and append (rather than set) the sender state, 2631 // as forwarded packets may already have existing state 2632 pkt->pushSenderState(mshr); 2633 2634 if (pkt->isClean() && blk && blk->isDirty()) { 2635 // A cache clean opearation is looking for a dirty block. Mark 2636 // the packet so that the destination xbar can determine that 2637 // there will be a follow-up write packet as well. 2638 pkt->setSatisfied(); 2639 } 2640 2641 if (!memSidePort->sendTimingReq(pkt)) { 2642 // we are awaiting a retry, but we 2643 // delete the packet and will be creating a new packet 2644 // when we get the opportunity 2645 delete pkt; 2646 2647 // note that we have now masked any requestBus and 2648 // schedSendEvent (we will wait for a retry before 2649 // doing anything), and this is so even if we do not 2650 // care about this packet and might override it before 2651 // it gets retried 2652 return true; 2653 } else { 2654 // As part of the call to sendTimingReq the packet is 2655 // forwarded to all neighbouring caches (and any caches 2656 // above them) as a snoop. Thus at this point we know if 2657 // any of the neighbouring caches are responding, and if 2658 // so, we know it is dirty, and we can determine if it is 2659 // being passed as Modified, making our MSHR the ordering 2660 // point 2661 bool pending_modified_resp = !pkt->hasSharers() && 2662 pkt->cacheResponding(); 2663 markInService(mshr, pending_modified_resp); 2664 if (pkt->isClean() && blk && blk->isDirty()) { 2665 // A cache clean opearation is looking for a dirty 2666 // block. If a dirty block is encountered a WriteClean 2667 // will update any copies to the path to the memory 2668 // until the point of reference. 2669 DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 2670 __func__, pkt->print(), blk->print()); 2671 PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), 2672 pkt->id); 2673 PacketList writebacks; 2674 writebacks.push_back(wb_pkt); 2675 doWritebacks(writebacks, 0); 2676 } 2677 2678 return false; 2679 } 2680} 2681 2682bool 2683Cache::sendWriteQueuePacket(WriteQueueEntry* wq_entry) 2684{ 2685 assert(wq_entry); 2686 2687 // always a single target for write queue entries 2688 PacketPtr tgt_pkt = wq_entry->getTarget()->pkt; 2689 2690 DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print()); 2691 2692 // forward as is, both for evictions and uncacheable writes 2693 if (!memSidePort->sendTimingReq(tgt_pkt)) { 2694 // note that we have now masked any requestBus and 2695 // schedSendEvent (we will wait for a retry before 2696 // doing anything), and this is so even if we do not 2697 // care about this packet and might override it before 2698 // it gets retried 2699 return true; 2700 } else { 2701 markInService(wq_entry); 2702 return false; 2703 } 2704} 2705 2706void 2707Cache::serialize(CheckpointOut &cp) const 2708{ 2709 bool dirty(isDirty()); 2710 2711 if (dirty) { 2712 warn("*** The cache still contains dirty data. ***\n"); 2713 warn(" Make sure to drain the system using the correct flags.\n"); 2714 warn(" This checkpoint will not restore correctly and dirty data " 2715 " in the cache will be lost!\n"); 2716 } 2717 2718 // Since we don't checkpoint the data in the cache, any dirty data 2719 // will be lost when restoring from a checkpoint of a system that 2720 // wasn't drained properly. Flag the checkpoint as invalid if the 2721 // cache contains dirty data. 2722 bool bad_checkpoint(dirty); 2723 SERIALIZE_SCALAR(bad_checkpoint); 2724} 2725 2726void 2727Cache::unserialize(CheckpointIn &cp) 2728{ 2729 bool bad_checkpoint; 2730 UNSERIALIZE_SCALAR(bad_checkpoint); 2731 if (bad_checkpoint) { 2732 fatal("Restoring from checkpoints with dirty caches is not supported " 2733 "in the classic memory system. Please remove any caches or " 2734 " drain them properly before taking checkpoints.\n"); 2735 } 2736} 2737 2738/////////////// 2739// 2740// CpuSidePort 2741// 2742/////////////// 2743 2744AddrRangeList 2745Cache::CpuSidePort::getAddrRanges() const 2746{ 2747 return cache->getAddrRanges(); 2748} 2749 2750bool 2751Cache::CpuSidePort::tryTiming(PacketPtr pkt) 2752{ 2753 assert(!cache->system->bypassCaches()); 2754 2755 // always let express snoop packets through if even if blocked 2756 if (pkt->isExpressSnoop()) { 2757 return true; 2758 } else if (isBlocked() || mustSendRetry) { 2759 // either already committed to send a retry, or blocked 2760 mustSendRetry = true; 2761 return false; 2762 } 2763 mustSendRetry = false; 2764 return true; 2765} 2766 2767bool 2768Cache::CpuSidePort::recvTimingReq(PacketPtr pkt) 2769{ 2770 assert(!cache->system->bypassCaches()); 2771 2772 // always let express snoop packets through if even if blocked 2773 if (pkt->isExpressSnoop()) { 2774 bool M5_VAR_USED bypass_success = cache->recvTimingReq(pkt); 2775 assert(bypass_success); 2776 return true; 2777 } 2778 2779 return tryTiming(pkt) && cache->recvTimingReq(pkt); 2780} 2781 2782Tick 2783Cache::CpuSidePort::recvAtomic(PacketPtr pkt) 2784{ 2785 return cache->recvAtomic(pkt); 2786} 2787 2788void 2789Cache::CpuSidePort::recvFunctional(PacketPtr pkt) 2790{ 2791 // functional request 2792 cache->functionalAccess(pkt, true); 2793} 2794 2795Cache:: 2796CpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache, 2797 const std::string &_label) 2798 : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache) 2799{ 2800} 2801 2802Cache* 2803CacheParams::create() 2804{ 2805 assert(tags); 2806 assert(replacement_policy); 2807 2808 return new Cache(this); 2809} 2810/////////////// 2811// 2812// MemSidePort 2813// 2814/////////////// 2815 2816bool 2817Cache::MemSidePort::recvTimingResp(PacketPtr pkt) 2818{ 2819 cache->recvTimingResp(pkt); 2820 return true; 2821} 2822 2823// Express snooping requests to memside port 2824void 2825Cache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 2826{ 2827 // handle snooping requests 2828 cache->recvTimingSnoopReq(pkt); 2829} 2830 2831Tick 2832Cache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 2833{ 2834 return cache->recvAtomicSnoop(pkt); 2835} 2836 2837void 2838Cache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 2839{ 2840 // functional snoop (note that in contrast to atomic we don't have 2841 // a specific functionalSnoop method, as they have the same 2842 // behaviour regardless) 2843 cache->functionalAccess(pkt, false); 2844} 2845 2846void 2847Cache::CacheReqPacketQueue::sendDeferredPacket() 2848{ 2849 // sanity check 2850 assert(!waitingOnRetry); 2851 2852 // there should never be any deferred request packets in the 2853 // queue, instead we resly on the cache to provide the packets 2854 // from the MSHR queue or write queue 2855 assert(deferredPacketReadyTime() == MaxTick); 2856 2857 // check for request packets (requests & writebacks) 2858 QueueEntry* entry = cache.getNextQueueEntry(); 2859 2860 if (!entry) { 2861 // can happen if e.g. we attempt a writeback and fail, but 2862 // before the retry, the writeback is eliminated because 2863 // we snoop another cache's ReadEx. 2864 } else { 2865 // let our snoop responses go first if there are responses to 2866 // the same addresses 2867 if (checkConflictingSnoop(entry->blkAddr)) { 2868 return; 2869 } 2870 waitingOnRetry = entry->sendPacket(cache); 2871 } 2872 2873 // if we succeeded and are not waiting for a retry, schedule the 2874 // next send considering when the next queue is ready, note that 2875 // snoop responses have their own packet queue and thus schedule 2876 // their own events 2877 if (!waitingOnRetry) { 2878 schedSendEvent(cache.nextQueueReadyTime()); 2879 } 2880} 2881 2882Cache:: 2883MemSidePort::MemSidePort(const std::string &_name, Cache *_cache, 2884 const std::string &_label) 2885 : BaseCache::CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 2886 _reqQueue(*_cache, *this, _snoopRespQueue, _label), 2887 _snoopRespQueue(*_cache, *this, _label), cache(_cache) 2888{ 2889} 2890