cache.cc revision 12346
12810Srdreslin@umich.edu/* 211375Sandreas.hansson@arm.com * Copyright (c) 2010-2016 ARM Limited 311051Sandreas.hansson@arm.com * All rights reserved. 411051Sandreas.hansson@arm.com * 511051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911051Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311051Sandreas.hansson@arm.com * 1411051Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511051Sandreas.hansson@arm.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 162810Srdreslin@umich.edu * All rights reserved. 172810Srdreslin@umich.edu * 182810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 192810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 202810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 212810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 222810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 232810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 242810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 252810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 262810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 272810Srdreslin@umich.edu * this software without specific prior written permission. 282810Srdreslin@umich.edu * 292810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810Srdreslin@umich.edu * 412810Srdreslin@umich.edu * Authors: Erik Hallnor 4211051Sandreas.hansson@arm.com * Dave Greene 4311051Sandreas.hansson@arm.com * Nathan Binkert 442810Srdreslin@umich.edu * Steve Reinhardt 4511051Sandreas.hansson@arm.com * Ron Dreslinski 4611051Sandreas.hansson@arm.com * Andreas Sandberg 472810Srdreslin@umich.edu */ 482810Srdreslin@umich.edu 492810Srdreslin@umich.edu/** 502810Srdreslin@umich.edu * @file 5111051Sandreas.hansson@arm.com * Cache definitions. 522810Srdreslin@umich.edu */ 532810Srdreslin@umich.edu 5411051Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 552810Srdreslin@umich.edu 5612334Sgabeblack@google.com#include "base/logging.hh" 5711051Sandreas.hansson@arm.com#include "base/types.hh" 5811051Sandreas.hansson@arm.com#include "debug/Cache.hh" 5911051Sandreas.hansson@arm.com#include "debug/CachePort.hh" 6011051Sandreas.hansson@arm.com#include "debug/CacheTags.hh" 6111288Ssteve.reinhardt@amd.com#include "debug/CacheVerbose.hh" 6211051Sandreas.hansson@arm.com#include "mem/cache/blk.hh" 6311051Sandreas.hansson@arm.com#include "mem/cache/mshr.hh" 6411051Sandreas.hansson@arm.com#include "mem/cache/prefetch/base.hh" 6511051Sandreas.hansson@arm.com#include "sim/sim_exit.hh" 6611051Sandreas.hansson@arm.com 6711053Sandreas.hansson@arm.comCache::Cache(const CacheParams *p) 6811053Sandreas.hansson@arm.com : BaseCache(p, p->system->cacheLineSize()), 6911051Sandreas.hansson@arm.com tags(p->tags), 7011051Sandreas.hansson@arm.com prefetcher(p->prefetcher), 7111051Sandreas.hansson@arm.com doFastWrites(true), 7211197Sandreas.hansson@arm.com prefetchOnAccess(p->prefetch_on_access), 7311197Sandreas.hansson@arm.com clusivity(p->clusivity), 7411199Sandreas.hansson@arm.com writebackClean(p->writeback_clean), 7511197Sandreas.hansson@arm.com tempBlockWriteback(nullptr), 7612084Sspwilson2@wisc.edu writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); }, 7712084Sspwilson2@wisc.edu name(), false, 7811197Sandreas.hansson@arm.com EventBase::Delayed_Writeback_Pri) 7911051Sandreas.hansson@arm.com{ 8011051Sandreas.hansson@arm.com tempBlock = new CacheBlk(); 8111051Sandreas.hansson@arm.com tempBlock->data = new uint8_t[blkSize]; 8211051Sandreas.hansson@arm.com 8311051Sandreas.hansson@arm.com cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this, 8411051Sandreas.hansson@arm.com "CpuSidePort"); 8511051Sandreas.hansson@arm.com memSidePort = new MemSidePort(p->name + ".mem_side", this, 8611051Sandreas.hansson@arm.com "MemSidePort"); 8711051Sandreas.hansson@arm.com 8811051Sandreas.hansson@arm.com tags->setCache(this); 8911051Sandreas.hansson@arm.com if (prefetcher) 9011051Sandreas.hansson@arm.com prefetcher->setCache(this); 9111051Sandreas.hansson@arm.com} 9211051Sandreas.hansson@arm.com 9311051Sandreas.hansson@arm.comCache::~Cache() 9411051Sandreas.hansson@arm.com{ 9511051Sandreas.hansson@arm.com delete [] tempBlock->data; 9611051Sandreas.hansson@arm.com delete tempBlock; 9711051Sandreas.hansson@arm.com 9811051Sandreas.hansson@arm.com delete cpuSidePort; 9911051Sandreas.hansson@arm.com delete memSidePort; 10011051Sandreas.hansson@arm.com} 10111051Sandreas.hansson@arm.com 10211051Sandreas.hansson@arm.comvoid 10311051Sandreas.hansson@arm.comCache::regStats() 10411051Sandreas.hansson@arm.com{ 10511051Sandreas.hansson@arm.com BaseCache::regStats(); 10611051Sandreas.hansson@arm.com} 10711051Sandreas.hansson@arm.com 10811051Sandreas.hansson@arm.comvoid 10911051Sandreas.hansson@arm.comCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 11011051Sandreas.hansson@arm.com{ 11111051Sandreas.hansson@arm.com assert(pkt->isRequest()); 11211051Sandreas.hansson@arm.com 11311051Sandreas.hansson@arm.com uint64_t overwrite_val; 11411051Sandreas.hansson@arm.com bool overwrite_mem; 11511051Sandreas.hansson@arm.com uint64_t condition_val64; 11611051Sandreas.hansson@arm.com uint32_t condition_val32; 11711051Sandreas.hansson@arm.com 11811051Sandreas.hansson@arm.com int offset = tags->extractBlkOffset(pkt->getAddr()); 11911051Sandreas.hansson@arm.com uint8_t *blk_data = blk->data + offset; 12011051Sandreas.hansson@arm.com 12111051Sandreas.hansson@arm.com assert(sizeof(uint64_t) >= pkt->getSize()); 12211051Sandreas.hansson@arm.com 12311051Sandreas.hansson@arm.com overwrite_mem = true; 12411051Sandreas.hansson@arm.com // keep a copy of our possible write value, and copy what is at the 12511051Sandreas.hansson@arm.com // memory address into the packet 12611051Sandreas.hansson@arm.com pkt->writeData((uint8_t *)&overwrite_val); 12711051Sandreas.hansson@arm.com pkt->setData(blk_data); 12811051Sandreas.hansson@arm.com 12911051Sandreas.hansson@arm.com if (pkt->req->isCondSwap()) { 13011051Sandreas.hansson@arm.com if (pkt->getSize() == sizeof(uint64_t)) { 13111051Sandreas.hansson@arm.com condition_val64 = pkt->req->getExtraData(); 13211051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val64, blk_data, 13311051Sandreas.hansson@arm.com sizeof(uint64_t)); 13411051Sandreas.hansson@arm.com } else if (pkt->getSize() == sizeof(uint32_t)) { 13511051Sandreas.hansson@arm.com condition_val32 = (uint32_t)pkt->req->getExtraData(); 13611051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val32, blk_data, 13711051Sandreas.hansson@arm.com sizeof(uint32_t)); 13811051Sandreas.hansson@arm.com } else 13911051Sandreas.hansson@arm.com panic("Invalid size for conditional read/write\n"); 14011051Sandreas.hansson@arm.com } 14111051Sandreas.hansson@arm.com 14211051Sandreas.hansson@arm.com if (overwrite_mem) { 14311051Sandreas.hansson@arm.com std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 14411051Sandreas.hansson@arm.com blk->status |= BlkDirty; 14511051Sandreas.hansson@arm.com } 14611051Sandreas.hansson@arm.com} 14711051Sandreas.hansson@arm.com 14811051Sandreas.hansson@arm.com 14911051Sandreas.hansson@arm.comvoid 15011601Sandreas.hansson@arm.comCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, 15111601Sandreas.hansson@arm.com bool deferred_response, bool pending_downgrade) 15211051Sandreas.hansson@arm.com{ 15311051Sandreas.hansson@arm.com assert(pkt->isRequest()); 15411051Sandreas.hansson@arm.com 15511051Sandreas.hansson@arm.com assert(blk && blk->isValid()); 15611051Sandreas.hansson@arm.com // Occasionally this is not true... if we are a lower-level cache 15711051Sandreas.hansson@arm.com // satisfying a string of Read and ReadEx requests from 15811051Sandreas.hansson@arm.com // upper-level caches, a Read will mark the block as shared but we 15911051Sandreas.hansson@arm.com // can satisfy a following ReadEx anyway since we can rely on the 16011051Sandreas.hansson@arm.com // Read requester(s) to have buffered the ReadEx snoop and to 16111051Sandreas.hansson@arm.com // invalidate their blocks after receiving them. 16211284Sandreas.hansson@arm.com // assert(!pkt->needsWritable() || blk->isWritable()); 16311051Sandreas.hansson@arm.com assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 16411051Sandreas.hansson@arm.com 16511051Sandreas.hansson@arm.com // Check RMW operations first since both isRead() and 16611051Sandreas.hansson@arm.com // isWrite() will be true for them 16711051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::SwapReq) { 16811051Sandreas.hansson@arm.com cmpAndSwap(blk, pkt); 16911051Sandreas.hansson@arm.com } else if (pkt->isWrite()) { 17011284Sandreas.hansson@arm.com // we have the block in a writable state and can go ahead, 17111284Sandreas.hansson@arm.com // note that the line may be also be considered writable in 17211284Sandreas.hansson@arm.com // downstream caches along the path to memory, but always 17311284Sandreas.hansson@arm.com // Exclusive, and never Modified 17411051Sandreas.hansson@arm.com assert(blk->isWritable()); 17511284Sandreas.hansson@arm.com // Write or WriteLine at the first cache with block in writable state 17611051Sandreas.hansson@arm.com if (blk->checkWrite(pkt)) { 17711051Sandreas.hansson@arm.com pkt->writeDataToBlock(blk->data, blkSize); 17811051Sandreas.hansson@arm.com } 17911284Sandreas.hansson@arm.com // Always mark the line as dirty (and thus transition to the 18011284Sandreas.hansson@arm.com // Modified state) even if we are a failed StoreCond so we 18111284Sandreas.hansson@arm.com // supply data to any snoops that have appended themselves to 18211284Sandreas.hansson@arm.com // this cache before knowing the store will fail. 18311051Sandreas.hansson@arm.com blk->status |= BlkDirty; 18411744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s (write)\n", __func__, pkt->print()); 18511051Sandreas.hansson@arm.com } else if (pkt->isRead()) { 18611051Sandreas.hansson@arm.com if (pkt->isLLSC()) { 18711051Sandreas.hansson@arm.com blk->trackLoadLocked(pkt); 18811051Sandreas.hansson@arm.com } 18911286Sandreas.hansson@arm.com 19011286Sandreas.hansson@arm.com // all read responses have a data payload 19111286Sandreas.hansson@arm.com assert(pkt->hasRespData()); 19211051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 19311286Sandreas.hansson@arm.com 19411600Sandreas.hansson@arm.com // determine if this read is from a (coherent) cache or not 19511600Sandreas.hansson@arm.com if (pkt->fromCache()) { 19611051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 19711051Sandreas.hansson@arm.com // special handling for coherent block requests from 19811051Sandreas.hansson@arm.com // upper-level caches 19911284Sandreas.hansson@arm.com if (pkt->needsWritable()) { 20011051Sandreas.hansson@arm.com // sanity check 20111051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::ReadExReq || 20211051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq); 20311602Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 20411051Sandreas.hansson@arm.com 20511051Sandreas.hansson@arm.com // if we have a dirty copy, make sure the recipient 20611284Sandreas.hansson@arm.com // keeps it marked dirty (in the modified state) 20711051Sandreas.hansson@arm.com if (blk->isDirty()) { 20811284Sandreas.hansson@arm.com pkt->setCacheResponding(); 20911602Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 21011051Sandreas.hansson@arm.com } 21111051Sandreas.hansson@arm.com } else if (blk->isWritable() && !pending_downgrade && 21211284Sandreas.hansson@arm.com !pkt->hasSharers() && 21311051Sandreas.hansson@arm.com pkt->cmd != MemCmd::ReadCleanReq) { 21411284Sandreas.hansson@arm.com // we can give the requester a writable copy on a read 21511284Sandreas.hansson@arm.com // request if: 21611284Sandreas.hansson@arm.com // - we have a writable copy at this level (& below) 21711051Sandreas.hansson@arm.com // - we don't have a pending snoop from below 21811051Sandreas.hansson@arm.com // signaling another read request 21911051Sandreas.hansson@arm.com // - no other cache above has a copy (otherwise it 22011284Sandreas.hansson@arm.com // would have set hasSharers flag when 22111284Sandreas.hansson@arm.com // snooping the packet) 22211284Sandreas.hansson@arm.com // - the read has explicitly asked for a clean 22311284Sandreas.hansson@arm.com // copy of the line 22411051Sandreas.hansson@arm.com if (blk->isDirty()) { 22511051Sandreas.hansson@arm.com // special considerations if we're owner: 22611051Sandreas.hansson@arm.com if (!deferred_response) { 22711284Sandreas.hansson@arm.com // respond with the line in Modified state 22811284Sandreas.hansson@arm.com // (cacheResponding set, hasSharers not set) 22911284Sandreas.hansson@arm.com pkt->setCacheResponding(); 23011197Sandreas.hansson@arm.com 23111601Sandreas.hansson@arm.com // if this cache is mostly inclusive, we 23211601Sandreas.hansson@arm.com // keep the block in the Exclusive state, 23311601Sandreas.hansson@arm.com // and pass it upwards as Modified 23411601Sandreas.hansson@arm.com // (writable and dirty), hence we have 23511601Sandreas.hansson@arm.com // multiple caches, all on the same path 23611601Sandreas.hansson@arm.com // towards memory, all considering the 23711601Sandreas.hansson@arm.com // same block writable, but only one 23811601Sandreas.hansson@arm.com // considering it Modified 23911197Sandreas.hansson@arm.com 24011601Sandreas.hansson@arm.com // we get away with multiple caches (on 24111601Sandreas.hansson@arm.com // the same path to memory) considering 24211601Sandreas.hansson@arm.com // the block writeable as we always enter 24311601Sandreas.hansson@arm.com // the cache hierarchy through a cache, 24411601Sandreas.hansson@arm.com // and first snoop upwards in all other 24511601Sandreas.hansson@arm.com // branches 24611601Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 24711051Sandreas.hansson@arm.com } else { 24811051Sandreas.hansson@arm.com // if we're responding after our own miss, 24911051Sandreas.hansson@arm.com // there's a window where the recipient didn't 25011051Sandreas.hansson@arm.com // know it was getting ownership and may not 25111051Sandreas.hansson@arm.com // have responded to snoops correctly, so we 25211284Sandreas.hansson@arm.com // have to respond with a shared line 25311284Sandreas.hansson@arm.com pkt->setHasSharers(); 25411051Sandreas.hansson@arm.com } 25511051Sandreas.hansson@arm.com } 25611051Sandreas.hansson@arm.com } else { 25711051Sandreas.hansson@arm.com // otherwise only respond with a shared copy 25811284Sandreas.hansson@arm.com pkt->setHasSharers(); 25911051Sandreas.hansson@arm.com } 26011051Sandreas.hansson@arm.com } 26111602Sandreas.hansson@arm.com } else if (pkt->isUpgrade()) { 26211602Sandreas.hansson@arm.com // sanity check 26311602Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 26411602Sandreas.hansson@arm.com 26511602Sandreas.hansson@arm.com if (blk->isDirty()) { 26611602Sandreas.hansson@arm.com // we were in the Owned state, and a cache above us that 26711602Sandreas.hansson@arm.com // has the line in Shared state needs to be made aware 26811602Sandreas.hansson@arm.com // that the data it already has is in fact dirty 26911602Sandreas.hansson@arm.com pkt->setCacheResponding(); 27011602Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 27111602Sandreas.hansson@arm.com } 27211051Sandreas.hansson@arm.com } else { 27311602Sandreas.hansson@arm.com assert(pkt->isInvalidate()); 27411197Sandreas.hansson@arm.com invalidateBlock(blk); 27511744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s (invalidation)\n", __func__, 27611744Snikos.nikoleris@arm.com pkt->print()); 27711051Sandreas.hansson@arm.com } 27811051Sandreas.hansson@arm.com} 27911051Sandreas.hansson@arm.com 28011051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28111051Sandreas.hansson@arm.com// 28211051Sandreas.hansson@arm.com// Access path: requests coming in from the CPU side 28311051Sandreas.hansson@arm.com// 28411051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28511051Sandreas.hansson@arm.com 28611051Sandreas.hansson@arm.combool 28711051Sandreas.hansson@arm.comCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 28811051Sandreas.hansson@arm.com PacketList &writebacks) 28911051Sandreas.hansson@arm.com{ 29011051Sandreas.hansson@arm.com // sanity check 29111051Sandreas.hansson@arm.com assert(pkt->isRequest()); 29211051Sandreas.hansson@arm.com 29311051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 29411051Sandreas.hansson@arm.com "Should never see a write in a read-only cache %s\n", 29511051Sandreas.hansson@arm.com name()); 29611051Sandreas.hansson@arm.com 29711744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s\n", __func__, pkt->print()); 29811051Sandreas.hansson@arm.com 29911051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 30011744Snikos.nikoleris@arm.com DPRINTF(Cache, "uncacheable: %s\n", pkt->print()); 30111051Sandreas.hansson@arm.com 30211051Sandreas.hansson@arm.com // flush and invalidate any existing block 30311051Sandreas.hansson@arm.com CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure())); 30411051Sandreas.hansson@arm.com if (old_blk && old_blk->isValid()) { 30511199Sandreas.hansson@arm.com if (old_blk->isDirty() || writebackClean) 30611051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(old_blk)); 30711051Sandreas.hansson@arm.com else 30811051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(old_blk)); 30911867Snikos.nikoleris@arm.com invalidateBlock(old_blk); 31011051Sandreas.hansson@arm.com } 31111051Sandreas.hansson@arm.com 31211484Snikos.nikoleris@arm.com blk = nullptr; 31311051Sandreas.hansson@arm.com // lookupLatency is the latency in case the request is uncacheable. 31411051Sandreas.hansson@arm.com lat = lookupLatency; 31511051Sandreas.hansson@arm.com return false; 31611051Sandreas.hansson@arm.com } 31711051Sandreas.hansson@arm.com 31811051Sandreas.hansson@arm.com // Here lat is the value passed as parameter to accessBlock() function 31911051Sandreas.hansson@arm.com // that can modify its value. 32011870Snikos.nikoleris@arm.com blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat); 32111051Sandreas.hansson@arm.com 32211744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s %s\n", pkt->print(), 32311051Sandreas.hansson@arm.com blk ? "hit " + blk->print() : "miss"); 32411051Sandreas.hansson@arm.com 32511051Sandreas.hansson@arm.com 32611199Sandreas.hansson@arm.com if (pkt->isEviction()) { 32711051Sandreas.hansson@arm.com // We check for presence of block in above caches before issuing 32811051Sandreas.hansson@arm.com // Writeback or CleanEvict to write buffer. Therefore the only 32911051Sandreas.hansson@arm.com // possible cases can be of a CleanEvict packet coming from above 33011051Sandreas.hansson@arm.com // encountering a Writeback generated in this cache peer cache and 33111051Sandreas.hansson@arm.com // waiting in the write buffer. Cases of upper level peer caches 33211051Sandreas.hansson@arm.com // generating CleanEvict and Writeback or simply CleanEvict and 33311051Sandreas.hansson@arm.com // CleanEvict almost simultaneously will be caught by snoops sent out 33411051Sandreas.hansson@arm.com // by crossbar. 33511375Sandreas.hansson@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(), 33611375Sandreas.hansson@arm.com pkt->isSecure()); 33711375Sandreas.hansson@arm.com if (wb_entry) { 33811199Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 33911199Sandreas.hansson@arm.com PacketPtr wbPkt = wb_entry->getTarget()->pkt; 34011199Sandreas.hansson@arm.com assert(wbPkt->isWriteback()); 34111199Sandreas.hansson@arm.com 34211199Sandreas.hansson@arm.com if (pkt->isCleanEviction()) { 34311199Sandreas.hansson@arm.com // The CleanEvict and WritebackClean snoops into other 34411199Sandreas.hansson@arm.com // peer caches of the same level while traversing the 34511199Sandreas.hansson@arm.com // crossbar. If a copy of the block is found, the 34611199Sandreas.hansson@arm.com // packet is deleted in the crossbar. Hence, none of 34711199Sandreas.hansson@arm.com // the other upper level caches connected to this 34811199Sandreas.hansson@arm.com // cache have the block, so we can clear the 34911199Sandreas.hansson@arm.com // BLOCK_CACHED flag in the Writeback if set and 35011199Sandreas.hansson@arm.com // discard the CleanEvict by returning true. 35111199Sandreas.hansson@arm.com wbPkt->clearBlockCached(); 35211199Sandreas.hansson@arm.com return true; 35311199Sandreas.hansson@arm.com } else { 35411199Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::WritebackDirty); 35511199Sandreas.hansson@arm.com // Dirty writeback from above trumps our clean 35611199Sandreas.hansson@arm.com // writeback... discard here 35711199Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 35811375Sandreas.hansson@arm.com markInService(wb_entry); 35911199Sandreas.hansson@arm.com delete wbPkt; 36011199Sandreas.hansson@arm.com } 36111051Sandreas.hansson@arm.com } 36211051Sandreas.hansson@arm.com } 36311051Sandreas.hansson@arm.com 36411051Sandreas.hansson@arm.com // Writeback handling is special case. We can write the block into 36511051Sandreas.hansson@arm.com // the cache without having a writeable copy (or any copy at all). 36611199Sandreas.hansson@arm.com if (pkt->isWriteback()) { 36711051Sandreas.hansson@arm.com assert(blkSize == pkt->getSize()); 36811199Sandreas.hansson@arm.com 36911199Sandreas.hansson@arm.com // we could get a clean writeback while we are having 37011199Sandreas.hansson@arm.com // outstanding accesses to a block, do the simple thing for 37111199Sandreas.hansson@arm.com // now and drop the clean writeback so that we do not upset 37211199Sandreas.hansson@arm.com // any ordering/decisions about ownership already taken 37311199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackClean && 37411199Sandreas.hansson@arm.com mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) { 37511199Sandreas.hansson@arm.com DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, " 37611199Sandreas.hansson@arm.com "dropping\n", pkt->getAddr()); 37711199Sandreas.hansson@arm.com return true; 37811199Sandreas.hansson@arm.com } 37911199Sandreas.hansson@arm.com 38011484Snikos.nikoleris@arm.com if (blk == nullptr) { 38111051Sandreas.hansson@arm.com // need to do a replacement 38211051Sandreas.hansson@arm.com blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks); 38311484Snikos.nikoleris@arm.com if (blk == nullptr) { 38411051Sandreas.hansson@arm.com // no replaceable block available: give up, fwd to next level. 38511051Sandreas.hansson@arm.com incMissCount(pkt); 38611051Sandreas.hansson@arm.com return false; 38711051Sandreas.hansson@arm.com } 38811051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 38911051Sandreas.hansson@arm.com 39011051Sandreas.hansson@arm.com blk->status = (BlkValid | BlkReadable); 39111051Sandreas.hansson@arm.com if (pkt->isSecure()) { 39211051Sandreas.hansson@arm.com blk->status |= BlkSecure; 39311051Sandreas.hansson@arm.com } 39411051Sandreas.hansson@arm.com } 39511199Sandreas.hansson@arm.com // only mark the block dirty if we got a writeback command, 39611199Sandreas.hansson@arm.com // and leave it as is for a clean writeback 39711199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackDirty) { 39811199Sandreas.hansson@arm.com blk->status |= BlkDirty; 39911199Sandreas.hansson@arm.com } 40011284Sandreas.hansson@arm.com // if the packet does not have sharers, it is passing 40111284Sandreas.hansson@arm.com // writable, and we got the writeback in Modified or Exclusive 40211284Sandreas.hansson@arm.com // state, if not we are in the Owned or Shared state 40311284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 40411051Sandreas.hansson@arm.com blk->status |= BlkWritable; 40511051Sandreas.hansson@arm.com } 40611051Sandreas.hansson@arm.com // nothing else to do; writeback doesn't expect response 40711051Sandreas.hansson@arm.com assert(!pkt->needsResponse()); 40811051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 40911051Sandreas.hansson@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 41011051Sandreas.hansson@arm.com incHitCount(pkt); 41111051Sandreas.hansson@arm.com return true; 41211051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::CleanEvict) { 41311484Snikos.nikoleris@arm.com if (blk != nullptr) { 41411051Sandreas.hansson@arm.com // Found the block in the tags, need to stop CleanEvict from 41511051Sandreas.hansson@arm.com // propagating further down the hierarchy. Returning true will 41611051Sandreas.hansson@arm.com // treat the CleanEvict like a satisfied write request and delete 41711051Sandreas.hansson@arm.com // it. 41811051Sandreas.hansson@arm.com return true; 41911051Sandreas.hansson@arm.com } 42011051Sandreas.hansson@arm.com // We didn't find the block here, propagate the CleanEvict further 42111051Sandreas.hansson@arm.com // down the memory hierarchy. Returning false will treat the CleanEvict 42211051Sandreas.hansson@arm.com // like a Writeback which could not find a replaceable block so has to 42311051Sandreas.hansson@arm.com // go to next level. 42411051Sandreas.hansson@arm.com return false; 42512345Snikos.nikoleris@arm.com } else if (pkt->cmd == MemCmd::WriteClean) { 42612345Snikos.nikoleris@arm.com // WriteClean handling is a special case. We can allocate a 42712345Snikos.nikoleris@arm.com // block directly if it doesn't exist and we can update the 42812345Snikos.nikoleris@arm.com // block immediately. The WriteClean transfers the ownership 42912345Snikos.nikoleris@arm.com // of the block as well. 43012345Snikos.nikoleris@arm.com assert(blkSize == pkt->getSize()); 43112345Snikos.nikoleris@arm.com 43212345Snikos.nikoleris@arm.com if (!blk) { 43312346Snikos.nikoleris@arm.com if (pkt->writeThrough()) { 43412346Snikos.nikoleris@arm.com // if this is a write through packet, we don't try to 43512346Snikos.nikoleris@arm.com // allocate if the block is not present 43612345Snikos.nikoleris@arm.com return false; 43712346Snikos.nikoleris@arm.com } else { 43812346Snikos.nikoleris@arm.com // a writeback that misses needs to allocate a new block 43912346Snikos.nikoleris@arm.com blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), 44012346Snikos.nikoleris@arm.com writebacks); 44112346Snikos.nikoleris@arm.com if (!blk) { 44212346Snikos.nikoleris@arm.com // no replaceable block available: give up, fwd to 44312346Snikos.nikoleris@arm.com // next level. 44412346Snikos.nikoleris@arm.com incMissCount(pkt); 44512346Snikos.nikoleris@arm.com return false; 44612346Snikos.nikoleris@arm.com } 44712346Snikos.nikoleris@arm.com tags->insertBlock(pkt, blk); 44812346Snikos.nikoleris@arm.com 44912346Snikos.nikoleris@arm.com blk->status = (BlkValid | BlkReadable); 45012346Snikos.nikoleris@arm.com if (pkt->isSecure()) { 45112346Snikos.nikoleris@arm.com blk->status |= BlkSecure; 45212346Snikos.nikoleris@arm.com } 45312345Snikos.nikoleris@arm.com } 45412345Snikos.nikoleris@arm.com } 45512345Snikos.nikoleris@arm.com 45612345Snikos.nikoleris@arm.com // at this point either this is a writeback or a write-through 45712345Snikos.nikoleris@arm.com // write clean operation and the block is already in this 45812345Snikos.nikoleris@arm.com // cache, we need to update the data and the block flags 45912345Snikos.nikoleris@arm.com assert(blk); 46012346Snikos.nikoleris@arm.com if (!pkt->writeThrough()) { 46112346Snikos.nikoleris@arm.com blk->status |= BlkDirty; 46212346Snikos.nikoleris@arm.com } 46312345Snikos.nikoleris@arm.com // nothing else to do; writeback doesn't expect response 46412345Snikos.nikoleris@arm.com assert(!pkt->needsResponse()); 46512345Snikos.nikoleris@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 46612345Snikos.nikoleris@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 46712345Snikos.nikoleris@arm.com 46812345Snikos.nikoleris@arm.com incHitCount(pkt); 46912345Snikos.nikoleris@arm.com // populate the time when the block will be ready to access. 47012345Snikos.nikoleris@arm.com blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay + 47112345Snikos.nikoleris@arm.com pkt->payloadDelay; 47212346Snikos.nikoleris@arm.com // if this a write-through packet it will be sent to cache 47312346Snikos.nikoleris@arm.com // below 47412346Snikos.nikoleris@arm.com return !pkt->writeThrough(); 47511601Sandreas.hansson@arm.com } else if (blk && (pkt->needsWritable() ? blk->isWritable() : 47611601Sandreas.hansson@arm.com blk->isReadable())) { 47711051Sandreas.hansson@arm.com // OK to satisfy access 47811051Sandreas.hansson@arm.com incHitCount(pkt); 47911601Sandreas.hansson@arm.com satisfyRequest(pkt, blk); 48011601Sandreas.hansson@arm.com maintainClusivity(pkt->fromCache(), blk); 48111601Sandreas.hansson@arm.com 48211051Sandreas.hansson@arm.com return true; 48311051Sandreas.hansson@arm.com } 48411051Sandreas.hansson@arm.com 48511484Snikos.nikoleris@arm.com // Can't satisfy access normally... either no block (blk == nullptr) 48611284Sandreas.hansson@arm.com // or have block but need writable 48711051Sandreas.hansson@arm.com 48811051Sandreas.hansson@arm.com incMissCount(pkt); 48911051Sandreas.hansson@arm.com 49011484Snikos.nikoleris@arm.com if (blk == nullptr && pkt->isLLSC() && pkt->isWrite()) { 49111051Sandreas.hansson@arm.com // complete miss on store conditional... just give up now 49211051Sandreas.hansson@arm.com pkt->req->setExtraData(0); 49311051Sandreas.hansson@arm.com return true; 49411051Sandreas.hansson@arm.com } 49511051Sandreas.hansson@arm.com 49611051Sandreas.hansson@arm.com return false; 49711051Sandreas.hansson@arm.com} 49811051Sandreas.hansson@arm.com 49911051Sandreas.hansson@arm.comvoid 50011601Sandreas.hansson@arm.comCache::maintainClusivity(bool from_cache, CacheBlk *blk) 50111601Sandreas.hansson@arm.com{ 50211601Sandreas.hansson@arm.com if (from_cache && blk && blk->isValid() && !blk->isDirty() && 50311601Sandreas.hansson@arm.com clusivity == Enums::mostly_excl) { 50411601Sandreas.hansson@arm.com // if we have responded to a cache, and our block is still 50511601Sandreas.hansson@arm.com // valid, but not dirty, and this cache is mostly exclusive 50611601Sandreas.hansson@arm.com // with respect to the cache above, drop the block 50711601Sandreas.hansson@arm.com invalidateBlock(blk); 50811601Sandreas.hansson@arm.com } 50911601Sandreas.hansson@arm.com} 51011601Sandreas.hansson@arm.com 51111601Sandreas.hansson@arm.comvoid 51211051Sandreas.hansson@arm.comCache::doWritebacks(PacketList& writebacks, Tick forward_time) 51311051Sandreas.hansson@arm.com{ 51411051Sandreas.hansson@arm.com while (!writebacks.empty()) { 51511051Sandreas.hansson@arm.com PacketPtr wbPkt = writebacks.front(); 51611051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying writebacks to 51712345Snikos.nikoleris@arm.com // write buffer. 51812345Snikos.nikoleris@arm.com 51912345Snikos.nikoleris@arm.com // Call isCachedAbove for Writebacks, CleanEvicts and 52012345Snikos.nikoleris@arm.com // WriteCleans to discover if the block is cached above. 52111051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) { 52211051Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::CleanEvict) { 52311051Sandreas.hansson@arm.com // Delete CleanEvict because cached copies exist above. The 52411051Sandreas.hansson@arm.com // packet destructor will delete the request object because 52511051Sandreas.hansson@arm.com // this is a non-snoop request packet which does not require a 52611051Sandreas.hansson@arm.com // response. 52711051Sandreas.hansson@arm.com delete wbPkt; 52811199Sandreas.hansson@arm.com } else if (wbPkt->cmd == MemCmd::WritebackClean) { 52911199Sandreas.hansson@arm.com // clean writeback, do not send since the block is 53011199Sandreas.hansson@arm.com // still cached above 53111199Sandreas.hansson@arm.com assert(writebackClean); 53211199Sandreas.hansson@arm.com delete wbPkt; 53311051Sandreas.hansson@arm.com } else { 53412345Snikos.nikoleris@arm.com assert(wbPkt->cmd == MemCmd::WritebackDirty || 53512345Snikos.nikoleris@arm.com wbPkt->cmd == MemCmd::WriteClean); 53611051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag in Writeback and send below, so that 53711051Sandreas.hansson@arm.com // the Writeback does not reset the bit corresponding to this 53811051Sandreas.hansson@arm.com // address in the snoop filter below. 53911051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 54011051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 54111051Sandreas.hansson@arm.com } 54211051Sandreas.hansson@arm.com } else { 54311051Sandreas.hansson@arm.com // If the block is not cached above, send packet below. Both 54411051Sandreas.hansson@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 54511051Sandreas.hansson@arm.com // reset the bit corresponding to this address in the snoop filter 54611051Sandreas.hansson@arm.com // below. 54711051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 54811051Sandreas.hansson@arm.com } 54911051Sandreas.hansson@arm.com writebacks.pop_front(); 55011051Sandreas.hansson@arm.com } 55111051Sandreas.hansson@arm.com} 55211051Sandreas.hansson@arm.com 55311130Sali.jafri@arm.comvoid 55411130Sali.jafri@arm.comCache::doWritebacksAtomic(PacketList& writebacks) 55511130Sali.jafri@arm.com{ 55611130Sali.jafri@arm.com while (!writebacks.empty()) { 55711130Sali.jafri@arm.com PacketPtr wbPkt = writebacks.front(); 55811130Sali.jafri@arm.com // Call isCachedAbove for both Writebacks and CleanEvicts. If 55911130Sali.jafri@arm.com // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks 56011130Sali.jafri@arm.com // and discard CleanEvicts. 56111130Sali.jafri@arm.com if (isCachedAbove(wbPkt, false)) { 56212345Snikos.nikoleris@arm.com if (wbPkt->cmd == MemCmd::WritebackDirty || 56312345Snikos.nikoleris@arm.com wbPkt->cmd == MemCmd::WriteClean) { 56411130Sali.jafri@arm.com // Set BLOCK_CACHED flag in Writeback and send below, 56511130Sali.jafri@arm.com // so that the Writeback does not reset the bit 56611130Sali.jafri@arm.com // corresponding to this address in the snoop filter 56711130Sali.jafri@arm.com // below. We can discard CleanEvicts because cached 56811130Sali.jafri@arm.com // copies exist above. Atomic mode isCachedAbove 56911130Sali.jafri@arm.com // modifies packet to set BLOCK_CACHED flag 57011130Sali.jafri@arm.com memSidePort->sendAtomic(wbPkt); 57111130Sali.jafri@arm.com } 57211130Sali.jafri@arm.com } else { 57311130Sali.jafri@arm.com // If the block is not cached above, send packet below. Both 57411130Sali.jafri@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 57511130Sali.jafri@arm.com // reset the bit corresponding to this address in the snoop filter 57611130Sali.jafri@arm.com // below. 57711130Sali.jafri@arm.com memSidePort->sendAtomic(wbPkt); 57811130Sali.jafri@arm.com } 57911130Sali.jafri@arm.com writebacks.pop_front(); 58011130Sali.jafri@arm.com // In case of CleanEvicts, the packet destructor will delete the 58111130Sali.jafri@arm.com // request object because this is a non-snoop request packet which 58211130Sali.jafri@arm.com // does not require a response. 58311130Sali.jafri@arm.com delete wbPkt; 58411130Sali.jafri@arm.com } 58511130Sali.jafri@arm.com} 58611130Sali.jafri@arm.com 58711051Sandreas.hansson@arm.com 58811051Sandreas.hansson@arm.comvoid 58911051Sandreas.hansson@arm.comCache::recvTimingSnoopResp(PacketPtr pkt) 59011051Sandreas.hansson@arm.com{ 59111744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s for %s\n", __func__, pkt->print()); 59211051Sandreas.hansson@arm.com 59311051Sandreas.hansson@arm.com assert(pkt->isResponse()); 59411051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 59511051Sandreas.hansson@arm.com 59611276Sandreas.hansson@arm.com // determine if the response is from a snoop request we created 59711276Sandreas.hansson@arm.com // (in which case it should be in the outstandingSnoop), or if we 59811276Sandreas.hansson@arm.com // merely forwarded someone else's snoop request 59911276Sandreas.hansson@arm.com const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) == 60011276Sandreas.hansson@arm.com outstandingSnoop.end(); 60111276Sandreas.hansson@arm.com 60211276Sandreas.hansson@arm.com if (!forwardAsSnoop) { 60311276Sandreas.hansson@arm.com // the packet came from this cache, so sink it here and do not 60411276Sandreas.hansson@arm.com // forward it 60511051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::HardPFResp); 60611276Sandreas.hansson@arm.com 60711276Sandreas.hansson@arm.com outstandingSnoop.erase(pkt->req); 60811276Sandreas.hansson@arm.com 60911276Sandreas.hansson@arm.com DPRINTF(Cache, "Got prefetch response from above for addr " 61011276Sandreas.hansson@arm.com "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 61111051Sandreas.hansson@arm.com recvTimingResp(pkt); 61211051Sandreas.hansson@arm.com return; 61311051Sandreas.hansson@arm.com } 61411051Sandreas.hansson@arm.com 61511051Sandreas.hansson@arm.com // forwardLatency is set here because there is a response from an 61611051Sandreas.hansson@arm.com // upper level cache. 61711051Sandreas.hansson@arm.com // To pay the delay that occurs if the packet comes from the bus, 61811051Sandreas.hansson@arm.com // we charge also headerDelay. 61911051Sandreas.hansson@arm.com Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay; 62011051Sandreas.hansson@arm.com // Reset the timing of the packet. 62111051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 62211051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, snoop_resp_time); 62311051Sandreas.hansson@arm.com} 62411051Sandreas.hansson@arm.com 62511051Sandreas.hansson@arm.comvoid 62611051Sandreas.hansson@arm.comCache::promoteWholeLineWrites(PacketPtr pkt) 62711051Sandreas.hansson@arm.com{ 62811051Sandreas.hansson@arm.com // Cache line clearing instructions 62911051Sandreas.hansson@arm.com if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) && 63011051Sandreas.hansson@arm.com (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) { 63111051Sandreas.hansson@arm.com pkt->cmd = MemCmd::WriteLineReq; 63211051Sandreas.hansson@arm.com DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n"); 63311051Sandreas.hansson@arm.com } 63411051Sandreas.hansson@arm.com} 63511051Sandreas.hansson@arm.com 63611051Sandreas.hansson@arm.combool 63711051Sandreas.hansson@arm.comCache::recvTimingReq(PacketPtr pkt) 63811051Sandreas.hansson@arm.com{ 63911830Sbaz21@cam.ac.uk DPRINTF(CacheTags, "%s tags:\n%s\n", __func__, tags->print()); 64011051Sandreas.hansson@arm.com 64111051Sandreas.hansson@arm.com assert(pkt->isRequest()); 64211051Sandreas.hansson@arm.com 64311051Sandreas.hansson@arm.com // Just forward the packet if caches are disabled. 64411051Sandreas.hansson@arm.com if (system->bypassCaches()) { 64511051Sandreas.hansson@arm.com // @todo This should really enqueue the packet rather 64611051Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt); 64711051Sandreas.hansson@arm.com assert(success); 64811051Sandreas.hansson@arm.com return true; 64911051Sandreas.hansson@arm.com } 65011051Sandreas.hansson@arm.com 65111051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 65211051Sandreas.hansson@arm.com 65311284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 65411051Sandreas.hansson@arm.com // a cache above us (but not where the packet came from) is 65511284Sandreas.hansson@arm.com // responding to the request, in other words it has the line 65611284Sandreas.hansson@arm.com // in Modified or Owned state 65711744Snikos.nikoleris@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 65811744Snikos.nikoleris@arm.com pkt->print()); 65911051Sandreas.hansson@arm.com 66011284Sandreas.hansson@arm.com // if the packet needs the block to be writable, and the cache 66111284Sandreas.hansson@arm.com // that has promised to respond (setting the cache responding 66211284Sandreas.hansson@arm.com // flag) is not providing writable (it is in Owned rather than 66311284Sandreas.hansson@arm.com // the Modified state), we know that there may be other Shared 66411284Sandreas.hansson@arm.com // copies in the system; go out and invalidate them all 66511334Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 66611284Sandreas.hansson@arm.com 66711334Sandreas.hansson@arm.com // an upstream cache that had the line in Owned state 66811334Sandreas.hansson@arm.com // (dirty, but not writable), is responding and thus 66911334Sandreas.hansson@arm.com // transferring the dirty line from one branch of the 67011334Sandreas.hansson@arm.com // cache hierarchy to another 67111284Sandreas.hansson@arm.com 67211334Sandreas.hansson@arm.com // send out an express snoop and invalidate all other 67311334Sandreas.hansson@arm.com // copies (snooping a packet that needs writable is the 67411334Sandreas.hansson@arm.com // same as an invalidation), thus turning the Owned line 67511334Sandreas.hansson@arm.com // into a Modified line, note that we don't invalidate the 67611334Sandreas.hansson@arm.com // block in the current cache or any other cache on the 67711334Sandreas.hansson@arm.com // path to memory 67811051Sandreas.hansson@arm.com 67911334Sandreas.hansson@arm.com // create a downstream express snoop with cleared packet 68011334Sandreas.hansson@arm.com // flags, there is no need to allocate any data as the 68111334Sandreas.hansson@arm.com // packet is merely used to co-ordinate state transitions 68211334Sandreas.hansson@arm.com Packet *snoop_pkt = new Packet(pkt, true, false); 68311051Sandreas.hansson@arm.com 68411334Sandreas.hansson@arm.com // also reset the bus time that the original packet has 68511334Sandreas.hansson@arm.com // not yet paid for 68611334Sandreas.hansson@arm.com snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0; 68711051Sandreas.hansson@arm.com 68811334Sandreas.hansson@arm.com // make this an instantaneous express snoop, and let the 68911334Sandreas.hansson@arm.com // other caches in the system know that the another cache 69011334Sandreas.hansson@arm.com // is responding, because we have found the authorative 69111334Sandreas.hansson@arm.com // copy (Modified or Owned) that will supply the right 69211334Sandreas.hansson@arm.com // data 69311334Sandreas.hansson@arm.com snoop_pkt->setExpressSnoop(); 69411334Sandreas.hansson@arm.com snoop_pkt->setCacheResponding(); 69511051Sandreas.hansson@arm.com 69611334Sandreas.hansson@arm.com // this express snoop travels towards the memory, and at 69711334Sandreas.hansson@arm.com // every crossbar it is snooped upwards thus reaching 69811334Sandreas.hansson@arm.com // every cache in the system 69911334Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(snoop_pkt); 70011334Sandreas.hansson@arm.com // express snoops always succeed 70111334Sandreas.hansson@arm.com assert(success); 70211334Sandreas.hansson@arm.com 70311334Sandreas.hansson@arm.com // main memory will delete the snoop packet 70411051Sandreas.hansson@arm.com 70511284Sandreas.hansson@arm.com // queue for deletion, as opposed to immediate deletion, as 70611284Sandreas.hansson@arm.com // the sending cache is still relying on the packet 70711190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 70811051Sandreas.hansson@arm.com 70911334Sandreas.hansson@arm.com // no need to take any further action in this particular cache 71011334Sandreas.hansson@arm.com // as an upstram cache has already committed to responding, 71111334Sandreas.hansson@arm.com // and we have already sent out any express snoops in the 71211334Sandreas.hansson@arm.com // section above to ensure all other copies in the system are 71311334Sandreas.hansson@arm.com // invalidated 71411051Sandreas.hansson@arm.com return true; 71511051Sandreas.hansson@arm.com } 71611051Sandreas.hansson@arm.com 71711051Sandreas.hansson@arm.com // anything that is merely forwarded pays for the forward latency and 71811051Sandreas.hansson@arm.com // the delay provided by the crossbar 71911051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 72011051Sandreas.hansson@arm.com 72111051Sandreas.hansson@arm.com // We use lookupLatency here because it is used to specify the latency 72211051Sandreas.hansson@arm.com // to access. 72311051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 72411484Snikos.nikoleris@arm.com CacheBlk *blk = nullptr; 72511051Sandreas.hansson@arm.com bool satisfied = false; 72611051Sandreas.hansson@arm.com { 72711051Sandreas.hansson@arm.com PacketList writebacks; 72811051Sandreas.hansson@arm.com // Note that lat is passed by reference here. The function 72911051Sandreas.hansson@arm.com // access() calls accessBlock() which can modify lat value. 73011051Sandreas.hansson@arm.com satisfied = access(pkt, blk, lat, writebacks); 73111051Sandreas.hansson@arm.com 73211051Sandreas.hansson@arm.com // copy writebacks to write buffer here to ensure they logically 73311051Sandreas.hansson@arm.com // proceed anything happening below 73411051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 73511051Sandreas.hansson@arm.com } 73611051Sandreas.hansson@arm.com 73711051Sandreas.hansson@arm.com // Here we charge the headerDelay that takes into account the latencies 73811051Sandreas.hansson@arm.com // of the bus, if the packet comes from it. 73911051Sandreas.hansson@arm.com // The latency charged it is just lat that is the value of lookupLatency 74011051Sandreas.hansson@arm.com // modified by access() function, or if not just lookupLatency. 74111051Sandreas.hansson@arm.com // In case of a hit we are neglecting response latency. 74211051Sandreas.hansson@arm.com // In case of a miss we are neglecting forward latency. 74311051Sandreas.hansson@arm.com Tick request_time = clockEdge(lat) + pkt->headerDelay; 74411051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 74511051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 74611051Sandreas.hansson@arm.com 74711051Sandreas.hansson@arm.com // track time of availability of next prefetch, if any 74811051Sandreas.hansson@arm.com Tick next_pf_time = MaxTick; 74911051Sandreas.hansson@arm.com 75011051Sandreas.hansson@arm.com bool needsResponse = pkt->needsResponse(); 75111051Sandreas.hansson@arm.com 75211051Sandreas.hansson@arm.com if (satisfied) { 75311051Sandreas.hansson@arm.com // should never be satisfying an uncacheable access as we 75411051Sandreas.hansson@arm.com // flush and invalidate any existing block as part of the 75511051Sandreas.hansson@arm.com // lookup 75611051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 75711051Sandreas.hansson@arm.com 75811051Sandreas.hansson@arm.com // hit (for all other request types) 75911051Sandreas.hansson@arm.com 76011483Snikos.nikoleris@arm.com if (prefetcher && (prefetchOnAccess || 76111483Snikos.nikoleris@arm.com (blk && blk->wasPrefetched()))) { 76211051Sandreas.hansson@arm.com if (blk) 76311051Sandreas.hansson@arm.com blk->status &= ~BlkHWPrefetched; 76411051Sandreas.hansson@arm.com 76511051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 76611051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 76711051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 76811051Sandreas.hansson@arm.com } 76911051Sandreas.hansson@arm.com 77011051Sandreas.hansson@arm.com if (needsResponse) { 77111051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 77211051Sandreas.hansson@arm.com // @todo: Make someone pay for this 77311051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 77411051Sandreas.hansson@arm.com 77511051Sandreas.hansson@arm.com // In this case we are considering request_time that takes 77611051Sandreas.hansson@arm.com // into account the delay of the xbar, if any, and just 77711051Sandreas.hansson@arm.com // lat, neglecting responseLatency, modelling hit latency 77811051Sandreas.hansson@arm.com // just as lookupLatency or or the value of lat overriden 77911051Sandreas.hansson@arm.com // by access(), that calls accessBlock() function. 78011194Sali.jafri@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 78111051Sandreas.hansson@arm.com } else { 78211744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__, 78311744Snikos.nikoleris@arm.com pkt->print()); 78411199Sandreas.hansson@arm.com 78511190Sandreas.hansson@arm.com // queue the packet for deletion, as the sending cache is 78611190Sandreas.hansson@arm.com // still relying on it; if the block is found in access(), 78711190Sandreas.hansson@arm.com // CleanEvict and Writeback messages will be deleted 78811190Sandreas.hansson@arm.com // here as well 78911190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 79011051Sandreas.hansson@arm.com } 79111051Sandreas.hansson@arm.com } else { 79211051Sandreas.hansson@arm.com // miss 79311051Sandreas.hansson@arm.com 79411892Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 79511051Sandreas.hansson@arm.com 79611051Sandreas.hansson@arm.com // ignore any existing MSHR if we are dealing with an 79711051Sandreas.hansson@arm.com // uncacheable request 79811051Sandreas.hansson@arm.com MSHR *mshr = pkt->req->isUncacheable() ? nullptr : 79911051Sandreas.hansson@arm.com mshrQueue.findMatch(blk_addr, pkt->isSecure()); 80011051Sandreas.hansson@arm.com 80111051Sandreas.hansson@arm.com // Software prefetch handling: 80211051Sandreas.hansson@arm.com // To keep the core from waiting on data it won't look at 80311051Sandreas.hansson@arm.com // anyway, send back a response with dummy data. Miss handling 80411051Sandreas.hansson@arm.com // will continue asynchronously. Unfortunately, the core will 80511051Sandreas.hansson@arm.com // insist upon freeing original Packet/Request, so we have to 80611051Sandreas.hansson@arm.com // create a new pair with a different lifecycle. Note that this 80711051Sandreas.hansson@arm.com // processing happens before any MSHR munging on the behalf of 80811051Sandreas.hansson@arm.com // this request because this new Request will be the one stored 80911051Sandreas.hansson@arm.com // into the MSHRs, not the original. 81011051Sandreas.hansson@arm.com if (pkt->cmd.isSWPrefetch()) { 81111051Sandreas.hansson@arm.com assert(needsResponse); 81211051Sandreas.hansson@arm.com assert(pkt->req->hasPaddr()); 81311051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 81411051Sandreas.hansson@arm.com 81511051Sandreas.hansson@arm.com // There's no reason to add a prefetch as an additional target 81611051Sandreas.hansson@arm.com // to an existing MSHR. If an outstanding request is already 81711051Sandreas.hansson@arm.com // in progress, there is nothing for the prefetch to do. 81811051Sandreas.hansson@arm.com // If this is the case, we don't even create a request at all. 81911051Sandreas.hansson@arm.com PacketPtr pf = nullptr; 82011051Sandreas.hansson@arm.com 82111051Sandreas.hansson@arm.com if (!mshr) { 82211051Sandreas.hansson@arm.com // copy the request and create a new SoftPFReq packet 82311051Sandreas.hansson@arm.com RequestPtr req = new Request(pkt->req->getPaddr(), 82411051Sandreas.hansson@arm.com pkt->req->getSize(), 82511051Sandreas.hansson@arm.com pkt->req->getFlags(), 82611051Sandreas.hansson@arm.com pkt->req->masterId()); 82711051Sandreas.hansson@arm.com pf = new Packet(req, pkt->cmd); 82811051Sandreas.hansson@arm.com pf->allocate(); 82911051Sandreas.hansson@arm.com assert(pf->getAddr() == pkt->getAddr()); 83011051Sandreas.hansson@arm.com assert(pf->getSize() == pkt->getSize()); 83111051Sandreas.hansson@arm.com } 83211051Sandreas.hansson@arm.com 83311051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 83411286Sandreas.hansson@arm.com 83511051Sandreas.hansson@arm.com // request_time is used here, taking into account lat and the delay 83611051Sandreas.hansson@arm.com // charged if the packet comes from the xbar. 83711194Sali.jafri@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 83811051Sandreas.hansson@arm.com 83911051Sandreas.hansson@arm.com // If an outstanding request is in progress (we found an 84011051Sandreas.hansson@arm.com // MSHR) this is set to null 84111051Sandreas.hansson@arm.com pkt = pf; 84211051Sandreas.hansson@arm.com } 84311051Sandreas.hansson@arm.com 84411051Sandreas.hansson@arm.com if (mshr) { 84511051Sandreas.hansson@arm.com /// MSHR hit 84611051Sandreas.hansson@arm.com /// @note writebacks will be checked in getNextMSHR() 84711051Sandreas.hansson@arm.com /// for any conflicting requests to the same block 84811051Sandreas.hansson@arm.com 84911051Sandreas.hansson@arm.com //@todo remove hw_pf here 85011051Sandreas.hansson@arm.com 85111051Sandreas.hansson@arm.com // Coalesce unless it was a software prefetch (see above). 85211051Sandreas.hansson@arm.com if (pkt) { 85311199Sandreas.hansson@arm.com assert(!pkt->isWriteback()); 85411199Sandreas.hansson@arm.com // CleanEvicts corresponding to blocks which have 85511199Sandreas.hansson@arm.com // outstanding requests in MSHRs are simply sunk here 85611051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::CleanEvict) { 85711190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 85811051Sandreas.hansson@arm.com } else { 85911744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s coalescing MSHR for %s\n", __func__, 86011744Snikos.nikoleris@arm.com pkt->print()); 86111051Sandreas.hansson@arm.com 86211051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 86311051Sandreas.hansson@arm.com mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 86411051Sandreas.hansson@arm.com // We use forward_time here because it is the same 86511051Sandreas.hansson@arm.com // considering new targets. We have multiple 86611051Sandreas.hansson@arm.com // requests for the same address here. It 86711051Sandreas.hansson@arm.com // specifies the latency to allocate an internal 86811051Sandreas.hansson@arm.com // buffer and to schedule an event to the queued 86911051Sandreas.hansson@arm.com // port and also takes into account the additional 87011051Sandreas.hansson@arm.com // delay of the xbar. 87111197Sandreas.hansson@arm.com mshr->allocateTarget(pkt, forward_time, order++, 87211197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 87311051Sandreas.hansson@arm.com if (mshr->getNumTargets() == numTarget) { 87411051Sandreas.hansson@arm.com noTargetMSHR = mshr; 87511051Sandreas.hansson@arm.com setBlocked(Blocked_NoTargets); 87611051Sandreas.hansson@arm.com // need to be careful with this... if this mshr isn't 87711051Sandreas.hansson@arm.com // ready yet (i.e. time > curTick()), we don't want to 87811051Sandreas.hansson@arm.com // move it ahead of mshrs that are ready 87911051Sandreas.hansson@arm.com // mshrQueue.moveToFront(mshr); 88011051Sandreas.hansson@arm.com } 88111051Sandreas.hansson@arm.com } 88211051Sandreas.hansson@arm.com // We should call the prefetcher reguardless if the request is 88311483Snikos.nikoleris@arm.com // satisfied or not, reguardless if the request is in the MSHR 88411483Snikos.nikoleris@arm.com // or not. The request could be a ReadReq hit, but still not 88511051Sandreas.hansson@arm.com // satisfied (potentially because of a prior write to the same 88611051Sandreas.hansson@arm.com // cache line. So, even when not satisfied, tehre is an MSHR 88711483Snikos.nikoleris@arm.com // already allocated for this, we need to let the prefetcher 88811483Snikos.nikoleris@arm.com // know about the request 88911051Sandreas.hansson@arm.com if (prefetcher) { 89011051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 89111051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 89211051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 89311051Sandreas.hansson@arm.com } 89411051Sandreas.hansson@arm.com } 89511051Sandreas.hansson@arm.com } else { 89611051Sandreas.hansson@arm.com // no MSHR 89711051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 89811051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 89911051Sandreas.hansson@arm.com mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++; 90011051Sandreas.hansson@arm.com } else { 90111051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 90211051Sandreas.hansson@arm.com } 90311051Sandreas.hansson@arm.com 90412345Snikos.nikoleris@arm.com if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean || 90511051Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 90611051Sandreas.hansson@arm.com // We use forward_time here because there is an 90711051Sandreas.hansson@arm.com // uncached memory write, forwarded to WriteBuffer. 90811051Sandreas.hansson@arm.com allocateWriteBuffer(pkt, forward_time); 90911051Sandreas.hansson@arm.com } else { 91011051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 91111051Sandreas.hansson@arm.com // should have flushed and have no valid block 91211051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 91311051Sandreas.hansson@arm.com 91411051Sandreas.hansson@arm.com // If we have a write miss to a valid block, we 91511051Sandreas.hansson@arm.com // need to mark the block non-readable. Otherwise 91611051Sandreas.hansson@arm.com // if we allow reads while there's an outstanding 91711051Sandreas.hansson@arm.com // write miss, the read could return stale data 91811051Sandreas.hansson@arm.com // out of the cache block... a more aggressive 91911051Sandreas.hansson@arm.com // system could detect the overlap (if any) and 92011051Sandreas.hansson@arm.com // forward data out of the MSHRs, but we don't do 92111051Sandreas.hansson@arm.com // that yet. Note that we do need to leave the 92211051Sandreas.hansson@arm.com // block valid so that it stays in the cache, in 92311051Sandreas.hansson@arm.com // case we get an upgrade response (and hence no 92411051Sandreas.hansson@arm.com // new data) when the write miss completes. 92511051Sandreas.hansson@arm.com // As long as CPUs do proper store/load forwarding 92611051Sandreas.hansson@arm.com // internally, and have a sufficiently weak memory 92711051Sandreas.hansson@arm.com // model, this is probably unnecessary, but at some 92811051Sandreas.hansson@arm.com // point it must have seemed like we needed it... 92911284Sandreas.hansson@arm.com assert(pkt->needsWritable()); 93011051Sandreas.hansson@arm.com assert(!blk->isWritable()); 93111051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 93211051Sandreas.hansson@arm.com } 93311051Sandreas.hansson@arm.com // Here we are using forward_time, modelling the latency of 93411051Sandreas.hansson@arm.com // a miss (outbound) just as forwardLatency, neglecting the 93511051Sandreas.hansson@arm.com // lookupLatency component. 93611051Sandreas.hansson@arm.com allocateMissBuffer(pkt, forward_time); 93711051Sandreas.hansson@arm.com } 93811051Sandreas.hansson@arm.com 93911051Sandreas.hansson@arm.com if (prefetcher) { 94011051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 94111051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 94211051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 94311051Sandreas.hansson@arm.com } 94411051Sandreas.hansson@arm.com } 94511051Sandreas.hansson@arm.com } 94611051Sandreas.hansson@arm.com 94711051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 94811051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 94911051Sandreas.hansson@arm.com 95011051Sandreas.hansson@arm.com return true; 95111051Sandreas.hansson@arm.com} 95211051Sandreas.hansson@arm.com 95311051Sandreas.hansson@arm.comPacketPtr 95411452Sandreas.hansson@arm.comCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 95511452Sandreas.hansson@arm.com bool needsWritable) const 95611051Sandreas.hansson@arm.com{ 95711452Sandreas.hansson@arm.com // should never see evictions here 95811452Sandreas.hansson@arm.com assert(!cpu_pkt->isEviction()); 95911452Sandreas.hansson@arm.com 96011051Sandreas.hansson@arm.com bool blkValid = blk && blk->isValid(); 96111051Sandreas.hansson@arm.com 96211452Sandreas.hansson@arm.com if (cpu_pkt->req->isUncacheable() || 96311745Sandreas.hansson@arm.com (!blkValid && cpu_pkt->isUpgrade()) || 96411745Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::InvalidateReq) { 96511452Sandreas.hansson@arm.com // uncacheable requests and upgrades from upper-level caches 96611452Sandreas.hansson@arm.com // that missed completely just go through as is 96711452Sandreas.hansson@arm.com return nullptr; 96811051Sandreas.hansson@arm.com } 96911051Sandreas.hansson@arm.com 97011051Sandreas.hansson@arm.com assert(cpu_pkt->needsResponse()); 97111051Sandreas.hansson@arm.com 97211051Sandreas.hansson@arm.com MemCmd cmd; 97311051Sandreas.hansson@arm.com // @TODO make useUpgrades a parameter. 97411051Sandreas.hansson@arm.com // Note that ownership protocols require upgrade, otherwise a 97511051Sandreas.hansson@arm.com // write miss on a shared owned block will generate a ReadExcl, 97611051Sandreas.hansson@arm.com // which will clobber the owned copy. 97711051Sandreas.hansson@arm.com const bool useUpgrades = true; 97811747Snikos.nikoleris@arm.com if (cpu_pkt->cmd == MemCmd::WriteLineReq) { 97911747Snikos.nikoleris@arm.com assert(!blkValid || !blk->isWritable()); 98011747Snikos.nikoleris@arm.com // forward as invalidate to all other caches, this gives us 98111747Snikos.nikoleris@arm.com // the line in Exclusive state, and invalidates all other 98211747Snikos.nikoleris@arm.com // copies 98311747Snikos.nikoleris@arm.com cmd = MemCmd::InvalidateReq; 98411747Snikos.nikoleris@arm.com } else if (blkValid && useUpgrades) { 98511284Sandreas.hansson@arm.com // only reason to be here is that blk is read only and we need 98611284Sandreas.hansson@arm.com // it to be writable 98711284Sandreas.hansson@arm.com assert(needsWritable); 98811051Sandreas.hansson@arm.com assert(!blk->isWritable()); 98911051Sandreas.hansson@arm.com cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq; 99011051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq || 99111051Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::StoreCondFailReq) { 99211051Sandreas.hansson@arm.com // Even though this SC will fail, we still need to send out the 99311051Sandreas.hansson@arm.com // request and get the data to supply it to other snoopers in the case 99411051Sandreas.hansson@arm.com // where the determination the StoreCond fails is delayed due to 99511051Sandreas.hansson@arm.com // all caches not being on the same local bus. 99611051Sandreas.hansson@arm.com cmd = MemCmd::SCUpgradeFailReq; 99711051Sandreas.hansson@arm.com } else { 99811051Sandreas.hansson@arm.com // block is invalid 99911284Sandreas.hansson@arm.com cmd = needsWritable ? MemCmd::ReadExReq : 100011051Sandreas.hansson@arm.com (isReadOnly ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq); 100111051Sandreas.hansson@arm.com } 100211051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize); 100311051Sandreas.hansson@arm.com 100411284Sandreas.hansson@arm.com // if there are upstream caches that have already marked the 100511284Sandreas.hansson@arm.com // packet as having sharers (not passing writable), pass that info 100611284Sandreas.hansson@arm.com // downstream 100711602Sandreas.hansson@arm.com if (cpu_pkt->hasSharers() && !needsWritable) { 100811051Sandreas.hansson@arm.com // note that cpu_pkt may have spent a considerable time in the 100911051Sandreas.hansson@arm.com // MSHR queue and that the information could possibly be out 101011051Sandreas.hansson@arm.com // of date, however, there is no harm in conservatively 101111284Sandreas.hansson@arm.com // assuming the block has sharers 101211284Sandreas.hansson@arm.com pkt->setHasSharers(); 101311744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: passing hasSharers from %s to %s\n", 101411744Snikos.nikoleris@arm.com __func__, cpu_pkt->print(), pkt->print()); 101511051Sandreas.hansson@arm.com } 101611051Sandreas.hansson@arm.com 101711051Sandreas.hansson@arm.com // the packet should be block aligned 101811892Snikos.nikoleris@arm.com assert(pkt->getAddr() == pkt->getBlockAddr(blkSize)); 101911051Sandreas.hansson@arm.com 102011051Sandreas.hansson@arm.com pkt->allocate(); 102111744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: created %s from %s\n", __func__, pkt->print(), 102211744Snikos.nikoleris@arm.com cpu_pkt->print()); 102311051Sandreas.hansson@arm.com return pkt; 102411051Sandreas.hansson@arm.com} 102511051Sandreas.hansson@arm.com 102611051Sandreas.hansson@arm.com 102711051Sandreas.hansson@arm.comTick 102811051Sandreas.hansson@arm.comCache::recvAtomic(PacketPtr pkt) 102911051Sandreas.hansson@arm.com{ 103011051Sandreas.hansson@arm.com // We are in atomic mode so we pay just for lookupLatency here. 103111051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 103211051Sandreas.hansson@arm.com 103311051Sandreas.hansson@arm.com // Forward the request if the system is in cache bypass mode. 103411051Sandreas.hansson@arm.com if (system->bypassCaches()) 103511051Sandreas.hansson@arm.com return ticksToCycles(memSidePort->sendAtomic(pkt)); 103611051Sandreas.hansson@arm.com 103711051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 103811051Sandreas.hansson@arm.com 103911333Sandreas.hansson@arm.com // follow the same flow as in recvTimingReq, and check if a cache 104011333Sandreas.hansson@arm.com // above us is responding 104111284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 104211744Snikos.nikoleris@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 104311744Snikos.nikoleris@arm.com pkt->print()); 104411333Sandreas.hansson@arm.com 104511333Sandreas.hansson@arm.com // if a cache is responding, and it had the line in Owned 104611333Sandreas.hansson@arm.com // rather than Modified state, we need to invalidate any 104711333Sandreas.hansson@arm.com // copies that are not on the same path to memory 104811334Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 104911334Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 105011051Sandreas.hansson@arm.com 105111051Sandreas.hansson@arm.com return lat * clockPeriod(); 105211051Sandreas.hansson@arm.com } 105311051Sandreas.hansson@arm.com 105411051Sandreas.hansson@arm.com // should assert here that there are no outstanding MSHRs or 105511051Sandreas.hansson@arm.com // writebacks... that would mean that someone used an atomic 105611051Sandreas.hansson@arm.com // access in timing mode 105711051Sandreas.hansson@arm.com 105811484Snikos.nikoleris@arm.com CacheBlk *blk = nullptr; 105911051Sandreas.hansson@arm.com PacketList writebacks; 106011051Sandreas.hansson@arm.com bool satisfied = access(pkt, blk, lat, writebacks); 106111051Sandreas.hansson@arm.com 106211051Sandreas.hansson@arm.com // handle writebacks resulting from the access here to ensure they 106311051Sandreas.hansson@arm.com // logically proceed anything happening below 106411130Sali.jafri@arm.com doWritebacksAtomic(writebacks); 106511051Sandreas.hansson@arm.com 106611051Sandreas.hansson@arm.com if (!satisfied) { 106711051Sandreas.hansson@arm.com // MISS 106811051Sandreas.hansson@arm.com 106911452Sandreas.hansson@arm.com // deal with the packets that go through the write path of 107012345Snikos.nikoleris@arm.com // the cache, i.e. any evictions and writes 107112345Snikos.nikoleris@arm.com if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean || 107211452Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 107311452Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 107411452Sandreas.hansson@arm.com return lat * clockPeriod(); 107511452Sandreas.hansson@arm.com } 107611452Sandreas.hansson@arm.com // only misses left 107711452Sandreas.hansson@arm.com 107811452Sandreas.hansson@arm.com PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable()); 107911051Sandreas.hansson@arm.com 108011484Snikos.nikoleris@arm.com bool is_forward = (bus_pkt == nullptr); 108111051Sandreas.hansson@arm.com 108211051Sandreas.hansson@arm.com if (is_forward) { 108311051Sandreas.hansson@arm.com // just forwarding the same request to the next level 108411051Sandreas.hansson@arm.com // no local cache operation involved 108511051Sandreas.hansson@arm.com bus_pkt = pkt; 108611051Sandreas.hansson@arm.com } 108711051Sandreas.hansson@arm.com 108811744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Sending an atomic %s\n", __func__, 108911744Snikos.nikoleris@arm.com bus_pkt->print()); 109011051Sandreas.hansson@arm.com 109111051Sandreas.hansson@arm.com#if TRACING_ON 109211051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 109311051Sandreas.hansson@arm.com#endif 109411051Sandreas.hansson@arm.com 109511051Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt)); 109611051Sandreas.hansson@arm.com 109711452Sandreas.hansson@arm.com bool is_invalidate = bus_pkt->isInvalidate(); 109811452Sandreas.hansson@arm.com 109911051Sandreas.hansson@arm.com // We are now dealing with the response handling 110011744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Receive response: %s in state %i\n", __func__, 110111744Snikos.nikoleris@arm.com bus_pkt->print(), old_state); 110211051Sandreas.hansson@arm.com 110311051Sandreas.hansson@arm.com // If packet was a forward, the response (if any) is already 110411051Sandreas.hansson@arm.com // in place in the bus_pkt == pkt structure, so we don't need 110511051Sandreas.hansson@arm.com // to do anything. Otherwise, use the separate bus_pkt to 110611051Sandreas.hansson@arm.com // generate response to pkt and then delete it. 110711051Sandreas.hansson@arm.com if (!is_forward) { 110811051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 110911051Sandreas.hansson@arm.com assert(bus_pkt->isResponse()); 111011051Sandreas.hansson@arm.com if (bus_pkt->isError()) { 111111051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 111211051Sandreas.hansson@arm.com pkt->copyError(bus_pkt); 111311051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::WriteLineReq) { 111411051Sandreas.hansson@arm.com // note the use of pkt, not bus_pkt here. 111511051Sandreas.hansson@arm.com 111611051Sandreas.hansson@arm.com // write-line request to the cache that promoted 111711051Sandreas.hansson@arm.com // the write to a whole line 111811197Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks, 111911197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 112011452Sandreas.hansson@arm.com assert(blk != NULL); 112111452Sandreas.hansson@arm.com is_invalidate = false; 112211601Sandreas.hansson@arm.com satisfyRequest(pkt, blk); 112311051Sandreas.hansson@arm.com } else if (bus_pkt->isRead() || 112411051Sandreas.hansson@arm.com bus_pkt->cmd == MemCmd::UpgradeResp) { 112511051Sandreas.hansson@arm.com // we're updating cache state to allow us to 112611051Sandreas.hansson@arm.com // satisfy the upstream request from the cache 112711197Sandreas.hansson@arm.com blk = handleFill(bus_pkt, blk, writebacks, 112811197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 112911601Sandreas.hansson@arm.com satisfyRequest(pkt, blk); 113011601Sandreas.hansson@arm.com maintainClusivity(pkt->fromCache(), blk); 113111051Sandreas.hansson@arm.com } else { 113211051Sandreas.hansson@arm.com // we're satisfying the upstream request without 113311051Sandreas.hansson@arm.com // modifying cache state, e.g., a write-through 113411051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 113511051Sandreas.hansson@arm.com } 113611051Sandreas.hansson@arm.com } 113711051Sandreas.hansson@arm.com delete bus_pkt; 113811051Sandreas.hansson@arm.com } 113911452Sandreas.hansson@arm.com 114011452Sandreas.hansson@arm.com if (is_invalidate && blk && blk->isValid()) { 114111452Sandreas.hansson@arm.com invalidateBlock(blk); 114211452Sandreas.hansson@arm.com } 114311051Sandreas.hansson@arm.com } 114411051Sandreas.hansson@arm.com 114511051Sandreas.hansson@arm.com // Note that we don't invoke the prefetcher at all in atomic mode. 114611051Sandreas.hansson@arm.com // It's not clear how to do it properly, particularly for 114711051Sandreas.hansson@arm.com // prefetchers that aggressively generate prefetch candidates and 114811051Sandreas.hansson@arm.com // rely on bandwidth contention to throttle them; these will tend 114911051Sandreas.hansson@arm.com // to pollute the cache in atomic mode since there is no bandwidth 115011051Sandreas.hansson@arm.com // contention. If we ever do want to enable prefetching in atomic 115111051Sandreas.hansson@arm.com // mode, though, this is the place to do it... see timingAccess() 115211051Sandreas.hansson@arm.com // for an example (though we'd want to issue the prefetch(es) 115311051Sandreas.hansson@arm.com // immediately rather than calling requestMemSideBus() as we do 115411051Sandreas.hansson@arm.com // there). 115511051Sandreas.hansson@arm.com 115611197Sandreas.hansson@arm.com // do any writebacks resulting from the response handling 115711130Sali.jafri@arm.com doWritebacksAtomic(writebacks); 115811051Sandreas.hansson@arm.com 115911197Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and if so 116011197Sandreas.hansson@arm.com // clear it out, but only do so after the call to recvAtomic is 116111197Sandreas.hansson@arm.com // finished so that any downstream observers (such as a snoop 116211197Sandreas.hansson@arm.com // filter), first see the fill, and only then see the eviction 116311197Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 116411197Sandreas.hansson@arm.com // the atomic CPU calls recvAtomic for fetch and load/store 116511197Sandreas.hansson@arm.com // sequentuially, and we may already have a tempBlock 116611197Sandreas.hansson@arm.com // writeback from the fetch that we have not yet sent 116711197Sandreas.hansson@arm.com if (tempBlockWriteback) { 116811197Sandreas.hansson@arm.com // if that is the case, write the prevoius one back, and 116911197Sandreas.hansson@arm.com // do not schedule any new event 117011197Sandreas.hansson@arm.com writebackTempBlockAtomic(); 117111197Sandreas.hansson@arm.com } else { 117211197Sandreas.hansson@arm.com // the writeback/clean eviction happens after the call to 117311197Sandreas.hansson@arm.com // recvAtomic has finished (but before any successive 117411197Sandreas.hansson@arm.com // calls), so that the response handling from the fill is 117511197Sandreas.hansson@arm.com // allowed to happen first 117611197Sandreas.hansson@arm.com schedule(writebackTempBlockAtomicEvent, curTick()); 117711197Sandreas.hansson@arm.com } 117811197Sandreas.hansson@arm.com 117911199Sandreas.hansson@arm.com tempBlockWriteback = (blk->isDirty() || writebackClean) ? 118011199Sandreas.hansson@arm.com writebackBlk(blk) : cleanEvictBlk(blk); 118111867Snikos.nikoleris@arm.com invalidateBlock(blk); 118211197Sandreas.hansson@arm.com } 118311197Sandreas.hansson@arm.com 118411051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 118511051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 118611051Sandreas.hansson@arm.com } 118711051Sandreas.hansson@arm.com 118811051Sandreas.hansson@arm.com return lat * clockPeriod(); 118911051Sandreas.hansson@arm.com} 119011051Sandreas.hansson@arm.com 119111051Sandreas.hansson@arm.com 119211051Sandreas.hansson@arm.comvoid 119311051Sandreas.hansson@arm.comCache::functionalAccess(PacketPtr pkt, bool fromCpuSide) 119411051Sandreas.hansson@arm.com{ 119511051Sandreas.hansson@arm.com if (system->bypassCaches()) { 119611051Sandreas.hansson@arm.com // Packets from the memory side are snoop request and 119711051Sandreas.hansson@arm.com // shouldn't happen in bypass mode. 119811051Sandreas.hansson@arm.com assert(fromCpuSide); 119911051Sandreas.hansson@arm.com 120011051Sandreas.hansson@arm.com // The cache should be flushed if we are in cache bypass mode, 120111051Sandreas.hansson@arm.com // so we don't need to check if we need to update anything. 120211051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 120311051Sandreas.hansson@arm.com return; 120411051Sandreas.hansson@arm.com } 120511051Sandreas.hansson@arm.com 120611892Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 120711051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 120811051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 120911051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 121011051Sandreas.hansson@arm.com 121111051Sandreas.hansson@arm.com pkt->pushLabel(name()); 121211051Sandreas.hansson@arm.com 121311051Sandreas.hansson@arm.com CacheBlkPrintWrapper cbpw(blk); 121411051Sandreas.hansson@arm.com 121511051Sandreas.hansson@arm.com // Note that just because an L2/L3 has valid data doesn't mean an 121611051Sandreas.hansson@arm.com // L1 doesn't have a more up-to-date modified copy that still 121711051Sandreas.hansson@arm.com // needs to be found. As a result we always update the request if 121811051Sandreas.hansson@arm.com // we have it, but only declare it satisfied if we are the owner. 121911051Sandreas.hansson@arm.com 122011051Sandreas.hansson@arm.com // see if we have data at all (owned or otherwise) 122111051Sandreas.hansson@arm.com bool have_data = blk && blk->isValid() 122211051Sandreas.hansson@arm.com && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize, 122311051Sandreas.hansson@arm.com blk->data); 122411051Sandreas.hansson@arm.com 122511284Sandreas.hansson@arm.com // data we have is dirty if marked as such or if we have an 122611284Sandreas.hansson@arm.com // in-service MSHR that is pending a modified line 122711051Sandreas.hansson@arm.com bool have_dirty = 122811051Sandreas.hansson@arm.com have_data && (blk->isDirty() || 122911284Sandreas.hansson@arm.com (mshr && mshr->inService && mshr->isPendingModified())); 123011051Sandreas.hansson@arm.com 123111051Sandreas.hansson@arm.com bool done = have_dirty 123211051Sandreas.hansson@arm.com || cpuSidePort->checkFunctional(pkt) 123311051Sandreas.hansson@arm.com || mshrQueue.checkFunctional(pkt, blk_addr) 123411051Sandreas.hansson@arm.com || writeBuffer.checkFunctional(pkt, blk_addr) 123511051Sandreas.hansson@arm.com || memSidePort->checkFunctional(pkt); 123611051Sandreas.hansson@arm.com 123711744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: %s %s%s%s\n", __func__, pkt->print(), 123811051Sandreas.hansson@arm.com (blk && blk->isValid()) ? "valid " : "", 123911051Sandreas.hansson@arm.com have_data ? "data " : "", done ? "done " : ""); 124011051Sandreas.hansson@arm.com 124111051Sandreas.hansson@arm.com // We're leaving the cache, so pop cache->name() label 124211051Sandreas.hansson@arm.com pkt->popLabel(); 124311051Sandreas.hansson@arm.com 124411051Sandreas.hansson@arm.com if (done) { 124511051Sandreas.hansson@arm.com pkt->makeResponse(); 124611051Sandreas.hansson@arm.com } else { 124711051Sandreas.hansson@arm.com // if it came as a request from the CPU side then make sure it 124811051Sandreas.hansson@arm.com // continues towards the memory side 124911051Sandreas.hansson@arm.com if (fromCpuSide) { 125011051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 125111485Snikos.nikoleris@arm.com } else if (cpuSidePort->isSnooping()) { 125211051Sandreas.hansson@arm.com // if it came from the memory side, it must be a snoop request 125311051Sandreas.hansson@arm.com // and we should only forward it if we are forwarding snoops 125411051Sandreas.hansson@arm.com cpuSidePort->sendFunctionalSnoop(pkt); 125511051Sandreas.hansson@arm.com } 125611051Sandreas.hansson@arm.com } 125711051Sandreas.hansson@arm.com} 125811051Sandreas.hansson@arm.com 125911051Sandreas.hansson@arm.com 126011051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 126111051Sandreas.hansson@arm.com// 126211051Sandreas.hansson@arm.com// Response handling: responses from the memory side 126311051Sandreas.hansson@arm.com// 126411051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 126511051Sandreas.hansson@arm.com 126611051Sandreas.hansson@arm.com 126711051Sandreas.hansson@arm.comvoid 126811375Sandreas.hansson@arm.comCache::handleUncacheableWriteResp(PacketPtr pkt) 126911375Sandreas.hansson@arm.com{ 127011375Sandreas.hansson@arm.com Tick completion_time = clockEdge(responseLatency) + 127111375Sandreas.hansson@arm.com pkt->headerDelay + pkt->payloadDelay; 127211375Sandreas.hansson@arm.com 127311453Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 127411453Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 127511375Sandreas.hansson@arm.com 127611453Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(pkt, completion_time, true); 127711375Sandreas.hansson@arm.com} 127811375Sandreas.hansson@arm.com 127911375Sandreas.hansson@arm.comvoid 128011051Sandreas.hansson@arm.comCache::recvTimingResp(PacketPtr pkt) 128111051Sandreas.hansson@arm.com{ 128211051Sandreas.hansson@arm.com assert(pkt->isResponse()); 128311051Sandreas.hansson@arm.com 128411051Sandreas.hansson@arm.com // all header delay should be paid for by the crossbar, unless 128511051Sandreas.hansson@arm.com // this is a prefetch response from above 128611051Sandreas.hansson@arm.com panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 128711051Sandreas.hansson@arm.com "%s saw a non-zero packet delay\n", name()); 128811051Sandreas.hansson@arm.com 128911051Sandreas.hansson@arm.com bool is_error = pkt->isError(); 129011051Sandreas.hansson@arm.com 129111051Sandreas.hansson@arm.com if (is_error) { 129211744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Cache received %s with error\n", __func__, 129311744Snikos.nikoleris@arm.com pkt->print()); 129411051Sandreas.hansson@arm.com } 129511051Sandreas.hansson@arm.com 129611744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Handling response %s\n", __func__, 129711744Snikos.nikoleris@arm.com pkt->print()); 129811051Sandreas.hansson@arm.com 129911375Sandreas.hansson@arm.com // if this is a write, we should be looking at an uncacheable 130011375Sandreas.hansson@arm.com // write 130111375Sandreas.hansson@arm.com if (pkt->isWrite()) { 130211375Sandreas.hansson@arm.com assert(pkt->req->isUncacheable()); 130311375Sandreas.hansson@arm.com handleUncacheableWriteResp(pkt); 130411375Sandreas.hansson@arm.com return; 130511375Sandreas.hansson@arm.com } 130611375Sandreas.hansson@arm.com 130711375Sandreas.hansson@arm.com // we have dealt with any (uncacheable) writes above, from here on 130811375Sandreas.hansson@arm.com // we know we are dealing with an MSHR due to a miss or a prefetch 130911453Sandreas.hansson@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState()); 131011375Sandreas.hansson@arm.com assert(mshr); 131111051Sandreas.hansson@arm.com 131211051Sandreas.hansson@arm.com if (mshr == noTargetMSHR) { 131311051Sandreas.hansson@arm.com // we always clear at least one target 131411051Sandreas.hansson@arm.com clearBlocked(Blocked_NoTargets); 131511484Snikos.nikoleris@arm.com noTargetMSHR = nullptr; 131611051Sandreas.hansson@arm.com } 131711051Sandreas.hansson@arm.com 131811051Sandreas.hansson@arm.com // Initial target is used just for stats 131911051Sandreas.hansson@arm.com MSHR::Target *initial_tgt = mshr->getTarget(); 132011051Sandreas.hansson@arm.com int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 132111051Sandreas.hansson@arm.com Tick miss_latency = curTick() - initial_tgt->recvTime; 132211051Sandreas.hansson@arm.com 132311051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 132411051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 132511051Sandreas.hansson@arm.com mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 132611051Sandreas.hansson@arm.com miss_latency; 132711051Sandreas.hansson@arm.com } else { 132811051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 132911051Sandreas.hansson@arm.com mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 133011051Sandreas.hansson@arm.com miss_latency; 133111051Sandreas.hansson@arm.com } 133211051Sandreas.hansson@arm.com 133311375Sandreas.hansson@arm.com bool wasFull = mshrQueue.isFull(); 133411375Sandreas.hansson@arm.com 133511375Sandreas.hansson@arm.com PacketList writebacks; 133611375Sandreas.hansson@arm.com 133711375Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 133811375Sandreas.hansson@arm.com 133911284Sandreas.hansson@arm.com // upgrade deferred targets if the response has no sharers, and is 134011284Sandreas.hansson@arm.com // thus passing writable 134111284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 134211284Sandreas.hansson@arm.com mshr->promoteWritable(); 134311177Sandreas.hansson@arm.com } 134411177Sandreas.hansson@arm.com 134511051Sandreas.hansson@arm.com bool is_fill = !mshr->isForward && 134611051Sandreas.hansson@arm.com (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp); 134711051Sandreas.hansson@arm.com 134811177Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 134911177Sandreas.hansson@arm.com 135011051Sandreas.hansson@arm.com if (is_fill && !is_error) { 135111051Sandreas.hansson@arm.com DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 135211051Sandreas.hansson@arm.com pkt->getAddr()); 135311051Sandreas.hansson@arm.com 135411741Snikos.nikoleris@arm.com blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill()); 135511484Snikos.nikoleris@arm.com assert(blk != nullptr); 135611051Sandreas.hansson@arm.com } 135711051Sandreas.hansson@arm.com 135811051Sandreas.hansson@arm.com // allow invalidation responses originating from write-line 135911051Sandreas.hansson@arm.com // requests to be discarded 136011136Sandreas.hansson@arm.com bool is_invalidate = pkt->isInvalidate(); 136111051Sandreas.hansson@arm.com 136211051Sandreas.hansson@arm.com // First offset for critical word first calculations 136311051Sandreas.hansson@arm.com int initial_offset = initial_tgt->pkt->getOffset(blkSize); 136411051Sandreas.hansson@arm.com 136511601Sandreas.hansson@arm.com bool from_cache = false; 136611742Snikos.nikoleris@arm.com MSHR::TargetList targets = mshr->extractServiceableTargets(pkt); 136711742Snikos.nikoleris@arm.com for (auto &target: targets) { 136811742Snikos.nikoleris@arm.com Packet *tgt_pkt = target.pkt; 136911742Snikos.nikoleris@arm.com switch (target.source) { 137011051Sandreas.hansson@arm.com case MSHR::Target::FromCPU: 137111051Sandreas.hansson@arm.com Tick completion_time; 137211051Sandreas.hansson@arm.com // Here we charge on completion_time the delay of the xbar if the 137311051Sandreas.hansson@arm.com // packet comes from it, charged on headerDelay. 137411051Sandreas.hansson@arm.com completion_time = pkt->headerDelay; 137511051Sandreas.hansson@arm.com 137611051Sandreas.hansson@arm.com // Software prefetch handling for cache closest to core 137711051Sandreas.hansson@arm.com if (tgt_pkt->cmd.isSWPrefetch()) { 137811483Snikos.nikoleris@arm.com // a software prefetch would have already been ack'd 137911483Snikos.nikoleris@arm.com // immediately with dummy data so the core would be able to 138011483Snikos.nikoleris@arm.com // retire it. This request completes right here, so we 138111483Snikos.nikoleris@arm.com // deallocate it. 138211051Sandreas.hansson@arm.com delete tgt_pkt->req; 138311051Sandreas.hansson@arm.com delete tgt_pkt; 138411051Sandreas.hansson@arm.com break; // skip response 138511051Sandreas.hansson@arm.com } 138611051Sandreas.hansson@arm.com 138711601Sandreas.hansson@arm.com // keep track of whether we have responded to another 138811601Sandreas.hansson@arm.com // cache 138911601Sandreas.hansson@arm.com from_cache = from_cache || tgt_pkt->fromCache(); 139011601Sandreas.hansson@arm.com 139111051Sandreas.hansson@arm.com // unlike the other packet flows, where data is found in other 139211051Sandreas.hansson@arm.com // caches or memory and brought back, write-line requests always 139311051Sandreas.hansson@arm.com // have the data right away, so the above check for "is fill?" 139411051Sandreas.hansson@arm.com // cannot actually be determined until examining the stored MSHR 139511051Sandreas.hansson@arm.com // state. We "catch up" with that logic here, which is duplicated 139611051Sandreas.hansson@arm.com // from above. 139711051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::WriteLineReq) { 139811051Sandreas.hansson@arm.com assert(!is_error); 139911284Sandreas.hansson@arm.com // we got the block in a writable state, so promote 140011284Sandreas.hansson@arm.com // any deferred targets if possible 140111284Sandreas.hansson@arm.com mshr->promoteWritable(); 140211051Sandreas.hansson@arm.com // NB: we use the original packet here and not the response! 140311741Snikos.nikoleris@arm.com blk = handleFill(tgt_pkt, blk, writebacks, 140411742Snikos.nikoleris@arm.com targets.allocOnFill); 140511484Snikos.nikoleris@arm.com assert(blk != nullptr); 140611051Sandreas.hansson@arm.com 140711051Sandreas.hansson@arm.com // treat as a fill, and discard the invalidation 140811051Sandreas.hansson@arm.com // response 140911051Sandreas.hansson@arm.com is_fill = true; 141011136Sandreas.hansson@arm.com is_invalidate = false; 141111051Sandreas.hansson@arm.com } 141211051Sandreas.hansson@arm.com 141311051Sandreas.hansson@arm.com if (is_fill) { 141411601Sandreas.hansson@arm.com satisfyRequest(tgt_pkt, blk, true, mshr->hasPostDowngrade()); 141511051Sandreas.hansson@arm.com 141611051Sandreas.hansson@arm.com // How many bytes past the first request is this one 141711051Sandreas.hansson@arm.com int transfer_offset = 141811051Sandreas.hansson@arm.com tgt_pkt->getOffset(blkSize) - initial_offset; 141911051Sandreas.hansson@arm.com if (transfer_offset < 0) { 142011051Sandreas.hansson@arm.com transfer_offset += blkSize; 142111051Sandreas.hansson@arm.com } 142211051Sandreas.hansson@arm.com 142311051Sandreas.hansson@arm.com // If not critical word (offset) return payloadDelay. 142411051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 142511051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 142611051Sandreas.hansson@arm.com // the core. 142711051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 142811051Sandreas.hansson@arm.com (transfer_offset ? pkt->payloadDelay : 0); 142911051Sandreas.hansson@arm.com 143011051Sandreas.hansson@arm.com assert(!tgt_pkt->req->isUncacheable()); 143111051Sandreas.hansson@arm.com 143211051Sandreas.hansson@arm.com assert(tgt_pkt->req->masterId() < system->maxMasters()); 143311051Sandreas.hansson@arm.com missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] += 143411742Snikos.nikoleris@arm.com completion_time - target.recvTime; 143511051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::UpgradeFailResp) { 143611051Sandreas.hansson@arm.com // failed StoreCond upgrade 143711051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::StoreCondReq || 143811051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::StoreCondFailReq || 143911051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::SCUpgradeFailReq); 144011051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 144111051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 144211051Sandreas.hansson@arm.com // the core. 144311051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 144411051Sandreas.hansson@arm.com pkt->payloadDelay; 144511051Sandreas.hansson@arm.com tgt_pkt->req->setExtraData(0); 144611051Sandreas.hansson@arm.com } else { 144711750Snikos.nikoleris@arm.com // We are about to send a response to a cache above 144811750Snikos.nikoleris@arm.com // that asked for an invalidation; we need to 144911750Snikos.nikoleris@arm.com // invalidate our copy immediately as the most 145011750Snikos.nikoleris@arm.com // up-to-date copy of the block will now be in the 145111750Snikos.nikoleris@arm.com // cache above. It will also prevent this cache from 145211750Snikos.nikoleris@arm.com // responding (if the block was previously dirty) to 145311750Snikos.nikoleris@arm.com // snoops as they should snoop the caches above where 145411750Snikos.nikoleris@arm.com // they will get the response from. 145511750Snikos.nikoleris@arm.com if (is_invalidate && blk && blk->isValid()) { 145611750Snikos.nikoleris@arm.com invalidateBlock(blk); 145711750Snikos.nikoleris@arm.com } 145811051Sandreas.hansson@arm.com // not a cache fill, just forwarding response 145911051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 146011051Sandreas.hansson@arm.com // from lower level cahces/memory to the core. 146111051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 146211051Sandreas.hansson@arm.com pkt->payloadDelay; 146311051Sandreas.hansson@arm.com if (pkt->isRead() && !is_error) { 146411051Sandreas.hansson@arm.com // sanity check 146511051Sandreas.hansson@arm.com assert(pkt->getAddr() == tgt_pkt->getAddr()); 146611051Sandreas.hansson@arm.com assert(pkt->getSize() >= tgt_pkt->getSize()); 146711051Sandreas.hansson@arm.com 146811051Sandreas.hansson@arm.com tgt_pkt->setData(pkt->getConstPtr<uint8_t>()); 146911051Sandreas.hansson@arm.com } 147011051Sandreas.hansson@arm.com } 147111051Sandreas.hansson@arm.com tgt_pkt->makeTimingResponse(); 147211051Sandreas.hansson@arm.com // if this packet is an error copy that to the new packet 147311051Sandreas.hansson@arm.com if (is_error) 147411051Sandreas.hansson@arm.com tgt_pkt->copyError(pkt); 147511051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::ReadResp && 147611136Sandreas.hansson@arm.com (is_invalidate || mshr->hasPostInvalidate())) { 147711051Sandreas.hansson@arm.com // If intermediate cache got ReadRespWithInvalidate, 147811051Sandreas.hansson@arm.com // propagate that. Response should not have 147911051Sandreas.hansson@arm.com // isInvalidate() set otherwise. 148011051Sandreas.hansson@arm.com tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate; 148111744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: updated cmd to %s\n", __func__, 148211744Snikos.nikoleris@arm.com tgt_pkt->print()); 148311051Sandreas.hansson@arm.com } 148411051Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 148511051Sandreas.hansson@arm.com tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; 148611194Sali.jafri@arm.com cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true); 148711051Sandreas.hansson@arm.com break; 148811051Sandreas.hansson@arm.com 148911051Sandreas.hansson@arm.com case MSHR::Target::FromPrefetcher: 149011051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::HardPFReq); 149111051Sandreas.hansson@arm.com if (blk) 149211051Sandreas.hansson@arm.com blk->status |= BlkHWPrefetched; 149311051Sandreas.hansson@arm.com delete tgt_pkt->req; 149411051Sandreas.hansson@arm.com delete tgt_pkt; 149511051Sandreas.hansson@arm.com break; 149611051Sandreas.hansson@arm.com 149711051Sandreas.hansson@arm.com case MSHR::Target::FromSnoop: 149811051Sandreas.hansson@arm.com // I don't believe that a snoop can be in an error state 149911051Sandreas.hansson@arm.com assert(!is_error); 150011051Sandreas.hansson@arm.com // response to snoop request 150111051Sandreas.hansson@arm.com DPRINTF(Cache, "processing deferred snoop...\n"); 150211749Snikos.nikoleris@arm.com // If the response is invalidating, a snooping target can 150311749Snikos.nikoleris@arm.com // be satisfied if it is also invalidating. If the reponse is, not 150411749Snikos.nikoleris@arm.com // only invalidating, but more specifically an InvalidateResp, the 150511749Snikos.nikoleris@arm.com // MSHR was created due to an InvalidateReq and a cache above is 150611749Snikos.nikoleris@arm.com // waiting to satisfy a WriteLineReq. In this case even an 150711749Snikos.nikoleris@arm.com // non-invalidating snoop is added as a target here since this is 150811749Snikos.nikoleris@arm.com // the ordering point. When the InvalidateResp reaches this cache, 150911749Snikos.nikoleris@arm.com // the snooping target will snoop further the cache above with the 151011749Snikos.nikoleris@arm.com // WriteLineReq. 151111749Snikos.nikoleris@arm.com assert(!(is_invalidate && 151211749Snikos.nikoleris@arm.com pkt->cmd != MemCmd::InvalidateResp && 151311749Snikos.nikoleris@arm.com !mshr->hasPostInvalidate())); 151411051Sandreas.hansson@arm.com handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate()); 151511051Sandreas.hansson@arm.com break; 151611051Sandreas.hansson@arm.com 151711051Sandreas.hansson@arm.com default: 151811742Snikos.nikoleris@arm.com panic("Illegal target->source enum %d\n", target.source); 151911051Sandreas.hansson@arm.com } 152011051Sandreas.hansson@arm.com } 152111051Sandreas.hansson@arm.com 152211601Sandreas.hansson@arm.com maintainClusivity(from_cache, blk); 152311601Sandreas.hansson@arm.com 152411051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 152511051Sandreas.hansson@arm.com // an invalidate response stemming from a write line request 152611051Sandreas.hansson@arm.com // should not invalidate the block, so check if the 152711051Sandreas.hansson@arm.com // invalidation should be discarded 152811136Sandreas.hansson@arm.com if (is_invalidate || mshr->hasPostInvalidate()) { 152911197Sandreas.hansson@arm.com invalidateBlock(blk); 153011051Sandreas.hansson@arm.com } else if (mshr->hasPostDowngrade()) { 153111051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 153211051Sandreas.hansson@arm.com } 153311051Sandreas.hansson@arm.com } 153411051Sandreas.hansson@arm.com 153511051Sandreas.hansson@arm.com if (mshr->promoteDeferredTargets()) { 153611051Sandreas.hansson@arm.com // avoid later read getting stale data while write miss is 153711051Sandreas.hansson@arm.com // outstanding.. see comment in timingAccess() 153811051Sandreas.hansson@arm.com if (blk) { 153911051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 154011051Sandreas.hansson@arm.com } 154111375Sandreas.hansson@arm.com mshrQueue.markPending(mshr); 154211051Sandreas.hansson@arm.com schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 154311051Sandreas.hansson@arm.com } else { 154411375Sandreas.hansson@arm.com mshrQueue.deallocate(mshr); 154511375Sandreas.hansson@arm.com if (wasFull && !mshrQueue.isFull()) { 154611375Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 154711051Sandreas.hansson@arm.com } 154811051Sandreas.hansson@arm.com 154911051Sandreas.hansson@arm.com // Request the bus for a prefetch if this deallocation freed enough 155011051Sandreas.hansson@arm.com // MSHRs for a prefetch to take place 155111375Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 155211051Sandreas.hansson@arm.com Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 155311051Sandreas.hansson@arm.com clockEdge()); 155411051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 155511051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 155611051Sandreas.hansson@arm.com } 155711051Sandreas.hansson@arm.com } 155811051Sandreas.hansson@arm.com // reset the xbar additional timinig as it is now accounted for 155911051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 156011051Sandreas.hansson@arm.com 156111051Sandreas.hansson@arm.com // copy writebacks to write buffer 156211051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 156311051Sandreas.hansson@arm.com 156411051Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and then clear it out 156511051Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 156611051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying 156711051Sandreas.hansson@arm.com // Writebacks/CleanEvicts to write buffer. It specifies the latency to 156811051Sandreas.hansson@arm.com // allocate an internal buffer and to schedule an event to the 156911051Sandreas.hansson@arm.com // queued port. 157011199Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 157111051Sandreas.hansson@arm.com PacketPtr wbPkt = writebackBlk(blk); 157211051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 157311051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag if cached above. 157411051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) 157511051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 157611051Sandreas.hansson@arm.com } else { 157711051Sandreas.hansson@arm.com PacketPtr wcPkt = cleanEvictBlk(blk); 157811051Sandreas.hansson@arm.com // Check to see if block is cached above. If not allocate 157911051Sandreas.hansson@arm.com // write buffer 158011051Sandreas.hansson@arm.com if (isCachedAbove(wcPkt)) 158111051Sandreas.hansson@arm.com delete wcPkt; 158211051Sandreas.hansson@arm.com else 158311051Sandreas.hansson@arm.com allocateWriteBuffer(wcPkt, forward_time); 158411051Sandreas.hansson@arm.com } 158511867Snikos.nikoleris@arm.com invalidateBlock(blk); 158611051Sandreas.hansson@arm.com } 158711051Sandreas.hansson@arm.com 158811744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print()); 158911051Sandreas.hansson@arm.com delete pkt; 159011051Sandreas.hansson@arm.com} 159111051Sandreas.hansson@arm.com 159211051Sandreas.hansson@arm.comPacketPtr 159311051Sandreas.hansson@arm.comCache::writebackBlk(CacheBlk *blk) 159411051Sandreas.hansson@arm.com{ 159511199Sandreas.hansson@arm.com chatty_assert(!isReadOnly || writebackClean, 159611199Sandreas.hansson@arm.com "Writeback from read-only cache"); 159711199Sandreas.hansson@arm.com assert(blk && blk->isValid() && (blk->isDirty() || writebackClean)); 159811051Sandreas.hansson@arm.com 159911051Sandreas.hansson@arm.com writebacks[Request::wbMasterId]++; 160011051Sandreas.hansson@arm.com 160111199Sandreas.hansson@arm.com Request *req = new Request(tags->regenerateBlkAddr(blk->tag, blk->set), 160211199Sandreas.hansson@arm.com blkSize, 0, Request::wbMasterId); 160311051Sandreas.hansson@arm.com if (blk->isSecure()) 160411199Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 160511051Sandreas.hansson@arm.com 160611199Sandreas.hansson@arm.com req->taskId(blk->task_id); 160711051Sandreas.hansson@arm.com blk->task_id= ContextSwitchTaskId::Unknown; 160811051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 160911051Sandreas.hansson@arm.com 161011199Sandreas.hansson@arm.com PacketPtr pkt = 161111199Sandreas.hansson@arm.com new Packet(req, blk->isDirty() ? 161211199Sandreas.hansson@arm.com MemCmd::WritebackDirty : MemCmd::WritebackClean); 161311199Sandreas.hansson@arm.com 161411744Snikos.nikoleris@arm.com DPRINTF(Cache, "Create Writeback %s writable: %d, dirty: %d\n", 161511744Snikos.nikoleris@arm.com pkt->print(), blk->isWritable(), blk->isDirty()); 161611199Sandreas.hansson@arm.com 161711051Sandreas.hansson@arm.com if (blk->isWritable()) { 161811051Sandreas.hansson@arm.com // not asserting shared means we pass the block in modified 161911051Sandreas.hansson@arm.com // state, mark our own block non-writeable 162011051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 162111051Sandreas.hansson@arm.com } else { 162211284Sandreas.hansson@arm.com // we are in the Owned state, tell the receiver 162311284Sandreas.hansson@arm.com pkt->setHasSharers(); 162411051Sandreas.hansson@arm.com } 162511051Sandreas.hansson@arm.com 162611199Sandreas.hansson@arm.com // make sure the block is not marked dirty 162711199Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 162811051Sandreas.hansson@arm.com 162911199Sandreas.hansson@arm.com pkt->allocate(); 163011199Sandreas.hansson@arm.com std::memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize); 163111199Sandreas.hansson@arm.com 163211199Sandreas.hansson@arm.com return pkt; 163311051Sandreas.hansson@arm.com} 163411051Sandreas.hansson@arm.com 163511051Sandreas.hansson@arm.comPacketPtr 163612346Snikos.nikoleris@arm.comCache::writecleanBlk(CacheBlk *blk, Request::Flags dest) 163712345Snikos.nikoleris@arm.com{ 163812345Snikos.nikoleris@arm.com Request *req = new Request(tags->regenerateBlkAddr(blk->tag, blk->set), 163912345Snikos.nikoleris@arm.com blkSize, 0, Request::wbMasterId); 164012345Snikos.nikoleris@arm.com if (blk->isSecure()) { 164112345Snikos.nikoleris@arm.com req->setFlags(Request::SECURE); 164212345Snikos.nikoleris@arm.com } 164312345Snikos.nikoleris@arm.com req->taskId(blk->task_id); 164412345Snikos.nikoleris@arm.com blk->task_id = ContextSwitchTaskId::Unknown; 164512345Snikos.nikoleris@arm.com PacketPtr pkt = new Packet(req, MemCmd::WriteClean); 164612345Snikos.nikoleris@arm.com DPRINTF(Cache, "Create %s writable: %d, dirty: %d\n", pkt->print(), 164712345Snikos.nikoleris@arm.com blk->isWritable(), blk->isDirty()); 164812345Snikos.nikoleris@arm.com // make sure the block is not marked dirty 164912345Snikos.nikoleris@arm.com blk->status &= ~BlkDirty; 165012345Snikos.nikoleris@arm.com pkt->allocate(); 165112345Snikos.nikoleris@arm.com // We inform the cache below that the block has sharers in the 165212345Snikos.nikoleris@arm.com // system as we retain our copy. 165312345Snikos.nikoleris@arm.com pkt->setHasSharers(); 165412346Snikos.nikoleris@arm.com if (dest) { 165512346Snikos.nikoleris@arm.com req->setFlags(dest); 165612346Snikos.nikoleris@arm.com pkt->setWriteThrough(); 165712346Snikos.nikoleris@arm.com } 165812345Snikos.nikoleris@arm.com std::memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize); 165912345Snikos.nikoleris@arm.com return pkt; 166012345Snikos.nikoleris@arm.com} 166112345Snikos.nikoleris@arm.com 166212345Snikos.nikoleris@arm.com 166312345Snikos.nikoleris@arm.comPacketPtr 166411051Sandreas.hansson@arm.comCache::cleanEvictBlk(CacheBlk *blk) 166511051Sandreas.hansson@arm.com{ 166611199Sandreas.hansson@arm.com assert(!writebackClean); 166711051Sandreas.hansson@arm.com assert(blk && blk->isValid() && !blk->isDirty()); 166811051Sandreas.hansson@arm.com // Creating a zero sized write, a message to the snoop filter 166911051Sandreas.hansson@arm.com Request *req = 167011051Sandreas.hansson@arm.com new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0, 167111051Sandreas.hansson@arm.com Request::wbMasterId); 167211051Sandreas.hansson@arm.com if (blk->isSecure()) 167311051Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 167411051Sandreas.hansson@arm.com 167511051Sandreas.hansson@arm.com req->taskId(blk->task_id); 167611051Sandreas.hansson@arm.com blk->task_id = ContextSwitchTaskId::Unknown; 167711051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 167811051Sandreas.hansson@arm.com 167911051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::CleanEvict); 168011051Sandreas.hansson@arm.com pkt->allocate(); 168111744Snikos.nikoleris@arm.com DPRINTF(Cache, "Create CleanEvict %s\n", pkt->print()); 168211051Sandreas.hansson@arm.com 168311051Sandreas.hansson@arm.com return pkt; 168411051Sandreas.hansson@arm.com} 168511051Sandreas.hansson@arm.com 168611051Sandreas.hansson@arm.comvoid 168711051Sandreas.hansson@arm.comCache::memWriteback() 168811051Sandreas.hansson@arm.com{ 168911051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::writebackVisitor); 169011051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 169111051Sandreas.hansson@arm.com} 169211051Sandreas.hansson@arm.com 169311051Sandreas.hansson@arm.comvoid 169411051Sandreas.hansson@arm.comCache::memInvalidate() 169511051Sandreas.hansson@arm.com{ 169611051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::invalidateVisitor); 169711051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 169811051Sandreas.hansson@arm.com} 169911051Sandreas.hansson@arm.com 170011051Sandreas.hansson@arm.combool 170111051Sandreas.hansson@arm.comCache::isDirty() const 170211051Sandreas.hansson@arm.com{ 170311051Sandreas.hansson@arm.com CacheBlkIsDirtyVisitor visitor; 170411051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 170511051Sandreas.hansson@arm.com 170611051Sandreas.hansson@arm.com return visitor.isDirty(); 170711051Sandreas.hansson@arm.com} 170811051Sandreas.hansson@arm.com 170911051Sandreas.hansson@arm.combool 171011051Sandreas.hansson@arm.comCache::writebackVisitor(CacheBlk &blk) 171111051Sandreas.hansson@arm.com{ 171211051Sandreas.hansson@arm.com if (blk.isDirty()) { 171311051Sandreas.hansson@arm.com assert(blk.isValid()); 171411051Sandreas.hansson@arm.com 171511051Sandreas.hansson@arm.com Request request(tags->regenerateBlkAddr(blk.tag, blk.set), 171611051Sandreas.hansson@arm.com blkSize, 0, Request::funcMasterId); 171711051Sandreas.hansson@arm.com request.taskId(blk.task_id); 171811865Snikos.nikoleris@arm.com if (blk.isSecure()) { 171911865Snikos.nikoleris@arm.com request.setFlags(Request::SECURE); 172011865Snikos.nikoleris@arm.com } 172111051Sandreas.hansson@arm.com 172211051Sandreas.hansson@arm.com Packet packet(&request, MemCmd::WriteReq); 172311051Sandreas.hansson@arm.com packet.dataStatic(blk.data); 172411051Sandreas.hansson@arm.com 172511051Sandreas.hansson@arm.com memSidePort->sendFunctional(&packet); 172611051Sandreas.hansson@arm.com 172711051Sandreas.hansson@arm.com blk.status &= ~BlkDirty; 172811051Sandreas.hansson@arm.com } 172911051Sandreas.hansson@arm.com 173011051Sandreas.hansson@arm.com return true; 173111051Sandreas.hansson@arm.com} 173211051Sandreas.hansson@arm.com 173311051Sandreas.hansson@arm.combool 173411051Sandreas.hansson@arm.comCache::invalidateVisitor(CacheBlk &blk) 173511051Sandreas.hansson@arm.com{ 173611051Sandreas.hansson@arm.com 173711051Sandreas.hansson@arm.com if (blk.isDirty()) 173811051Sandreas.hansson@arm.com warn_once("Invalidating dirty cache lines. Expect things to break.\n"); 173911051Sandreas.hansson@arm.com 174011051Sandreas.hansson@arm.com if (blk.isValid()) { 174111051Sandreas.hansson@arm.com assert(!blk.isDirty()); 174211867Snikos.nikoleris@arm.com invalidateBlock(&blk); 174311051Sandreas.hansson@arm.com } 174411051Sandreas.hansson@arm.com 174511051Sandreas.hansson@arm.com return true; 174611051Sandreas.hansson@arm.com} 174711051Sandreas.hansson@arm.com 174811051Sandreas.hansson@arm.comCacheBlk* 174911051Sandreas.hansson@arm.comCache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks) 175011051Sandreas.hansson@arm.com{ 175111051Sandreas.hansson@arm.com CacheBlk *blk = tags->findVictim(addr); 175211051Sandreas.hansson@arm.com 175311484Snikos.nikoleris@arm.com // It is valid to return nullptr if there is no victim 175411051Sandreas.hansson@arm.com if (!blk) 175511051Sandreas.hansson@arm.com return nullptr; 175611051Sandreas.hansson@arm.com 175711051Sandreas.hansson@arm.com if (blk->isValid()) { 175811051Sandreas.hansson@arm.com Addr repl_addr = tags->regenerateBlkAddr(blk->tag, blk->set); 175911051Sandreas.hansson@arm.com MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure()); 176011051Sandreas.hansson@arm.com if (repl_mshr) { 176111051Sandreas.hansson@arm.com // must be an outstanding upgrade request 176211051Sandreas.hansson@arm.com // on a block we're about to replace... 176311051Sandreas.hansson@arm.com assert(!blk->isWritable() || blk->isDirty()); 176411284Sandreas.hansson@arm.com assert(repl_mshr->needsWritable()); 176511051Sandreas.hansson@arm.com // too hard to replace block with transient state 176611051Sandreas.hansson@arm.com // allocation failed, block not inserted 176711484Snikos.nikoleris@arm.com return nullptr; 176811051Sandreas.hansson@arm.com } else { 176911483Snikos.nikoleris@arm.com DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx " 177011483Snikos.nikoleris@arm.com "(%s): %s\n", repl_addr, blk->isSecure() ? "s" : "ns", 177111051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", 177211051Sandreas.hansson@arm.com blk->isDirty() ? "writeback" : "clean"); 177311051Sandreas.hansson@arm.com 177411436SRekai.GonzalezAlberquilla@arm.com if (blk->wasPrefetched()) { 177511436SRekai.GonzalezAlberquilla@arm.com unusedPrefetches++; 177611436SRekai.GonzalezAlberquilla@arm.com } 177711051Sandreas.hansson@arm.com // Will send up Writeback/CleanEvict snoops via isCachedAbove 177811051Sandreas.hansson@arm.com // when pushing this writeback list into the write buffer. 177911199Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 178011051Sandreas.hansson@arm.com // Save writeback packet for handling by caller 178111051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(blk)); 178211051Sandreas.hansson@arm.com } else { 178311051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(blk)); 178411051Sandreas.hansson@arm.com } 178511051Sandreas.hansson@arm.com } 178611051Sandreas.hansson@arm.com } 178711051Sandreas.hansson@arm.com 178811051Sandreas.hansson@arm.com return blk; 178911051Sandreas.hansson@arm.com} 179011051Sandreas.hansson@arm.com 179111197Sandreas.hansson@arm.comvoid 179211197Sandreas.hansson@arm.comCache::invalidateBlock(CacheBlk *blk) 179311197Sandreas.hansson@arm.com{ 179411197Sandreas.hansson@arm.com if (blk != tempBlock) 179511197Sandreas.hansson@arm.com tags->invalidate(blk); 179611197Sandreas.hansson@arm.com blk->invalidate(); 179711197Sandreas.hansson@arm.com} 179811051Sandreas.hansson@arm.com 179911051Sandreas.hansson@arm.com// Note that the reason we return a list of writebacks rather than 180011051Sandreas.hansson@arm.com// inserting them directly in the write buffer is that this function 180111051Sandreas.hansson@arm.com// is called by both atomic and timing-mode accesses, and in atomic 180211051Sandreas.hansson@arm.com// mode we don't mess with the write buffer (we just perform the 180311051Sandreas.hansson@arm.com// writebacks atomically once the original request is complete). 180411051Sandreas.hansson@arm.comCacheBlk* 180511197Sandreas.hansson@arm.comCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, 180611197Sandreas.hansson@arm.com bool allocate) 180711051Sandreas.hansson@arm.com{ 180811051Sandreas.hansson@arm.com assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq); 180911051Sandreas.hansson@arm.com Addr addr = pkt->getAddr(); 181011051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 181111051Sandreas.hansson@arm.com#if TRACING_ON 181211051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 181311051Sandreas.hansson@arm.com#endif 181411051Sandreas.hansson@arm.com 181511375Sandreas.hansson@arm.com // When handling a fill, we should have no writes to this line. 181611892Snikos.nikoleris@arm.com assert(addr == pkt->getBlockAddr(blkSize)); 181711375Sandreas.hansson@arm.com assert(!writeBuffer.findMatch(addr, is_secure)); 181811051Sandreas.hansson@arm.com 181911484Snikos.nikoleris@arm.com if (blk == nullptr) { 182011051Sandreas.hansson@arm.com // better have read new data... 182111051Sandreas.hansson@arm.com assert(pkt->hasData()); 182211051Sandreas.hansson@arm.com 182311051Sandreas.hansson@arm.com // only read responses and write-line requests have data; 182411051Sandreas.hansson@arm.com // note that we don't write the data here for write-line - that 182511601Sandreas.hansson@arm.com // happens in the subsequent call to satisfyRequest 182611051Sandreas.hansson@arm.com assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq); 182711051Sandreas.hansson@arm.com 182811197Sandreas.hansson@arm.com // need to do a replacement if allocating, otherwise we stick 182911197Sandreas.hansson@arm.com // with the temporary storage 183011484Snikos.nikoleris@arm.com blk = allocate ? allocateBlock(addr, is_secure, writebacks) : nullptr; 183111197Sandreas.hansson@arm.com 183211484Snikos.nikoleris@arm.com if (blk == nullptr) { 183311197Sandreas.hansson@arm.com // No replaceable block or a mostly exclusive 183411197Sandreas.hansson@arm.com // cache... just use temporary storage to complete the 183511197Sandreas.hansson@arm.com // current request and then get rid of it 183611051Sandreas.hansson@arm.com assert(!tempBlock->isValid()); 183711051Sandreas.hansson@arm.com blk = tempBlock; 183811051Sandreas.hansson@arm.com tempBlock->set = tags->extractSet(addr); 183911051Sandreas.hansson@arm.com tempBlock->tag = tags->extractTag(addr); 184011051Sandreas.hansson@arm.com // @todo: set security state as well... 184111051Sandreas.hansson@arm.com DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr, 184211051Sandreas.hansson@arm.com is_secure ? "s" : "ns"); 184311051Sandreas.hansson@arm.com } else { 184411051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 184511051Sandreas.hansson@arm.com } 184611051Sandreas.hansson@arm.com 184711051Sandreas.hansson@arm.com // we should never be overwriting a valid block 184811051Sandreas.hansson@arm.com assert(!blk->isValid()); 184911051Sandreas.hansson@arm.com } else { 185011051Sandreas.hansson@arm.com // existing block... probably an upgrade 185111051Sandreas.hansson@arm.com assert(blk->tag == tags->extractTag(addr)); 185211051Sandreas.hansson@arm.com // either we're getting new data or the block should already be valid 185311051Sandreas.hansson@arm.com assert(pkt->hasData() || blk->isValid()); 185411051Sandreas.hansson@arm.com // don't clear block status... if block is already dirty we 185511051Sandreas.hansson@arm.com // don't want to lose that 185611051Sandreas.hansson@arm.com } 185711051Sandreas.hansson@arm.com 185811051Sandreas.hansson@arm.com if (is_secure) 185911051Sandreas.hansson@arm.com blk->status |= BlkSecure; 186011051Sandreas.hansson@arm.com blk->status |= BlkValid | BlkReadable; 186111051Sandreas.hansson@arm.com 186211137Sandreas.hansson@arm.com // sanity check for whole-line writes, which should always be 186311137Sandreas.hansson@arm.com // marked as writable as part of the fill, and then later marked 186411601Sandreas.hansson@arm.com // dirty as part of satisfyRequest 186511137Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WriteLineReq) { 186611284Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 186711137Sandreas.hansson@arm.com } 186811137Sandreas.hansson@arm.com 186911284Sandreas.hansson@arm.com // here we deal with setting the appropriate state of the line, 187011284Sandreas.hansson@arm.com // and we start by looking at the hasSharers flag, and ignore the 187111284Sandreas.hansson@arm.com // cacheResponding flag (normally signalling dirty data) if the 187211284Sandreas.hansson@arm.com // packet has sharers, thus the line is never allocated as Owned 187311284Sandreas.hansson@arm.com // (dirty but not writable), and always ends up being either 187411284Sandreas.hansson@arm.com // Shared, Exclusive or Modified, see Packet::setCacheResponding 187511284Sandreas.hansson@arm.com // for more details 187611284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 187711284Sandreas.hansson@arm.com // we could get a writable line from memory (rather than a 187811284Sandreas.hansson@arm.com // cache) even in a read-only cache, note that we set this bit 187911284Sandreas.hansson@arm.com // even for a read-only cache, possibly revisit this decision 188011051Sandreas.hansson@arm.com blk->status |= BlkWritable; 188111051Sandreas.hansson@arm.com 188211284Sandreas.hansson@arm.com // check if we got this via cache-to-cache transfer (i.e., from a 188311284Sandreas.hansson@arm.com // cache that had the block in Modified or Owned state) 188411284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 188511284Sandreas.hansson@arm.com // we got the block in Modified state, and invalidated the 188611284Sandreas.hansson@arm.com // owners copy 188711051Sandreas.hansson@arm.com blk->status |= BlkDirty; 188811051Sandreas.hansson@arm.com 188911051Sandreas.hansson@arm.com chatty_assert(!isReadOnly, "Should never see dirty snoop response " 189011051Sandreas.hansson@arm.com "in read-only cache %s\n", name()); 189111051Sandreas.hansson@arm.com } 189211051Sandreas.hansson@arm.com } 189311051Sandreas.hansson@arm.com 189411051Sandreas.hansson@arm.com DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n", 189511051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", old_state, blk->print()); 189611051Sandreas.hansson@arm.com 189711051Sandreas.hansson@arm.com // if we got new data, copy it in (checking for a read response 189811051Sandreas.hansson@arm.com // and a response that has data is the same in the end) 189911051Sandreas.hansson@arm.com if (pkt->isRead()) { 190011051Sandreas.hansson@arm.com // sanity checks 190111051Sandreas.hansson@arm.com assert(pkt->hasData()); 190211051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 190311051Sandreas.hansson@arm.com 190411051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 190511051Sandreas.hansson@arm.com } 190611051Sandreas.hansson@arm.com // We pay for fillLatency here. 190711051Sandreas.hansson@arm.com blk->whenReady = clockEdge() + fillLatency * clockPeriod() + 190811051Sandreas.hansson@arm.com pkt->payloadDelay; 190911051Sandreas.hansson@arm.com 191011051Sandreas.hansson@arm.com return blk; 191111051Sandreas.hansson@arm.com} 191211051Sandreas.hansson@arm.com 191311051Sandreas.hansson@arm.com 191411051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 191511051Sandreas.hansson@arm.com// 191611051Sandreas.hansson@arm.com// Snoop path: requests coming in from the memory side 191711051Sandreas.hansson@arm.com// 191811051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 191911051Sandreas.hansson@arm.com 192011051Sandreas.hansson@arm.comvoid 192111051Sandreas.hansson@arm.comCache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 192211051Sandreas.hansson@arm.com bool already_copied, bool pending_inval) 192311051Sandreas.hansson@arm.com{ 192411051Sandreas.hansson@arm.com // sanity check 192511051Sandreas.hansson@arm.com assert(req_pkt->isRequest()); 192611051Sandreas.hansson@arm.com assert(req_pkt->needsResponse()); 192711051Sandreas.hansson@arm.com 192811744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: for %s\n", __func__, req_pkt->print()); 192911051Sandreas.hansson@arm.com // timing-mode snoop responses require a new packet, unless we 193011051Sandreas.hansson@arm.com // already made a copy... 193111051Sandreas.hansson@arm.com PacketPtr pkt = req_pkt; 193211051Sandreas.hansson@arm.com if (!already_copied) 193311051Sandreas.hansson@arm.com // do not clear flags, and allocate space for data if the 193411051Sandreas.hansson@arm.com // packet needs it (the only packets that carry data are read 193511051Sandreas.hansson@arm.com // responses) 193611051Sandreas.hansson@arm.com pkt = new Packet(req_pkt, false, req_pkt->isRead()); 193711051Sandreas.hansson@arm.com 193811051Sandreas.hansson@arm.com assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() || 193911284Sandreas.hansson@arm.com pkt->hasSharers()); 194011051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 194111051Sandreas.hansson@arm.com if (pkt->isRead()) { 194211051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk_data, blkSize); 194311051Sandreas.hansson@arm.com } 194411051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadResp && pending_inval) { 194511051Sandreas.hansson@arm.com // Assume we defer a response to a read from a far-away cache 194611051Sandreas.hansson@arm.com // A, then later defer a ReadExcl from a cache B on the same 194711284Sandreas.hansson@arm.com // bus as us. We'll assert cacheResponding in both cases, but 194811284Sandreas.hansson@arm.com // in the latter case cacheResponding will keep the 194911284Sandreas.hansson@arm.com // invalidation from reaching cache A. This special response 195011284Sandreas.hansson@arm.com // tells cache A that it gets the block to satisfy its read, 195111284Sandreas.hansson@arm.com // but must immediately invalidate it. 195211051Sandreas.hansson@arm.com pkt->cmd = MemCmd::ReadRespWithInvalidate; 195311051Sandreas.hansson@arm.com } 195411051Sandreas.hansson@arm.com // Here we consider forward_time, paying for just forward latency and 195511051Sandreas.hansson@arm.com // also charging the delay provided by the xbar. 195611051Sandreas.hansson@arm.com // forward_time is used as send_time in next allocateWriteBuffer(). 195711051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 195811051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 195911051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 196011744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: created response: %s tick: %lu\n", __func__, 196111744Snikos.nikoleris@arm.com pkt->print(), forward_time); 196211051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, forward_time, true); 196311051Sandreas.hansson@arm.com} 196411051Sandreas.hansson@arm.com 196511127Sandreas.hansson@arm.comuint32_t 196611051Sandreas.hansson@arm.comCache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, 196711051Sandreas.hansson@arm.com bool is_deferred, bool pending_inval) 196811051Sandreas.hansson@arm.com{ 196911744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 197011051Sandreas.hansson@arm.com // deferred snoops can only happen in timing mode 197111051Sandreas.hansson@arm.com assert(!(is_deferred && !is_timing)); 197211051Sandreas.hansson@arm.com // pending_inval only makes sense on deferred snoops 197311051Sandreas.hansson@arm.com assert(!(pending_inval && !is_deferred)); 197411051Sandreas.hansson@arm.com assert(pkt->isRequest()); 197511051Sandreas.hansson@arm.com 197611051Sandreas.hansson@arm.com // the packet may get modified if we or a forwarded snooper 197711051Sandreas.hansson@arm.com // responds in atomic mode, so remember a few things about the 197811051Sandreas.hansson@arm.com // original packet up front 197911051Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 198011284Sandreas.hansson@arm.com bool M5_VAR_USED needs_writable = pkt->needsWritable(); 198111051Sandreas.hansson@arm.com 198211285Sandreas.hansson@arm.com // at the moment we could get an uncacheable write which does not 198311285Sandreas.hansson@arm.com // have the invalidate flag, and we need a suitable way of dealing 198411285Sandreas.hansson@arm.com // with this case 198511285Sandreas.hansson@arm.com panic_if(invalidate && pkt->req->isUncacheable(), 198611744Snikos.nikoleris@arm.com "%s got an invalidating uncacheable snoop request %s", 198711744Snikos.nikoleris@arm.com name(), pkt->print()); 198811285Sandreas.hansson@arm.com 198911127Sandreas.hansson@arm.com uint32_t snoop_delay = 0; 199011127Sandreas.hansson@arm.com 199111051Sandreas.hansson@arm.com if (forwardSnoops) { 199211051Sandreas.hansson@arm.com // first propagate snoop upward to see if anyone above us wants to 199311051Sandreas.hansson@arm.com // handle it. save & restore packet src since it will get 199411051Sandreas.hansson@arm.com // rewritten to be relative to cpu-side bus (if any) 199511284Sandreas.hansson@arm.com bool alreadyResponded = pkt->cacheResponding(); 199611051Sandreas.hansson@arm.com if (is_timing) { 199711051Sandreas.hansson@arm.com // copy the packet so that we can clear any flags before 199811051Sandreas.hansson@arm.com // forwarding it upwards, we also allocate data (passing 199911051Sandreas.hansson@arm.com // the pointer along in case of static data), in case 200011051Sandreas.hansson@arm.com // there is a snoop hit in upper levels 200111051Sandreas.hansson@arm.com Packet snoopPkt(pkt, true, true); 200211051Sandreas.hansson@arm.com snoopPkt.setExpressSnoop(); 200311051Sandreas.hansson@arm.com // the snoop packet does not need to wait any additional 200411051Sandreas.hansson@arm.com // time 200511051Sandreas.hansson@arm.com snoopPkt.headerDelay = snoopPkt.payloadDelay = 0; 200611051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoopPkt); 200711127Sandreas.hansson@arm.com 200811127Sandreas.hansson@arm.com // add the header delay (including crossbar and snoop 200911127Sandreas.hansson@arm.com // delays) of the upward snoop to the snoop delay for this 201011127Sandreas.hansson@arm.com // cache 201111127Sandreas.hansson@arm.com snoop_delay += snoopPkt.headerDelay; 201211127Sandreas.hansson@arm.com 201311284Sandreas.hansson@arm.com if (snoopPkt.cacheResponding()) { 201411051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache 201511051Sandreas.hansson@arm.com assert(!alreadyResponded); 201611284Sandreas.hansson@arm.com pkt->setCacheResponding(); 201711051Sandreas.hansson@arm.com } 201811284Sandreas.hansson@arm.com // upstream cache has the block, or has an outstanding 201911284Sandreas.hansson@arm.com // MSHR, pass the flag on 202011284Sandreas.hansson@arm.com if (snoopPkt.hasSharers()) { 202111284Sandreas.hansson@arm.com pkt->setHasSharers(); 202211051Sandreas.hansson@arm.com } 202311051Sandreas.hansson@arm.com // If this request is a prefetch or clean evict and an upper level 202411051Sandreas.hansson@arm.com // signals block present, make sure to propagate the block 202511051Sandreas.hansson@arm.com // presence to the requester. 202611051Sandreas.hansson@arm.com if (snoopPkt.isBlockCached()) { 202711051Sandreas.hansson@arm.com pkt->setBlockCached(); 202811051Sandreas.hansson@arm.com } 202911051Sandreas.hansson@arm.com } else { 203011051Sandreas.hansson@arm.com cpuSidePort->sendAtomicSnoop(pkt); 203111284Sandreas.hansson@arm.com if (!alreadyResponded && pkt->cacheResponding()) { 203211051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache: 203311051Sandreas.hansson@arm.com // forward response to original requester 203411051Sandreas.hansson@arm.com assert(pkt->isResponse()); 203511051Sandreas.hansson@arm.com } 203611051Sandreas.hansson@arm.com } 203711051Sandreas.hansson@arm.com } 203811051Sandreas.hansson@arm.com 203911051Sandreas.hansson@arm.com if (!blk || !blk->isValid()) { 204011744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: snoop miss for %s\n", __func__, 204111744Snikos.nikoleris@arm.com pkt->print()); 204211493Sandreas.hansson@arm.com if (is_deferred) { 204311493Sandreas.hansson@arm.com // we no longer have the block, and will not respond, but a 204411493Sandreas.hansson@arm.com // packet was allocated in MSHR::handleSnoop and we have 204511493Sandreas.hansson@arm.com // to delete it 204611493Sandreas.hansson@arm.com assert(pkt->needsResponse()); 204711493Sandreas.hansson@arm.com 204811493Sandreas.hansson@arm.com // we have passed the block to a cache upstream, that 204911493Sandreas.hansson@arm.com // cache should be responding 205011493Sandreas.hansson@arm.com assert(pkt->cacheResponding()); 205111493Sandreas.hansson@arm.com 205211493Sandreas.hansson@arm.com delete pkt; 205311493Sandreas.hansson@arm.com } 205411127Sandreas.hansson@arm.com return snoop_delay; 205511051Sandreas.hansson@arm.com } else { 205611744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: snoop hit for %s, old state is %s\n", __func__, 205711744Snikos.nikoleris@arm.com pkt->print(), blk->print()); 205811051Sandreas.hansson@arm.com } 205911051Sandreas.hansson@arm.com 206011051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && blk->isDirty()), 206111051Sandreas.hansson@arm.com "Should never have a dirty block in a read-only cache %s\n", 206211051Sandreas.hansson@arm.com name()); 206311051Sandreas.hansson@arm.com 206411051Sandreas.hansson@arm.com // We may end up modifying both the block state and the packet (if 206511051Sandreas.hansson@arm.com // we respond in atomic mode), so just figure out what to do now 206611751Snikos.nikoleris@arm.com // and then do it later. We respond to all snoops that need 206711751Snikos.nikoleris@arm.com // responses provided we have the block in dirty state. The 206811051Sandreas.hansson@arm.com // invalidation itself is taken care of below. 206911751Snikos.nikoleris@arm.com bool respond = blk->isDirty() && pkt->needsResponse(); 207011284Sandreas.hansson@arm.com bool have_writable = blk->isWritable(); 207111051Sandreas.hansson@arm.com 207211051Sandreas.hansson@arm.com // Invalidate any prefetch's from below that would strip write permissions 207311051Sandreas.hansson@arm.com // MemCmd::HardPFReq is only observed by upstream caches. After missing 207411051Sandreas.hansson@arm.com // above and in it's own cache, a new MemCmd::ReadReq is created that 207511051Sandreas.hansson@arm.com // downstream caches observe. 207611051Sandreas.hansson@arm.com if (pkt->mustCheckAbove()) { 207711483Snikos.nikoleris@arm.com DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s " 207811744Snikos.nikoleris@arm.com "from lower cache\n", pkt->getAddr(), pkt->print()); 207911051Sandreas.hansson@arm.com pkt->setBlockCached(); 208011127Sandreas.hansson@arm.com return snoop_delay; 208111051Sandreas.hansson@arm.com } 208211051Sandreas.hansson@arm.com 208311285Sandreas.hansson@arm.com if (pkt->isRead() && !invalidate) { 208411285Sandreas.hansson@arm.com // reading without requiring the line in a writable state 208511284Sandreas.hansson@arm.com assert(!needs_writable); 208611284Sandreas.hansson@arm.com pkt->setHasSharers(); 208711285Sandreas.hansson@arm.com 208811285Sandreas.hansson@arm.com // if the requesting packet is uncacheable, retain the line in 208911285Sandreas.hansson@arm.com // the current state, otherwhise unset the writable flag, 209011285Sandreas.hansson@arm.com // which means we go from Modified to Owned (and will respond 209111285Sandreas.hansson@arm.com // below), remain in Owned (and will respond below), from 209211285Sandreas.hansson@arm.com // Exclusive to Shared, or remain in Shared 209311285Sandreas.hansson@arm.com if (!pkt->req->isUncacheable()) 209411285Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 209511051Sandreas.hansson@arm.com } 209611051Sandreas.hansson@arm.com 209711051Sandreas.hansson@arm.com if (respond) { 209811051Sandreas.hansson@arm.com // prevent anyone else from responding, cache as well as 209911051Sandreas.hansson@arm.com // memory, and also prevent any memory from even seeing the 210011284Sandreas.hansson@arm.com // request 210111284Sandreas.hansson@arm.com pkt->setCacheResponding(); 210211284Sandreas.hansson@arm.com if (have_writable) { 210311284Sandreas.hansson@arm.com // inform the cache hierarchy that this cache had the line 210411284Sandreas.hansson@arm.com // in the Modified state so that we avoid unnecessary 210511284Sandreas.hansson@arm.com // invalidations (see Packet::setResponderHadWritable) 210611284Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 210711284Sandreas.hansson@arm.com 210811081Sandreas.hansson@arm.com // in the case of an uncacheable request there is no point 210911284Sandreas.hansson@arm.com // in setting the responderHadWritable flag, but since the 211011284Sandreas.hansson@arm.com // recipient does not care there is no harm in doing so 211111284Sandreas.hansson@arm.com } else { 211211284Sandreas.hansson@arm.com // if the packet has needsWritable set we invalidate our 211311284Sandreas.hansson@arm.com // copy below and all other copies will be invalidates 211411284Sandreas.hansson@arm.com // through express snoops, and if needsWritable is not set 211511284Sandreas.hansson@arm.com // we already called setHasSharers above 211611051Sandreas.hansson@arm.com } 211711284Sandreas.hansson@arm.com 211811285Sandreas.hansson@arm.com // if we are returning a writable and dirty (Modified) line, 211911285Sandreas.hansson@arm.com // we should be invalidating the line 212011285Sandreas.hansson@arm.com panic_if(!invalidate && !pkt->hasSharers(), 212111744Snikos.nikoleris@arm.com "%s is passing a Modified line through %s, " 212211744Snikos.nikoleris@arm.com "but keeping the block", name(), pkt->print()); 212311285Sandreas.hansson@arm.com 212411051Sandreas.hansson@arm.com if (is_timing) { 212511051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval); 212611051Sandreas.hansson@arm.com } else { 212711051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 212811286Sandreas.hansson@arm.com // packets such as upgrades do not actually have any data 212911286Sandreas.hansson@arm.com // payload 213011286Sandreas.hansson@arm.com if (pkt->hasData()) 213111286Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 213211051Sandreas.hansson@arm.com } 213311051Sandreas.hansson@arm.com } 213411051Sandreas.hansson@arm.com 213511602Sandreas.hansson@arm.com if (!respond && is_deferred) { 213611051Sandreas.hansson@arm.com assert(pkt->needsResponse()); 213711602Sandreas.hansson@arm.com 213811602Sandreas.hansson@arm.com // if we copied the deferred packet with the intention to 213911602Sandreas.hansson@arm.com // respond, but are not responding, then a cache above us must 214011602Sandreas.hansson@arm.com // be, and we can use this as the indication of whether this 214111602Sandreas.hansson@arm.com // is a packet where we created a copy of the request or not 214211602Sandreas.hansson@arm.com if (!pkt->cacheResponding()) { 214311602Sandreas.hansson@arm.com delete pkt->req; 214411602Sandreas.hansson@arm.com } 214511602Sandreas.hansson@arm.com 214611051Sandreas.hansson@arm.com delete pkt; 214711051Sandreas.hansson@arm.com } 214811051Sandreas.hansson@arm.com 214911051Sandreas.hansson@arm.com // Do this last in case it deallocates block data or something 215011051Sandreas.hansson@arm.com // like that 215111051Sandreas.hansson@arm.com if (invalidate) { 215211197Sandreas.hansson@arm.com invalidateBlock(blk); 215311051Sandreas.hansson@arm.com } 215411051Sandreas.hansson@arm.com 215511051Sandreas.hansson@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 215611127Sandreas.hansson@arm.com 215711127Sandreas.hansson@arm.com return snoop_delay; 215811051Sandreas.hansson@arm.com} 215911051Sandreas.hansson@arm.com 216011051Sandreas.hansson@arm.com 216111051Sandreas.hansson@arm.comvoid 216211051Sandreas.hansson@arm.comCache::recvTimingSnoopReq(PacketPtr pkt) 216311051Sandreas.hansson@arm.com{ 216411744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 216511051Sandreas.hansson@arm.com 216611051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 216711051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 216811051Sandreas.hansson@arm.com 216911130Sali.jafri@arm.com // no need to snoop requests that are not in range 217011051Sandreas.hansson@arm.com if (!inRange(pkt->getAddr())) { 217111051Sandreas.hansson@arm.com return; 217211051Sandreas.hansson@arm.com } 217311051Sandreas.hansson@arm.com 217411051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 217511051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 217611051Sandreas.hansson@arm.com 217711892Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 217811051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 217911051Sandreas.hansson@arm.com 218011127Sandreas.hansson@arm.com // Update the latency cost of the snoop so that the crossbar can 218111127Sandreas.hansson@arm.com // account for it. Do not overwrite what other neighbouring caches 218211127Sandreas.hansson@arm.com // have already done, rather take the maximum. The update is 218311127Sandreas.hansson@arm.com // tentative, for cases where we return before an upward snoop 218411127Sandreas.hansson@arm.com // happens below. 218511127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, 218611127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 218711127Sandreas.hansson@arm.com 218811051Sandreas.hansson@arm.com // Inform request(Prefetch, CleanEvict or Writeback) from below of 218911051Sandreas.hansson@arm.com // MSHR hit, set setBlockCached. 219011051Sandreas.hansson@arm.com if (mshr && pkt->mustCheckAbove()) { 219111744Snikos.nikoleris@arm.com DPRINTF(Cache, "Setting block cached for %s from lower cache on " 219211744Snikos.nikoleris@arm.com "mshr hit\n", pkt->print()); 219311051Sandreas.hansson@arm.com pkt->setBlockCached(); 219411051Sandreas.hansson@arm.com return; 219511051Sandreas.hansson@arm.com } 219611051Sandreas.hansson@arm.com 219711051Sandreas.hansson@arm.com // Let the MSHR itself track the snoop and decide whether we want 219811051Sandreas.hansson@arm.com // to go ahead and do the regular cache snoop 219911051Sandreas.hansson@arm.com if (mshr && mshr->handleSnoop(pkt, order++)) { 220011051Sandreas.hansson@arm.com DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)." 220111051Sandreas.hansson@arm.com "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns", 220211051Sandreas.hansson@arm.com mshr->print()); 220311051Sandreas.hansson@arm.com 220411051Sandreas.hansson@arm.com if (mshr->getNumTargets() > numTarget) 220511051Sandreas.hansson@arm.com warn("allocating bonus target for snoop"); //handle later 220611051Sandreas.hansson@arm.com return; 220711051Sandreas.hansson@arm.com } 220811051Sandreas.hansson@arm.com 220911051Sandreas.hansson@arm.com //We also need to check the writeback buffers and handle those 221011375Sandreas.hansson@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(blk_addr, is_secure); 221111375Sandreas.hansson@arm.com if (wb_entry) { 221211051Sandreas.hansson@arm.com DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n", 221311051Sandreas.hansson@arm.com pkt->getAddr(), is_secure ? "s" : "ns"); 221411051Sandreas.hansson@arm.com // Expect to see only Writebacks and/or CleanEvicts here, both of 221511051Sandreas.hansson@arm.com // which should not be generated for uncacheable data. 221611051Sandreas.hansson@arm.com assert(!wb_entry->isUncacheable()); 221711051Sandreas.hansson@arm.com // There should only be a single request responsible for generating 221811051Sandreas.hansson@arm.com // Writebacks/CleanEvicts. 221911051Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 222011051Sandreas.hansson@arm.com PacketPtr wb_pkt = wb_entry->getTarget()->pkt; 222112345Snikos.nikoleris@arm.com assert(wb_pkt->isEviction() || wb_pkt->cmd == MemCmd::WriteClean); 222211051Sandreas.hansson@arm.com 222311199Sandreas.hansson@arm.com if (pkt->isEviction()) { 222411051Sandreas.hansson@arm.com // if the block is found in the write queue, set the BLOCK_CACHED 222511051Sandreas.hansson@arm.com // flag for Writeback/CleanEvict snoop. On return the snoop will 222611051Sandreas.hansson@arm.com // propagate the BLOCK_CACHED flag in Writeback packets and prevent 222711051Sandreas.hansson@arm.com // any CleanEvicts from travelling down the memory hierarchy. 222811051Sandreas.hansson@arm.com pkt->setBlockCached(); 222911744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Squashing %s from lower cache on writequeue " 223011744Snikos.nikoleris@arm.com "hit\n", __func__, pkt->print()); 223111051Sandreas.hansson@arm.com return; 223211051Sandreas.hansson@arm.com } 223311051Sandreas.hansson@arm.com 223411332Sandreas.hansson@arm.com // conceptually writebacks are no different to other blocks in 223511332Sandreas.hansson@arm.com // this cache, so the behaviour is modelled after handleSnoop, 223611332Sandreas.hansson@arm.com // the difference being that instead of querying the block 223711332Sandreas.hansson@arm.com // state to determine if it is dirty and writable, we use the 223811332Sandreas.hansson@arm.com // command and fields of the writeback packet 223911332Sandreas.hansson@arm.com bool respond = wb_pkt->cmd == MemCmd::WritebackDirty && 224011751Snikos.nikoleris@arm.com pkt->needsResponse(); 224111332Sandreas.hansson@arm.com bool have_writable = !wb_pkt->hasSharers(); 224211332Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 224311332Sandreas.hansson@arm.com 224411332Sandreas.hansson@arm.com if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) { 224511332Sandreas.hansson@arm.com assert(!pkt->needsWritable()); 224611332Sandreas.hansson@arm.com pkt->setHasSharers(); 224711332Sandreas.hansson@arm.com wb_pkt->setHasSharers(); 224811332Sandreas.hansson@arm.com } 224911332Sandreas.hansson@arm.com 225011332Sandreas.hansson@arm.com if (respond) { 225111284Sandreas.hansson@arm.com pkt->setCacheResponding(); 225211332Sandreas.hansson@arm.com 225311332Sandreas.hansson@arm.com if (have_writable) { 225411332Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 225511051Sandreas.hansson@arm.com } 225611332Sandreas.hansson@arm.com 225711051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(), 225811051Sandreas.hansson@arm.com false, false); 225911051Sandreas.hansson@arm.com } 226011051Sandreas.hansson@arm.com 226111332Sandreas.hansson@arm.com if (invalidate) { 226211051Sandreas.hansson@arm.com // Invalidation trumps our writeback... discard here 226311051Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 226411375Sandreas.hansson@arm.com markInService(wb_entry); 226511051Sandreas.hansson@arm.com delete wb_pkt; 226611051Sandreas.hansson@arm.com } 226711051Sandreas.hansson@arm.com } 226811051Sandreas.hansson@arm.com 226911051Sandreas.hansson@arm.com // If this was a shared writeback, there may still be 227011051Sandreas.hansson@arm.com // other shared copies above that require invalidation. 227111051Sandreas.hansson@arm.com // We could be more selective and return here if the 227211051Sandreas.hansson@arm.com // request is non-exclusive or if the writeback is 227311051Sandreas.hansson@arm.com // exclusive. 227411127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false); 227511127Sandreas.hansson@arm.com 227611127Sandreas.hansson@arm.com // Override what we did when we first saw the snoop, as we now 227711127Sandreas.hansson@arm.com // also have the cost of the upwards snoops to account for 227811127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay + 227911127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 228011051Sandreas.hansson@arm.com} 228111051Sandreas.hansson@arm.com 228211051Sandreas.hansson@arm.combool 228311051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 228411051Sandreas.hansson@arm.com{ 228511051Sandreas.hansson@arm.com // Express snoop responses from master to slave, e.g., from L1 to L2 228611051Sandreas.hansson@arm.com cache->recvTimingSnoopResp(pkt); 228711051Sandreas.hansson@arm.com return true; 228811051Sandreas.hansson@arm.com} 228911051Sandreas.hansson@arm.com 229011051Sandreas.hansson@arm.comTick 229111051Sandreas.hansson@arm.comCache::recvAtomicSnoop(PacketPtr pkt) 229211051Sandreas.hansson@arm.com{ 229311051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 229411051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 229511051Sandreas.hansson@arm.com 229611130Sali.jafri@arm.com // no need to snoop requests that are not in range. 229711130Sali.jafri@arm.com if (!inRange(pkt->getAddr())) { 229811051Sandreas.hansson@arm.com return 0; 229911051Sandreas.hansson@arm.com } 230011051Sandreas.hansson@arm.com 230111051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 230211127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false); 230311127Sandreas.hansson@arm.com return snoop_delay + lookupLatency * clockPeriod(); 230411051Sandreas.hansson@arm.com} 230511051Sandreas.hansson@arm.com 230611051Sandreas.hansson@arm.com 230711375Sandreas.hansson@arm.comQueueEntry* 230811375Sandreas.hansson@arm.comCache::getNextQueueEntry() 230911051Sandreas.hansson@arm.com{ 231011051Sandreas.hansson@arm.com // Check both MSHR queue and write buffer for potential requests, 231111051Sandreas.hansson@arm.com // note that null does not mean there is no request, it could 231211051Sandreas.hansson@arm.com // simply be that it is not ready 231311375Sandreas.hansson@arm.com MSHR *miss_mshr = mshrQueue.getNext(); 231411375Sandreas.hansson@arm.com WriteQueueEntry *wq_entry = writeBuffer.getNext(); 231511051Sandreas.hansson@arm.com 231611051Sandreas.hansson@arm.com // If we got a write buffer request ready, first priority is a 231711453Sandreas.hansson@arm.com // full write buffer, otherwise we favour the miss requests 231811453Sandreas.hansson@arm.com if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) { 231911051Sandreas.hansson@arm.com // need to search MSHR queue for conflicting earlier miss. 232011051Sandreas.hansson@arm.com MSHR *conflict_mshr = 232111375Sandreas.hansson@arm.com mshrQueue.findPending(wq_entry->blkAddr, 232211375Sandreas.hansson@arm.com wq_entry->isSecure); 232311375Sandreas.hansson@arm.com 232411375Sandreas.hansson@arm.com if (conflict_mshr && conflict_mshr->order < wq_entry->order) { 232511051Sandreas.hansson@arm.com // Service misses in order until conflict is cleared. 232611051Sandreas.hansson@arm.com return conflict_mshr; 232711051Sandreas.hansson@arm.com 232811051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 232911051Sandreas.hansson@arm.com } 233011051Sandreas.hansson@arm.com 233111051Sandreas.hansson@arm.com // No conflicts; issue write 233211375Sandreas.hansson@arm.com return wq_entry; 233311051Sandreas.hansson@arm.com } else if (miss_mshr) { 233411051Sandreas.hansson@arm.com // need to check for conflicting earlier writeback 233511375Sandreas.hansson@arm.com WriteQueueEntry *conflict_mshr = 233611051Sandreas.hansson@arm.com writeBuffer.findPending(miss_mshr->blkAddr, 233711051Sandreas.hansson@arm.com miss_mshr->isSecure); 233811051Sandreas.hansson@arm.com if (conflict_mshr) { 233911051Sandreas.hansson@arm.com // not sure why we don't check order here... it was in the 234011051Sandreas.hansson@arm.com // original code but commented out. 234111051Sandreas.hansson@arm.com 234211051Sandreas.hansson@arm.com // The only way this happens is if we are 234311051Sandreas.hansson@arm.com // doing a write and we didn't have permissions 234411051Sandreas.hansson@arm.com // then subsequently saw a writeback (owned got evicted) 234511051Sandreas.hansson@arm.com // We need to make sure to perform the writeback first 234611051Sandreas.hansson@arm.com // To preserve the dirty data, then we can issue the write 234711051Sandreas.hansson@arm.com 234811375Sandreas.hansson@arm.com // should we return wq_entry here instead? I.e. do we 234911051Sandreas.hansson@arm.com // have to flush writes in order? I don't think so... not 235011051Sandreas.hansson@arm.com // for Alpha anyway. Maybe for x86? 235111051Sandreas.hansson@arm.com return conflict_mshr; 235211051Sandreas.hansson@arm.com 235311051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 235411051Sandreas.hansson@arm.com } 235511051Sandreas.hansson@arm.com 235611051Sandreas.hansson@arm.com // No conflicts; issue read 235711051Sandreas.hansson@arm.com return miss_mshr; 235811051Sandreas.hansson@arm.com } 235911051Sandreas.hansson@arm.com 236011051Sandreas.hansson@arm.com // fall through... no pending requests. Try a prefetch. 236111375Sandreas.hansson@arm.com assert(!miss_mshr && !wq_entry); 236211051Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 236311051Sandreas.hansson@arm.com // If we have a miss queue slot, we can try a prefetch 236411051Sandreas.hansson@arm.com PacketPtr pkt = prefetcher->getPacket(); 236511051Sandreas.hansson@arm.com if (pkt) { 236611892Snikos.nikoleris@arm.com Addr pf_addr = pkt->getBlockAddr(blkSize); 236711051Sandreas.hansson@arm.com if (!tags->findBlock(pf_addr, pkt->isSecure()) && 236811051Sandreas.hansson@arm.com !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 236911051Sandreas.hansson@arm.com !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 237011051Sandreas.hansson@arm.com // Update statistic on number of prefetches issued 237111051Sandreas.hansson@arm.com // (hwpf_mshr_misses) 237211051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 237311051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 237411051Sandreas.hansson@arm.com 237511051Sandreas.hansson@arm.com // allocate an MSHR and return it, note 237611051Sandreas.hansson@arm.com // that we send the packet straight away, so do not 237711051Sandreas.hansson@arm.com // schedule the send 237811051Sandreas.hansson@arm.com return allocateMissBuffer(pkt, curTick(), false); 237911051Sandreas.hansson@arm.com } else { 238011051Sandreas.hansson@arm.com // free the request and packet 238111051Sandreas.hansson@arm.com delete pkt->req; 238211051Sandreas.hansson@arm.com delete pkt; 238311051Sandreas.hansson@arm.com } 238411051Sandreas.hansson@arm.com } 238511051Sandreas.hansson@arm.com } 238611051Sandreas.hansson@arm.com 238711375Sandreas.hansson@arm.com return nullptr; 238811051Sandreas.hansson@arm.com} 238911051Sandreas.hansson@arm.com 239011051Sandreas.hansson@arm.combool 239111130Sali.jafri@arm.comCache::isCachedAbove(PacketPtr pkt, bool is_timing) const 239211051Sandreas.hansson@arm.com{ 239311051Sandreas.hansson@arm.com if (!forwardSnoops) 239411051Sandreas.hansson@arm.com return false; 239511051Sandreas.hansson@arm.com // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and 239611051Sandreas.hansson@arm.com // Writeback snoops into upper level caches to check for copies of the 239711051Sandreas.hansson@arm.com // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict 239811051Sandreas.hansson@arm.com // packet, the cache can inform the crossbar below of presence or absence 239911051Sandreas.hansson@arm.com // of the block. 240011130Sali.jafri@arm.com if (is_timing) { 240111130Sali.jafri@arm.com Packet snoop_pkt(pkt, true, false); 240211130Sali.jafri@arm.com snoop_pkt.setExpressSnoop(); 240311130Sali.jafri@arm.com // Assert that packet is either Writeback or CleanEvict and not a 240411130Sali.jafri@arm.com // prefetch request because prefetch requests need an MSHR and may 240511130Sali.jafri@arm.com // generate a snoop response. 240612345Snikos.nikoleris@arm.com assert(pkt->isEviction() || pkt->cmd == MemCmd::WriteClean); 240711484Snikos.nikoleris@arm.com snoop_pkt.senderState = nullptr; 240811130Sali.jafri@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 240911130Sali.jafri@arm.com // Writeback/CleanEvict snoops do not generate a snoop response. 241011284Sandreas.hansson@arm.com assert(!(snoop_pkt.cacheResponding())); 241111130Sali.jafri@arm.com return snoop_pkt.isBlockCached(); 241211130Sali.jafri@arm.com } else { 241311130Sali.jafri@arm.com cpuSidePort->sendAtomicSnoop(pkt); 241411130Sali.jafri@arm.com return pkt->isBlockCached(); 241511130Sali.jafri@arm.com } 241611051Sandreas.hansson@arm.com} 241711051Sandreas.hansson@arm.com 241811375Sandreas.hansson@arm.comTick 241911375Sandreas.hansson@arm.comCache::nextQueueReadyTime() const 242011051Sandreas.hansson@arm.com{ 242111375Sandreas.hansson@arm.com Tick nextReady = std::min(mshrQueue.nextReadyTime(), 242211375Sandreas.hansson@arm.com writeBuffer.nextReadyTime()); 242311375Sandreas.hansson@arm.com 242411375Sandreas.hansson@arm.com // Don't signal prefetch ready time if no MSHRs available 242511375Sandreas.hansson@arm.com // Will signal once enoguh MSHRs are deallocated 242611375Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 242711375Sandreas.hansson@arm.com nextReady = std::min(nextReady, 242811375Sandreas.hansson@arm.com prefetcher->nextPrefetchReadyTime()); 242911051Sandreas.hansson@arm.com } 243011051Sandreas.hansson@arm.com 243111375Sandreas.hansson@arm.com return nextReady; 243211375Sandreas.hansson@arm.com} 243311375Sandreas.hansson@arm.com 243411375Sandreas.hansson@arm.combool 243511375Sandreas.hansson@arm.comCache::sendMSHRQueuePacket(MSHR* mshr) 243611375Sandreas.hansson@arm.com{ 243711375Sandreas.hansson@arm.com assert(mshr); 243811375Sandreas.hansson@arm.com 243911051Sandreas.hansson@arm.com // use request from 1st target 244011051Sandreas.hansson@arm.com PacketPtr tgt_pkt = mshr->getTarget()->pkt; 244111375Sandreas.hansson@arm.com 244211744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print()); 244311051Sandreas.hansson@arm.com 244411051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 244511051Sandreas.hansson@arm.com 244611051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) { 244711375Sandreas.hansson@arm.com // we should never have hardware prefetches to allocated 244811375Sandreas.hansson@arm.com // blocks 244911484Snikos.nikoleris@arm.com assert(blk == nullptr); 245011375Sandreas.hansson@arm.com 245111051Sandreas.hansson@arm.com // We need to check the caches above us to verify that 245211051Sandreas.hansson@arm.com // they don't have a copy of this block in the dirty state 245311051Sandreas.hansson@arm.com // at the moment. Without this check we could get a stale 245411051Sandreas.hansson@arm.com // copy from memory that might get used in place of the 245511051Sandreas.hansson@arm.com // dirty one. 245611051Sandreas.hansson@arm.com Packet snoop_pkt(tgt_pkt, true, false); 245711051Sandreas.hansson@arm.com snoop_pkt.setExpressSnoop(); 245811275Sandreas.hansson@arm.com // We are sending this packet upwards, but if it hits we will 245911275Sandreas.hansson@arm.com // get a snoop response that we end up treating just like a 246011275Sandreas.hansson@arm.com // normal response, hence it needs the MSHR as its sender 246111275Sandreas.hansson@arm.com // state 246211051Sandreas.hansson@arm.com snoop_pkt.senderState = mshr; 246311051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 246411051Sandreas.hansson@arm.com 246511051Sandreas.hansson@arm.com // Check to see if the prefetch was squashed by an upper cache (to 246611051Sandreas.hansson@arm.com // prevent us from grabbing the line) or if a Check to see if a 246711051Sandreas.hansson@arm.com // writeback arrived between the time the prefetch was placed in 246811051Sandreas.hansson@arm.com // the MSHRs and when it was selected to be sent or if the 246911051Sandreas.hansson@arm.com // prefetch was squashed by an upper cache. 247011051Sandreas.hansson@arm.com 247111284Sandreas.hansson@arm.com // It is important to check cacheResponding before 247211284Sandreas.hansson@arm.com // prefetchSquashed. If another cache has committed to 247311284Sandreas.hansson@arm.com // responding, it will be sending a dirty response which will 247411284Sandreas.hansson@arm.com // arrive at the MSHR allocated for this request. Checking the 247511284Sandreas.hansson@arm.com // prefetchSquash first may result in the MSHR being 247611284Sandreas.hansson@arm.com // prematurely deallocated. 247711284Sandreas.hansson@arm.com if (snoop_pkt.cacheResponding()) { 247811276Sandreas.hansson@arm.com auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req); 247911276Sandreas.hansson@arm.com assert(r.second); 248011284Sandreas.hansson@arm.com 248111284Sandreas.hansson@arm.com // if we are getting a snoop response with no sharers it 248211284Sandreas.hansson@arm.com // will be allocated as Modified 248311284Sandreas.hansson@arm.com bool pending_modified_resp = !snoop_pkt.hasSharers(); 248411284Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 248511284Sandreas.hansson@arm.com 248611051Sandreas.hansson@arm.com DPRINTF(Cache, "Upward snoop of prefetch for addr" 248711051Sandreas.hansson@arm.com " %#x (%s) hit\n", 248811051Sandreas.hansson@arm.com tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns"); 248911375Sandreas.hansson@arm.com return false; 249011051Sandreas.hansson@arm.com } 249111051Sandreas.hansson@arm.com 249211375Sandreas.hansson@arm.com if (snoop_pkt.isBlockCached()) { 249311051Sandreas.hansson@arm.com DPRINTF(Cache, "Block present, prefetch squashed by cache. " 249411051Sandreas.hansson@arm.com "Deallocating mshr target %#x.\n", 249511051Sandreas.hansson@arm.com mshr->blkAddr); 249611375Sandreas.hansson@arm.com 249711051Sandreas.hansson@arm.com // Deallocate the mshr target 249811375Sandreas.hansson@arm.com if (mshrQueue.forceDeallocateTarget(mshr)) { 249911277Sandreas.hansson@arm.com // Clear block if this deallocation resulted freed an 250011277Sandreas.hansson@arm.com // mshr when all had previously been utilized 250111375Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 250211051Sandreas.hansson@arm.com } 250312167Spau.cabre@metempsy.com 250412167Spau.cabre@metempsy.com // given that no response is expected, delete Request and Packet 250512167Spau.cabre@metempsy.com delete tgt_pkt->req; 250612167Spau.cabre@metempsy.com delete tgt_pkt; 250712167Spau.cabre@metempsy.com 250811375Sandreas.hansson@arm.com return false; 250911051Sandreas.hansson@arm.com } 251011051Sandreas.hansson@arm.com } 251111051Sandreas.hansson@arm.com 251211375Sandreas.hansson@arm.com // either a prefetch that is not present upstream, or a normal 251311375Sandreas.hansson@arm.com // MSHR request, proceed to get the packet to send downstream 251411452Sandreas.hansson@arm.com PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable()); 251511375Sandreas.hansson@arm.com 251611484Snikos.nikoleris@arm.com mshr->isForward = (pkt == nullptr); 251711375Sandreas.hansson@arm.com 251811375Sandreas.hansson@arm.com if (mshr->isForward) { 251911375Sandreas.hansson@arm.com // not a cache block request, but a response is expected 252011375Sandreas.hansson@arm.com // make copy of current packet to forward, keep current 252111375Sandreas.hansson@arm.com // copy for response handling 252211375Sandreas.hansson@arm.com pkt = new Packet(tgt_pkt, false, true); 252311375Sandreas.hansson@arm.com assert(!pkt->isWrite()); 252411375Sandreas.hansson@arm.com } 252511375Sandreas.hansson@arm.com 252611375Sandreas.hansson@arm.com // play it safe and append (rather than set) the sender state, 252711375Sandreas.hansson@arm.com // as forwarded packets may already have existing state 252811375Sandreas.hansson@arm.com pkt->pushSenderState(mshr); 252911375Sandreas.hansson@arm.com 253011375Sandreas.hansson@arm.com if (!memSidePort->sendTimingReq(pkt)) { 253111375Sandreas.hansson@arm.com // we are awaiting a retry, but we 253211375Sandreas.hansson@arm.com // delete the packet and will be creating a new packet 253311375Sandreas.hansson@arm.com // when we get the opportunity 253411375Sandreas.hansson@arm.com delete pkt; 253511375Sandreas.hansson@arm.com 253611375Sandreas.hansson@arm.com // note that we have now masked any requestBus and 253711375Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 253811375Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 253911375Sandreas.hansson@arm.com // care about this packet and might override it before 254011375Sandreas.hansson@arm.com // it gets retried 254111375Sandreas.hansson@arm.com return true; 254211375Sandreas.hansson@arm.com } else { 254311375Sandreas.hansson@arm.com // As part of the call to sendTimingReq the packet is 254411375Sandreas.hansson@arm.com // forwarded to all neighbouring caches (and any caches 254511375Sandreas.hansson@arm.com // above them) as a snoop. Thus at this point we know if 254611375Sandreas.hansson@arm.com // any of the neighbouring caches are responding, and if 254711375Sandreas.hansson@arm.com // so, we know it is dirty, and we can determine if it is 254811375Sandreas.hansson@arm.com // being passed as Modified, making our MSHR the ordering 254911375Sandreas.hansson@arm.com // point 255011375Sandreas.hansson@arm.com bool pending_modified_resp = !pkt->hasSharers() && 255111375Sandreas.hansson@arm.com pkt->cacheResponding(); 255211375Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 255311375Sandreas.hansson@arm.com return false; 255411375Sandreas.hansson@arm.com } 255511375Sandreas.hansson@arm.com} 255611375Sandreas.hansson@arm.com 255711375Sandreas.hansson@arm.combool 255811375Sandreas.hansson@arm.comCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry) 255911375Sandreas.hansson@arm.com{ 256011375Sandreas.hansson@arm.com assert(wq_entry); 256111375Sandreas.hansson@arm.com 256211375Sandreas.hansson@arm.com // always a single target for write queue entries 256311375Sandreas.hansson@arm.com PacketPtr tgt_pkt = wq_entry->getTarget()->pkt; 256411375Sandreas.hansson@arm.com 256511744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print()); 256611375Sandreas.hansson@arm.com 256711453Sandreas.hansson@arm.com // forward as is, both for evictions and uncacheable writes 256811453Sandreas.hansson@arm.com if (!memSidePort->sendTimingReq(tgt_pkt)) { 256911375Sandreas.hansson@arm.com // note that we have now masked any requestBus and 257011375Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 257111375Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 257211375Sandreas.hansson@arm.com // care about this packet and might override it before 257311375Sandreas.hansson@arm.com // it gets retried 257411375Sandreas.hansson@arm.com return true; 257511375Sandreas.hansson@arm.com } else { 257611375Sandreas.hansson@arm.com markInService(wq_entry); 257711375Sandreas.hansson@arm.com return false; 257811051Sandreas.hansson@arm.com } 257911051Sandreas.hansson@arm.com} 258011051Sandreas.hansson@arm.com 258111051Sandreas.hansson@arm.comvoid 258211051Sandreas.hansson@arm.comCache::serialize(CheckpointOut &cp) const 258311051Sandreas.hansson@arm.com{ 258411051Sandreas.hansson@arm.com bool dirty(isDirty()); 258511051Sandreas.hansson@arm.com 258611051Sandreas.hansson@arm.com if (dirty) { 258711051Sandreas.hansson@arm.com warn("*** The cache still contains dirty data. ***\n"); 258811051Sandreas.hansson@arm.com warn(" Make sure to drain the system using the correct flags.\n"); 258911483Snikos.nikoleris@arm.com warn(" This checkpoint will not restore correctly and dirty data " 259011483Snikos.nikoleris@arm.com " in the cache will be lost!\n"); 259111051Sandreas.hansson@arm.com } 259211051Sandreas.hansson@arm.com 259311051Sandreas.hansson@arm.com // Since we don't checkpoint the data in the cache, any dirty data 259411051Sandreas.hansson@arm.com // will be lost when restoring from a checkpoint of a system that 259511051Sandreas.hansson@arm.com // wasn't drained properly. Flag the checkpoint as invalid if the 259611051Sandreas.hansson@arm.com // cache contains dirty data. 259711051Sandreas.hansson@arm.com bool bad_checkpoint(dirty); 259811051Sandreas.hansson@arm.com SERIALIZE_SCALAR(bad_checkpoint); 259911051Sandreas.hansson@arm.com} 260011051Sandreas.hansson@arm.com 260111051Sandreas.hansson@arm.comvoid 260211051Sandreas.hansson@arm.comCache::unserialize(CheckpointIn &cp) 260311051Sandreas.hansson@arm.com{ 260411051Sandreas.hansson@arm.com bool bad_checkpoint; 260511051Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(bad_checkpoint); 260611051Sandreas.hansson@arm.com if (bad_checkpoint) { 260711051Sandreas.hansson@arm.com fatal("Restoring from checkpoints with dirty caches is not supported " 260811051Sandreas.hansson@arm.com "in the classic memory system. Please remove any caches or " 260911051Sandreas.hansson@arm.com " drain them properly before taking checkpoints.\n"); 261011051Sandreas.hansson@arm.com } 261111051Sandreas.hansson@arm.com} 261211051Sandreas.hansson@arm.com 261311051Sandreas.hansson@arm.com/////////////// 261411051Sandreas.hansson@arm.com// 261511051Sandreas.hansson@arm.com// CpuSidePort 261611051Sandreas.hansson@arm.com// 261711051Sandreas.hansson@arm.com/////////////// 261811051Sandreas.hansson@arm.com 261911051Sandreas.hansson@arm.comAddrRangeList 262011051Sandreas.hansson@arm.comCache::CpuSidePort::getAddrRanges() const 262111051Sandreas.hansson@arm.com{ 262211051Sandreas.hansson@arm.com return cache->getAddrRanges(); 262311051Sandreas.hansson@arm.com} 262411051Sandreas.hansson@arm.com 262511051Sandreas.hansson@arm.combool 262612343Snikos.nikoleris@arm.comCache::CpuSidePort::tryTiming(PacketPtr pkt) 262712343Snikos.nikoleris@arm.com{ 262812343Snikos.nikoleris@arm.com assert(!cache->system->bypassCaches()); 262912343Snikos.nikoleris@arm.com 263012343Snikos.nikoleris@arm.com // always let express snoop packets through if even if blocked 263112343Snikos.nikoleris@arm.com if (pkt->isExpressSnoop()) { 263212343Snikos.nikoleris@arm.com return true; 263312343Snikos.nikoleris@arm.com } else if (isBlocked() || mustSendRetry) { 263412343Snikos.nikoleris@arm.com // either already committed to send a retry, or blocked 263512343Snikos.nikoleris@arm.com mustSendRetry = true; 263612343Snikos.nikoleris@arm.com return false; 263712343Snikos.nikoleris@arm.com } 263812343Snikos.nikoleris@arm.com mustSendRetry = false; 263912343Snikos.nikoleris@arm.com return true; 264012343Snikos.nikoleris@arm.com} 264112343Snikos.nikoleris@arm.com 264212343Snikos.nikoleris@arm.combool 264311051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingReq(PacketPtr pkt) 264411051Sandreas.hansson@arm.com{ 264511051Sandreas.hansson@arm.com assert(!cache->system->bypassCaches()); 264611051Sandreas.hansson@arm.com 264711334Sandreas.hansson@arm.com // always let express snoop packets through if even if blocked 264811334Sandreas.hansson@arm.com if (pkt->isExpressSnoop()) { 264911051Sandreas.hansson@arm.com bool M5_VAR_USED bypass_success = cache->recvTimingReq(pkt); 265011051Sandreas.hansson@arm.com assert(bypass_success); 265111051Sandreas.hansson@arm.com return true; 265211051Sandreas.hansson@arm.com } 265311051Sandreas.hansson@arm.com 265412343Snikos.nikoleris@arm.com return tryTiming(pkt) && cache->recvTimingReq(pkt); 265511051Sandreas.hansson@arm.com} 265611051Sandreas.hansson@arm.com 265711051Sandreas.hansson@arm.comTick 265811051Sandreas.hansson@arm.comCache::CpuSidePort::recvAtomic(PacketPtr pkt) 265911051Sandreas.hansson@arm.com{ 266011051Sandreas.hansson@arm.com return cache->recvAtomic(pkt); 266111051Sandreas.hansson@arm.com} 266211051Sandreas.hansson@arm.com 266311051Sandreas.hansson@arm.comvoid 266411051Sandreas.hansson@arm.comCache::CpuSidePort::recvFunctional(PacketPtr pkt) 266511051Sandreas.hansson@arm.com{ 266611051Sandreas.hansson@arm.com // functional request 266711051Sandreas.hansson@arm.com cache->functionalAccess(pkt, true); 266811051Sandreas.hansson@arm.com} 266911051Sandreas.hansson@arm.com 267011051Sandreas.hansson@arm.comCache:: 267111051Sandreas.hansson@arm.comCpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache, 267211051Sandreas.hansson@arm.com const std::string &_label) 267311051Sandreas.hansson@arm.com : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache) 267411051Sandreas.hansson@arm.com{ 267511051Sandreas.hansson@arm.com} 267611051Sandreas.hansson@arm.com 267711053Sandreas.hansson@arm.comCache* 267811053Sandreas.hansson@arm.comCacheParams::create() 267911053Sandreas.hansson@arm.com{ 268011053Sandreas.hansson@arm.com assert(tags); 268111053Sandreas.hansson@arm.com 268211053Sandreas.hansson@arm.com return new Cache(this); 268311053Sandreas.hansson@arm.com} 268411051Sandreas.hansson@arm.com/////////////// 268511051Sandreas.hansson@arm.com// 268611051Sandreas.hansson@arm.com// MemSidePort 268711051Sandreas.hansson@arm.com// 268811051Sandreas.hansson@arm.com/////////////// 268911051Sandreas.hansson@arm.com 269011051Sandreas.hansson@arm.combool 269111051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingResp(PacketPtr pkt) 269211051Sandreas.hansson@arm.com{ 269311051Sandreas.hansson@arm.com cache->recvTimingResp(pkt); 269411051Sandreas.hansson@arm.com return true; 269511051Sandreas.hansson@arm.com} 269611051Sandreas.hansson@arm.com 269711051Sandreas.hansson@arm.com// Express snooping requests to memside port 269811051Sandreas.hansson@arm.comvoid 269911051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 270011051Sandreas.hansson@arm.com{ 270111051Sandreas.hansson@arm.com // handle snooping requests 270211051Sandreas.hansson@arm.com cache->recvTimingSnoopReq(pkt); 270311051Sandreas.hansson@arm.com} 270411051Sandreas.hansson@arm.com 270511051Sandreas.hansson@arm.comTick 270611051Sandreas.hansson@arm.comCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 270711051Sandreas.hansson@arm.com{ 270811051Sandreas.hansson@arm.com return cache->recvAtomicSnoop(pkt); 270911051Sandreas.hansson@arm.com} 271011051Sandreas.hansson@arm.com 271111051Sandreas.hansson@arm.comvoid 271211051Sandreas.hansson@arm.comCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 271311051Sandreas.hansson@arm.com{ 271411051Sandreas.hansson@arm.com // functional snoop (note that in contrast to atomic we don't have 271511051Sandreas.hansson@arm.com // a specific functionalSnoop method, as they have the same 271611051Sandreas.hansson@arm.com // behaviour regardless) 271711051Sandreas.hansson@arm.com cache->functionalAccess(pkt, false); 271811051Sandreas.hansson@arm.com} 271911051Sandreas.hansson@arm.com 272011051Sandreas.hansson@arm.comvoid 272111051Sandreas.hansson@arm.comCache::CacheReqPacketQueue::sendDeferredPacket() 272211051Sandreas.hansson@arm.com{ 272311051Sandreas.hansson@arm.com // sanity check 272411051Sandreas.hansson@arm.com assert(!waitingOnRetry); 272511051Sandreas.hansson@arm.com 272611051Sandreas.hansson@arm.com // there should never be any deferred request packets in the 272711051Sandreas.hansson@arm.com // queue, instead we resly on the cache to provide the packets 272811051Sandreas.hansson@arm.com // from the MSHR queue or write queue 272911051Sandreas.hansson@arm.com assert(deferredPacketReadyTime() == MaxTick); 273011051Sandreas.hansson@arm.com 273111051Sandreas.hansson@arm.com // check for request packets (requests & writebacks) 273211375Sandreas.hansson@arm.com QueueEntry* entry = cache.getNextQueueEntry(); 273311375Sandreas.hansson@arm.com 273411375Sandreas.hansson@arm.com if (!entry) { 273511051Sandreas.hansson@arm.com // can happen if e.g. we attempt a writeback and fail, but 273611051Sandreas.hansson@arm.com // before the retry, the writeback is eliminated because 273711051Sandreas.hansson@arm.com // we snoop another cache's ReadEx. 273811051Sandreas.hansson@arm.com } else { 273911051Sandreas.hansson@arm.com // let our snoop responses go first if there are responses to 274011375Sandreas.hansson@arm.com // the same addresses 274111375Sandreas.hansson@arm.com if (checkConflictingSnoop(entry->blkAddr)) { 274211051Sandreas.hansson@arm.com return; 274311051Sandreas.hansson@arm.com } 274411375Sandreas.hansson@arm.com waitingOnRetry = entry->sendPacket(cache); 274511051Sandreas.hansson@arm.com } 274611051Sandreas.hansson@arm.com 274711051Sandreas.hansson@arm.com // if we succeeded and are not waiting for a retry, schedule the 274811375Sandreas.hansson@arm.com // next send considering when the next queue is ready, note that 274911051Sandreas.hansson@arm.com // snoop responses have their own packet queue and thus schedule 275011051Sandreas.hansson@arm.com // their own events 275111051Sandreas.hansson@arm.com if (!waitingOnRetry) { 275211375Sandreas.hansson@arm.com schedSendEvent(cache.nextQueueReadyTime()); 275311051Sandreas.hansson@arm.com } 275411051Sandreas.hansson@arm.com} 275511051Sandreas.hansson@arm.com 275611051Sandreas.hansson@arm.comCache:: 275711051Sandreas.hansson@arm.comMemSidePort::MemSidePort(const std::string &_name, Cache *_cache, 275811051Sandreas.hansson@arm.com const std::string &_label) 275911051Sandreas.hansson@arm.com : BaseCache::CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 276011051Sandreas.hansson@arm.com _reqQueue(*_cache, *this, _snoopRespQueue, _label), 276111051Sandreas.hansson@arm.com _snoopRespQueue(*_cache, *this, _label), cache(_cache) 276211051Sandreas.hansson@arm.com{ 276311051Sandreas.hansson@arm.com} 2764