cache.cc revision 11750
12810Srdreslin@umich.edu/* 211375Sandreas.hansson@arm.com * Copyright (c) 2010-2016 ARM Limited 311051Sandreas.hansson@arm.com * All rights reserved. 411051Sandreas.hansson@arm.com * 511051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911051Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311051Sandreas.hansson@arm.com * 1411051Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511051Sandreas.hansson@arm.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 162810Srdreslin@umich.edu * All rights reserved. 172810Srdreslin@umich.edu * 182810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 192810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 202810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 212810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 222810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 232810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 242810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 252810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 262810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 272810Srdreslin@umich.edu * this software without specific prior written permission. 282810Srdreslin@umich.edu * 292810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810Srdreslin@umich.edu * 412810Srdreslin@umich.edu * Authors: Erik Hallnor 4211051Sandreas.hansson@arm.com * Dave Greene 4311051Sandreas.hansson@arm.com * Nathan Binkert 442810Srdreslin@umich.edu * Steve Reinhardt 4511051Sandreas.hansson@arm.com * Ron Dreslinski 4611051Sandreas.hansson@arm.com * Andreas Sandberg 472810Srdreslin@umich.edu */ 482810Srdreslin@umich.edu 492810Srdreslin@umich.edu/** 502810Srdreslin@umich.edu * @file 5111051Sandreas.hansson@arm.com * Cache definitions. 522810Srdreslin@umich.edu */ 532810Srdreslin@umich.edu 5411051Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 552810Srdreslin@umich.edu 5611051Sandreas.hansson@arm.com#include "base/misc.hh" 5711051Sandreas.hansson@arm.com#include "base/types.hh" 5811051Sandreas.hansson@arm.com#include "debug/Cache.hh" 5911051Sandreas.hansson@arm.com#include "debug/CachePort.hh" 6011051Sandreas.hansson@arm.com#include "debug/CacheTags.hh" 6111288Ssteve.reinhardt@amd.com#include "debug/CacheVerbose.hh" 6211051Sandreas.hansson@arm.com#include "mem/cache/blk.hh" 6311051Sandreas.hansson@arm.com#include "mem/cache/mshr.hh" 6411051Sandreas.hansson@arm.com#include "mem/cache/prefetch/base.hh" 6511051Sandreas.hansson@arm.com#include "sim/sim_exit.hh" 6611051Sandreas.hansson@arm.com 6711053Sandreas.hansson@arm.comCache::Cache(const CacheParams *p) 6811053Sandreas.hansson@arm.com : BaseCache(p, p->system->cacheLineSize()), 6911051Sandreas.hansson@arm.com tags(p->tags), 7011051Sandreas.hansson@arm.com prefetcher(p->prefetcher), 7111051Sandreas.hansson@arm.com doFastWrites(true), 7211197Sandreas.hansson@arm.com prefetchOnAccess(p->prefetch_on_access), 7311197Sandreas.hansson@arm.com clusivity(p->clusivity), 7411199Sandreas.hansson@arm.com writebackClean(p->writeback_clean), 7511197Sandreas.hansson@arm.com tempBlockWriteback(nullptr), 7611197Sandreas.hansson@arm.com writebackTempBlockAtomicEvent(this, false, 7711197Sandreas.hansson@arm.com EventBase::Delayed_Writeback_Pri) 7811051Sandreas.hansson@arm.com{ 7911051Sandreas.hansson@arm.com tempBlock = new CacheBlk(); 8011051Sandreas.hansson@arm.com tempBlock->data = new uint8_t[blkSize]; 8111051Sandreas.hansson@arm.com 8211051Sandreas.hansson@arm.com cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this, 8311051Sandreas.hansson@arm.com "CpuSidePort"); 8411051Sandreas.hansson@arm.com memSidePort = new MemSidePort(p->name + ".mem_side", this, 8511051Sandreas.hansson@arm.com "MemSidePort"); 8611051Sandreas.hansson@arm.com 8711051Sandreas.hansson@arm.com tags->setCache(this); 8811051Sandreas.hansson@arm.com if (prefetcher) 8911051Sandreas.hansson@arm.com prefetcher->setCache(this); 9011051Sandreas.hansson@arm.com} 9111051Sandreas.hansson@arm.com 9211051Sandreas.hansson@arm.comCache::~Cache() 9311051Sandreas.hansson@arm.com{ 9411051Sandreas.hansson@arm.com delete [] tempBlock->data; 9511051Sandreas.hansson@arm.com delete tempBlock; 9611051Sandreas.hansson@arm.com 9711051Sandreas.hansson@arm.com delete cpuSidePort; 9811051Sandreas.hansson@arm.com delete memSidePort; 9911051Sandreas.hansson@arm.com} 10011051Sandreas.hansson@arm.com 10111051Sandreas.hansson@arm.comvoid 10211051Sandreas.hansson@arm.comCache::regStats() 10311051Sandreas.hansson@arm.com{ 10411051Sandreas.hansson@arm.com BaseCache::regStats(); 10511051Sandreas.hansson@arm.com} 10611051Sandreas.hansson@arm.com 10711051Sandreas.hansson@arm.comvoid 10811051Sandreas.hansson@arm.comCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 10911051Sandreas.hansson@arm.com{ 11011051Sandreas.hansson@arm.com assert(pkt->isRequest()); 11111051Sandreas.hansson@arm.com 11211051Sandreas.hansson@arm.com uint64_t overwrite_val; 11311051Sandreas.hansson@arm.com bool overwrite_mem; 11411051Sandreas.hansson@arm.com uint64_t condition_val64; 11511051Sandreas.hansson@arm.com uint32_t condition_val32; 11611051Sandreas.hansson@arm.com 11711051Sandreas.hansson@arm.com int offset = tags->extractBlkOffset(pkt->getAddr()); 11811051Sandreas.hansson@arm.com uint8_t *blk_data = blk->data + offset; 11911051Sandreas.hansson@arm.com 12011051Sandreas.hansson@arm.com assert(sizeof(uint64_t) >= pkt->getSize()); 12111051Sandreas.hansson@arm.com 12211051Sandreas.hansson@arm.com overwrite_mem = true; 12311051Sandreas.hansson@arm.com // keep a copy of our possible write value, and copy what is at the 12411051Sandreas.hansson@arm.com // memory address into the packet 12511051Sandreas.hansson@arm.com pkt->writeData((uint8_t *)&overwrite_val); 12611051Sandreas.hansson@arm.com pkt->setData(blk_data); 12711051Sandreas.hansson@arm.com 12811051Sandreas.hansson@arm.com if (pkt->req->isCondSwap()) { 12911051Sandreas.hansson@arm.com if (pkt->getSize() == sizeof(uint64_t)) { 13011051Sandreas.hansson@arm.com condition_val64 = pkt->req->getExtraData(); 13111051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val64, blk_data, 13211051Sandreas.hansson@arm.com sizeof(uint64_t)); 13311051Sandreas.hansson@arm.com } else if (pkt->getSize() == sizeof(uint32_t)) { 13411051Sandreas.hansson@arm.com condition_val32 = (uint32_t)pkt->req->getExtraData(); 13511051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val32, blk_data, 13611051Sandreas.hansson@arm.com sizeof(uint32_t)); 13711051Sandreas.hansson@arm.com } else 13811051Sandreas.hansson@arm.com panic("Invalid size for conditional read/write\n"); 13911051Sandreas.hansson@arm.com } 14011051Sandreas.hansson@arm.com 14111051Sandreas.hansson@arm.com if (overwrite_mem) { 14211051Sandreas.hansson@arm.com std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 14311051Sandreas.hansson@arm.com blk->status |= BlkDirty; 14411051Sandreas.hansson@arm.com } 14511051Sandreas.hansson@arm.com} 14611051Sandreas.hansson@arm.com 14711051Sandreas.hansson@arm.com 14811051Sandreas.hansson@arm.comvoid 14911601Sandreas.hansson@arm.comCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, 15011601Sandreas.hansson@arm.com bool deferred_response, bool pending_downgrade) 15111051Sandreas.hansson@arm.com{ 15211051Sandreas.hansson@arm.com assert(pkt->isRequest()); 15311051Sandreas.hansson@arm.com 15411051Sandreas.hansson@arm.com assert(blk && blk->isValid()); 15511051Sandreas.hansson@arm.com // Occasionally this is not true... if we are a lower-level cache 15611051Sandreas.hansson@arm.com // satisfying a string of Read and ReadEx requests from 15711051Sandreas.hansson@arm.com // upper-level caches, a Read will mark the block as shared but we 15811051Sandreas.hansson@arm.com // can satisfy a following ReadEx anyway since we can rely on the 15911051Sandreas.hansson@arm.com // Read requester(s) to have buffered the ReadEx snoop and to 16011051Sandreas.hansson@arm.com // invalidate their blocks after receiving them. 16111284Sandreas.hansson@arm.com // assert(!pkt->needsWritable() || blk->isWritable()); 16211051Sandreas.hansson@arm.com assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 16311051Sandreas.hansson@arm.com 16411051Sandreas.hansson@arm.com // Check RMW operations first since both isRead() and 16511051Sandreas.hansson@arm.com // isWrite() will be true for them 16611051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::SwapReq) { 16711051Sandreas.hansson@arm.com cmpAndSwap(blk, pkt); 16811051Sandreas.hansson@arm.com } else if (pkt->isWrite()) { 16911284Sandreas.hansson@arm.com // we have the block in a writable state and can go ahead, 17011284Sandreas.hansson@arm.com // note that the line may be also be considered writable in 17111284Sandreas.hansson@arm.com // downstream caches along the path to memory, but always 17211284Sandreas.hansson@arm.com // Exclusive, and never Modified 17311051Sandreas.hansson@arm.com assert(blk->isWritable()); 17411284Sandreas.hansson@arm.com // Write or WriteLine at the first cache with block in writable state 17511051Sandreas.hansson@arm.com if (blk->checkWrite(pkt)) { 17611051Sandreas.hansson@arm.com pkt->writeDataToBlock(blk->data, blkSize); 17711051Sandreas.hansson@arm.com } 17811284Sandreas.hansson@arm.com // Always mark the line as dirty (and thus transition to the 17911284Sandreas.hansson@arm.com // Modified state) even if we are a failed StoreCond so we 18011284Sandreas.hansson@arm.com // supply data to any snoops that have appended themselves to 18111284Sandreas.hansson@arm.com // this cache before knowing the store will fail. 18211051Sandreas.hansson@arm.com blk->status |= BlkDirty; 18311744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s (write)\n", __func__, pkt->print()); 18411051Sandreas.hansson@arm.com } else if (pkt->isRead()) { 18511051Sandreas.hansson@arm.com if (pkt->isLLSC()) { 18611051Sandreas.hansson@arm.com blk->trackLoadLocked(pkt); 18711051Sandreas.hansson@arm.com } 18811286Sandreas.hansson@arm.com 18911286Sandreas.hansson@arm.com // all read responses have a data payload 19011286Sandreas.hansson@arm.com assert(pkt->hasRespData()); 19111051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 19211286Sandreas.hansson@arm.com 19311600Sandreas.hansson@arm.com // determine if this read is from a (coherent) cache or not 19411600Sandreas.hansson@arm.com if (pkt->fromCache()) { 19511051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 19611051Sandreas.hansson@arm.com // special handling for coherent block requests from 19711051Sandreas.hansson@arm.com // upper-level caches 19811284Sandreas.hansson@arm.com if (pkt->needsWritable()) { 19911051Sandreas.hansson@arm.com // sanity check 20011051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::ReadExReq || 20111051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq); 20211602Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 20311051Sandreas.hansson@arm.com 20411051Sandreas.hansson@arm.com // if we have a dirty copy, make sure the recipient 20511284Sandreas.hansson@arm.com // keeps it marked dirty (in the modified state) 20611051Sandreas.hansson@arm.com if (blk->isDirty()) { 20711284Sandreas.hansson@arm.com pkt->setCacheResponding(); 20811602Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 20911051Sandreas.hansson@arm.com } 21011051Sandreas.hansson@arm.com } else if (blk->isWritable() && !pending_downgrade && 21111284Sandreas.hansson@arm.com !pkt->hasSharers() && 21211051Sandreas.hansson@arm.com pkt->cmd != MemCmd::ReadCleanReq) { 21311284Sandreas.hansson@arm.com // we can give the requester a writable copy on a read 21411284Sandreas.hansson@arm.com // request if: 21511284Sandreas.hansson@arm.com // - we have a writable copy at this level (& below) 21611051Sandreas.hansson@arm.com // - we don't have a pending snoop from below 21711051Sandreas.hansson@arm.com // signaling another read request 21811051Sandreas.hansson@arm.com // - no other cache above has a copy (otherwise it 21911284Sandreas.hansson@arm.com // would have set hasSharers flag when 22011284Sandreas.hansson@arm.com // snooping the packet) 22111284Sandreas.hansson@arm.com // - the read has explicitly asked for a clean 22211284Sandreas.hansson@arm.com // copy of the line 22311051Sandreas.hansson@arm.com if (blk->isDirty()) { 22411051Sandreas.hansson@arm.com // special considerations if we're owner: 22511051Sandreas.hansson@arm.com if (!deferred_response) { 22611284Sandreas.hansson@arm.com // respond with the line in Modified state 22711284Sandreas.hansson@arm.com // (cacheResponding set, hasSharers not set) 22811284Sandreas.hansson@arm.com pkt->setCacheResponding(); 22911197Sandreas.hansson@arm.com 23011601Sandreas.hansson@arm.com // if this cache is mostly inclusive, we 23111601Sandreas.hansson@arm.com // keep the block in the Exclusive state, 23211601Sandreas.hansson@arm.com // and pass it upwards as Modified 23311601Sandreas.hansson@arm.com // (writable and dirty), hence we have 23411601Sandreas.hansson@arm.com // multiple caches, all on the same path 23511601Sandreas.hansson@arm.com // towards memory, all considering the 23611601Sandreas.hansson@arm.com // same block writable, but only one 23711601Sandreas.hansson@arm.com // considering it Modified 23811197Sandreas.hansson@arm.com 23911601Sandreas.hansson@arm.com // we get away with multiple caches (on 24011601Sandreas.hansson@arm.com // the same path to memory) considering 24111601Sandreas.hansson@arm.com // the block writeable as we always enter 24211601Sandreas.hansson@arm.com // the cache hierarchy through a cache, 24311601Sandreas.hansson@arm.com // and first snoop upwards in all other 24411601Sandreas.hansson@arm.com // branches 24511601Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 24611051Sandreas.hansson@arm.com } else { 24711051Sandreas.hansson@arm.com // if we're responding after our own miss, 24811051Sandreas.hansson@arm.com // there's a window where the recipient didn't 24911051Sandreas.hansson@arm.com // know it was getting ownership and may not 25011051Sandreas.hansson@arm.com // have responded to snoops correctly, so we 25111284Sandreas.hansson@arm.com // have to respond with a shared line 25211284Sandreas.hansson@arm.com pkt->setHasSharers(); 25311051Sandreas.hansson@arm.com } 25411051Sandreas.hansson@arm.com } 25511051Sandreas.hansson@arm.com } else { 25611051Sandreas.hansson@arm.com // otherwise only respond with a shared copy 25711284Sandreas.hansson@arm.com pkt->setHasSharers(); 25811051Sandreas.hansson@arm.com } 25911051Sandreas.hansson@arm.com } 26011602Sandreas.hansson@arm.com } else if (pkt->isUpgrade()) { 26111602Sandreas.hansson@arm.com // sanity check 26211602Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 26311602Sandreas.hansson@arm.com 26411602Sandreas.hansson@arm.com if (blk->isDirty()) { 26511602Sandreas.hansson@arm.com // we were in the Owned state, and a cache above us that 26611602Sandreas.hansson@arm.com // has the line in Shared state needs to be made aware 26711602Sandreas.hansson@arm.com // that the data it already has is in fact dirty 26811602Sandreas.hansson@arm.com pkt->setCacheResponding(); 26911602Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 27011602Sandreas.hansson@arm.com } 27111051Sandreas.hansson@arm.com } else { 27211602Sandreas.hansson@arm.com assert(pkt->isInvalidate()); 27311197Sandreas.hansson@arm.com invalidateBlock(blk); 27411744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s (invalidation)\n", __func__, 27511744Snikos.nikoleris@arm.com pkt->print()); 27611051Sandreas.hansson@arm.com } 27711051Sandreas.hansson@arm.com} 27811051Sandreas.hansson@arm.com 27911051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28011051Sandreas.hansson@arm.com// 28111051Sandreas.hansson@arm.com// Access path: requests coming in from the CPU side 28211051Sandreas.hansson@arm.com// 28311051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28411051Sandreas.hansson@arm.com 28511051Sandreas.hansson@arm.combool 28611051Sandreas.hansson@arm.comCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 28711051Sandreas.hansson@arm.com PacketList &writebacks) 28811051Sandreas.hansson@arm.com{ 28911051Sandreas.hansson@arm.com // sanity check 29011051Sandreas.hansson@arm.com assert(pkt->isRequest()); 29111051Sandreas.hansson@arm.com 29211051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 29311051Sandreas.hansson@arm.com "Should never see a write in a read-only cache %s\n", 29411051Sandreas.hansson@arm.com name()); 29511051Sandreas.hansson@arm.com 29611744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s\n", __func__, pkt->print()); 29711051Sandreas.hansson@arm.com 29811051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 29911744Snikos.nikoleris@arm.com DPRINTF(Cache, "uncacheable: %s\n", pkt->print()); 30011051Sandreas.hansson@arm.com 30111051Sandreas.hansson@arm.com // flush and invalidate any existing block 30211051Sandreas.hansson@arm.com CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure())); 30311051Sandreas.hansson@arm.com if (old_blk && old_blk->isValid()) { 30411199Sandreas.hansson@arm.com if (old_blk->isDirty() || writebackClean) 30511051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(old_blk)); 30611051Sandreas.hansson@arm.com else 30711051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(old_blk)); 30811051Sandreas.hansson@arm.com tags->invalidate(old_blk); 30911051Sandreas.hansson@arm.com old_blk->invalidate(); 31011051Sandreas.hansson@arm.com } 31111051Sandreas.hansson@arm.com 31211484Snikos.nikoleris@arm.com blk = nullptr; 31311051Sandreas.hansson@arm.com // lookupLatency is the latency in case the request is uncacheable. 31411051Sandreas.hansson@arm.com lat = lookupLatency; 31511051Sandreas.hansson@arm.com return false; 31611051Sandreas.hansson@arm.com } 31711051Sandreas.hansson@arm.com 31811051Sandreas.hansson@arm.com ContextID id = pkt->req->hasContextId() ? 31911051Sandreas.hansson@arm.com pkt->req->contextId() : InvalidContextID; 32011051Sandreas.hansson@arm.com // Here lat is the value passed as parameter to accessBlock() function 32111051Sandreas.hansson@arm.com // that can modify its value. 32211051Sandreas.hansson@arm.com blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat, id); 32311051Sandreas.hansson@arm.com 32411744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s %s\n", pkt->print(), 32511051Sandreas.hansson@arm.com blk ? "hit " + blk->print() : "miss"); 32611051Sandreas.hansson@arm.com 32711051Sandreas.hansson@arm.com 32811199Sandreas.hansson@arm.com if (pkt->isEviction()) { 32911051Sandreas.hansson@arm.com // We check for presence of block in above caches before issuing 33011051Sandreas.hansson@arm.com // Writeback or CleanEvict to write buffer. Therefore the only 33111051Sandreas.hansson@arm.com // possible cases can be of a CleanEvict packet coming from above 33211051Sandreas.hansson@arm.com // encountering a Writeback generated in this cache peer cache and 33311051Sandreas.hansson@arm.com // waiting in the write buffer. Cases of upper level peer caches 33411051Sandreas.hansson@arm.com // generating CleanEvict and Writeback or simply CleanEvict and 33511051Sandreas.hansson@arm.com // CleanEvict almost simultaneously will be caught by snoops sent out 33611051Sandreas.hansson@arm.com // by crossbar. 33711375Sandreas.hansson@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(), 33811375Sandreas.hansson@arm.com pkt->isSecure()); 33911375Sandreas.hansson@arm.com if (wb_entry) { 34011199Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 34111199Sandreas.hansson@arm.com PacketPtr wbPkt = wb_entry->getTarget()->pkt; 34211199Sandreas.hansson@arm.com assert(wbPkt->isWriteback()); 34311199Sandreas.hansson@arm.com 34411199Sandreas.hansson@arm.com if (pkt->isCleanEviction()) { 34511199Sandreas.hansson@arm.com // The CleanEvict and WritebackClean snoops into other 34611199Sandreas.hansson@arm.com // peer caches of the same level while traversing the 34711199Sandreas.hansson@arm.com // crossbar. If a copy of the block is found, the 34811199Sandreas.hansson@arm.com // packet is deleted in the crossbar. Hence, none of 34911199Sandreas.hansson@arm.com // the other upper level caches connected to this 35011199Sandreas.hansson@arm.com // cache have the block, so we can clear the 35111199Sandreas.hansson@arm.com // BLOCK_CACHED flag in the Writeback if set and 35211199Sandreas.hansson@arm.com // discard the CleanEvict by returning true. 35311199Sandreas.hansson@arm.com wbPkt->clearBlockCached(); 35411199Sandreas.hansson@arm.com return true; 35511199Sandreas.hansson@arm.com } else { 35611199Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::WritebackDirty); 35711199Sandreas.hansson@arm.com // Dirty writeback from above trumps our clean 35811199Sandreas.hansson@arm.com // writeback... discard here 35911199Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 36011375Sandreas.hansson@arm.com markInService(wb_entry); 36111199Sandreas.hansson@arm.com delete wbPkt; 36211199Sandreas.hansson@arm.com } 36311051Sandreas.hansson@arm.com } 36411051Sandreas.hansson@arm.com } 36511051Sandreas.hansson@arm.com 36611051Sandreas.hansson@arm.com // Writeback handling is special case. We can write the block into 36711051Sandreas.hansson@arm.com // the cache without having a writeable copy (or any copy at all). 36811199Sandreas.hansson@arm.com if (pkt->isWriteback()) { 36911051Sandreas.hansson@arm.com assert(blkSize == pkt->getSize()); 37011199Sandreas.hansson@arm.com 37111199Sandreas.hansson@arm.com // we could get a clean writeback while we are having 37211199Sandreas.hansson@arm.com // outstanding accesses to a block, do the simple thing for 37311199Sandreas.hansson@arm.com // now and drop the clean writeback so that we do not upset 37411199Sandreas.hansson@arm.com // any ordering/decisions about ownership already taken 37511199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackClean && 37611199Sandreas.hansson@arm.com mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) { 37711199Sandreas.hansson@arm.com DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, " 37811199Sandreas.hansson@arm.com "dropping\n", pkt->getAddr()); 37911199Sandreas.hansson@arm.com return true; 38011199Sandreas.hansson@arm.com } 38111199Sandreas.hansson@arm.com 38211484Snikos.nikoleris@arm.com if (blk == nullptr) { 38311051Sandreas.hansson@arm.com // need to do a replacement 38411051Sandreas.hansson@arm.com blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks); 38511484Snikos.nikoleris@arm.com if (blk == nullptr) { 38611051Sandreas.hansson@arm.com // no replaceable block available: give up, fwd to next level. 38711051Sandreas.hansson@arm.com incMissCount(pkt); 38811051Sandreas.hansson@arm.com return false; 38911051Sandreas.hansson@arm.com } 39011051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 39111051Sandreas.hansson@arm.com 39211051Sandreas.hansson@arm.com blk->status = (BlkValid | BlkReadable); 39311051Sandreas.hansson@arm.com if (pkt->isSecure()) { 39411051Sandreas.hansson@arm.com blk->status |= BlkSecure; 39511051Sandreas.hansson@arm.com } 39611051Sandreas.hansson@arm.com } 39711199Sandreas.hansson@arm.com // only mark the block dirty if we got a writeback command, 39811199Sandreas.hansson@arm.com // and leave it as is for a clean writeback 39911199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackDirty) { 40011199Sandreas.hansson@arm.com blk->status |= BlkDirty; 40111199Sandreas.hansson@arm.com } 40211284Sandreas.hansson@arm.com // if the packet does not have sharers, it is passing 40311284Sandreas.hansson@arm.com // writable, and we got the writeback in Modified or Exclusive 40411284Sandreas.hansson@arm.com // state, if not we are in the Owned or Shared state 40511284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 40611051Sandreas.hansson@arm.com blk->status |= BlkWritable; 40711051Sandreas.hansson@arm.com } 40811051Sandreas.hansson@arm.com // nothing else to do; writeback doesn't expect response 40911051Sandreas.hansson@arm.com assert(!pkt->needsResponse()); 41011051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 41111051Sandreas.hansson@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 41211051Sandreas.hansson@arm.com incHitCount(pkt); 41311051Sandreas.hansson@arm.com return true; 41411051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::CleanEvict) { 41511484Snikos.nikoleris@arm.com if (blk != nullptr) { 41611051Sandreas.hansson@arm.com // Found the block in the tags, need to stop CleanEvict from 41711051Sandreas.hansson@arm.com // propagating further down the hierarchy. Returning true will 41811051Sandreas.hansson@arm.com // treat the CleanEvict like a satisfied write request and delete 41911051Sandreas.hansson@arm.com // it. 42011051Sandreas.hansson@arm.com return true; 42111051Sandreas.hansson@arm.com } 42211051Sandreas.hansson@arm.com // We didn't find the block here, propagate the CleanEvict further 42311051Sandreas.hansson@arm.com // down the memory hierarchy. Returning false will treat the CleanEvict 42411051Sandreas.hansson@arm.com // like a Writeback which could not find a replaceable block so has to 42511051Sandreas.hansson@arm.com // go to next level. 42611051Sandreas.hansson@arm.com return false; 42711601Sandreas.hansson@arm.com } else if (blk && (pkt->needsWritable() ? blk->isWritable() : 42811601Sandreas.hansson@arm.com blk->isReadable())) { 42911051Sandreas.hansson@arm.com // OK to satisfy access 43011051Sandreas.hansson@arm.com incHitCount(pkt); 43111601Sandreas.hansson@arm.com satisfyRequest(pkt, blk); 43211601Sandreas.hansson@arm.com maintainClusivity(pkt->fromCache(), blk); 43311601Sandreas.hansson@arm.com 43411051Sandreas.hansson@arm.com return true; 43511051Sandreas.hansson@arm.com } 43611051Sandreas.hansson@arm.com 43711484Snikos.nikoleris@arm.com // Can't satisfy access normally... either no block (blk == nullptr) 43811284Sandreas.hansson@arm.com // or have block but need writable 43911051Sandreas.hansson@arm.com 44011051Sandreas.hansson@arm.com incMissCount(pkt); 44111051Sandreas.hansson@arm.com 44211484Snikos.nikoleris@arm.com if (blk == nullptr && pkt->isLLSC() && pkt->isWrite()) { 44311051Sandreas.hansson@arm.com // complete miss on store conditional... just give up now 44411051Sandreas.hansson@arm.com pkt->req->setExtraData(0); 44511051Sandreas.hansson@arm.com return true; 44611051Sandreas.hansson@arm.com } 44711051Sandreas.hansson@arm.com 44811051Sandreas.hansson@arm.com return false; 44911051Sandreas.hansson@arm.com} 45011051Sandreas.hansson@arm.com 45111051Sandreas.hansson@arm.comvoid 45211601Sandreas.hansson@arm.comCache::maintainClusivity(bool from_cache, CacheBlk *blk) 45311601Sandreas.hansson@arm.com{ 45411601Sandreas.hansson@arm.com if (from_cache && blk && blk->isValid() && !blk->isDirty() && 45511601Sandreas.hansson@arm.com clusivity == Enums::mostly_excl) { 45611601Sandreas.hansson@arm.com // if we have responded to a cache, and our block is still 45711601Sandreas.hansson@arm.com // valid, but not dirty, and this cache is mostly exclusive 45811601Sandreas.hansson@arm.com // with respect to the cache above, drop the block 45911601Sandreas.hansson@arm.com invalidateBlock(blk); 46011601Sandreas.hansson@arm.com } 46111601Sandreas.hansson@arm.com} 46211601Sandreas.hansson@arm.com 46311601Sandreas.hansson@arm.comvoid 46411051Sandreas.hansson@arm.comCache::doWritebacks(PacketList& writebacks, Tick forward_time) 46511051Sandreas.hansson@arm.com{ 46611051Sandreas.hansson@arm.com while (!writebacks.empty()) { 46711051Sandreas.hansson@arm.com PacketPtr wbPkt = writebacks.front(); 46811051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying writebacks to 46911051Sandreas.hansson@arm.com // write buffer. Call isCachedAbove for both Writebacks and 47011051Sandreas.hansson@arm.com // CleanEvicts. If isCachedAbove returns true we set BLOCK_CACHED flag 47111051Sandreas.hansson@arm.com // in Writebacks and discard CleanEvicts. 47211051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) { 47311051Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::CleanEvict) { 47411051Sandreas.hansson@arm.com // Delete CleanEvict because cached copies exist above. The 47511051Sandreas.hansson@arm.com // packet destructor will delete the request object because 47611051Sandreas.hansson@arm.com // this is a non-snoop request packet which does not require a 47711051Sandreas.hansson@arm.com // response. 47811051Sandreas.hansson@arm.com delete wbPkt; 47911199Sandreas.hansson@arm.com } else if (wbPkt->cmd == MemCmd::WritebackClean) { 48011199Sandreas.hansson@arm.com // clean writeback, do not send since the block is 48111199Sandreas.hansson@arm.com // still cached above 48211199Sandreas.hansson@arm.com assert(writebackClean); 48311199Sandreas.hansson@arm.com delete wbPkt; 48411051Sandreas.hansson@arm.com } else { 48511199Sandreas.hansson@arm.com assert(wbPkt->cmd == MemCmd::WritebackDirty); 48611051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag in Writeback and send below, so that 48711051Sandreas.hansson@arm.com // the Writeback does not reset the bit corresponding to this 48811051Sandreas.hansson@arm.com // address in the snoop filter below. 48911051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 49011051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 49111051Sandreas.hansson@arm.com } 49211051Sandreas.hansson@arm.com } else { 49311051Sandreas.hansson@arm.com // If the block is not cached above, send packet below. Both 49411051Sandreas.hansson@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 49511051Sandreas.hansson@arm.com // reset the bit corresponding to this address in the snoop filter 49611051Sandreas.hansson@arm.com // below. 49711051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 49811051Sandreas.hansson@arm.com } 49911051Sandreas.hansson@arm.com writebacks.pop_front(); 50011051Sandreas.hansson@arm.com } 50111051Sandreas.hansson@arm.com} 50211051Sandreas.hansson@arm.com 50311130Sali.jafri@arm.comvoid 50411130Sali.jafri@arm.comCache::doWritebacksAtomic(PacketList& writebacks) 50511130Sali.jafri@arm.com{ 50611130Sali.jafri@arm.com while (!writebacks.empty()) { 50711130Sali.jafri@arm.com PacketPtr wbPkt = writebacks.front(); 50811130Sali.jafri@arm.com // Call isCachedAbove for both Writebacks and CleanEvicts. If 50911130Sali.jafri@arm.com // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks 51011130Sali.jafri@arm.com // and discard CleanEvicts. 51111130Sali.jafri@arm.com if (isCachedAbove(wbPkt, false)) { 51211199Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::WritebackDirty) { 51311130Sali.jafri@arm.com // Set BLOCK_CACHED flag in Writeback and send below, 51411130Sali.jafri@arm.com // so that the Writeback does not reset the bit 51511130Sali.jafri@arm.com // corresponding to this address in the snoop filter 51611130Sali.jafri@arm.com // below. We can discard CleanEvicts because cached 51711130Sali.jafri@arm.com // copies exist above. Atomic mode isCachedAbove 51811130Sali.jafri@arm.com // modifies packet to set BLOCK_CACHED flag 51911130Sali.jafri@arm.com memSidePort->sendAtomic(wbPkt); 52011130Sali.jafri@arm.com } 52111130Sali.jafri@arm.com } else { 52211130Sali.jafri@arm.com // If the block is not cached above, send packet below. Both 52311130Sali.jafri@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 52411130Sali.jafri@arm.com // reset the bit corresponding to this address in the snoop filter 52511130Sali.jafri@arm.com // below. 52611130Sali.jafri@arm.com memSidePort->sendAtomic(wbPkt); 52711130Sali.jafri@arm.com } 52811130Sali.jafri@arm.com writebacks.pop_front(); 52911130Sali.jafri@arm.com // In case of CleanEvicts, the packet destructor will delete the 53011130Sali.jafri@arm.com // request object because this is a non-snoop request packet which 53111130Sali.jafri@arm.com // does not require a response. 53211130Sali.jafri@arm.com delete wbPkt; 53311130Sali.jafri@arm.com } 53411130Sali.jafri@arm.com} 53511130Sali.jafri@arm.com 53611051Sandreas.hansson@arm.com 53711051Sandreas.hansson@arm.comvoid 53811051Sandreas.hansson@arm.comCache::recvTimingSnoopResp(PacketPtr pkt) 53911051Sandreas.hansson@arm.com{ 54011744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s for %s\n", __func__, pkt->print()); 54111051Sandreas.hansson@arm.com 54211051Sandreas.hansson@arm.com assert(pkt->isResponse()); 54311051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 54411051Sandreas.hansson@arm.com 54511276Sandreas.hansson@arm.com // determine if the response is from a snoop request we created 54611276Sandreas.hansson@arm.com // (in which case it should be in the outstandingSnoop), or if we 54711276Sandreas.hansson@arm.com // merely forwarded someone else's snoop request 54811276Sandreas.hansson@arm.com const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) == 54911276Sandreas.hansson@arm.com outstandingSnoop.end(); 55011276Sandreas.hansson@arm.com 55111276Sandreas.hansson@arm.com if (!forwardAsSnoop) { 55211276Sandreas.hansson@arm.com // the packet came from this cache, so sink it here and do not 55311276Sandreas.hansson@arm.com // forward it 55411051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::HardPFResp); 55511276Sandreas.hansson@arm.com 55611276Sandreas.hansson@arm.com outstandingSnoop.erase(pkt->req); 55711276Sandreas.hansson@arm.com 55811276Sandreas.hansson@arm.com DPRINTF(Cache, "Got prefetch response from above for addr " 55911276Sandreas.hansson@arm.com "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 56011051Sandreas.hansson@arm.com recvTimingResp(pkt); 56111051Sandreas.hansson@arm.com return; 56211051Sandreas.hansson@arm.com } 56311051Sandreas.hansson@arm.com 56411051Sandreas.hansson@arm.com // forwardLatency is set here because there is a response from an 56511051Sandreas.hansson@arm.com // upper level cache. 56611051Sandreas.hansson@arm.com // To pay the delay that occurs if the packet comes from the bus, 56711051Sandreas.hansson@arm.com // we charge also headerDelay. 56811051Sandreas.hansson@arm.com Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay; 56911051Sandreas.hansson@arm.com // Reset the timing of the packet. 57011051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 57111051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, snoop_resp_time); 57211051Sandreas.hansson@arm.com} 57311051Sandreas.hansson@arm.com 57411051Sandreas.hansson@arm.comvoid 57511051Sandreas.hansson@arm.comCache::promoteWholeLineWrites(PacketPtr pkt) 57611051Sandreas.hansson@arm.com{ 57711051Sandreas.hansson@arm.com // Cache line clearing instructions 57811051Sandreas.hansson@arm.com if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) && 57911051Sandreas.hansson@arm.com (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) { 58011051Sandreas.hansson@arm.com pkt->cmd = MemCmd::WriteLineReq; 58111051Sandreas.hansson@arm.com DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n"); 58211051Sandreas.hansson@arm.com } 58311051Sandreas.hansson@arm.com} 58411051Sandreas.hansson@arm.com 58511051Sandreas.hansson@arm.combool 58611051Sandreas.hansson@arm.comCache::recvTimingReq(PacketPtr pkt) 58711051Sandreas.hansson@arm.com{ 58811051Sandreas.hansson@arm.com DPRINTF(CacheTags, "%s tags: %s\n", __func__, tags->print()); 58911051Sandreas.hansson@arm.com 59011051Sandreas.hansson@arm.com assert(pkt->isRequest()); 59111051Sandreas.hansson@arm.com 59211051Sandreas.hansson@arm.com // Just forward the packet if caches are disabled. 59311051Sandreas.hansson@arm.com if (system->bypassCaches()) { 59411051Sandreas.hansson@arm.com // @todo This should really enqueue the packet rather 59511051Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt); 59611051Sandreas.hansson@arm.com assert(success); 59711051Sandreas.hansson@arm.com return true; 59811051Sandreas.hansson@arm.com } 59911051Sandreas.hansson@arm.com 60011051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 60111051Sandreas.hansson@arm.com 60211284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 60311051Sandreas.hansson@arm.com // a cache above us (but not where the packet came from) is 60411284Sandreas.hansson@arm.com // responding to the request, in other words it has the line 60511284Sandreas.hansson@arm.com // in Modified or Owned state 60611744Snikos.nikoleris@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 60711744Snikos.nikoleris@arm.com pkt->print()); 60811051Sandreas.hansson@arm.com 60911284Sandreas.hansson@arm.com // if the packet needs the block to be writable, and the cache 61011284Sandreas.hansson@arm.com // that has promised to respond (setting the cache responding 61111284Sandreas.hansson@arm.com // flag) is not providing writable (it is in Owned rather than 61211284Sandreas.hansson@arm.com // the Modified state), we know that there may be other Shared 61311284Sandreas.hansson@arm.com // copies in the system; go out and invalidate them all 61411334Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 61511284Sandreas.hansson@arm.com 61611334Sandreas.hansson@arm.com // an upstream cache that had the line in Owned state 61711334Sandreas.hansson@arm.com // (dirty, but not writable), is responding and thus 61811334Sandreas.hansson@arm.com // transferring the dirty line from one branch of the 61911334Sandreas.hansson@arm.com // cache hierarchy to another 62011284Sandreas.hansson@arm.com 62111334Sandreas.hansson@arm.com // send out an express snoop and invalidate all other 62211334Sandreas.hansson@arm.com // copies (snooping a packet that needs writable is the 62311334Sandreas.hansson@arm.com // same as an invalidation), thus turning the Owned line 62411334Sandreas.hansson@arm.com // into a Modified line, note that we don't invalidate the 62511334Sandreas.hansson@arm.com // block in the current cache or any other cache on the 62611334Sandreas.hansson@arm.com // path to memory 62711051Sandreas.hansson@arm.com 62811334Sandreas.hansson@arm.com // create a downstream express snoop with cleared packet 62911334Sandreas.hansson@arm.com // flags, there is no need to allocate any data as the 63011334Sandreas.hansson@arm.com // packet is merely used to co-ordinate state transitions 63111334Sandreas.hansson@arm.com Packet *snoop_pkt = new Packet(pkt, true, false); 63211051Sandreas.hansson@arm.com 63311334Sandreas.hansson@arm.com // also reset the bus time that the original packet has 63411334Sandreas.hansson@arm.com // not yet paid for 63511334Sandreas.hansson@arm.com snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0; 63611051Sandreas.hansson@arm.com 63711334Sandreas.hansson@arm.com // make this an instantaneous express snoop, and let the 63811334Sandreas.hansson@arm.com // other caches in the system know that the another cache 63911334Sandreas.hansson@arm.com // is responding, because we have found the authorative 64011334Sandreas.hansson@arm.com // copy (Modified or Owned) that will supply the right 64111334Sandreas.hansson@arm.com // data 64211334Sandreas.hansson@arm.com snoop_pkt->setExpressSnoop(); 64311334Sandreas.hansson@arm.com snoop_pkt->setCacheResponding(); 64411051Sandreas.hansson@arm.com 64511334Sandreas.hansson@arm.com // this express snoop travels towards the memory, and at 64611334Sandreas.hansson@arm.com // every crossbar it is snooped upwards thus reaching 64711334Sandreas.hansson@arm.com // every cache in the system 64811334Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(snoop_pkt); 64911334Sandreas.hansson@arm.com // express snoops always succeed 65011334Sandreas.hansson@arm.com assert(success); 65111334Sandreas.hansson@arm.com 65211334Sandreas.hansson@arm.com // main memory will delete the snoop packet 65311051Sandreas.hansson@arm.com 65411284Sandreas.hansson@arm.com // queue for deletion, as opposed to immediate deletion, as 65511284Sandreas.hansson@arm.com // the sending cache is still relying on the packet 65611190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 65711051Sandreas.hansson@arm.com 65811334Sandreas.hansson@arm.com // no need to take any further action in this particular cache 65911334Sandreas.hansson@arm.com // as an upstram cache has already committed to responding, 66011334Sandreas.hansson@arm.com // and we have already sent out any express snoops in the 66111334Sandreas.hansson@arm.com // section above to ensure all other copies in the system are 66211334Sandreas.hansson@arm.com // invalidated 66311051Sandreas.hansson@arm.com return true; 66411051Sandreas.hansson@arm.com } 66511051Sandreas.hansson@arm.com 66611051Sandreas.hansson@arm.com // anything that is merely forwarded pays for the forward latency and 66711051Sandreas.hansson@arm.com // the delay provided by the crossbar 66811051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 66911051Sandreas.hansson@arm.com 67011051Sandreas.hansson@arm.com // We use lookupLatency here because it is used to specify the latency 67111051Sandreas.hansson@arm.com // to access. 67211051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 67311484Snikos.nikoleris@arm.com CacheBlk *blk = nullptr; 67411051Sandreas.hansson@arm.com bool satisfied = false; 67511051Sandreas.hansson@arm.com { 67611051Sandreas.hansson@arm.com PacketList writebacks; 67711051Sandreas.hansson@arm.com // Note that lat is passed by reference here. The function 67811051Sandreas.hansson@arm.com // access() calls accessBlock() which can modify lat value. 67911051Sandreas.hansson@arm.com satisfied = access(pkt, blk, lat, writebacks); 68011051Sandreas.hansson@arm.com 68111051Sandreas.hansson@arm.com // copy writebacks to write buffer here to ensure they logically 68211051Sandreas.hansson@arm.com // proceed anything happening below 68311051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 68411051Sandreas.hansson@arm.com } 68511051Sandreas.hansson@arm.com 68611051Sandreas.hansson@arm.com // Here we charge the headerDelay that takes into account the latencies 68711051Sandreas.hansson@arm.com // of the bus, if the packet comes from it. 68811051Sandreas.hansson@arm.com // The latency charged it is just lat that is the value of lookupLatency 68911051Sandreas.hansson@arm.com // modified by access() function, or if not just lookupLatency. 69011051Sandreas.hansson@arm.com // In case of a hit we are neglecting response latency. 69111051Sandreas.hansson@arm.com // In case of a miss we are neglecting forward latency. 69211051Sandreas.hansson@arm.com Tick request_time = clockEdge(lat) + pkt->headerDelay; 69311051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 69411051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 69511051Sandreas.hansson@arm.com 69611051Sandreas.hansson@arm.com // track time of availability of next prefetch, if any 69711051Sandreas.hansson@arm.com Tick next_pf_time = MaxTick; 69811051Sandreas.hansson@arm.com 69911051Sandreas.hansson@arm.com bool needsResponse = pkt->needsResponse(); 70011051Sandreas.hansson@arm.com 70111051Sandreas.hansson@arm.com if (satisfied) { 70211051Sandreas.hansson@arm.com // should never be satisfying an uncacheable access as we 70311051Sandreas.hansson@arm.com // flush and invalidate any existing block as part of the 70411051Sandreas.hansson@arm.com // lookup 70511051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 70611051Sandreas.hansson@arm.com 70711051Sandreas.hansson@arm.com // hit (for all other request types) 70811051Sandreas.hansson@arm.com 70911483Snikos.nikoleris@arm.com if (prefetcher && (prefetchOnAccess || 71011483Snikos.nikoleris@arm.com (blk && blk->wasPrefetched()))) { 71111051Sandreas.hansson@arm.com if (blk) 71211051Sandreas.hansson@arm.com blk->status &= ~BlkHWPrefetched; 71311051Sandreas.hansson@arm.com 71411051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 71511051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 71611051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 71711051Sandreas.hansson@arm.com } 71811051Sandreas.hansson@arm.com 71911051Sandreas.hansson@arm.com if (needsResponse) { 72011051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 72111051Sandreas.hansson@arm.com // @todo: Make someone pay for this 72211051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 72311051Sandreas.hansson@arm.com 72411051Sandreas.hansson@arm.com // In this case we are considering request_time that takes 72511051Sandreas.hansson@arm.com // into account the delay of the xbar, if any, and just 72611051Sandreas.hansson@arm.com // lat, neglecting responseLatency, modelling hit latency 72711051Sandreas.hansson@arm.com // just as lookupLatency or or the value of lat overriden 72811051Sandreas.hansson@arm.com // by access(), that calls accessBlock() function. 72911194Sali.jafri@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 73011051Sandreas.hansson@arm.com } else { 73111744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__, 73211744Snikos.nikoleris@arm.com pkt->print()); 73311199Sandreas.hansson@arm.com 73411190Sandreas.hansson@arm.com // queue the packet for deletion, as the sending cache is 73511190Sandreas.hansson@arm.com // still relying on it; if the block is found in access(), 73611190Sandreas.hansson@arm.com // CleanEvict and Writeback messages will be deleted 73711190Sandreas.hansson@arm.com // here as well 73811190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 73911051Sandreas.hansson@arm.com } 74011051Sandreas.hansson@arm.com } else { 74111051Sandreas.hansson@arm.com // miss 74211051Sandreas.hansson@arm.com 74311051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 74411051Sandreas.hansson@arm.com 74511051Sandreas.hansson@arm.com // ignore any existing MSHR if we are dealing with an 74611051Sandreas.hansson@arm.com // uncacheable request 74711051Sandreas.hansson@arm.com MSHR *mshr = pkt->req->isUncacheable() ? nullptr : 74811051Sandreas.hansson@arm.com mshrQueue.findMatch(blk_addr, pkt->isSecure()); 74911051Sandreas.hansson@arm.com 75011051Sandreas.hansson@arm.com // Software prefetch handling: 75111051Sandreas.hansson@arm.com // To keep the core from waiting on data it won't look at 75211051Sandreas.hansson@arm.com // anyway, send back a response with dummy data. Miss handling 75311051Sandreas.hansson@arm.com // will continue asynchronously. Unfortunately, the core will 75411051Sandreas.hansson@arm.com // insist upon freeing original Packet/Request, so we have to 75511051Sandreas.hansson@arm.com // create a new pair with a different lifecycle. Note that this 75611051Sandreas.hansson@arm.com // processing happens before any MSHR munging on the behalf of 75711051Sandreas.hansson@arm.com // this request because this new Request will be the one stored 75811051Sandreas.hansson@arm.com // into the MSHRs, not the original. 75911051Sandreas.hansson@arm.com if (pkt->cmd.isSWPrefetch()) { 76011051Sandreas.hansson@arm.com assert(needsResponse); 76111051Sandreas.hansson@arm.com assert(pkt->req->hasPaddr()); 76211051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 76311051Sandreas.hansson@arm.com 76411051Sandreas.hansson@arm.com // There's no reason to add a prefetch as an additional target 76511051Sandreas.hansson@arm.com // to an existing MSHR. If an outstanding request is already 76611051Sandreas.hansson@arm.com // in progress, there is nothing for the prefetch to do. 76711051Sandreas.hansson@arm.com // If this is the case, we don't even create a request at all. 76811051Sandreas.hansson@arm.com PacketPtr pf = nullptr; 76911051Sandreas.hansson@arm.com 77011051Sandreas.hansson@arm.com if (!mshr) { 77111051Sandreas.hansson@arm.com // copy the request and create a new SoftPFReq packet 77211051Sandreas.hansson@arm.com RequestPtr req = new Request(pkt->req->getPaddr(), 77311051Sandreas.hansson@arm.com pkt->req->getSize(), 77411051Sandreas.hansson@arm.com pkt->req->getFlags(), 77511051Sandreas.hansson@arm.com pkt->req->masterId()); 77611051Sandreas.hansson@arm.com pf = new Packet(req, pkt->cmd); 77711051Sandreas.hansson@arm.com pf->allocate(); 77811051Sandreas.hansson@arm.com assert(pf->getAddr() == pkt->getAddr()); 77911051Sandreas.hansson@arm.com assert(pf->getSize() == pkt->getSize()); 78011051Sandreas.hansson@arm.com } 78111051Sandreas.hansson@arm.com 78211051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 78311286Sandreas.hansson@arm.com 78411051Sandreas.hansson@arm.com // request_time is used here, taking into account lat and the delay 78511051Sandreas.hansson@arm.com // charged if the packet comes from the xbar. 78611194Sali.jafri@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 78711051Sandreas.hansson@arm.com 78811051Sandreas.hansson@arm.com // If an outstanding request is in progress (we found an 78911051Sandreas.hansson@arm.com // MSHR) this is set to null 79011051Sandreas.hansson@arm.com pkt = pf; 79111051Sandreas.hansson@arm.com } 79211051Sandreas.hansson@arm.com 79311051Sandreas.hansson@arm.com if (mshr) { 79411051Sandreas.hansson@arm.com /// MSHR hit 79511051Sandreas.hansson@arm.com /// @note writebacks will be checked in getNextMSHR() 79611051Sandreas.hansson@arm.com /// for any conflicting requests to the same block 79711051Sandreas.hansson@arm.com 79811051Sandreas.hansson@arm.com //@todo remove hw_pf here 79911051Sandreas.hansson@arm.com 80011051Sandreas.hansson@arm.com // Coalesce unless it was a software prefetch (see above). 80111051Sandreas.hansson@arm.com if (pkt) { 80211199Sandreas.hansson@arm.com assert(!pkt->isWriteback()); 80311199Sandreas.hansson@arm.com // CleanEvicts corresponding to blocks which have 80411199Sandreas.hansson@arm.com // outstanding requests in MSHRs are simply sunk here 80511051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::CleanEvict) { 80611190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 80711051Sandreas.hansson@arm.com } else { 80811744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s coalescing MSHR for %s\n", __func__, 80911744Snikos.nikoleris@arm.com pkt->print()); 81011051Sandreas.hansson@arm.com 81111051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 81211051Sandreas.hansson@arm.com mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 81311051Sandreas.hansson@arm.com // We use forward_time here because it is the same 81411051Sandreas.hansson@arm.com // considering new targets. We have multiple 81511051Sandreas.hansson@arm.com // requests for the same address here. It 81611051Sandreas.hansson@arm.com // specifies the latency to allocate an internal 81711051Sandreas.hansson@arm.com // buffer and to schedule an event to the queued 81811051Sandreas.hansson@arm.com // port and also takes into account the additional 81911051Sandreas.hansson@arm.com // delay of the xbar. 82011197Sandreas.hansson@arm.com mshr->allocateTarget(pkt, forward_time, order++, 82111197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 82211051Sandreas.hansson@arm.com if (mshr->getNumTargets() == numTarget) { 82311051Sandreas.hansson@arm.com noTargetMSHR = mshr; 82411051Sandreas.hansson@arm.com setBlocked(Blocked_NoTargets); 82511051Sandreas.hansson@arm.com // need to be careful with this... if this mshr isn't 82611051Sandreas.hansson@arm.com // ready yet (i.e. time > curTick()), we don't want to 82711051Sandreas.hansson@arm.com // move it ahead of mshrs that are ready 82811051Sandreas.hansson@arm.com // mshrQueue.moveToFront(mshr); 82911051Sandreas.hansson@arm.com } 83011051Sandreas.hansson@arm.com } 83111051Sandreas.hansson@arm.com // We should call the prefetcher reguardless if the request is 83211483Snikos.nikoleris@arm.com // satisfied or not, reguardless if the request is in the MSHR 83311483Snikos.nikoleris@arm.com // or not. The request could be a ReadReq hit, but still not 83411051Sandreas.hansson@arm.com // satisfied (potentially because of a prior write to the same 83511051Sandreas.hansson@arm.com // cache line. So, even when not satisfied, tehre is an MSHR 83611483Snikos.nikoleris@arm.com // already allocated for this, we need to let the prefetcher 83711483Snikos.nikoleris@arm.com // know about the request 83811051Sandreas.hansson@arm.com if (prefetcher) { 83911051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 84011051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 84111051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 84211051Sandreas.hansson@arm.com } 84311051Sandreas.hansson@arm.com } 84411051Sandreas.hansson@arm.com } else { 84511051Sandreas.hansson@arm.com // no MSHR 84611051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 84711051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 84811051Sandreas.hansson@arm.com mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++; 84911051Sandreas.hansson@arm.com } else { 85011051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 85111051Sandreas.hansson@arm.com } 85211051Sandreas.hansson@arm.com 85311199Sandreas.hansson@arm.com if (pkt->isEviction() || 85411051Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 85511051Sandreas.hansson@arm.com // We use forward_time here because there is an 85611051Sandreas.hansson@arm.com // uncached memory write, forwarded to WriteBuffer. 85711051Sandreas.hansson@arm.com allocateWriteBuffer(pkt, forward_time); 85811051Sandreas.hansson@arm.com } else { 85911051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 86011051Sandreas.hansson@arm.com // should have flushed and have no valid block 86111051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 86211051Sandreas.hansson@arm.com 86311051Sandreas.hansson@arm.com // If we have a write miss to a valid block, we 86411051Sandreas.hansson@arm.com // need to mark the block non-readable. Otherwise 86511051Sandreas.hansson@arm.com // if we allow reads while there's an outstanding 86611051Sandreas.hansson@arm.com // write miss, the read could return stale data 86711051Sandreas.hansson@arm.com // out of the cache block... a more aggressive 86811051Sandreas.hansson@arm.com // system could detect the overlap (if any) and 86911051Sandreas.hansson@arm.com // forward data out of the MSHRs, but we don't do 87011051Sandreas.hansson@arm.com // that yet. Note that we do need to leave the 87111051Sandreas.hansson@arm.com // block valid so that it stays in the cache, in 87211051Sandreas.hansson@arm.com // case we get an upgrade response (and hence no 87311051Sandreas.hansson@arm.com // new data) when the write miss completes. 87411051Sandreas.hansson@arm.com // As long as CPUs do proper store/load forwarding 87511051Sandreas.hansson@arm.com // internally, and have a sufficiently weak memory 87611051Sandreas.hansson@arm.com // model, this is probably unnecessary, but at some 87711051Sandreas.hansson@arm.com // point it must have seemed like we needed it... 87811284Sandreas.hansson@arm.com assert(pkt->needsWritable()); 87911051Sandreas.hansson@arm.com assert(!blk->isWritable()); 88011051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 88111051Sandreas.hansson@arm.com } 88211051Sandreas.hansson@arm.com // Here we are using forward_time, modelling the latency of 88311051Sandreas.hansson@arm.com // a miss (outbound) just as forwardLatency, neglecting the 88411051Sandreas.hansson@arm.com // lookupLatency component. 88511051Sandreas.hansson@arm.com allocateMissBuffer(pkt, forward_time); 88611051Sandreas.hansson@arm.com } 88711051Sandreas.hansson@arm.com 88811051Sandreas.hansson@arm.com if (prefetcher) { 88911051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 89011051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 89111051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 89211051Sandreas.hansson@arm.com } 89311051Sandreas.hansson@arm.com } 89411051Sandreas.hansson@arm.com } 89511051Sandreas.hansson@arm.com 89611051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 89711051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 89811051Sandreas.hansson@arm.com 89911051Sandreas.hansson@arm.com return true; 90011051Sandreas.hansson@arm.com} 90111051Sandreas.hansson@arm.com 90211051Sandreas.hansson@arm.comPacketPtr 90311452Sandreas.hansson@arm.comCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 90411452Sandreas.hansson@arm.com bool needsWritable) const 90511051Sandreas.hansson@arm.com{ 90611452Sandreas.hansson@arm.com // should never see evictions here 90711452Sandreas.hansson@arm.com assert(!cpu_pkt->isEviction()); 90811452Sandreas.hansson@arm.com 90911051Sandreas.hansson@arm.com bool blkValid = blk && blk->isValid(); 91011051Sandreas.hansson@arm.com 91111452Sandreas.hansson@arm.com if (cpu_pkt->req->isUncacheable() || 91211745Sandreas.hansson@arm.com (!blkValid && cpu_pkt->isUpgrade()) || 91311745Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::InvalidateReq) { 91411452Sandreas.hansson@arm.com // uncacheable requests and upgrades from upper-level caches 91511452Sandreas.hansson@arm.com // that missed completely just go through as is 91611452Sandreas.hansson@arm.com return nullptr; 91711051Sandreas.hansson@arm.com } 91811051Sandreas.hansson@arm.com 91911051Sandreas.hansson@arm.com assert(cpu_pkt->needsResponse()); 92011051Sandreas.hansson@arm.com 92111051Sandreas.hansson@arm.com MemCmd cmd; 92211051Sandreas.hansson@arm.com // @TODO make useUpgrades a parameter. 92311051Sandreas.hansson@arm.com // Note that ownership protocols require upgrade, otherwise a 92411051Sandreas.hansson@arm.com // write miss on a shared owned block will generate a ReadExcl, 92511051Sandreas.hansson@arm.com // which will clobber the owned copy. 92611051Sandreas.hansson@arm.com const bool useUpgrades = true; 92711747Snikos.nikoleris@arm.com if (cpu_pkt->cmd == MemCmd::WriteLineReq) { 92811747Snikos.nikoleris@arm.com assert(!blkValid || !blk->isWritable()); 92911747Snikos.nikoleris@arm.com // forward as invalidate to all other caches, this gives us 93011747Snikos.nikoleris@arm.com // the line in Exclusive state, and invalidates all other 93111747Snikos.nikoleris@arm.com // copies 93211747Snikos.nikoleris@arm.com cmd = MemCmd::InvalidateReq; 93311747Snikos.nikoleris@arm.com } else if (blkValid && useUpgrades) { 93411284Sandreas.hansson@arm.com // only reason to be here is that blk is read only and we need 93511284Sandreas.hansson@arm.com // it to be writable 93611284Sandreas.hansson@arm.com assert(needsWritable); 93711051Sandreas.hansson@arm.com assert(!blk->isWritable()); 93811051Sandreas.hansson@arm.com cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq; 93911051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq || 94011051Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::StoreCondFailReq) { 94111051Sandreas.hansson@arm.com // Even though this SC will fail, we still need to send out the 94211051Sandreas.hansson@arm.com // request and get the data to supply it to other snoopers in the case 94311051Sandreas.hansson@arm.com // where the determination the StoreCond fails is delayed due to 94411051Sandreas.hansson@arm.com // all caches not being on the same local bus. 94511051Sandreas.hansson@arm.com cmd = MemCmd::SCUpgradeFailReq; 94611051Sandreas.hansson@arm.com } else { 94711051Sandreas.hansson@arm.com // block is invalid 94811284Sandreas.hansson@arm.com cmd = needsWritable ? MemCmd::ReadExReq : 94911051Sandreas.hansson@arm.com (isReadOnly ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq); 95011051Sandreas.hansson@arm.com } 95111051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize); 95211051Sandreas.hansson@arm.com 95311284Sandreas.hansson@arm.com // if there are upstream caches that have already marked the 95411284Sandreas.hansson@arm.com // packet as having sharers (not passing writable), pass that info 95511284Sandreas.hansson@arm.com // downstream 95611602Sandreas.hansson@arm.com if (cpu_pkt->hasSharers() && !needsWritable) { 95711051Sandreas.hansson@arm.com // note that cpu_pkt may have spent a considerable time in the 95811051Sandreas.hansson@arm.com // MSHR queue and that the information could possibly be out 95911051Sandreas.hansson@arm.com // of date, however, there is no harm in conservatively 96011284Sandreas.hansson@arm.com // assuming the block has sharers 96111284Sandreas.hansson@arm.com pkt->setHasSharers(); 96211744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: passing hasSharers from %s to %s\n", 96311744Snikos.nikoleris@arm.com __func__, cpu_pkt->print(), pkt->print()); 96411051Sandreas.hansson@arm.com } 96511051Sandreas.hansson@arm.com 96611051Sandreas.hansson@arm.com // the packet should be block aligned 96711051Sandreas.hansson@arm.com assert(pkt->getAddr() == blockAlign(pkt->getAddr())); 96811051Sandreas.hansson@arm.com 96911051Sandreas.hansson@arm.com pkt->allocate(); 97011744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: created %s from %s\n", __func__, pkt->print(), 97111744Snikos.nikoleris@arm.com cpu_pkt->print()); 97211051Sandreas.hansson@arm.com return pkt; 97311051Sandreas.hansson@arm.com} 97411051Sandreas.hansson@arm.com 97511051Sandreas.hansson@arm.com 97611051Sandreas.hansson@arm.comTick 97711051Sandreas.hansson@arm.comCache::recvAtomic(PacketPtr pkt) 97811051Sandreas.hansson@arm.com{ 97911051Sandreas.hansson@arm.com // We are in atomic mode so we pay just for lookupLatency here. 98011051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 98111051Sandreas.hansson@arm.com 98211051Sandreas.hansson@arm.com // Forward the request if the system is in cache bypass mode. 98311051Sandreas.hansson@arm.com if (system->bypassCaches()) 98411051Sandreas.hansson@arm.com return ticksToCycles(memSidePort->sendAtomic(pkt)); 98511051Sandreas.hansson@arm.com 98611051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 98711051Sandreas.hansson@arm.com 98811333Sandreas.hansson@arm.com // follow the same flow as in recvTimingReq, and check if a cache 98911333Sandreas.hansson@arm.com // above us is responding 99011284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 99111744Snikos.nikoleris@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 99211744Snikos.nikoleris@arm.com pkt->print()); 99311333Sandreas.hansson@arm.com 99411333Sandreas.hansson@arm.com // if a cache is responding, and it had the line in Owned 99511333Sandreas.hansson@arm.com // rather than Modified state, we need to invalidate any 99611333Sandreas.hansson@arm.com // copies that are not on the same path to memory 99711334Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 99811334Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 99911051Sandreas.hansson@arm.com 100011051Sandreas.hansson@arm.com return lat * clockPeriod(); 100111051Sandreas.hansson@arm.com } 100211051Sandreas.hansson@arm.com 100311051Sandreas.hansson@arm.com // should assert here that there are no outstanding MSHRs or 100411051Sandreas.hansson@arm.com // writebacks... that would mean that someone used an atomic 100511051Sandreas.hansson@arm.com // access in timing mode 100611051Sandreas.hansson@arm.com 100711484Snikos.nikoleris@arm.com CacheBlk *blk = nullptr; 100811051Sandreas.hansson@arm.com PacketList writebacks; 100911051Sandreas.hansson@arm.com bool satisfied = access(pkt, blk, lat, writebacks); 101011051Sandreas.hansson@arm.com 101111051Sandreas.hansson@arm.com // handle writebacks resulting from the access here to ensure they 101211051Sandreas.hansson@arm.com // logically proceed anything happening below 101311130Sali.jafri@arm.com doWritebacksAtomic(writebacks); 101411051Sandreas.hansson@arm.com 101511051Sandreas.hansson@arm.com if (!satisfied) { 101611051Sandreas.hansson@arm.com // MISS 101711051Sandreas.hansson@arm.com 101811452Sandreas.hansson@arm.com // deal with the packets that go through the write path of 101911452Sandreas.hansson@arm.com // the cache, i.e. any evictions and uncacheable writes 102011452Sandreas.hansson@arm.com if (pkt->isEviction() || 102111452Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 102211452Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 102311452Sandreas.hansson@arm.com return lat * clockPeriod(); 102411452Sandreas.hansson@arm.com } 102511452Sandreas.hansson@arm.com // only misses left 102611452Sandreas.hansson@arm.com 102711452Sandreas.hansson@arm.com PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable()); 102811051Sandreas.hansson@arm.com 102911484Snikos.nikoleris@arm.com bool is_forward = (bus_pkt == nullptr); 103011051Sandreas.hansson@arm.com 103111051Sandreas.hansson@arm.com if (is_forward) { 103211051Sandreas.hansson@arm.com // just forwarding the same request to the next level 103311051Sandreas.hansson@arm.com // no local cache operation involved 103411051Sandreas.hansson@arm.com bus_pkt = pkt; 103511051Sandreas.hansson@arm.com } 103611051Sandreas.hansson@arm.com 103711744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Sending an atomic %s\n", __func__, 103811744Snikos.nikoleris@arm.com bus_pkt->print()); 103911051Sandreas.hansson@arm.com 104011051Sandreas.hansson@arm.com#if TRACING_ON 104111051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 104211051Sandreas.hansson@arm.com#endif 104311051Sandreas.hansson@arm.com 104411051Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt)); 104511051Sandreas.hansson@arm.com 104611452Sandreas.hansson@arm.com bool is_invalidate = bus_pkt->isInvalidate(); 104711452Sandreas.hansson@arm.com 104811051Sandreas.hansson@arm.com // We are now dealing with the response handling 104911744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Receive response: %s in state %i\n", __func__, 105011744Snikos.nikoleris@arm.com bus_pkt->print(), old_state); 105111051Sandreas.hansson@arm.com 105211051Sandreas.hansson@arm.com // If packet was a forward, the response (if any) is already 105311051Sandreas.hansson@arm.com // in place in the bus_pkt == pkt structure, so we don't need 105411051Sandreas.hansson@arm.com // to do anything. Otherwise, use the separate bus_pkt to 105511051Sandreas.hansson@arm.com // generate response to pkt and then delete it. 105611051Sandreas.hansson@arm.com if (!is_forward) { 105711051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 105811051Sandreas.hansson@arm.com assert(bus_pkt->isResponse()); 105911051Sandreas.hansson@arm.com if (bus_pkt->isError()) { 106011051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 106111051Sandreas.hansson@arm.com pkt->copyError(bus_pkt); 106211051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::WriteLineReq) { 106311051Sandreas.hansson@arm.com // note the use of pkt, not bus_pkt here. 106411051Sandreas.hansson@arm.com 106511051Sandreas.hansson@arm.com // write-line request to the cache that promoted 106611051Sandreas.hansson@arm.com // the write to a whole line 106711197Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks, 106811197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 106911452Sandreas.hansson@arm.com assert(blk != NULL); 107011452Sandreas.hansson@arm.com is_invalidate = false; 107111601Sandreas.hansson@arm.com satisfyRequest(pkt, blk); 107211051Sandreas.hansson@arm.com } else if (bus_pkt->isRead() || 107311051Sandreas.hansson@arm.com bus_pkt->cmd == MemCmd::UpgradeResp) { 107411051Sandreas.hansson@arm.com // we're updating cache state to allow us to 107511051Sandreas.hansson@arm.com // satisfy the upstream request from the cache 107611197Sandreas.hansson@arm.com blk = handleFill(bus_pkt, blk, writebacks, 107711197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 107811601Sandreas.hansson@arm.com satisfyRequest(pkt, blk); 107911601Sandreas.hansson@arm.com maintainClusivity(pkt->fromCache(), blk); 108011051Sandreas.hansson@arm.com } else { 108111051Sandreas.hansson@arm.com // we're satisfying the upstream request without 108211051Sandreas.hansson@arm.com // modifying cache state, e.g., a write-through 108311051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 108411051Sandreas.hansson@arm.com } 108511051Sandreas.hansson@arm.com } 108611051Sandreas.hansson@arm.com delete bus_pkt; 108711051Sandreas.hansson@arm.com } 108811452Sandreas.hansson@arm.com 108911452Sandreas.hansson@arm.com if (is_invalidate && blk && blk->isValid()) { 109011452Sandreas.hansson@arm.com invalidateBlock(blk); 109111452Sandreas.hansson@arm.com } 109211051Sandreas.hansson@arm.com } 109311051Sandreas.hansson@arm.com 109411051Sandreas.hansson@arm.com // Note that we don't invoke the prefetcher at all in atomic mode. 109511051Sandreas.hansson@arm.com // It's not clear how to do it properly, particularly for 109611051Sandreas.hansson@arm.com // prefetchers that aggressively generate prefetch candidates and 109711051Sandreas.hansson@arm.com // rely on bandwidth contention to throttle them; these will tend 109811051Sandreas.hansson@arm.com // to pollute the cache in atomic mode since there is no bandwidth 109911051Sandreas.hansson@arm.com // contention. If we ever do want to enable prefetching in atomic 110011051Sandreas.hansson@arm.com // mode, though, this is the place to do it... see timingAccess() 110111051Sandreas.hansson@arm.com // for an example (though we'd want to issue the prefetch(es) 110211051Sandreas.hansson@arm.com // immediately rather than calling requestMemSideBus() as we do 110311051Sandreas.hansson@arm.com // there). 110411051Sandreas.hansson@arm.com 110511197Sandreas.hansson@arm.com // do any writebacks resulting from the response handling 110611130Sali.jafri@arm.com doWritebacksAtomic(writebacks); 110711051Sandreas.hansson@arm.com 110811197Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and if so 110911197Sandreas.hansson@arm.com // clear it out, but only do so after the call to recvAtomic is 111011197Sandreas.hansson@arm.com // finished so that any downstream observers (such as a snoop 111111197Sandreas.hansson@arm.com // filter), first see the fill, and only then see the eviction 111211197Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 111311197Sandreas.hansson@arm.com // the atomic CPU calls recvAtomic for fetch and load/store 111411197Sandreas.hansson@arm.com // sequentuially, and we may already have a tempBlock 111511197Sandreas.hansson@arm.com // writeback from the fetch that we have not yet sent 111611197Sandreas.hansson@arm.com if (tempBlockWriteback) { 111711197Sandreas.hansson@arm.com // if that is the case, write the prevoius one back, and 111811197Sandreas.hansson@arm.com // do not schedule any new event 111911197Sandreas.hansson@arm.com writebackTempBlockAtomic(); 112011197Sandreas.hansson@arm.com } else { 112111197Sandreas.hansson@arm.com // the writeback/clean eviction happens after the call to 112211197Sandreas.hansson@arm.com // recvAtomic has finished (but before any successive 112311197Sandreas.hansson@arm.com // calls), so that the response handling from the fill is 112411197Sandreas.hansson@arm.com // allowed to happen first 112511197Sandreas.hansson@arm.com schedule(writebackTempBlockAtomicEvent, curTick()); 112611197Sandreas.hansson@arm.com } 112711197Sandreas.hansson@arm.com 112811199Sandreas.hansson@arm.com tempBlockWriteback = (blk->isDirty() || writebackClean) ? 112911199Sandreas.hansson@arm.com writebackBlk(blk) : cleanEvictBlk(blk); 113011197Sandreas.hansson@arm.com blk->invalidate(); 113111197Sandreas.hansson@arm.com } 113211197Sandreas.hansson@arm.com 113311051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 113411051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 113511051Sandreas.hansson@arm.com } 113611051Sandreas.hansson@arm.com 113711051Sandreas.hansson@arm.com return lat * clockPeriod(); 113811051Sandreas.hansson@arm.com} 113911051Sandreas.hansson@arm.com 114011051Sandreas.hansson@arm.com 114111051Sandreas.hansson@arm.comvoid 114211051Sandreas.hansson@arm.comCache::functionalAccess(PacketPtr pkt, bool fromCpuSide) 114311051Sandreas.hansson@arm.com{ 114411051Sandreas.hansson@arm.com if (system->bypassCaches()) { 114511051Sandreas.hansson@arm.com // Packets from the memory side are snoop request and 114611051Sandreas.hansson@arm.com // shouldn't happen in bypass mode. 114711051Sandreas.hansson@arm.com assert(fromCpuSide); 114811051Sandreas.hansson@arm.com 114911051Sandreas.hansson@arm.com // The cache should be flushed if we are in cache bypass mode, 115011051Sandreas.hansson@arm.com // so we don't need to check if we need to update anything. 115111051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 115211051Sandreas.hansson@arm.com return; 115311051Sandreas.hansson@arm.com } 115411051Sandreas.hansson@arm.com 115511051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 115611051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 115711051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 115811051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 115911051Sandreas.hansson@arm.com 116011051Sandreas.hansson@arm.com pkt->pushLabel(name()); 116111051Sandreas.hansson@arm.com 116211051Sandreas.hansson@arm.com CacheBlkPrintWrapper cbpw(blk); 116311051Sandreas.hansson@arm.com 116411051Sandreas.hansson@arm.com // Note that just because an L2/L3 has valid data doesn't mean an 116511051Sandreas.hansson@arm.com // L1 doesn't have a more up-to-date modified copy that still 116611051Sandreas.hansson@arm.com // needs to be found. As a result we always update the request if 116711051Sandreas.hansson@arm.com // we have it, but only declare it satisfied if we are the owner. 116811051Sandreas.hansson@arm.com 116911051Sandreas.hansson@arm.com // see if we have data at all (owned or otherwise) 117011051Sandreas.hansson@arm.com bool have_data = blk && blk->isValid() 117111051Sandreas.hansson@arm.com && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize, 117211051Sandreas.hansson@arm.com blk->data); 117311051Sandreas.hansson@arm.com 117411284Sandreas.hansson@arm.com // data we have is dirty if marked as such or if we have an 117511284Sandreas.hansson@arm.com // in-service MSHR that is pending a modified line 117611051Sandreas.hansson@arm.com bool have_dirty = 117711051Sandreas.hansson@arm.com have_data && (blk->isDirty() || 117811284Sandreas.hansson@arm.com (mshr && mshr->inService && mshr->isPendingModified())); 117911051Sandreas.hansson@arm.com 118011051Sandreas.hansson@arm.com bool done = have_dirty 118111051Sandreas.hansson@arm.com || cpuSidePort->checkFunctional(pkt) 118211051Sandreas.hansson@arm.com || mshrQueue.checkFunctional(pkt, blk_addr) 118311051Sandreas.hansson@arm.com || writeBuffer.checkFunctional(pkt, blk_addr) 118411051Sandreas.hansson@arm.com || memSidePort->checkFunctional(pkt); 118511051Sandreas.hansson@arm.com 118611744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: %s %s%s%s\n", __func__, pkt->print(), 118711051Sandreas.hansson@arm.com (blk && blk->isValid()) ? "valid " : "", 118811051Sandreas.hansson@arm.com have_data ? "data " : "", done ? "done " : ""); 118911051Sandreas.hansson@arm.com 119011051Sandreas.hansson@arm.com // We're leaving the cache, so pop cache->name() label 119111051Sandreas.hansson@arm.com pkt->popLabel(); 119211051Sandreas.hansson@arm.com 119311051Sandreas.hansson@arm.com if (done) { 119411051Sandreas.hansson@arm.com pkt->makeResponse(); 119511051Sandreas.hansson@arm.com } else { 119611051Sandreas.hansson@arm.com // if it came as a request from the CPU side then make sure it 119711051Sandreas.hansson@arm.com // continues towards the memory side 119811051Sandreas.hansson@arm.com if (fromCpuSide) { 119911051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 120011485Snikos.nikoleris@arm.com } else if (cpuSidePort->isSnooping()) { 120111051Sandreas.hansson@arm.com // if it came from the memory side, it must be a snoop request 120211051Sandreas.hansson@arm.com // and we should only forward it if we are forwarding snoops 120311051Sandreas.hansson@arm.com cpuSidePort->sendFunctionalSnoop(pkt); 120411051Sandreas.hansson@arm.com } 120511051Sandreas.hansson@arm.com } 120611051Sandreas.hansson@arm.com} 120711051Sandreas.hansson@arm.com 120811051Sandreas.hansson@arm.com 120911051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 121011051Sandreas.hansson@arm.com// 121111051Sandreas.hansson@arm.com// Response handling: responses from the memory side 121211051Sandreas.hansson@arm.com// 121311051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 121411051Sandreas.hansson@arm.com 121511051Sandreas.hansson@arm.com 121611051Sandreas.hansson@arm.comvoid 121711375Sandreas.hansson@arm.comCache::handleUncacheableWriteResp(PacketPtr pkt) 121811375Sandreas.hansson@arm.com{ 121911375Sandreas.hansson@arm.com Tick completion_time = clockEdge(responseLatency) + 122011375Sandreas.hansson@arm.com pkt->headerDelay + pkt->payloadDelay; 122111375Sandreas.hansson@arm.com 122211453Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 122311453Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 122411375Sandreas.hansson@arm.com 122511453Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(pkt, completion_time, true); 122611375Sandreas.hansson@arm.com} 122711375Sandreas.hansson@arm.com 122811375Sandreas.hansson@arm.comvoid 122911051Sandreas.hansson@arm.comCache::recvTimingResp(PacketPtr pkt) 123011051Sandreas.hansson@arm.com{ 123111051Sandreas.hansson@arm.com assert(pkt->isResponse()); 123211051Sandreas.hansson@arm.com 123311051Sandreas.hansson@arm.com // all header delay should be paid for by the crossbar, unless 123411051Sandreas.hansson@arm.com // this is a prefetch response from above 123511051Sandreas.hansson@arm.com panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 123611051Sandreas.hansson@arm.com "%s saw a non-zero packet delay\n", name()); 123711051Sandreas.hansson@arm.com 123811051Sandreas.hansson@arm.com bool is_error = pkt->isError(); 123911051Sandreas.hansson@arm.com 124011051Sandreas.hansson@arm.com if (is_error) { 124111744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Cache received %s with error\n", __func__, 124211744Snikos.nikoleris@arm.com pkt->print()); 124311051Sandreas.hansson@arm.com } 124411051Sandreas.hansson@arm.com 124511744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Handling response %s\n", __func__, 124611744Snikos.nikoleris@arm.com pkt->print()); 124711051Sandreas.hansson@arm.com 124811375Sandreas.hansson@arm.com // if this is a write, we should be looking at an uncacheable 124911375Sandreas.hansson@arm.com // write 125011375Sandreas.hansson@arm.com if (pkt->isWrite()) { 125111375Sandreas.hansson@arm.com assert(pkt->req->isUncacheable()); 125211375Sandreas.hansson@arm.com handleUncacheableWriteResp(pkt); 125311375Sandreas.hansson@arm.com return; 125411375Sandreas.hansson@arm.com } 125511375Sandreas.hansson@arm.com 125611375Sandreas.hansson@arm.com // we have dealt with any (uncacheable) writes above, from here on 125711375Sandreas.hansson@arm.com // we know we are dealing with an MSHR due to a miss or a prefetch 125811453Sandreas.hansson@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState()); 125911375Sandreas.hansson@arm.com assert(mshr); 126011051Sandreas.hansson@arm.com 126111051Sandreas.hansson@arm.com if (mshr == noTargetMSHR) { 126211051Sandreas.hansson@arm.com // we always clear at least one target 126311051Sandreas.hansson@arm.com clearBlocked(Blocked_NoTargets); 126411484Snikos.nikoleris@arm.com noTargetMSHR = nullptr; 126511051Sandreas.hansson@arm.com } 126611051Sandreas.hansson@arm.com 126711051Sandreas.hansson@arm.com // Initial target is used just for stats 126811051Sandreas.hansson@arm.com MSHR::Target *initial_tgt = mshr->getTarget(); 126911051Sandreas.hansson@arm.com int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 127011051Sandreas.hansson@arm.com Tick miss_latency = curTick() - initial_tgt->recvTime; 127111051Sandreas.hansson@arm.com 127211051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 127311051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 127411051Sandreas.hansson@arm.com mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 127511051Sandreas.hansson@arm.com miss_latency; 127611051Sandreas.hansson@arm.com } else { 127711051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 127811051Sandreas.hansson@arm.com mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 127911051Sandreas.hansson@arm.com miss_latency; 128011051Sandreas.hansson@arm.com } 128111051Sandreas.hansson@arm.com 128211375Sandreas.hansson@arm.com bool wasFull = mshrQueue.isFull(); 128311375Sandreas.hansson@arm.com 128411375Sandreas.hansson@arm.com PacketList writebacks; 128511375Sandreas.hansson@arm.com 128611375Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 128711375Sandreas.hansson@arm.com 128811284Sandreas.hansson@arm.com // upgrade deferred targets if the response has no sharers, and is 128911284Sandreas.hansson@arm.com // thus passing writable 129011284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 129111284Sandreas.hansson@arm.com mshr->promoteWritable(); 129211177Sandreas.hansson@arm.com } 129311177Sandreas.hansson@arm.com 129411051Sandreas.hansson@arm.com bool is_fill = !mshr->isForward && 129511051Sandreas.hansson@arm.com (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp); 129611051Sandreas.hansson@arm.com 129711177Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 129811177Sandreas.hansson@arm.com 129911051Sandreas.hansson@arm.com if (is_fill && !is_error) { 130011051Sandreas.hansson@arm.com DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 130111051Sandreas.hansson@arm.com pkt->getAddr()); 130211051Sandreas.hansson@arm.com 130311741Snikos.nikoleris@arm.com blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill()); 130411484Snikos.nikoleris@arm.com assert(blk != nullptr); 130511051Sandreas.hansson@arm.com } 130611051Sandreas.hansson@arm.com 130711051Sandreas.hansson@arm.com // allow invalidation responses originating from write-line 130811051Sandreas.hansson@arm.com // requests to be discarded 130911136Sandreas.hansson@arm.com bool is_invalidate = pkt->isInvalidate(); 131011051Sandreas.hansson@arm.com 131111051Sandreas.hansson@arm.com // First offset for critical word first calculations 131211051Sandreas.hansson@arm.com int initial_offset = initial_tgt->pkt->getOffset(blkSize); 131311051Sandreas.hansson@arm.com 131411601Sandreas.hansson@arm.com bool from_cache = false; 131511742Snikos.nikoleris@arm.com MSHR::TargetList targets = mshr->extractServiceableTargets(pkt); 131611742Snikos.nikoleris@arm.com for (auto &target: targets) { 131711742Snikos.nikoleris@arm.com Packet *tgt_pkt = target.pkt; 131811742Snikos.nikoleris@arm.com switch (target.source) { 131911051Sandreas.hansson@arm.com case MSHR::Target::FromCPU: 132011051Sandreas.hansson@arm.com Tick completion_time; 132111051Sandreas.hansson@arm.com // Here we charge on completion_time the delay of the xbar if the 132211051Sandreas.hansson@arm.com // packet comes from it, charged on headerDelay. 132311051Sandreas.hansson@arm.com completion_time = pkt->headerDelay; 132411051Sandreas.hansson@arm.com 132511051Sandreas.hansson@arm.com // Software prefetch handling for cache closest to core 132611051Sandreas.hansson@arm.com if (tgt_pkt->cmd.isSWPrefetch()) { 132711483Snikos.nikoleris@arm.com // a software prefetch would have already been ack'd 132811483Snikos.nikoleris@arm.com // immediately with dummy data so the core would be able to 132911483Snikos.nikoleris@arm.com // retire it. This request completes right here, so we 133011483Snikos.nikoleris@arm.com // deallocate it. 133111051Sandreas.hansson@arm.com delete tgt_pkt->req; 133211051Sandreas.hansson@arm.com delete tgt_pkt; 133311051Sandreas.hansson@arm.com break; // skip response 133411051Sandreas.hansson@arm.com } 133511051Sandreas.hansson@arm.com 133611601Sandreas.hansson@arm.com // keep track of whether we have responded to another 133711601Sandreas.hansson@arm.com // cache 133811601Sandreas.hansson@arm.com from_cache = from_cache || tgt_pkt->fromCache(); 133911601Sandreas.hansson@arm.com 134011051Sandreas.hansson@arm.com // unlike the other packet flows, where data is found in other 134111051Sandreas.hansson@arm.com // caches or memory and brought back, write-line requests always 134211051Sandreas.hansson@arm.com // have the data right away, so the above check for "is fill?" 134311051Sandreas.hansson@arm.com // cannot actually be determined until examining the stored MSHR 134411051Sandreas.hansson@arm.com // state. We "catch up" with that logic here, which is duplicated 134511051Sandreas.hansson@arm.com // from above. 134611051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::WriteLineReq) { 134711051Sandreas.hansson@arm.com assert(!is_error); 134811284Sandreas.hansson@arm.com // we got the block in a writable state, so promote 134911284Sandreas.hansson@arm.com // any deferred targets if possible 135011284Sandreas.hansson@arm.com mshr->promoteWritable(); 135111051Sandreas.hansson@arm.com // NB: we use the original packet here and not the response! 135211741Snikos.nikoleris@arm.com blk = handleFill(tgt_pkt, blk, writebacks, 135311742Snikos.nikoleris@arm.com targets.allocOnFill); 135411484Snikos.nikoleris@arm.com assert(blk != nullptr); 135511051Sandreas.hansson@arm.com 135611051Sandreas.hansson@arm.com // treat as a fill, and discard the invalidation 135711051Sandreas.hansson@arm.com // response 135811051Sandreas.hansson@arm.com is_fill = true; 135911136Sandreas.hansson@arm.com is_invalidate = false; 136011051Sandreas.hansson@arm.com } 136111051Sandreas.hansson@arm.com 136211051Sandreas.hansson@arm.com if (is_fill) { 136311601Sandreas.hansson@arm.com satisfyRequest(tgt_pkt, blk, true, mshr->hasPostDowngrade()); 136411051Sandreas.hansson@arm.com 136511051Sandreas.hansson@arm.com // How many bytes past the first request is this one 136611051Sandreas.hansson@arm.com int transfer_offset = 136711051Sandreas.hansson@arm.com tgt_pkt->getOffset(blkSize) - initial_offset; 136811051Sandreas.hansson@arm.com if (transfer_offset < 0) { 136911051Sandreas.hansson@arm.com transfer_offset += blkSize; 137011051Sandreas.hansson@arm.com } 137111051Sandreas.hansson@arm.com 137211051Sandreas.hansson@arm.com // If not critical word (offset) return payloadDelay. 137311051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 137411051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 137511051Sandreas.hansson@arm.com // the core. 137611051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 137711051Sandreas.hansson@arm.com (transfer_offset ? pkt->payloadDelay : 0); 137811051Sandreas.hansson@arm.com 137911051Sandreas.hansson@arm.com assert(!tgt_pkt->req->isUncacheable()); 138011051Sandreas.hansson@arm.com 138111051Sandreas.hansson@arm.com assert(tgt_pkt->req->masterId() < system->maxMasters()); 138211051Sandreas.hansson@arm.com missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] += 138311742Snikos.nikoleris@arm.com completion_time - target.recvTime; 138411051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::UpgradeFailResp) { 138511051Sandreas.hansson@arm.com // failed StoreCond upgrade 138611051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::StoreCondReq || 138711051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::StoreCondFailReq || 138811051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::SCUpgradeFailReq); 138911051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 139011051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 139111051Sandreas.hansson@arm.com // the core. 139211051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 139311051Sandreas.hansson@arm.com pkt->payloadDelay; 139411051Sandreas.hansson@arm.com tgt_pkt->req->setExtraData(0); 139511051Sandreas.hansson@arm.com } else { 139611750Snikos.nikoleris@arm.com // We are about to send a response to a cache above 139711750Snikos.nikoleris@arm.com // that asked for an invalidation; we need to 139811750Snikos.nikoleris@arm.com // invalidate our copy immediately as the most 139911750Snikos.nikoleris@arm.com // up-to-date copy of the block will now be in the 140011750Snikos.nikoleris@arm.com // cache above. It will also prevent this cache from 140111750Snikos.nikoleris@arm.com // responding (if the block was previously dirty) to 140211750Snikos.nikoleris@arm.com // snoops as they should snoop the caches above where 140311750Snikos.nikoleris@arm.com // they will get the response from. 140411750Snikos.nikoleris@arm.com if (is_invalidate && blk && blk->isValid()) { 140511750Snikos.nikoleris@arm.com invalidateBlock(blk); 140611750Snikos.nikoleris@arm.com } 140711051Sandreas.hansson@arm.com // not a cache fill, just forwarding response 140811051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 140911051Sandreas.hansson@arm.com // from lower level cahces/memory to the core. 141011051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 141111051Sandreas.hansson@arm.com pkt->payloadDelay; 141211051Sandreas.hansson@arm.com if (pkt->isRead() && !is_error) { 141311051Sandreas.hansson@arm.com // sanity check 141411051Sandreas.hansson@arm.com assert(pkt->getAddr() == tgt_pkt->getAddr()); 141511051Sandreas.hansson@arm.com assert(pkt->getSize() >= tgt_pkt->getSize()); 141611051Sandreas.hansson@arm.com 141711051Sandreas.hansson@arm.com tgt_pkt->setData(pkt->getConstPtr<uint8_t>()); 141811051Sandreas.hansson@arm.com } 141911051Sandreas.hansson@arm.com } 142011051Sandreas.hansson@arm.com tgt_pkt->makeTimingResponse(); 142111051Sandreas.hansson@arm.com // if this packet is an error copy that to the new packet 142211051Sandreas.hansson@arm.com if (is_error) 142311051Sandreas.hansson@arm.com tgt_pkt->copyError(pkt); 142411051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::ReadResp && 142511136Sandreas.hansson@arm.com (is_invalidate || mshr->hasPostInvalidate())) { 142611051Sandreas.hansson@arm.com // If intermediate cache got ReadRespWithInvalidate, 142711051Sandreas.hansson@arm.com // propagate that. Response should not have 142811051Sandreas.hansson@arm.com // isInvalidate() set otherwise. 142911051Sandreas.hansson@arm.com tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate; 143011744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: updated cmd to %s\n", __func__, 143111744Snikos.nikoleris@arm.com tgt_pkt->print()); 143211051Sandreas.hansson@arm.com } 143311051Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 143411051Sandreas.hansson@arm.com tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; 143511194Sali.jafri@arm.com cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true); 143611051Sandreas.hansson@arm.com break; 143711051Sandreas.hansson@arm.com 143811051Sandreas.hansson@arm.com case MSHR::Target::FromPrefetcher: 143911051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::HardPFReq); 144011051Sandreas.hansson@arm.com if (blk) 144111051Sandreas.hansson@arm.com blk->status |= BlkHWPrefetched; 144211051Sandreas.hansson@arm.com delete tgt_pkt->req; 144311051Sandreas.hansson@arm.com delete tgt_pkt; 144411051Sandreas.hansson@arm.com break; 144511051Sandreas.hansson@arm.com 144611051Sandreas.hansson@arm.com case MSHR::Target::FromSnoop: 144711051Sandreas.hansson@arm.com // I don't believe that a snoop can be in an error state 144811051Sandreas.hansson@arm.com assert(!is_error); 144911051Sandreas.hansson@arm.com // response to snoop request 145011051Sandreas.hansson@arm.com DPRINTF(Cache, "processing deferred snoop...\n"); 145111749Snikos.nikoleris@arm.com // If the response is invalidating, a snooping target can 145211749Snikos.nikoleris@arm.com // be satisfied if it is also invalidating. If the reponse is, not 145311749Snikos.nikoleris@arm.com // only invalidating, but more specifically an InvalidateResp, the 145411749Snikos.nikoleris@arm.com // MSHR was created due to an InvalidateReq and a cache above is 145511749Snikos.nikoleris@arm.com // waiting to satisfy a WriteLineReq. In this case even an 145611749Snikos.nikoleris@arm.com // non-invalidating snoop is added as a target here since this is 145711749Snikos.nikoleris@arm.com // the ordering point. When the InvalidateResp reaches this cache, 145811749Snikos.nikoleris@arm.com // the snooping target will snoop further the cache above with the 145911749Snikos.nikoleris@arm.com // WriteLineReq. 146011749Snikos.nikoleris@arm.com assert(!(is_invalidate && 146111749Snikos.nikoleris@arm.com pkt->cmd != MemCmd::InvalidateResp && 146211749Snikos.nikoleris@arm.com !mshr->hasPostInvalidate())); 146311051Sandreas.hansson@arm.com handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate()); 146411051Sandreas.hansson@arm.com break; 146511051Sandreas.hansson@arm.com 146611051Sandreas.hansson@arm.com default: 146711742Snikos.nikoleris@arm.com panic("Illegal target->source enum %d\n", target.source); 146811051Sandreas.hansson@arm.com } 146911051Sandreas.hansson@arm.com } 147011051Sandreas.hansson@arm.com 147111601Sandreas.hansson@arm.com maintainClusivity(from_cache, blk); 147211601Sandreas.hansson@arm.com 147311051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 147411051Sandreas.hansson@arm.com // an invalidate response stemming from a write line request 147511051Sandreas.hansson@arm.com // should not invalidate the block, so check if the 147611051Sandreas.hansson@arm.com // invalidation should be discarded 147711136Sandreas.hansson@arm.com if (is_invalidate || mshr->hasPostInvalidate()) { 147811197Sandreas.hansson@arm.com invalidateBlock(blk); 147911051Sandreas.hansson@arm.com } else if (mshr->hasPostDowngrade()) { 148011051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 148111051Sandreas.hansson@arm.com } 148211051Sandreas.hansson@arm.com } 148311051Sandreas.hansson@arm.com 148411051Sandreas.hansson@arm.com if (mshr->promoteDeferredTargets()) { 148511051Sandreas.hansson@arm.com // avoid later read getting stale data while write miss is 148611051Sandreas.hansson@arm.com // outstanding.. see comment in timingAccess() 148711051Sandreas.hansson@arm.com if (blk) { 148811051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 148911051Sandreas.hansson@arm.com } 149011375Sandreas.hansson@arm.com mshrQueue.markPending(mshr); 149111051Sandreas.hansson@arm.com schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 149211051Sandreas.hansson@arm.com } else { 149311375Sandreas.hansson@arm.com mshrQueue.deallocate(mshr); 149411375Sandreas.hansson@arm.com if (wasFull && !mshrQueue.isFull()) { 149511375Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 149611051Sandreas.hansson@arm.com } 149711051Sandreas.hansson@arm.com 149811051Sandreas.hansson@arm.com // Request the bus for a prefetch if this deallocation freed enough 149911051Sandreas.hansson@arm.com // MSHRs for a prefetch to take place 150011375Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 150111051Sandreas.hansson@arm.com Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 150211051Sandreas.hansson@arm.com clockEdge()); 150311051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 150411051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 150511051Sandreas.hansson@arm.com } 150611051Sandreas.hansson@arm.com } 150711051Sandreas.hansson@arm.com // reset the xbar additional timinig as it is now accounted for 150811051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 150911051Sandreas.hansson@arm.com 151011051Sandreas.hansson@arm.com // copy writebacks to write buffer 151111051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 151211051Sandreas.hansson@arm.com 151311051Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and then clear it out 151411051Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 151511051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying 151611051Sandreas.hansson@arm.com // Writebacks/CleanEvicts to write buffer. It specifies the latency to 151711051Sandreas.hansson@arm.com // allocate an internal buffer and to schedule an event to the 151811051Sandreas.hansson@arm.com // queued port. 151911199Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 152011051Sandreas.hansson@arm.com PacketPtr wbPkt = writebackBlk(blk); 152111051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 152211051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag if cached above. 152311051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) 152411051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 152511051Sandreas.hansson@arm.com } else { 152611051Sandreas.hansson@arm.com PacketPtr wcPkt = cleanEvictBlk(blk); 152711051Sandreas.hansson@arm.com // Check to see if block is cached above. If not allocate 152811051Sandreas.hansson@arm.com // write buffer 152911051Sandreas.hansson@arm.com if (isCachedAbove(wcPkt)) 153011051Sandreas.hansson@arm.com delete wcPkt; 153111051Sandreas.hansson@arm.com else 153211051Sandreas.hansson@arm.com allocateWriteBuffer(wcPkt, forward_time); 153311051Sandreas.hansson@arm.com } 153411051Sandreas.hansson@arm.com blk->invalidate(); 153511051Sandreas.hansson@arm.com } 153611051Sandreas.hansson@arm.com 153711744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print()); 153811051Sandreas.hansson@arm.com delete pkt; 153911051Sandreas.hansson@arm.com} 154011051Sandreas.hansson@arm.com 154111051Sandreas.hansson@arm.comPacketPtr 154211051Sandreas.hansson@arm.comCache::writebackBlk(CacheBlk *blk) 154311051Sandreas.hansson@arm.com{ 154411199Sandreas.hansson@arm.com chatty_assert(!isReadOnly || writebackClean, 154511199Sandreas.hansson@arm.com "Writeback from read-only cache"); 154611199Sandreas.hansson@arm.com assert(blk && blk->isValid() && (blk->isDirty() || writebackClean)); 154711051Sandreas.hansson@arm.com 154811051Sandreas.hansson@arm.com writebacks[Request::wbMasterId]++; 154911051Sandreas.hansson@arm.com 155011199Sandreas.hansson@arm.com Request *req = new Request(tags->regenerateBlkAddr(blk->tag, blk->set), 155111199Sandreas.hansson@arm.com blkSize, 0, Request::wbMasterId); 155211051Sandreas.hansson@arm.com if (blk->isSecure()) 155311199Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 155411051Sandreas.hansson@arm.com 155511199Sandreas.hansson@arm.com req->taskId(blk->task_id); 155611051Sandreas.hansson@arm.com blk->task_id= ContextSwitchTaskId::Unknown; 155711051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 155811051Sandreas.hansson@arm.com 155911199Sandreas.hansson@arm.com PacketPtr pkt = 156011199Sandreas.hansson@arm.com new Packet(req, blk->isDirty() ? 156111199Sandreas.hansson@arm.com MemCmd::WritebackDirty : MemCmd::WritebackClean); 156211199Sandreas.hansson@arm.com 156311744Snikos.nikoleris@arm.com DPRINTF(Cache, "Create Writeback %s writable: %d, dirty: %d\n", 156411744Snikos.nikoleris@arm.com pkt->print(), blk->isWritable(), blk->isDirty()); 156511199Sandreas.hansson@arm.com 156611051Sandreas.hansson@arm.com if (blk->isWritable()) { 156711051Sandreas.hansson@arm.com // not asserting shared means we pass the block in modified 156811051Sandreas.hansson@arm.com // state, mark our own block non-writeable 156911051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 157011051Sandreas.hansson@arm.com } else { 157111284Sandreas.hansson@arm.com // we are in the Owned state, tell the receiver 157211284Sandreas.hansson@arm.com pkt->setHasSharers(); 157311051Sandreas.hansson@arm.com } 157411051Sandreas.hansson@arm.com 157511199Sandreas.hansson@arm.com // make sure the block is not marked dirty 157611199Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 157711051Sandreas.hansson@arm.com 157811199Sandreas.hansson@arm.com pkt->allocate(); 157911199Sandreas.hansson@arm.com std::memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize); 158011199Sandreas.hansson@arm.com 158111199Sandreas.hansson@arm.com return pkt; 158211051Sandreas.hansson@arm.com} 158311051Sandreas.hansson@arm.com 158411051Sandreas.hansson@arm.comPacketPtr 158511051Sandreas.hansson@arm.comCache::cleanEvictBlk(CacheBlk *blk) 158611051Sandreas.hansson@arm.com{ 158711199Sandreas.hansson@arm.com assert(!writebackClean); 158811051Sandreas.hansson@arm.com assert(blk && blk->isValid() && !blk->isDirty()); 158911051Sandreas.hansson@arm.com // Creating a zero sized write, a message to the snoop filter 159011051Sandreas.hansson@arm.com Request *req = 159111051Sandreas.hansson@arm.com new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0, 159211051Sandreas.hansson@arm.com Request::wbMasterId); 159311051Sandreas.hansson@arm.com if (blk->isSecure()) 159411051Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 159511051Sandreas.hansson@arm.com 159611051Sandreas.hansson@arm.com req->taskId(blk->task_id); 159711051Sandreas.hansson@arm.com blk->task_id = ContextSwitchTaskId::Unknown; 159811051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 159911051Sandreas.hansson@arm.com 160011051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::CleanEvict); 160111051Sandreas.hansson@arm.com pkt->allocate(); 160211744Snikos.nikoleris@arm.com DPRINTF(Cache, "Create CleanEvict %s\n", pkt->print()); 160311051Sandreas.hansson@arm.com 160411051Sandreas.hansson@arm.com return pkt; 160511051Sandreas.hansson@arm.com} 160611051Sandreas.hansson@arm.com 160711051Sandreas.hansson@arm.comvoid 160811051Sandreas.hansson@arm.comCache::memWriteback() 160911051Sandreas.hansson@arm.com{ 161011051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::writebackVisitor); 161111051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 161211051Sandreas.hansson@arm.com} 161311051Sandreas.hansson@arm.com 161411051Sandreas.hansson@arm.comvoid 161511051Sandreas.hansson@arm.comCache::memInvalidate() 161611051Sandreas.hansson@arm.com{ 161711051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::invalidateVisitor); 161811051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 161911051Sandreas.hansson@arm.com} 162011051Sandreas.hansson@arm.com 162111051Sandreas.hansson@arm.combool 162211051Sandreas.hansson@arm.comCache::isDirty() const 162311051Sandreas.hansson@arm.com{ 162411051Sandreas.hansson@arm.com CacheBlkIsDirtyVisitor visitor; 162511051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 162611051Sandreas.hansson@arm.com 162711051Sandreas.hansson@arm.com return visitor.isDirty(); 162811051Sandreas.hansson@arm.com} 162911051Sandreas.hansson@arm.com 163011051Sandreas.hansson@arm.combool 163111051Sandreas.hansson@arm.comCache::writebackVisitor(CacheBlk &blk) 163211051Sandreas.hansson@arm.com{ 163311051Sandreas.hansson@arm.com if (blk.isDirty()) { 163411051Sandreas.hansson@arm.com assert(blk.isValid()); 163511051Sandreas.hansson@arm.com 163611051Sandreas.hansson@arm.com Request request(tags->regenerateBlkAddr(blk.tag, blk.set), 163711051Sandreas.hansson@arm.com blkSize, 0, Request::funcMasterId); 163811051Sandreas.hansson@arm.com request.taskId(blk.task_id); 163911051Sandreas.hansson@arm.com 164011051Sandreas.hansson@arm.com Packet packet(&request, MemCmd::WriteReq); 164111051Sandreas.hansson@arm.com packet.dataStatic(blk.data); 164211051Sandreas.hansson@arm.com 164311051Sandreas.hansson@arm.com memSidePort->sendFunctional(&packet); 164411051Sandreas.hansson@arm.com 164511051Sandreas.hansson@arm.com blk.status &= ~BlkDirty; 164611051Sandreas.hansson@arm.com } 164711051Sandreas.hansson@arm.com 164811051Sandreas.hansson@arm.com return true; 164911051Sandreas.hansson@arm.com} 165011051Sandreas.hansson@arm.com 165111051Sandreas.hansson@arm.combool 165211051Sandreas.hansson@arm.comCache::invalidateVisitor(CacheBlk &blk) 165311051Sandreas.hansson@arm.com{ 165411051Sandreas.hansson@arm.com 165511051Sandreas.hansson@arm.com if (blk.isDirty()) 165611051Sandreas.hansson@arm.com warn_once("Invalidating dirty cache lines. Expect things to break.\n"); 165711051Sandreas.hansson@arm.com 165811051Sandreas.hansson@arm.com if (blk.isValid()) { 165911051Sandreas.hansson@arm.com assert(!blk.isDirty()); 166011051Sandreas.hansson@arm.com tags->invalidate(&blk); 166111051Sandreas.hansson@arm.com blk.invalidate(); 166211051Sandreas.hansson@arm.com } 166311051Sandreas.hansson@arm.com 166411051Sandreas.hansson@arm.com return true; 166511051Sandreas.hansson@arm.com} 166611051Sandreas.hansson@arm.com 166711051Sandreas.hansson@arm.comCacheBlk* 166811051Sandreas.hansson@arm.comCache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks) 166911051Sandreas.hansson@arm.com{ 167011051Sandreas.hansson@arm.com CacheBlk *blk = tags->findVictim(addr); 167111051Sandreas.hansson@arm.com 167211484Snikos.nikoleris@arm.com // It is valid to return nullptr if there is no victim 167311051Sandreas.hansson@arm.com if (!blk) 167411051Sandreas.hansson@arm.com return nullptr; 167511051Sandreas.hansson@arm.com 167611051Sandreas.hansson@arm.com if (blk->isValid()) { 167711051Sandreas.hansson@arm.com Addr repl_addr = tags->regenerateBlkAddr(blk->tag, blk->set); 167811051Sandreas.hansson@arm.com MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure()); 167911051Sandreas.hansson@arm.com if (repl_mshr) { 168011051Sandreas.hansson@arm.com // must be an outstanding upgrade request 168111051Sandreas.hansson@arm.com // on a block we're about to replace... 168211051Sandreas.hansson@arm.com assert(!blk->isWritable() || blk->isDirty()); 168311284Sandreas.hansson@arm.com assert(repl_mshr->needsWritable()); 168411051Sandreas.hansson@arm.com // too hard to replace block with transient state 168511051Sandreas.hansson@arm.com // allocation failed, block not inserted 168611484Snikos.nikoleris@arm.com return nullptr; 168711051Sandreas.hansson@arm.com } else { 168811483Snikos.nikoleris@arm.com DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx " 168911483Snikos.nikoleris@arm.com "(%s): %s\n", repl_addr, blk->isSecure() ? "s" : "ns", 169011051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", 169111051Sandreas.hansson@arm.com blk->isDirty() ? "writeback" : "clean"); 169211051Sandreas.hansson@arm.com 169311436SRekai.GonzalezAlberquilla@arm.com if (blk->wasPrefetched()) { 169411436SRekai.GonzalezAlberquilla@arm.com unusedPrefetches++; 169511436SRekai.GonzalezAlberquilla@arm.com } 169611051Sandreas.hansson@arm.com // Will send up Writeback/CleanEvict snoops via isCachedAbove 169711051Sandreas.hansson@arm.com // when pushing this writeback list into the write buffer. 169811199Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 169911051Sandreas.hansson@arm.com // Save writeback packet for handling by caller 170011051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(blk)); 170111051Sandreas.hansson@arm.com } else { 170211051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(blk)); 170311051Sandreas.hansson@arm.com } 170411051Sandreas.hansson@arm.com } 170511051Sandreas.hansson@arm.com } 170611051Sandreas.hansson@arm.com 170711051Sandreas.hansson@arm.com return blk; 170811051Sandreas.hansson@arm.com} 170911051Sandreas.hansson@arm.com 171011197Sandreas.hansson@arm.comvoid 171111197Sandreas.hansson@arm.comCache::invalidateBlock(CacheBlk *blk) 171211197Sandreas.hansson@arm.com{ 171311197Sandreas.hansson@arm.com if (blk != tempBlock) 171411197Sandreas.hansson@arm.com tags->invalidate(blk); 171511197Sandreas.hansson@arm.com blk->invalidate(); 171611197Sandreas.hansson@arm.com} 171711051Sandreas.hansson@arm.com 171811051Sandreas.hansson@arm.com// Note that the reason we return a list of writebacks rather than 171911051Sandreas.hansson@arm.com// inserting them directly in the write buffer is that this function 172011051Sandreas.hansson@arm.com// is called by both atomic and timing-mode accesses, and in atomic 172111051Sandreas.hansson@arm.com// mode we don't mess with the write buffer (we just perform the 172211051Sandreas.hansson@arm.com// writebacks atomically once the original request is complete). 172311051Sandreas.hansson@arm.comCacheBlk* 172411197Sandreas.hansson@arm.comCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, 172511197Sandreas.hansson@arm.com bool allocate) 172611051Sandreas.hansson@arm.com{ 172711051Sandreas.hansson@arm.com assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq); 172811051Sandreas.hansson@arm.com Addr addr = pkt->getAddr(); 172911051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 173011051Sandreas.hansson@arm.com#if TRACING_ON 173111051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 173211051Sandreas.hansson@arm.com#endif 173311051Sandreas.hansson@arm.com 173411375Sandreas.hansson@arm.com // When handling a fill, we should have no writes to this line. 173511375Sandreas.hansson@arm.com assert(addr == blockAlign(addr)); 173611375Sandreas.hansson@arm.com assert(!writeBuffer.findMatch(addr, is_secure)); 173711051Sandreas.hansson@arm.com 173811484Snikos.nikoleris@arm.com if (blk == nullptr) { 173911051Sandreas.hansson@arm.com // better have read new data... 174011051Sandreas.hansson@arm.com assert(pkt->hasData()); 174111051Sandreas.hansson@arm.com 174211051Sandreas.hansson@arm.com // only read responses and write-line requests have data; 174311051Sandreas.hansson@arm.com // note that we don't write the data here for write-line - that 174411601Sandreas.hansson@arm.com // happens in the subsequent call to satisfyRequest 174511051Sandreas.hansson@arm.com assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq); 174611051Sandreas.hansson@arm.com 174711197Sandreas.hansson@arm.com // need to do a replacement if allocating, otherwise we stick 174811197Sandreas.hansson@arm.com // with the temporary storage 174911484Snikos.nikoleris@arm.com blk = allocate ? allocateBlock(addr, is_secure, writebacks) : nullptr; 175011197Sandreas.hansson@arm.com 175111484Snikos.nikoleris@arm.com if (blk == nullptr) { 175211197Sandreas.hansson@arm.com // No replaceable block or a mostly exclusive 175311197Sandreas.hansson@arm.com // cache... just use temporary storage to complete the 175411197Sandreas.hansson@arm.com // current request and then get rid of it 175511051Sandreas.hansson@arm.com assert(!tempBlock->isValid()); 175611051Sandreas.hansson@arm.com blk = tempBlock; 175711051Sandreas.hansson@arm.com tempBlock->set = tags->extractSet(addr); 175811051Sandreas.hansson@arm.com tempBlock->tag = tags->extractTag(addr); 175911051Sandreas.hansson@arm.com // @todo: set security state as well... 176011051Sandreas.hansson@arm.com DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr, 176111051Sandreas.hansson@arm.com is_secure ? "s" : "ns"); 176211051Sandreas.hansson@arm.com } else { 176311051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 176411051Sandreas.hansson@arm.com } 176511051Sandreas.hansson@arm.com 176611051Sandreas.hansson@arm.com // we should never be overwriting a valid block 176711051Sandreas.hansson@arm.com assert(!blk->isValid()); 176811051Sandreas.hansson@arm.com } else { 176911051Sandreas.hansson@arm.com // existing block... probably an upgrade 177011051Sandreas.hansson@arm.com assert(blk->tag == tags->extractTag(addr)); 177111051Sandreas.hansson@arm.com // either we're getting new data or the block should already be valid 177211051Sandreas.hansson@arm.com assert(pkt->hasData() || blk->isValid()); 177311051Sandreas.hansson@arm.com // don't clear block status... if block is already dirty we 177411051Sandreas.hansson@arm.com // don't want to lose that 177511051Sandreas.hansson@arm.com } 177611051Sandreas.hansson@arm.com 177711051Sandreas.hansson@arm.com if (is_secure) 177811051Sandreas.hansson@arm.com blk->status |= BlkSecure; 177911051Sandreas.hansson@arm.com blk->status |= BlkValid | BlkReadable; 178011051Sandreas.hansson@arm.com 178111137Sandreas.hansson@arm.com // sanity check for whole-line writes, which should always be 178211137Sandreas.hansson@arm.com // marked as writable as part of the fill, and then later marked 178311601Sandreas.hansson@arm.com // dirty as part of satisfyRequest 178411137Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WriteLineReq) { 178511284Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 178611137Sandreas.hansson@arm.com // at the moment other caches do not respond to the 178711137Sandreas.hansson@arm.com // invalidation requests corresponding to a whole-line write 178811284Sandreas.hansson@arm.com assert(!pkt->cacheResponding()); 178911137Sandreas.hansson@arm.com } 179011137Sandreas.hansson@arm.com 179111284Sandreas.hansson@arm.com // here we deal with setting the appropriate state of the line, 179211284Sandreas.hansson@arm.com // and we start by looking at the hasSharers flag, and ignore the 179311284Sandreas.hansson@arm.com // cacheResponding flag (normally signalling dirty data) if the 179411284Sandreas.hansson@arm.com // packet has sharers, thus the line is never allocated as Owned 179511284Sandreas.hansson@arm.com // (dirty but not writable), and always ends up being either 179611284Sandreas.hansson@arm.com // Shared, Exclusive or Modified, see Packet::setCacheResponding 179711284Sandreas.hansson@arm.com // for more details 179811284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 179911284Sandreas.hansson@arm.com // we could get a writable line from memory (rather than a 180011284Sandreas.hansson@arm.com // cache) even in a read-only cache, note that we set this bit 180111284Sandreas.hansson@arm.com // even for a read-only cache, possibly revisit this decision 180211051Sandreas.hansson@arm.com blk->status |= BlkWritable; 180311051Sandreas.hansson@arm.com 180411284Sandreas.hansson@arm.com // check if we got this via cache-to-cache transfer (i.e., from a 180511284Sandreas.hansson@arm.com // cache that had the block in Modified or Owned state) 180611284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 180711284Sandreas.hansson@arm.com // we got the block in Modified state, and invalidated the 180811284Sandreas.hansson@arm.com // owners copy 180911051Sandreas.hansson@arm.com blk->status |= BlkDirty; 181011051Sandreas.hansson@arm.com 181111051Sandreas.hansson@arm.com chatty_assert(!isReadOnly, "Should never see dirty snoop response " 181211051Sandreas.hansson@arm.com "in read-only cache %s\n", name()); 181311051Sandreas.hansson@arm.com } 181411051Sandreas.hansson@arm.com } 181511051Sandreas.hansson@arm.com 181611051Sandreas.hansson@arm.com DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n", 181711051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", old_state, blk->print()); 181811051Sandreas.hansson@arm.com 181911051Sandreas.hansson@arm.com // if we got new data, copy it in (checking for a read response 182011051Sandreas.hansson@arm.com // and a response that has data is the same in the end) 182111051Sandreas.hansson@arm.com if (pkt->isRead()) { 182211051Sandreas.hansson@arm.com // sanity checks 182311051Sandreas.hansson@arm.com assert(pkt->hasData()); 182411051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 182511051Sandreas.hansson@arm.com 182611051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 182711051Sandreas.hansson@arm.com } 182811051Sandreas.hansson@arm.com // We pay for fillLatency here. 182911051Sandreas.hansson@arm.com blk->whenReady = clockEdge() + fillLatency * clockPeriod() + 183011051Sandreas.hansson@arm.com pkt->payloadDelay; 183111051Sandreas.hansson@arm.com 183211051Sandreas.hansson@arm.com return blk; 183311051Sandreas.hansson@arm.com} 183411051Sandreas.hansson@arm.com 183511051Sandreas.hansson@arm.com 183611051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 183711051Sandreas.hansson@arm.com// 183811051Sandreas.hansson@arm.com// Snoop path: requests coming in from the memory side 183911051Sandreas.hansson@arm.com// 184011051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 184111051Sandreas.hansson@arm.com 184211051Sandreas.hansson@arm.comvoid 184311051Sandreas.hansson@arm.comCache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 184411051Sandreas.hansson@arm.com bool already_copied, bool pending_inval) 184511051Sandreas.hansson@arm.com{ 184611051Sandreas.hansson@arm.com // sanity check 184711051Sandreas.hansson@arm.com assert(req_pkt->isRequest()); 184811051Sandreas.hansson@arm.com assert(req_pkt->needsResponse()); 184911051Sandreas.hansson@arm.com 185011744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: for %s\n", __func__, req_pkt->print()); 185111051Sandreas.hansson@arm.com // timing-mode snoop responses require a new packet, unless we 185211051Sandreas.hansson@arm.com // already made a copy... 185311051Sandreas.hansson@arm.com PacketPtr pkt = req_pkt; 185411051Sandreas.hansson@arm.com if (!already_copied) 185511051Sandreas.hansson@arm.com // do not clear flags, and allocate space for data if the 185611051Sandreas.hansson@arm.com // packet needs it (the only packets that carry data are read 185711051Sandreas.hansson@arm.com // responses) 185811051Sandreas.hansson@arm.com pkt = new Packet(req_pkt, false, req_pkt->isRead()); 185911051Sandreas.hansson@arm.com 186011051Sandreas.hansson@arm.com assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() || 186111284Sandreas.hansson@arm.com pkt->hasSharers()); 186211051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 186311051Sandreas.hansson@arm.com if (pkt->isRead()) { 186411051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk_data, blkSize); 186511051Sandreas.hansson@arm.com } 186611051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadResp && pending_inval) { 186711051Sandreas.hansson@arm.com // Assume we defer a response to a read from a far-away cache 186811051Sandreas.hansson@arm.com // A, then later defer a ReadExcl from a cache B on the same 186911284Sandreas.hansson@arm.com // bus as us. We'll assert cacheResponding in both cases, but 187011284Sandreas.hansson@arm.com // in the latter case cacheResponding will keep the 187111284Sandreas.hansson@arm.com // invalidation from reaching cache A. This special response 187211284Sandreas.hansson@arm.com // tells cache A that it gets the block to satisfy its read, 187311284Sandreas.hansson@arm.com // but must immediately invalidate it. 187411051Sandreas.hansson@arm.com pkt->cmd = MemCmd::ReadRespWithInvalidate; 187511051Sandreas.hansson@arm.com } 187611051Sandreas.hansson@arm.com // Here we consider forward_time, paying for just forward latency and 187711051Sandreas.hansson@arm.com // also charging the delay provided by the xbar. 187811051Sandreas.hansson@arm.com // forward_time is used as send_time in next allocateWriteBuffer(). 187911051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 188011051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 188111051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 188211744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: created response: %s tick: %lu\n", __func__, 188311744Snikos.nikoleris@arm.com pkt->print(), forward_time); 188411051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, forward_time, true); 188511051Sandreas.hansson@arm.com} 188611051Sandreas.hansson@arm.com 188711127Sandreas.hansson@arm.comuint32_t 188811051Sandreas.hansson@arm.comCache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, 188911051Sandreas.hansson@arm.com bool is_deferred, bool pending_inval) 189011051Sandreas.hansson@arm.com{ 189111744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 189211051Sandreas.hansson@arm.com // deferred snoops can only happen in timing mode 189311051Sandreas.hansson@arm.com assert(!(is_deferred && !is_timing)); 189411051Sandreas.hansson@arm.com // pending_inval only makes sense on deferred snoops 189511051Sandreas.hansson@arm.com assert(!(pending_inval && !is_deferred)); 189611051Sandreas.hansson@arm.com assert(pkt->isRequest()); 189711051Sandreas.hansson@arm.com 189811051Sandreas.hansson@arm.com // the packet may get modified if we or a forwarded snooper 189911051Sandreas.hansson@arm.com // responds in atomic mode, so remember a few things about the 190011051Sandreas.hansson@arm.com // original packet up front 190111051Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 190211284Sandreas.hansson@arm.com bool M5_VAR_USED needs_writable = pkt->needsWritable(); 190311051Sandreas.hansson@arm.com 190411285Sandreas.hansson@arm.com // at the moment we could get an uncacheable write which does not 190511285Sandreas.hansson@arm.com // have the invalidate flag, and we need a suitable way of dealing 190611285Sandreas.hansson@arm.com // with this case 190711285Sandreas.hansson@arm.com panic_if(invalidate && pkt->req->isUncacheable(), 190811744Snikos.nikoleris@arm.com "%s got an invalidating uncacheable snoop request %s", 190911744Snikos.nikoleris@arm.com name(), pkt->print()); 191011285Sandreas.hansson@arm.com 191111127Sandreas.hansson@arm.com uint32_t snoop_delay = 0; 191211127Sandreas.hansson@arm.com 191311051Sandreas.hansson@arm.com if (forwardSnoops) { 191411051Sandreas.hansson@arm.com // first propagate snoop upward to see if anyone above us wants to 191511051Sandreas.hansson@arm.com // handle it. save & restore packet src since it will get 191611051Sandreas.hansson@arm.com // rewritten to be relative to cpu-side bus (if any) 191711284Sandreas.hansson@arm.com bool alreadyResponded = pkt->cacheResponding(); 191811051Sandreas.hansson@arm.com if (is_timing) { 191911051Sandreas.hansson@arm.com // copy the packet so that we can clear any flags before 192011051Sandreas.hansson@arm.com // forwarding it upwards, we also allocate data (passing 192111051Sandreas.hansson@arm.com // the pointer along in case of static data), in case 192211051Sandreas.hansson@arm.com // there is a snoop hit in upper levels 192311051Sandreas.hansson@arm.com Packet snoopPkt(pkt, true, true); 192411051Sandreas.hansson@arm.com snoopPkt.setExpressSnoop(); 192511051Sandreas.hansson@arm.com // the snoop packet does not need to wait any additional 192611051Sandreas.hansson@arm.com // time 192711051Sandreas.hansson@arm.com snoopPkt.headerDelay = snoopPkt.payloadDelay = 0; 192811051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoopPkt); 192911127Sandreas.hansson@arm.com 193011127Sandreas.hansson@arm.com // add the header delay (including crossbar and snoop 193111127Sandreas.hansson@arm.com // delays) of the upward snoop to the snoop delay for this 193211127Sandreas.hansson@arm.com // cache 193311127Sandreas.hansson@arm.com snoop_delay += snoopPkt.headerDelay; 193411127Sandreas.hansson@arm.com 193511284Sandreas.hansson@arm.com if (snoopPkt.cacheResponding()) { 193611051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache 193711051Sandreas.hansson@arm.com assert(!alreadyResponded); 193811284Sandreas.hansson@arm.com pkt->setCacheResponding(); 193911051Sandreas.hansson@arm.com } 194011284Sandreas.hansson@arm.com // upstream cache has the block, or has an outstanding 194111284Sandreas.hansson@arm.com // MSHR, pass the flag on 194211284Sandreas.hansson@arm.com if (snoopPkt.hasSharers()) { 194311284Sandreas.hansson@arm.com pkt->setHasSharers(); 194411051Sandreas.hansson@arm.com } 194511051Sandreas.hansson@arm.com // If this request is a prefetch or clean evict and an upper level 194611051Sandreas.hansson@arm.com // signals block present, make sure to propagate the block 194711051Sandreas.hansson@arm.com // presence to the requester. 194811051Sandreas.hansson@arm.com if (snoopPkt.isBlockCached()) { 194911051Sandreas.hansson@arm.com pkt->setBlockCached(); 195011051Sandreas.hansson@arm.com } 195111051Sandreas.hansson@arm.com } else { 195211051Sandreas.hansson@arm.com cpuSidePort->sendAtomicSnoop(pkt); 195311284Sandreas.hansson@arm.com if (!alreadyResponded && pkt->cacheResponding()) { 195411051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache: 195511051Sandreas.hansson@arm.com // forward response to original requester 195611051Sandreas.hansson@arm.com assert(pkt->isResponse()); 195711051Sandreas.hansson@arm.com } 195811051Sandreas.hansson@arm.com } 195911051Sandreas.hansson@arm.com } 196011051Sandreas.hansson@arm.com 196111051Sandreas.hansson@arm.com if (!blk || !blk->isValid()) { 196211744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: snoop miss for %s\n", __func__, 196311744Snikos.nikoleris@arm.com pkt->print()); 196411493Sandreas.hansson@arm.com if (is_deferred) { 196511493Sandreas.hansson@arm.com // we no longer have the block, and will not respond, but a 196611493Sandreas.hansson@arm.com // packet was allocated in MSHR::handleSnoop and we have 196711493Sandreas.hansson@arm.com // to delete it 196811493Sandreas.hansson@arm.com assert(pkt->needsResponse()); 196911493Sandreas.hansson@arm.com 197011493Sandreas.hansson@arm.com // we have passed the block to a cache upstream, that 197111493Sandreas.hansson@arm.com // cache should be responding 197211493Sandreas.hansson@arm.com assert(pkt->cacheResponding()); 197311493Sandreas.hansson@arm.com 197411493Sandreas.hansson@arm.com delete pkt; 197511493Sandreas.hansson@arm.com } 197611127Sandreas.hansson@arm.com return snoop_delay; 197711051Sandreas.hansson@arm.com } else { 197811744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: snoop hit for %s, old state is %s\n", __func__, 197911744Snikos.nikoleris@arm.com pkt->print(), blk->print()); 198011051Sandreas.hansson@arm.com } 198111051Sandreas.hansson@arm.com 198211051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && blk->isDirty()), 198311051Sandreas.hansson@arm.com "Should never have a dirty block in a read-only cache %s\n", 198411051Sandreas.hansson@arm.com name()); 198511051Sandreas.hansson@arm.com 198611051Sandreas.hansson@arm.com // We may end up modifying both the block state and the packet (if 198711051Sandreas.hansson@arm.com // we respond in atomic mode), so just figure out what to do now 198811051Sandreas.hansson@arm.com // and then do it later. If we find dirty data while snooping for 198911051Sandreas.hansson@arm.com // an invalidate, we don't need to send a response. The 199011051Sandreas.hansson@arm.com // invalidation itself is taken care of below. 199111051Sandreas.hansson@arm.com bool respond = blk->isDirty() && pkt->needsResponse() && 199211051Sandreas.hansson@arm.com pkt->cmd != MemCmd::InvalidateReq; 199311284Sandreas.hansson@arm.com bool have_writable = blk->isWritable(); 199411051Sandreas.hansson@arm.com 199511051Sandreas.hansson@arm.com // Invalidate any prefetch's from below that would strip write permissions 199611051Sandreas.hansson@arm.com // MemCmd::HardPFReq is only observed by upstream caches. After missing 199711051Sandreas.hansson@arm.com // above and in it's own cache, a new MemCmd::ReadReq is created that 199811051Sandreas.hansson@arm.com // downstream caches observe. 199911051Sandreas.hansson@arm.com if (pkt->mustCheckAbove()) { 200011483Snikos.nikoleris@arm.com DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s " 200111744Snikos.nikoleris@arm.com "from lower cache\n", pkt->getAddr(), pkt->print()); 200211051Sandreas.hansson@arm.com pkt->setBlockCached(); 200311127Sandreas.hansson@arm.com return snoop_delay; 200411051Sandreas.hansson@arm.com } 200511051Sandreas.hansson@arm.com 200611285Sandreas.hansson@arm.com if (pkt->isRead() && !invalidate) { 200711285Sandreas.hansson@arm.com // reading without requiring the line in a writable state 200811284Sandreas.hansson@arm.com assert(!needs_writable); 200911284Sandreas.hansson@arm.com pkt->setHasSharers(); 201011285Sandreas.hansson@arm.com 201111285Sandreas.hansson@arm.com // if the requesting packet is uncacheable, retain the line in 201211285Sandreas.hansson@arm.com // the current state, otherwhise unset the writable flag, 201311285Sandreas.hansson@arm.com // which means we go from Modified to Owned (and will respond 201411285Sandreas.hansson@arm.com // below), remain in Owned (and will respond below), from 201511285Sandreas.hansson@arm.com // Exclusive to Shared, or remain in Shared 201611285Sandreas.hansson@arm.com if (!pkt->req->isUncacheable()) 201711285Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 201811051Sandreas.hansson@arm.com } 201911051Sandreas.hansson@arm.com 202011051Sandreas.hansson@arm.com if (respond) { 202111051Sandreas.hansson@arm.com // prevent anyone else from responding, cache as well as 202211051Sandreas.hansson@arm.com // memory, and also prevent any memory from even seeing the 202311284Sandreas.hansson@arm.com // request 202411284Sandreas.hansson@arm.com pkt->setCacheResponding(); 202511284Sandreas.hansson@arm.com if (have_writable) { 202611284Sandreas.hansson@arm.com // inform the cache hierarchy that this cache had the line 202711284Sandreas.hansson@arm.com // in the Modified state so that we avoid unnecessary 202811284Sandreas.hansson@arm.com // invalidations (see Packet::setResponderHadWritable) 202911284Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 203011284Sandreas.hansson@arm.com 203111081Sandreas.hansson@arm.com // in the case of an uncacheable request there is no point 203211284Sandreas.hansson@arm.com // in setting the responderHadWritable flag, but since the 203311284Sandreas.hansson@arm.com // recipient does not care there is no harm in doing so 203411284Sandreas.hansson@arm.com } else { 203511284Sandreas.hansson@arm.com // if the packet has needsWritable set we invalidate our 203611284Sandreas.hansson@arm.com // copy below and all other copies will be invalidates 203711284Sandreas.hansson@arm.com // through express snoops, and if needsWritable is not set 203811284Sandreas.hansson@arm.com // we already called setHasSharers above 203911051Sandreas.hansson@arm.com } 204011284Sandreas.hansson@arm.com 204111285Sandreas.hansson@arm.com // if we are returning a writable and dirty (Modified) line, 204211285Sandreas.hansson@arm.com // we should be invalidating the line 204311285Sandreas.hansson@arm.com panic_if(!invalidate && !pkt->hasSharers(), 204411744Snikos.nikoleris@arm.com "%s is passing a Modified line through %s, " 204511744Snikos.nikoleris@arm.com "but keeping the block", name(), pkt->print()); 204611285Sandreas.hansson@arm.com 204711051Sandreas.hansson@arm.com if (is_timing) { 204811051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval); 204911051Sandreas.hansson@arm.com } else { 205011051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 205111286Sandreas.hansson@arm.com // packets such as upgrades do not actually have any data 205211286Sandreas.hansson@arm.com // payload 205311286Sandreas.hansson@arm.com if (pkt->hasData()) 205411286Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 205511051Sandreas.hansson@arm.com } 205611051Sandreas.hansson@arm.com } 205711051Sandreas.hansson@arm.com 205811602Sandreas.hansson@arm.com if (!respond && is_deferred) { 205911051Sandreas.hansson@arm.com assert(pkt->needsResponse()); 206011602Sandreas.hansson@arm.com 206111602Sandreas.hansson@arm.com // if we copied the deferred packet with the intention to 206211602Sandreas.hansson@arm.com // respond, but are not responding, then a cache above us must 206311602Sandreas.hansson@arm.com // be, and we can use this as the indication of whether this 206411602Sandreas.hansson@arm.com // is a packet where we created a copy of the request or not 206511602Sandreas.hansson@arm.com if (!pkt->cacheResponding()) { 206611602Sandreas.hansson@arm.com delete pkt->req; 206711602Sandreas.hansson@arm.com } 206811602Sandreas.hansson@arm.com 206911051Sandreas.hansson@arm.com delete pkt; 207011051Sandreas.hansson@arm.com } 207111051Sandreas.hansson@arm.com 207211051Sandreas.hansson@arm.com // Do this last in case it deallocates block data or something 207311051Sandreas.hansson@arm.com // like that 207411051Sandreas.hansson@arm.com if (invalidate) { 207511197Sandreas.hansson@arm.com invalidateBlock(blk); 207611051Sandreas.hansson@arm.com } 207711051Sandreas.hansson@arm.com 207811051Sandreas.hansson@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 207911127Sandreas.hansson@arm.com 208011127Sandreas.hansson@arm.com return snoop_delay; 208111051Sandreas.hansson@arm.com} 208211051Sandreas.hansson@arm.com 208311051Sandreas.hansson@arm.com 208411051Sandreas.hansson@arm.comvoid 208511051Sandreas.hansson@arm.comCache::recvTimingSnoopReq(PacketPtr pkt) 208611051Sandreas.hansson@arm.com{ 208711744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 208811051Sandreas.hansson@arm.com 208911051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 209011051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 209111051Sandreas.hansson@arm.com 209211130Sali.jafri@arm.com // no need to snoop requests that are not in range 209311051Sandreas.hansson@arm.com if (!inRange(pkt->getAddr())) { 209411051Sandreas.hansson@arm.com return; 209511051Sandreas.hansson@arm.com } 209611051Sandreas.hansson@arm.com 209711051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 209811051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 209911051Sandreas.hansson@arm.com 210011051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 210111051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 210211051Sandreas.hansson@arm.com 210311127Sandreas.hansson@arm.com // Update the latency cost of the snoop so that the crossbar can 210411127Sandreas.hansson@arm.com // account for it. Do not overwrite what other neighbouring caches 210511127Sandreas.hansson@arm.com // have already done, rather take the maximum. The update is 210611127Sandreas.hansson@arm.com // tentative, for cases where we return before an upward snoop 210711127Sandreas.hansson@arm.com // happens below. 210811127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, 210911127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 211011127Sandreas.hansson@arm.com 211111051Sandreas.hansson@arm.com // Inform request(Prefetch, CleanEvict or Writeback) from below of 211211051Sandreas.hansson@arm.com // MSHR hit, set setBlockCached. 211311051Sandreas.hansson@arm.com if (mshr && pkt->mustCheckAbove()) { 211411744Snikos.nikoleris@arm.com DPRINTF(Cache, "Setting block cached for %s from lower cache on " 211511744Snikos.nikoleris@arm.com "mshr hit\n", pkt->print()); 211611051Sandreas.hansson@arm.com pkt->setBlockCached(); 211711051Sandreas.hansson@arm.com return; 211811051Sandreas.hansson@arm.com } 211911051Sandreas.hansson@arm.com 212011051Sandreas.hansson@arm.com // Let the MSHR itself track the snoop and decide whether we want 212111051Sandreas.hansson@arm.com // to go ahead and do the regular cache snoop 212211051Sandreas.hansson@arm.com if (mshr && mshr->handleSnoop(pkt, order++)) { 212311051Sandreas.hansson@arm.com DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)." 212411051Sandreas.hansson@arm.com "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns", 212511051Sandreas.hansson@arm.com mshr->print()); 212611051Sandreas.hansson@arm.com 212711051Sandreas.hansson@arm.com if (mshr->getNumTargets() > numTarget) 212811051Sandreas.hansson@arm.com warn("allocating bonus target for snoop"); //handle later 212911051Sandreas.hansson@arm.com return; 213011051Sandreas.hansson@arm.com } 213111051Sandreas.hansson@arm.com 213211051Sandreas.hansson@arm.com //We also need to check the writeback buffers and handle those 213311375Sandreas.hansson@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(blk_addr, is_secure); 213411375Sandreas.hansson@arm.com if (wb_entry) { 213511051Sandreas.hansson@arm.com DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n", 213611051Sandreas.hansson@arm.com pkt->getAddr(), is_secure ? "s" : "ns"); 213711051Sandreas.hansson@arm.com // Expect to see only Writebacks and/or CleanEvicts here, both of 213811051Sandreas.hansson@arm.com // which should not be generated for uncacheable data. 213911051Sandreas.hansson@arm.com assert(!wb_entry->isUncacheable()); 214011051Sandreas.hansson@arm.com // There should only be a single request responsible for generating 214111051Sandreas.hansson@arm.com // Writebacks/CleanEvicts. 214211051Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 214311051Sandreas.hansson@arm.com PacketPtr wb_pkt = wb_entry->getTarget()->pkt; 214411199Sandreas.hansson@arm.com assert(wb_pkt->isEviction()); 214511051Sandreas.hansson@arm.com 214611199Sandreas.hansson@arm.com if (pkt->isEviction()) { 214711051Sandreas.hansson@arm.com // if the block is found in the write queue, set the BLOCK_CACHED 214811051Sandreas.hansson@arm.com // flag for Writeback/CleanEvict snoop. On return the snoop will 214911051Sandreas.hansson@arm.com // propagate the BLOCK_CACHED flag in Writeback packets and prevent 215011051Sandreas.hansson@arm.com // any CleanEvicts from travelling down the memory hierarchy. 215111051Sandreas.hansson@arm.com pkt->setBlockCached(); 215211744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Squashing %s from lower cache on writequeue " 215311744Snikos.nikoleris@arm.com "hit\n", __func__, pkt->print()); 215411051Sandreas.hansson@arm.com return; 215511051Sandreas.hansson@arm.com } 215611051Sandreas.hansson@arm.com 215711332Sandreas.hansson@arm.com // conceptually writebacks are no different to other blocks in 215811332Sandreas.hansson@arm.com // this cache, so the behaviour is modelled after handleSnoop, 215911332Sandreas.hansson@arm.com // the difference being that instead of querying the block 216011332Sandreas.hansson@arm.com // state to determine if it is dirty and writable, we use the 216111332Sandreas.hansson@arm.com // command and fields of the writeback packet 216211332Sandreas.hansson@arm.com bool respond = wb_pkt->cmd == MemCmd::WritebackDirty && 216311332Sandreas.hansson@arm.com pkt->needsResponse() && pkt->cmd != MemCmd::InvalidateReq; 216411332Sandreas.hansson@arm.com bool have_writable = !wb_pkt->hasSharers(); 216511332Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 216611332Sandreas.hansson@arm.com 216711332Sandreas.hansson@arm.com if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) { 216811332Sandreas.hansson@arm.com assert(!pkt->needsWritable()); 216911332Sandreas.hansson@arm.com pkt->setHasSharers(); 217011332Sandreas.hansson@arm.com wb_pkt->setHasSharers(); 217111332Sandreas.hansson@arm.com } 217211332Sandreas.hansson@arm.com 217311332Sandreas.hansson@arm.com if (respond) { 217411284Sandreas.hansson@arm.com pkt->setCacheResponding(); 217511332Sandreas.hansson@arm.com 217611332Sandreas.hansson@arm.com if (have_writable) { 217711332Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 217811051Sandreas.hansson@arm.com } 217911332Sandreas.hansson@arm.com 218011051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(), 218111051Sandreas.hansson@arm.com false, false); 218211051Sandreas.hansson@arm.com } 218311051Sandreas.hansson@arm.com 218411332Sandreas.hansson@arm.com if (invalidate) { 218511051Sandreas.hansson@arm.com // Invalidation trumps our writeback... discard here 218611051Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 218711375Sandreas.hansson@arm.com markInService(wb_entry); 218811051Sandreas.hansson@arm.com delete wb_pkt; 218911051Sandreas.hansson@arm.com } 219011051Sandreas.hansson@arm.com } 219111051Sandreas.hansson@arm.com 219211051Sandreas.hansson@arm.com // If this was a shared writeback, there may still be 219311051Sandreas.hansson@arm.com // other shared copies above that require invalidation. 219411051Sandreas.hansson@arm.com // We could be more selective and return here if the 219511051Sandreas.hansson@arm.com // request is non-exclusive or if the writeback is 219611051Sandreas.hansson@arm.com // exclusive. 219711127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false); 219811127Sandreas.hansson@arm.com 219911127Sandreas.hansson@arm.com // Override what we did when we first saw the snoop, as we now 220011127Sandreas.hansson@arm.com // also have the cost of the upwards snoops to account for 220111127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay + 220211127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 220311051Sandreas.hansson@arm.com} 220411051Sandreas.hansson@arm.com 220511051Sandreas.hansson@arm.combool 220611051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 220711051Sandreas.hansson@arm.com{ 220811051Sandreas.hansson@arm.com // Express snoop responses from master to slave, e.g., from L1 to L2 220911051Sandreas.hansson@arm.com cache->recvTimingSnoopResp(pkt); 221011051Sandreas.hansson@arm.com return true; 221111051Sandreas.hansson@arm.com} 221211051Sandreas.hansson@arm.com 221311051Sandreas.hansson@arm.comTick 221411051Sandreas.hansson@arm.comCache::recvAtomicSnoop(PacketPtr pkt) 221511051Sandreas.hansson@arm.com{ 221611051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 221711051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 221811051Sandreas.hansson@arm.com 221911130Sali.jafri@arm.com // no need to snoop requests that are not in range. 222011130Sali.jafri@arm.com if (!inRange(pkt->getAddr())) { 222111051Sandreas.hansson@arm.com return 0; 222211051Sandreas.hansson@arm.com } 222311051Sandreas.hansson@arm.com 222411051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 222511127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false); 222611127Sandreas.hansson@arm.com return snoop_delay + lookupLatency * clockPeriod(); 222711051Sandreas.hansson@arm.com} 222811051Sandreas.hansson@arm.com 222911051Sandreas.hansson@arm.com 223011375Sandreas.hansson@arm.comQueueEntry* 223111375Sandreas.hansson@arm.comCache::getNextQueueEntry() 223211051Sandreas.hansson@arm.com{ 223311051Sandreas.hansson@arm.com // Check both MSHR queue and write buffer for potential requests, 223411051Sandreas.hansson@arm.com // note that null does not mean there is no request, it could 223511051Sandreas.hansson@arm.com // simply be that it is not ready 223611375Sandreas.hansson@arm.com MSHR *miss_mshr = mshrQueue.getNext(); 223711375Sandreas.hansson@arm.com WriteQueueEntry *wq_entry = writeBuffer.getNext(); 223811051Sandreas.hansson@arm.com 223911051Sandreas.hansson@arm.com // If we got a write buffer request ready, first priority is a 224011453Sandreas.hansson@arm.com // full write buffer, otherwise we favour the miss requests 224111453Sandreas.hansson@arm.com if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) { 224211051Sandreas.hansson@arm.com // need to search MSHR queue for conflicting earlier miss. 224311051Sandreas.hansson@arm.com MSHR *conflict_mshr = 224411375Sandreas.hansson@arm.com mshrQueue.findPending(wq_entry->blkAddr, 224511375Sandreas.hansson@arm.com wq_entry->isSecure); 224611375Sandreas.hansson@arm.com 224711375Sandreas.hansson@arm.com if (conflict_mshr && conflict_mshr->order < wq_entry->order) { 224811051Sandreas.hansson@arm.com // Service misses in order until conflict is cleared. 224911051Sandreas.hansson@arm.com return conflict_mshr; 225011051Sandreas.hansson@arm.com 225111051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 225211051Sandreas.hansson@arm.com } 225311051Sandreas.hansson@arm.com 225411051Sandreas.hansson@arm.com // No conflicts; issue write 225511375Sandreas.hansson@arm.com return wq_entry; 225611051Sandreas.hansson@arm.com } else if (miss_mshr) { 225711051Sandreas.hansson@arm.com // need to check for conflicting earlier writeback 225811375Sandreas.hansson@arm.com WriteQueueEntry *conflict_mshr = 225911051Sandreas.hansson@arm.com writeBuffer.findPending(miss_mshr->blkAddr, 226011051Sandreas.hansson@arm.com miss_mshr->isSecure); 226111051Sandreas.hansson@arm.com if (conflict_mshr) { 226211051Sandreas.hansson@arm.com // not sure why we don't check order here... it was in the 226311051Sandreas.hansson@arm.com // original code but commented out. 226411051Sandreas.hansson@arm.com 226511051Sandreas.hansson@arm.com // The only way this happens is if we are 226611051Sandreas.hansson@arm.com // doing a write and we didn't have permissions 226711051Sandreas.hansson@arm.com // then subsequently saw a writeback (owned got evicted) 226811051Sandreas.hansson@arm.com // We need to make sure to perform the writeback first 226911051Sandreas.hansson@arm.com // To preserve the dirty data, then we can issue the write 227011051Sandreas.hansson@arm.com 227111375Sandreas.hansson@arm.com // should we return wq_entry here instead? I.e. do we 227211051Sandreas.hansson@arm.com // have to flush writes in order? I don't think so... not 227311051Sandreas.hansson@arm.com // for Alpha anyway. Maybe for x86? 227411051Sandreas.hansson@arm.com return conflict_mshr; 227511051Sandreas.hansson@arm.com 227611051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 227711051Sandreas.hansson@arm.com } 227811051Sandreas.hansson@arm.com 227911051Sandreas.hansson@arm.com // No conflicts; issue read 228011051Sandreas.hansson@arm.com return miss_mshr; 228111051Sandreas.hansson@arm.com } 228211051Sandreas.hansson@arm.com 228311051Sandreas.hansson@arm.com // fall through... no pending requests. Try a prefetch. 228411375Sandreas.hansson@arm.com assert(!miss_mshr && !wq_entry); 228511051Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 228611051Sandreas.hansson@arm.com // If we have a miss queue slot, we can try a prefetch 228711051Sandreas.hansson@arm.com PacketPtr pkt = prefetcher->getPacket(); 228811051Sandreas.hansson@arm.com if (pkt) { 228911051Sandreas.hansson@arm.com Addr pf_addr = blockAlign(pkt->getAddr()); 229011051Sandreas.hansson@arm.com if (!tags->findBlock(pf_addr, pkt->isSecure()) && 229111051Sandreas.hansson@arm.com !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 229211051Sandreas.hansson@arm.com !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 229311051Sandreas.hansson@arm.com // Update statistic on number of prefetches issued 229411051Sandreas.hansson@arm.com // (hwpf_mshr_misses) 229511051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 229611051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 229711051Sandreas.hansson@arm.com 229811051Sandreas.hansson@arm.com // allocate an MSHR and return it, note 229911051Sandreas.hansson@arm.com // that we send the packet straight away, so do not 230011051Sandreas.hansson@arm.com // schedule the send 230111051Sandreas.hansson@arm.com return allocateMissBuffer(pkt, curTick(), false); 230211051Sandreas.hansson@arm.com } else { 230311051Sandreas.hansson@arm.com // free the request and packet 230411051Sandreas.hansson@arm.com delete pkt->req; 230511051Sandreas.hansson@arm.com delete pkt; 230611051Sandreas.hansson@arm.com } 230711051Sandreas.hansson@arm.com } 230811051Sandreas.hansson@arm.com } 230911051Sandreas.hansson@arm.com 231011375Sandreas.hansson@arm.com return nullptr; 231111051Sandreas.hansson@arm.com} 231211051Sandreas.hansson@arm.com 231311051Sandreas.hansson@arm.combool 231411130Sali.jafri@arm.comCache::isCachedAbove(PacketPtr pkt, bool is_timing) const 231511051Sandreas.hansson@arm.com{ 231611051Sandreas.hansson@arm.com if (!forwardSnoops) 231711051Sandreas.hansson@arm.com return false; 231811051Sandreas.hansson@arm.com // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and 231911051Sandreas.hansson@arm.com // Writeback snoops into upper level caches to check for copies of the 232011051Sandreas.hansson@arm.com // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict 232111051Sandreas.hansson@arm.com // packet, the cache can inform the crossbar below of presence or absence 232211051Sandreas.hansson@arm.com // of the block. 232311130Sali.jafri@arm.com if (is_timing) { 232411130Sali.jafri@arm.com Packet snoop_pkt(pkt, true, false); 232511130Sali.jafri@arm.com snoop_pkt.setExpressSnoop(); 232611130Sali.jafri@arm.com // Assert that packet is either Writeback or CleanEvict and not a 232711130Sali.jafri@arm.com // prefetch request because prefetch requests need an MSHR and may 232811130Sali.jafri@arm.com // generate a snoop response. 232911199Sandreas.hansson@arm.com assert(pkt->isEviction()); 233011484Snikos.nikoleris@arm.com snoop_pkt.senderState = nullptr; 233111130Sali.jafri@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 233211130Sali.jafri@arm.com // Writeback/CleanEvict snoops do not generate a snoop response. 233311284Sandreas.hansson@arm.com assert(!(snoop_pkt.cacheResponding())); 233411130Sali.jafri@arm.com return snoop_pkt.isBlockCached(); 233511130Sali.jafri@arm.com } else { 233611130Sali.jafri@arm.com cpuSidePort->sendAtomicSnoop(pkt); 233711130Sali.jafri@arm.com return pkt->isBlockCached(); 233811130Sali.jafri@arm.com } 233911051Sandreas.hansson@arm.com} 234011051Sandreas.hansson@arm.com 234111375Sandreas.hansson@arm.comTick 234211375Sandreas.hansson@arm.comCache::nextQueueReadyTime() const 234311051Sandreas.hansson@arm.com{ 234411375Sandreas.hansson@arm.com Tick nextReady = std::min(mshrQueue.nextReadyTime(), 234511375Sandreas.hansson@arm.com writeBuffer.nextReadyTime()); 234611375Sandreas.hansson@arm.com 234711375Sandreas.hansson@arm.com // Don't signal prefetch ready time if no MSHRs available 234811375Sandreas.hansson@arm.com // Will signal once enoguh MSHRs are deallocated 234911375Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 235011375Sandreas.hansson@arm.com nextReady = std::min(nextReady, 235111375Sandreas.hansson@arm.com prefetcher->nextPrefetchReadyTime()); 235211051Sandreas.hansson@arm.com } 235311051Sandreas.hansson@arm.com 235411375Sandreas.hansson@arm.com return nextReady; 235511375Sandreas.hansson@arm.com} 235611375Sandreas.hansson@arm.com 235711375Sandreas.hansson@arm.combool 235811375Sandreas.hansson@arm.comCache::sendMSHRQueuePacket(MSHR* mshr) 235911375Sandreas.hansson@arm.com{ 236011375Sandreas.hansson@arm.com assert(mshr); 236111375Sandreas.hansson@arm.com 236211051Sandreas.hansson@arm.com // use request from 1st target 236311051Sandreas.hansson@arm.com PacketPtr tgt_pkt = mshr->getTarget()->pkt; 236411375Sandreas.hansson@arm.com 236511744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print()); 236611051Sandreas.hansson@arm.com 236711051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 236811051Sandreas.hansson@arm.com 236911051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) { 237011375Sandreas.hansson@arm.com // we should never have hardware prefetches to allocated 237111375Sandreas.hansson@arm.com // blocks 237211484Snikos.nikoleris@arm.com assert(blk == nullptr); 237311375Sandreas.hansson@arm.com 237411051Sandreas.hansson@arm.com // We need to check the caches above us to verify that 237511051Sandreas.hansson@arm.com // they don't have a copy of this block in the dirty state 237611051Sandreas.hansson@arm.com // at the moment. Without this check we could get a stale 237711051Sandreas.hansson@arm.com // copy from memory that might get used in place of the 237811051Sandreas.hansson@arm.com // dirty one. 237911051Sandreas.hansson@arm.com Packet snoop_pkt(tgt_pkt, true, false); 238011051Sandreas.hansson@arm.com snoop_pkt.setExpressSnoop(); 238111275Sandreas.hansson@arm.com // We are sending this packet upwards, but if it hits we will 238211275Sandreas.hansson@arm.com // get a snoop response that we end up treating just like a 238311275Sandreas.hansson@arm.com // normal response, hence it needs the MSHR as its sender 238411275Sandreas.hansson@arm.com // state 238511051Sandreas.hansson@arm.com snoop_pkt.senderState = mshr; 238611051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 238711051Sandreas.hansson@arm.com 238811051Sandreas.hansson@arm.com // Check to see if the prefetch was squashed by an upper cache (to 238911051Sandreas.hansson@arm.com // prevent us from grabbing the line) or if a Check to see if a 239011051Sandreas.hansson@arm.com // writeback arrived between the time the prefetch was placed in 239111051Sandreas.hansson@arm.com // the MSHRs and when it was selected to be sent or if the 239211051Sandreas.hansson@arm.com // prefetch was squashed by an upper cache. 239311051Sandreas.hansson@arm.com 239411284Sandreas.hansson@arm.com // It is important to check cacheResponding before 239511284Sandreas.hansson@arm.com // prefetchSquashed. If another cache has committed to 239611284Sandreas.hansson@arm.com // responding, it will be sending a dirty response which will 239711284Sandreas.hansson@arm.com // arrive at the MSHR allocated for this request. Checking the 239811284Sandreas.hansson@arm.com // prefetchSquash first may result in the MSHR being 239911284Sandreas.hansson@arm.com // prematurely deallocated. 240011284Sandreas.hansson@arm.com if (snoop_pkt.cacheResponding()) { 240111276Sandreas.hansson@arm.com auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req); 240211276Sandreas.hansson@arm.com assert(r.second); 240311284Sandreas.hansson@arm.com 240411284Sandreas.hansson@arm.com // if we are getting a snoop response with no sharers it 240511284Sandreas.hansson@arm.com // will be allocated as Modified 240611284Sandreas.hansson@arm.com bool pending_modified_resp = !snoop_pkt.hasSharers(); 240711284Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 240811284Sandreas.hansson@arm.com 240911051Sandreas.hansson@arm.com DPRINTF(Cache, "Upward snoop of prefetch for addr" 241011051Sandreas.hansson@arm.com " %#x (%s) hit\n", 241111051Sandreas.hansson@arm.com tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns"); 241211375Sandreas.hansson@arm.com return false; 241311051Sandreas.hansson@arm.com } 241411051Sandreas.hansson@arm.com 241511375Sandreas.hansson@arm.com if (snoop_pkt.isBlockCached()) { 241611051Sandreas.hansson@arm.com DPRINTF(Cache, "Block present, prefetch squashed by cache. " 241711051Sandreas.hansson@arm.com "Deallocating mshr target %#x.\n", 241811051Sandreas.hansson@arm.com mshr->blkAddr); 241911375Sandreas.hansson@arm.com 242011051Sandreas.hansson@arm.com // Deallocate the mshr target 242111375Sandreas.hansson@arm.com if (mshrQueue.forceDeallocateTarget(mshr)) { 242211277Sandreas.hansson@arm.com // Clear block if this deallocation resulted freed an 242311277Sandreas.hansson@arm.com // mshr when all had previously been utilized 242411375Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 242511051Sandreas.hansson@arm.com } 242611375Sandreas.hansson@arm.com return false; 242711051Sandreas.hansson@arm.com } 242811051Sandreas.hansson@arm.com } 242911051Sandreas.hansson@arm.com 243011375Sandreas.hansson@arm.com // either a prefetch that is not present upstream, or a normal 243111375Sandreas.hansson@arm.com // MSHR request, proceed to get the packet to send downstream 243211452Sandreas.hansson@arm.com PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable()); 243311375Sandreas.hansson@arm.com 243411484Snikos.nikoleris@arm.com mshr->isForward = (pkt == nullptr); 243511375Sandreas.hansson@arm.com 243611375Sandreas.hansson@arm.com if (mshr->isForward) { 243711375Sandreas.hansson@arm.com // not a cache block request, but a response is expected 243811375Sandreas.hansson@arm.com // make copy of current packet to forward, keep current 243911375Sandreas.hansson@arm.com // copy for response handling 244011375Sandreas.hansson@arm.com pkt = new Packet(tgt_pkt, false, true); 244111375Sandreas.hansson@arm.com assert(!pkt->isWrite()); 244211375Sandreas.hansson@arm.com } 244311375Sandreas.hansson@arm.com 244411375Sandreas.hansson@arm.com // play it safe and append (rather than set) the sender state, 244511375Sandreas.hansson@arm.com // as forwarded packets may already have existing state 244611375Sandreas.hansson@arm.com pkt->pushSenderState(mshr); 244711375Sandreas.hansson@arm.com 244811375Sandreas.hansson@arm.com if (!memSidePort->sendTimingReq(pkt)) { 244911375Sandreas.hansson@arm.com // we are awaiting a retry, but we 245011375Sandreas.hansson@arm.com // delete the packet and will be creating a new packet 245111375Sandreas.hansson@arm.com // when we get the opportunity 245211375Sandreas.hansson@arm.com delete pkt; 245311375Sandreas.hansson@arm.com 245411375Sandreas.hansson@arm.com // note that we have now masked any requestBus and 245511375Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 245611375Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 245711375Sandreas.hansson@arm.com // care about this packet and might override it before 245811375Sandreas.hansson@arm.com // it gets retried 245911375Sandreas.hansson@arm.com return true; 246011375Sandreas.hansson@arm.com } else { 246111375Sandreas.hansson@arm.com // As part of the call to sendTimingReq the packet is 246211375Sandreas.hansson@arm.com // forwarded to all neighbouring caches (and any caches 246311375Sandreas.hansson@arm.com // above them) as a snoop. Thus at this point we know if 246411375Sandreas.hansson@arm.com // any of the neighbouring caches are responding, and if 246511375Sandreas.hansson@arm.com // so, we know it is dirty, and we can determine if it is 246611375Sandreas.hansson@arm.com // being passed as Modified, making our MSHR the ordering 246711375Sandreas.hansson@arm.com // point 246811375Sandreas.hansson@arm.com bool pending_modified_resp = !pkt->hasSharers() && 246911375Sandreas.hansson@arm.com pkt->cacheResponding(); 247011375Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 247111375Sandreas.hansson@arm.com return false; 247211375Sandreas.hansson@arm.com } 247311375Sandreas.hansson@arm.com} 247411375Sandreas.hansson@arm.com 247511375Sandreas.hansson@arm.combool 247611375Sandreas.hansson@arm.comCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry) 247711375Sandreas.hansson@arm.com{ 247811375Sandreas.hansson@arm.com assert(wq_entry); 247911375Sandreas.hansson@arm.com 248011375Sandreas.hansson@arm.com // always a single target for write queue entries 248111375Sandreas.hansson@arm.com PacketPtr tgt_pkt = wq_entry->getTarget()->pkt; 248211375Sandreas.hansson@arm.com 248311744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print()); 248411375Sandreas.hansson@arm.com 248511453Sandreas.hansson@arm.com // forward as is, both for evictions and uncacheable writes 248611453Sandreas.hansson@arm.com if (!memSidePort->sendTimingReq(tgt_pkt)) { 248711375Sandreas.hansson@arm.com // note that we have now masked any requestBus and 248811375Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 248911375Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 249011375Sandreas.hansson@arm.com // care about this packet and might override it before 249111375Sandreas.hansson@arm.com // it gets retried 249211375Sandreas.hansson@arm.com return true; 249311375Sandreas.hansson@arm.com } else { 249411375Sandreas.hansson@arm.com markInService(wq_entry); 249511375Sandreas.hansson@arm.com return false; 249611051Sandreas.hansson@arm.com } 249711051Sandreas.hansson@arm.com} 249811051Sandreas.hansson@arm.com 249911051Sandreas.hansson@arm.comvoid 250011051Sandreas.hansson@arm.comCache::serialize(CheckpointOut &cp) const 250111051Sandreas.hansson@arm.com{ 250211051Sandreas.hansson@arm.com bool dirty(isDirty()); 250311051Sandreas.hansson@arm.com 250411051Sandreas.hansson@arm.com if (dirty) { 250511051Sandreas.hansson@arm.com warn("*** The cache still contains dirty data. ***\n"); 250611051Sandreas.hansson@arm.com warn(" Make sure to drain the system using the correct flags.\n"); 250711483Snikos.nikoleris@arm.com warn(" This checkpoint will not restore correctly and dirty data " 250811483Snikos.nikoleris@arm.com " in the cache will be lost!\n"); 250911051Sandreas.hansson@arm.com } 251011051Sandreas.hansson@arm.com 251111051Sandreas.hansson@arm.com // Since we don't checkpoint the data in the cache, any dirty data 251211051Sandreas.hansson@arm.com // will be lost when restoring from a checkpoint of a system that 251311051Sandreas.hansson@arm.com // wasn't drained properly. Flag the checkpoint as invalid if the 251411051Sandreas.hansson@arm.com // cache contains dirty data. 251511051Sandreas.hansson@arm.com bool bad_checkpoint(dirty); 251611051Sandreas.hansson@arm.com SERIALIZE_SCALAR(bad_checkpoint); 251711051Sandreas.hansson@arm.com} 251811051Sandreas.hansson@arm.com 251911051Sandreas.hansson@arm.comvoid 252011051Sandreas.hansson@arm.comCache::unserialize(CheckpointIn &cp) 252111051Sandreas.hansson@arm.com{ 252211051Sandreas.hansson@arm.com bool bad_checkpoint; 252311051Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(bad_checkpoint); 252411051Sandreas.hansson@arm.com if (bad_checkpoint) { 252511051Sandreas.hansson@arm.com fatal("Restoring from checkpoints with dirty caches is not supported " 252611051Sandreas.hansson@arm.com "in the classic memory system. Please remove any caches or " 252711051Sandreas.hansson@arm.com " drain them properly before taking checkpoints.\n"); 252811051Sandreas.hansson@arm.com } 252911051Sandreas.hansson@arm.com} 253011051Sandreas.hansson@arm.com 253111051Sandreas.hansson@arm.com/////////////// 253211051Sandreas.hansson@arm.com// 253311051Sandreas.hansson@arm.com// CpuSidePort 253411051Sandreas.hansson@arm.com// 253511051Sandreas.hansson@arm.com/////////////// 253611051Sandreas.hansson@arm.com 253711051Sandreas.hansson@arm.comAddrRangeList 253811051Sandreas.hansson@arm.comCache::CpuSidePort::getAddrRanges() const 253911051Sandreas.hansson@arm.com{ 254011051Sandreas.hansson@arm.com return cache->getAddrRanges(); 254111051Sandreas.hansson@arm.com} 254211051Sandreas.hansson@arm.com 254311051Sandreas.hansson@arm.combool 254411051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingReq(PacketPtr pkt) 254511051Sandreas.hansson@arm.com{ 254611051Sandreas.hansson@arm.com assert(!cache->system->bypassCaches()); 254711051Sandreas.hansson@arm.com 254811051Sandreas.hansson@arm.com bool success = false; 254911051Sandreas.hansson@arm.com 255011334Sandreas.hansson@arm.com // always let express snoop packets through if even if blocked 255111334Sandreas.hansson@arm.com if (pkt->isExpressSnoop()) { 255211051Sandreas.hansson@arm.com // do not change the current retry state 255311051Sandreas.hansson@arm.com bool M5_VAR_USED bypass_success = cache->recvTimingReq(pkt); 255411051Sandreas.hansson@arm.com assert(bypass_success); 255511051Sandreas.hansson@arm.com return true; 255611051Sandreas.hansson@arm.com } else if (blocked || mustSendRetry) { 255711051Sandreas.hansson@arm.com // either already committed to send a retry, or blocked 255811051Sandreas.hansson@arm.com success = false; 255911051Sandreas.hansson@arm.com } else { 256011051Sandreas.hansson@arm.com // pass it on to the cache, and let the cache decide if we 256111051Sandreas.hansson@arm.com // have to retry or not 256211051Sandreas.hansson@arm.com success = cache->recvTimingReq(pkt); 256311051Sandreas.hansson@arm.com } 256411051Sandreas.hansson@arm.com 256511051Sandreas.hansson@arm.com // remember if we have to retry 256611051Sandreas.hansson@arm.com mustSendRetry = !success; 256711051Sandreas.hansson@arm.com return success; 256811051Sandreas.hansson@arm.com} 256911051Sandreas.hansson@arm.com 257011051Sandreas.hansson@arm.comTick 257111051Sandreas.hansson@arm.comCache::CpuSidePort::recvAtomic(PacketPtr pkt) 257211051Sandreas.hansson@arm.com{ 257311051Sandreas.hansson@arm.com return cache->recvAtomic(pkt); 257411051Sandreas.hansson@arm.com} 257511051Sandreas.hansson@arm.com 257611051Sandreas.hansson@arm.comvoid 257711051Sandreas.hansson@arm.comCache::CpuSidePort::recvFunctional(PacketPtr pkt) 257811051Sandreas.hansson@arm.com{ 257911051Sandreas.hansson@arm.com // functional request 258011051Sandreas.hansson@arm.com cache->functionalAccess(pkt, true); 258111051Sandreas.hansson@arm.com} 258211051Sandreas.hansson@arm.com 258311051Sandreas.hansson@arm.comCache:: 258411051Sandreas.hansson@arm.comCpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache, 258511051Sandreas.hansson@arm.com const std::string &_label) 258611051Sandreas.hansson@arm.com : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache) 258711051Sandreas.hansson@arm.com{ 258811051Sandreas.hansson@arm.com} 258911051Sandreas.hansson@arm.com 259011053Sandreas.hansson@arm.comCache* 259111053Sandreas.hansson@arm.comCacheParams::create() 259211053Sandreas.hansson@arm.com{ 259311053Sandreas.hansson@arm.com assert(tags); 259411053Sandreas.hansson@arm.com 259511053Sandreas.hansson@arm.com return new Cache(this); 259611053Sandreas.hansson@arm.com} 259711051Sandreas.hansson@arm.com/////////////// 259811051Sandreas.hansson@arm.com// 259911051Sandreas.hansson@arm.com// MemSidePort 260011051Sandreas.hansson@arm.com// 260111051Sandreas.hansson@arm.com/////////////// 260211051Sandreas.hansson@arm.com 260311051Sandreas.hansson@arm.combool 260411051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingResp(PacketPtr pkt) 260511051Sandreas.hansson@arm.com{ 260611051Sandreas.hansson@arm.com cache->recvTimingResp(pkt); 260711051Sandreas.hansson@arm.com return true; 260811051Sandreas.hansson@arm.com} 260911051Sandreas.hansson@arm.com 261011051Sandreas.hansson@arm.com// Express snooping requests to memside port 261111051Sandreas.hansson@arm.comvoid 261211051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 261311051Sandreas.hansson@arm.com{ 261411051Sandreas.hansson@arm.com // handle snooping requests 261511051Sandreas.hansson@arm.com cache->recvTimingSnoopReq(pkt); 261611051Sandreas.hansson@arm.com} 261711051Sandreas.hansson@arm.com 261811051Sandreas.hansson@arm.comTick 261911051Sandreas.hansson@arm.comCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 262011051Sandreas.hansson@arm.com{ 262111051Sandreas.hansson@arm.com return cache->recvAtomicSnoop(pkt); 262211051Sandreas.hansson@arm.com} 262311051Sandreas.hansson@arm.com 262411051Sandreas.hansson@arm.comvoid 262511051Sandreas.hansson@arm.comCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 262611051Sandreas.hansson@arm.com{ 262711051Sandreas.hansson@arm.com // functional snoop (note that in contrast to atomic we don't have 262811051Sandreas.hansson@arm.com // a specific functionalSnoop method, as they have the same 262911051Sandreas.hansson@arm.com // behaviour regardless) 263011051Sandreas.hansson@arm.com cache->functionalAccess(pkt, false); 263111051Sandreas.hansson@arm.com} 263211051Sandreas.hansson@arm.com 263311051Sandreas.hansson@arm.comvoid 263411051Sandreas.hansson@arm.comCache::CacheReqPacketQueue::sendDeferredPacket() 263511051Sandreas.hansson@arm.com{ 263611051Sandreas.hansson@arm.com // sanity check 263711051Sandreas.hansson@arm.com assert(!waitingOnRetry); 263811051Sandreas.hansson@arm.com 263911051Sandreas.hansson@arm.com // there should never be any deferred request packets in the 264011051Sandreas.hansson@arm.com // queue, instead we resly on the cache to provide the packets 264111051Sandreas.hansson@arm.com // from the MSHR queue or write queue 264211051Sandreas.hansson@arm.com assert(deferredPacketReadyTime() == MaxTick); 264311051Sandreas.hansson@arm.com 264411051Sandreas.hansson@arm.com // check for request packets (requests & writebacks) 264511375Sandreas.hansson@arm.com QueueEntry* entry = cache.getNextQueueEntry(); 264611375Sandreas.hansson@arm.com 264711375Sandreas.hansson@arm.com if (!entry) { 264811051Sandreas.hansson@arm.com // can happen if e.g. we attempt a writeback and fail, but 264911051Sandreas.hansson@arm.com // before the retry, the writeback is eliminated because 265011051Sandreas.hansson@arm.com // we snoop another cache's ReadEx. 265111051Sandreas.hansson@arm.com } else { 265211051Sandreas.hansson@arm.com // let our snoop responses go first if there are responses to 265311375Sandreas.hansson@arm.com // the same addresses 265411375Sandreas.hansson@arm.com if (checkConflictingSnoop(entry->blkAddr)) { 265511051Sandreas.hansson@arm.com return; 265611051Sandreas.hansson@arm.com } 265711375Sandreas.hansson@arm.com waitingOnRetry = entry->sendPacket(cache); 265811051Sandreas.hansson@arm.com } 265911051Sandreas.hansson@arm.com 266011051Sandreas.hansson@arm.com // if we succeeded and are not waiting for a retry, schedule the 266111375Sandreas.hansson@arm.com // next send considering when the next queue is ready, note that 266211051Sandreas.hansson@arm.com // snoop responses have their own packet queue and thus schedule 266311051Sandreas.hansson@arm.com // their own events 266411051Sandreas.hansson@arm.com if (!waitingOnRetry) { 266511375Sandreas.hansson@arm.com schedSendEvent(cache.nextQueueReadyTime()); 266611051Sandreas.hansson@arm.com } 266711051Sandreas.hansson@arm.com} 266811051Sandreas.hansson@arm.com 266911051Sandreas.hansson@arm.comCache:: 267011051Sandreas.hansson@arm.comMemSidePort::MemSidePort(const std::string &_name, Cache *_cache, 267111051Sandreas.hansson@arm.com const std::string &_label) 267211051Sandreas.hansson@arm.com : BaseCache::CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 267311051Sandreas.hansson@arm.com _reqQueue(*_cache, *this, _snoopRespQueue, _label), 267411051Sandreas.hansson@arm.com _snoopRespQueue(*_cache, *this, _label), cache(_cache) 267511051Sandreas.hansson@arm.com{ 267611051Sandreas.hansson@arm.com} 2677