cache.cc revision 11375
12810Srdreslin@umich.edu/* 211375Sandreas.hansson@arm.com * Copyright (c) 2010-2016 ARM Limited 311051Sandreas.hansson@arm.com * All rights reserved. 411051Sandreas.hansson@arm.com * 511051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911051Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311051Sandreas.hansson@arm.com * 1411051Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511051Sandreas.hansson@arm.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 162810Srdreslin@umich.edu * All rights reserved. 172810Srdreslin@umich.edu * 182810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 192810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 202810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 212810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 222810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 232810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 242810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 252810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 262810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 272810Srdreslin@umich.edu * this software without specific prior written permission. 282810Srdreslin@umich.edu * 292810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810Srdreslin@umich.edu * 412810Srdreslin@umich.edu * Authors: Erik Hallnor 4211051Sandreas.hansson@arm.com * Dave Greene 4311051Sandreas.hansson@arm.com * Nathan Binkert 442810Srdreslin@umich.edu * Steve Reinhardt 4511051Sandreas.hansson@arm.com * Ron Dreslinski 4611051Sandreas.hansson@arm.com * Andreas Sandberg 472810Srdreslin@umich.edu */ 482810Srdreslin@umich.edu 492810Srdreslin@umich.edu/** 502810Srdreslin@umich.edu * @file 5111051Sandreas.hansson@arm.com * Cache definitions. 522810Srdreslin@umich.edu */ 532810Srdreslin@umich.edu 5411051Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 552810Srdreslin@umich.edu 5611051Sandreas.hansson@arm.com#include "base/misc.hh" 5711051Sandreas.hansson@arm.com#include "base/types.hh" 5811051Sandreas.hansson@arm.com#include "debug/Cache.hh" 5911051Sandreas.hansson@arm.com#include "debug/CachePort.hh" 6011051Sandreas.hansson@arm.com#include "debug/CacheTags.hh" 6111288Ssteve.reinhardt@amd.com#include "debug/CacheVerbose.hh" 6211051Sandreas.hansson@arm.com#include "mem/cache/blk.hh" 6311051Sandreas.hansson@arm.com#include "mem/cache/mshr.hh" 6411051Sandreas.hansson@arm.com#include "mem/cache/prefetch/base.hh" 6511051Sandreas.hansson@arm.com#include "sim/sim_exit.hh" 6611051Sandreas.hansson@arm.com 6711053Sandreas.hansson@arm.comCache::Cache(const CacheParams *p) 6811053Sandreas.hansson@arm.com : BaseCache(p, p->system->cacheLineSize()), 6911051Sandreas.hansson@arm.com tags(p->tags), 7011051Sandreas.hansson@arm.com prefetcher(p->prefetcher), 7111051Sandreas.hansson@arm.com doFastWrites(true), 7211197Sandreas.hansson@arm.com prefetchOnAccess(p->prefetch_on_access), 7311197Sandreas.hansson@arm.com clusivity(p->clusivity), 7411199Sandreas.hansson@arm.com writebackClean(p->writeback_clean), 7511197Sandreas.hansson@arm.com tempBlockWriteback(nullptr), 7611197Sandreas.hansson@arm.com writebackTempBlockAtomicEvent(this, false, 7711197Sandreas.hansson@arm.com EventBase::Delayed_Writeback_Pri) 7811051Sandreas.hansson@arm.com{ 7911051Sandreas.hansson@arm.com tempBlock = new CacheBlk(); 8011051Sandreas.hansson@arm.com tempBlock->data = new uint8_t[blkSize]; 8111051Sandreas.hansson@arm.com 8211051Sandreas.hansson@arm.com cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this, 8311051Sandreas.hansson@arm.com "CpuSidePort"); 8411051Sandreas.hansson@arm.com memSidePort = new MemSidePort(p->name + ".mem_side", this, 8511051Sandreas.hansson@arm.com "MemSidePort"); 8611051Sandreas.hansson@arm.com 8711051Sandreas.hansson@arm.com tags->setCache(this); 8811051Sandreas.hansson@arm.com if (prefetcher) 8911051Sandreas.hansson@arm.com prefetcher->setCache(this); 9011051Sandreas.hansson@arm.com} 9111051Sandreas.hansson@arm.com 9211051Sandreas.hansson@arm.comCache::~Cache() 9311051Sandreas.hansson@arm.com{ 9411051Sandreas.hansson@arm.com delete [] tempBlock->data; 9511051Sandreas.hansson@arm.com delete tempBlock; 9611051Sandreas.hansson@arm.com 9711051Sandreas.hansson@arm.com delete cpuSidePort; 9811051Sandreas.hansson@arm.com delete memSidePort; 9911051Sandreas.hansson@arm.com} 10011051Sandreas.hansson@arm.com 10111051Sandreas.hansson@arm.comvoid 10211051Sandreas.hansson@arm.comCache::regStats() 10311051Sandreas.hansson@arm.com{ 10411051Sandreas.hansson@arm.com BaseCache::regStats(); 10511051Sandreas.hansson@arm.com} 10611051Sandreas.hansson@arm.com 10711051Sandreas.hansson@arm.comvoid 10811051Sandreas.hansson@arm.comCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 10911051Sandreas.hansson@arm.com{ 11011051Sandreas.hansson@arm.com assert(pkt->isRequest()); 11111051Sandreas.hansson@arm.com 11211051Sandreas.hansson@arm.com uint64_t overwrite_val; 11311051Sandreas.hansson@arm.com bool overwrite_mem; 11411051Sandreas.hansson@arm.com uint64_t condition_val64; 11511051Sandreas.hansson@arm.com uint32_t condition_val32; 11611051Sandreas.hansson@arm.com 11711051Sandreas.hansson@arm.com int offset = tags->extractBlkOffset(pkt->getAddr()); 11811051Sandreas.hansson@arm.com uint8_t *blk_data = blk->data + offset; 11911051Sandreas.hansson@arm.com 12011051Sandreas.hansson@arm.com assert(sizeof(uint64_t) >= pkt->getSize()); 12111051Sandreas.hansson@arm.com 12211051Sandreas.hansson@arm.com overwrite_mem = true; 12311051Sandreas.hansson@arm.com // keep a copy of our possible write value, and copy what is at the 12411051Sandreas.hansson@arm.com // memory address into the packet 12511051Sandreas.hansson@arm.com pkt->writeData((uint8_t *)&overwrite_val); 12611051Sandreas.hansson@arm.com pkt->setData(blk_data); 12711051Sandreas.hansson@arm.com 12811051Sandreas.hansson@arm.com if (pkt->req->isCondSwap()) { 12911051Sandreas.hansson@arm.com if (pkt->getSize() == sizeof(uint64_t)) { 13011051Sandreas.hansson@arm.com condition_val64 = pkt->req->getExtraData(); 13111051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val64, blk_data, 13211051Sandreas.hansson@arm.com sizeof(uint64_t)); 13311051Sandreas.hansson@arm.com } else if (pkt->getSize() == sizeof(uint32_t)) { 13411051Sandreas.hansson@arm.com condition_val32 = (uint32_t)pkt->req->getExtraData(); 13511051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val32, blk_data, 13611051Sandreas.hansson@arm.com sizeof(uint32_t)); 13711051Sandreas.hansson@arm.com } else 13811051Sandreas.hansson@arm.com panic("Invalid size for conditional read/write\n"); 13911051Sandreas.hansson@arm.com } 14011051Sandreas.hansson@arm.com 14111051Sandreas.hansson@arm.com if (overwrite_mem) { 14211051Sandreas.hansson@arm.com std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 14311051Sandreas.hansson@arm.com blk->status |= BlkDirty; 14411051Sandreas.hansson@arm.com } 14511051Sandreas.hansson@arm.com} 14611051Sandreas.hansson@arm.com 14711051Sandreas.hansson@arm.com 14811051Sandreas.hansson@arm.comvoid 14911051Sandreas.hansson@arm.comCache::satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk, 15011051Sandreas.hansson@arm.com bool deferred_response, bool pending_downgrade) 15111051Sandreas.hansson@arm.com{ 15211051Sandreas.hansson@arm.com assert(pkt->isRequest()); 15311051Sandreas.hansson@arm.com 15411051Sandreas.hansson@arm.com assert(blk && blk->isValid()); 15511051Sandreas.hansson@arm.com // Occasionally this is not true... if we are a lower-level cache 15611051Sandreas.hansson@arm.com // satisfying a string of Read and ReadEx requests from 15711051Sandreas.hansson@arm.com // upper-level caches, a Read will mark the block as shared but we 15811051Sandreas.hansson@arm.com // can satisfy a following ReadEx anyway since we can rely on the 15911051Sandreas.hansson@arm.com // Read requester(s) to have buffered the ReadEx snoop and to 16011051Sandreas.hansson@arm.com // invalidate their blocks after receiving them. 16111284Sandreas.hansson@arm.com // assert(!pkt->needsWritable() || blk->isWritable()); 16211051Sandreas.hansson@arm.com assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 16311051Sandreas.hansson@arm.com 16411051Sandreas.hansson@arm.com // Check RMW operations first since both isRead() and 16511051Sandreas.hansson@arm.com // isWrite() will be true for them 16611051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::SwapReq) { 16711051Sandreas.hansson@arm.com cmpAndSwap(blk, pkt); 16811051Sandreas.hansson@arm.com } else if (pkt->isWrite()) { 16911284Sandreas.hansson@arm.com // we have the block in a writable state and can go ahead, 17011284Sandreas.hansson@arm.com // note that the line may be also be considered writable in 17111284Sandreas.hansson@arm.com // downstream caches along the path to memory, but always 17211284Sandreas.hansson@arm.com // Exclusive, and never Modified 17311051Sandreas.hansson@arm.com assert(blk->isWritable()); 17411284Sandreas.hansson@arm.com // Write or WriteLine at the first cache with block in writable state 17511051Sandreas.hansson@arm.com if (blk->checkWrite(pkt)) { 17611051Sandreas.hansson@arm.com pkt->writeDataToBlock(blk->data, blkSize); 17711051Sandreas.hansson@arm.com } 17811284Sandreas.hansson@arm.com // Always mark the line as dirty (and thus transition to the 17911284Sandreas.hansson@arm.com // Modified state) even if we are a failed StoreCond so we 18011284Sandreas.hansson@arm.com // supply data to any snoops that have appended themselves to 18111284Sandreas.hansson@arm.com // this cache before knowing the store will fail. 18211051Sandreas.hansson@arm.com blk->status |= BlkDirty; 18311288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d (write)\n", 18411288Ssteve.reinhardt@amd.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 18511051Sandreas.hansson@arm.com } else if (pkt->isRead()) { 18611051Sandreas.hansson@arm.com if (pkt->isLLSC()) { 18711051Sandreas.hansson@arm.com blk->trackLoadLocked(pkt); 18811051Sandreas.hansson@arm.com } 18911286Sandreas.hansson@arm.com 19011286Sandreas.hansson@arm.com // all read responses have a data payload 19111286Sandreas.hansson@arm.com assert(pkt->hasRespData()); 19211051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 19311286Sandreas.hansson@arm.com 19411051Sandreas.hansson@arm.com // determine if this read is from a (coherent) cache, or not 19511051Sandreas.hansson@arm.com // by looking at the command type; we could potentially add a 19611051Sandreas.hansson@arm.com // packet attribute such as 'FromCache' to make this check a 19711051Sandreas.hansson@arm.com // bit cleaner 19811051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadExReq || 19911051Sandreas.hansson@arm.com pkt->cmd == MemCmd::ReadSharedReq || 20011051Sandreas.hansson@arm.com pkt->cmd == MemCmd::ReadCleanReq || 20111051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq) { 20211051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 20311051Sandreas.hansson@arm.com // special handling for coherent block requests from 20411051Sandreas.hansson@arm.com // upper-level caches 20511284Sandreas.hansson@arm.com if (pkt->needsWritable()) { 20611051Sandreas.hansson@arm.com // sanity check 20711051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::ReadExReq || 20811051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq); 20911051Sandreas.hansson@arm.com 21011051Sandreas.hansson@arm.com // if we have a dirty copy, make sure the recipient 21111284Sandreas.hansson@arm.com // keeps it marked dirty (in the modified state) 21211051Sandreas.hansson@arm.com if (blk->isDirty()) { 21311284Sandreas.hansson@arm.com pkt->setCacheResponding(); 21411051Sandreas.hansson@arm.com } 21511197Sandreas.hansson@arm.com // on ReadExReq we give up our copy unconditionally, 21611197Sandreas.hansson@arm.com // even if this cache is mostly inclusive, we may want 21711197Sandreas.hansson@arm.com // to revisit this 21811197Sandreas.hansson@arm.com invalidateBlock(blk); 21911051Sandreas.hansson@arm.com } else if (blk->isWritable() && !pending_downgrade && 22011284Sandreas.hansson@arm.com !pkt->hasSharers() && 22111051Sandreas.hansson@arm.com pkt->cmd != MemCmd::ReadCleanReq) { 22211284Sandreas.hansson@arm.com // we can give the requester a writable copy on a read 22311284Sandreas.hansson@arm.com // request if: 22411284Sandreas.hansson@arm.com // - we have a writable copy at this level (& below) 22511051Sandreas.hansson@arm.com // - we don't have a pending snoop from below 22611051Sandreas.hansson@arm.com // signaling another read request 22711051Sandreas.hansson@arm.com // - no other cache above has a copy (otherwise it 22811284Sandreas.hansson@arm.com // would have set hasSharers flag when 22911284Sandreas.hansson@arm.com // snooping the packet) 23011284Sandreas.hansson@arm.com // - the read has explicitly asked for a clean 23111284Sandreas.hansson@arm.com // copy of the line 23211051Sandreas.hansson@arm.com if (blk->isDirty()) { 23311051Sandreas.hansson@arm.com // special considerations if we're owner: 23411051Sandreas.hansson@arm.com if (!deferred_response) { 23511284Sandreas.hansson@arm.com // respond with the line in Modified state 23611284Sandreas.hansson@arm.com // (cacheResponding set, hasSharers not set) 23711284Sandreas.hansson@arm.com pkt->setCacheResponding(); 23811197Sandreas.hansson@arm.com 23911284Sandreas.hansson@arm.com if (clusivity == Enums::mostly_excl) { 24011284Sandreas.hansson@arm.com // if this cache is mostly exclusive with 24111284Sandreas.hansson@arm.com // respect to the cache above, drop the 24211284Sandreas.hansson@arm.com // block, no need to first unset the dirty 24311284Sandreas.hansson@arm.com // bit 24411284Sandreas.hansson@arm.com invalidateBlock(blk); 24511284Sandreas.hansson@arm.com } else { 24611284Sandreas.hansson@arm.com // if this cache is mostly inclusive, we 24711284Sandreas.hansson@arm.com // keep the block in the Exclusive state, 24811284Sandreas.hansson@arm.com // and pass it upwards as Modified 24911284Sandreas.hansson@arm.com // (writable and dirty), hence we have 25011284Sandreas.hansson@arm.com // multiple caches, all on the same path 25111284Sandreas.hansson@arm.com // towards memory, all considering the 25211284Sandreas.hansson@arm.com // same block writable, but only one 25311284Sandreas.hansson@arm.com // considering it Modified 25411197Sandreas.hansson@arm.com 25511284Sandreas.hansson@arm.com // we get away with multiple caches (on 25611284Sandreas.hansson@arm.com // the same path to memory) considering 25711284Sandreas.hansson@arm.com // the block writeable as we always enter 25811284Sandreas.hansson@arm.com // the cache hierarchy through a cache, 25911284Sandreas.hansson@arm.com // and first snoop upwards in all other 26011284Sandreas.hansson@arm.com // branches 26111284Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 26211197Sandreas.hansson@arm.com } 26311051Sandreas.hansson@arm.com } else { 26411051Sandreas.hansson@arm.com // if we're responding after our own miss, 26511051Sandreas.hansson@arm.com // there's a window where the recipient didn't 26611051Sandreas.hansson@arm.com // know it was getting ownership and may not 26711051Sandreas.hansson@arm.com // have responded to snoops correctly, so we 26811284Sandreas.hansson@arm.com // have to respond with a shared line 26911284Sandreas.hansson@arm.com pkt->setHasSharers(); 27011051Sandreas.hansson@arm.com } 27111051Sandreas.hansson@arm.com } 27211051Sandreas.hansson@arm.com } else { 27311051Sandreas.hansson@arm.com // otherwise only respond with a shared copy 27411284Sandreas.hansson@arm.com pkt->setHasSharers(); 27511051Sandreas.hansson@arm.com } 27611051Sandreas.hansson@arm.com } 27711051Sandreas.hansson@arm.com } else { 27811284Sandreas.hansson@arm.com // Upgrade or Invalidate 27911051Sandreas.hansson@arm.com assert(pkt->isUpgrade() || pkt->isInvalidate()); 28011197Sandreas.hansson@arm.com 28111197Sandreas.hansson@arm.com // for invalidations we could be looking at the temp block 28211197Sandreas.hansson@arm.com // (for upgrades we always allocate) 28311197Sandreas.hansson@arm.com invalidateBlock(blk); 28411288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d (invalidation)\n", 28511051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 28611051Sandreas.hansson@arm.com } 28711051Sandreas.hansson@arm.com} 28811051Sandreas.hansson@arm.com 28911051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 29011051Sandreas.hansson@arm.com// 29111051Sandreas.hansson@arm.com// Access path: requests coming in from the CPU side 29211051Sandreas.hansson@arm.com// 29311051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 29411051Sandreas.hansson@arm.com 29511051Sandreas.hansson@arm.combool 29611051Sandreas.hansson@arm.comCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 29711051Sandreas.hansson@arm.com PacketList &writebacks) 29811051Sandreas.hansson@arm.com{ 29911051Sandreas.hansson@arm.com // sanity check 30011051Sandreas.hansson@arm.com assert(pkt->isRequest()); 30111051Sandreas.hansson@arm.com 30211051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 30311051Sandreas.hansson@arm.com "Should never see a write in a read-only cache %s\n", 30411051Sandreas.hansson@arm.com name()); 30511051Sandreas.hansson@arm.com 30611288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d\n", __func__, 30711051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 30811051Sandreas.hansson@arm.com 30911051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 31011051Sandreas.hansson@arm.com DPRINTF(Cache, "%s%s addr %#llx uncacheable\n", pkt->cmdString(), 31111051Sandreas.hansson@arm.com pkt->req->isInstFetch() ? " (ifetch)" : "", 31211051Sandreas.hansson@arm.com pkt->getAddr()); 31311051Sandreas.hansson@arm.com 31411051Sandreas.hansson@arm.com // flush and invalidate any existing block 31511051Sandreas.hansson@arm.com CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure())); 31611051Sandreas.hansson@arm.com if (old_blk && old_blk->isValid()) { 31711199Sandreas.hansson@arm.com if (old_blk->isDirty() || writebackClean) 31811051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(old_blk)); 31911051Sandreas.hansson@arm.com else 32011051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(old_blk)); 32111051Sandreas.hansson@arm.com tags->invalidate(old_blk); 32211051Sandreas.hansson@arm.com old_blk->invalidate(); 32311051Sandreas.hansson@arm.com } 32411051Sandreas.hansson@arm.com 32511051Sandreas.hansson@arm.com blk = NULL; 32611051Sandreas.hansson@arm.com // lookupLatency is the latency in case the request is uncacheable. 32711051Sandreas.hansson@arm.com lat = lookupLatency; 32811051Sandreas.hansson@arm.com return false; 32911051Sandreas.hansson@arm.com } 33011051Sandreas.hansson@arm.com 33111051Sandreas.hansson@arm.com ContextID id = pkt->req->hasContextId() ? 33211051Sandreas.hansson@arm.com pkt->req->contextId() : InvalidContextID; 33311051Sandreas.hansson@arm.com // Here lat is the value passed as parameter to accessBlock() function 33411051Sandreas.hansson@arm.com // that can modify its value. 33511051Sandreas.hansson@arm.com blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat, id); 33611051Sandreas.hansson@arm.com 33711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s%s addr %#llx size %d (%s) %s\n", pkt->cmdString(), 33811051Sandreas.hansson@arm.com pkt->req->isInstFetch() ? " (ifetch)" : "", 33911051Sandreas.hansson@arm.com pkt->getAddr(), pkt->getSize(), pkt->isSecure() ? "s" : "ns", 34011051Sandreas.hansson@arm.com blk ? "hit " + blk->print() : "miss"); 34111051Sandreas.hansson@arm.com 34211051Sandreas.hansson@arm.com 34311199Sandreas.hansson@arm.com if (pkt->isEviction()) { 34411051Sandreas.hansson@arm.com // We check for presence of block in above caches before issuing 34511051Sandreas.hansson@arm.com // Writeback or CleanEvict to write buffer. Therefore the only 34611051Sandreas.hansson@arm.com // possible cases can be of a CleanEvict packet coming from above 34711051Sandreas.hansson@arm.com // encountering a Writeback generated in this cache peer cache and 34811051Sandreas.hansson@arm.com // waiting in the write buffer. Cases of upper level peer caches 34911051Sandreas.hansson@arm.com // generating CleanEvict and Writeback or simply CleanEvict and 35011051Sandreas.hansson@arm.com // CleanEvict almost simultaneously will be caught by snoops sent out 35111051Sandreas.hansson@arm.com // by crossbar. 35211375Sandreas.hansson@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(), 35311375Sandreas.hansson@arm.com pkt->isSecure()); 35411375Sandreas.hansson@arm.com if (wb_entry) { 35511199Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 35611199Sandreas.hansson@arm.com PacketPtr wbPkt = wb_entry->getTarget()->pkt; 35711199Sandreas.hansson@arm.com assert(wbPkt->isWriteback()); 35811199Sandreas.hansson@arm.com 35911199Sandreas.hansson@arm.com if (pkt->isCleanEviction()) { 36011199Sandreas.hansson@arm.com // The CleanEvict and WritebackClean snoops into other 36111199Sandreas.hansson@arm.com // peer caches of the same level while traversing the 36211199Sandreas.hansson@arm.com // crossbar. If a copy of the block is found, the 36311199Sandreas.hansson@arm.com // packet is deleted in the crossbar. Hence, none of 36411199Sandreas.hansson@arm.com // the other upper level caches connected to this 36511199Sandreas.hansson@arm.com // cache have the block, so we can clear the 36611199Sandreas.hansson@arm.com // BLOCK_CACHED flag in the Writeback if set and 36711199Sandreas.hansson@arm.com // discard the CleanEvict by returning true. 36811199Sandreas.hansson@arm.com wbPkt->clearBlockCached(); 36911199Sandreas.hansson@arm.com return true; 37011199Sandreas.hansson@arm.com } else { 37111199Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::WritebackDirty); 37211199Sandreas.hansson@arm.com // Dirty writeback from above trumps our clean 37311199Sandreas.hansson@arm.com // writeback... discard here 37411199Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 37511375Sandreas.hansson@arm.com markInService(wb_entry); 37611199Sandreas.hansson@arm.com delete wbPkt; 37711199Sandreas.hansson@arm.com } 37811051Sandreas.hansson@arm.com } 37911051Sandreas.hansson@arm.com } 38011051Sandreas.hansson@arm.com 38111051Sandreas.hansson@arm.com // Writeback handling is special case. We can write the block into 38211051Sandreas.hansson@arm.com // the cache without having a writeable copy (or any copy at all). 38311199Sandreas.hansson@arm.com if (pkt->isWriteback()) { 38411051Sandreas.hansson@arm.com assert(blkSize == pkt->getSize()); 38511199Sandreas.hansson@arm.com 38611199Sandreas.hansson@arm.com // we could get a clean writeback while we are having 38711199Sandreas.hansson@arm.com // outstanding accesses to a block, do the simple thing for 38811199Sandreas.hansson@arm.com // now and drop the clean writeback so that we do not upset 38911199Sandreas.hansson@arm.com // any ordering/decisions about ownership already taken 39011199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackClean && 39111199Sandreas.hansson@arm.com mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) { 39211199Sandreas.hansson@arm.com DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, " 39311199Sandreas.hansson@arm.com "dropping\n", pkt->getAddr()); 39411199Sandreas.hansson@arm.com return true; 39511199Sandreas.hansson@arm.com } 39611199Sandreas.hansson@arm.com 39711051Sandreas.hansson@arm.com if (blk == NULL) { 39811051Sandreas.hansson@arm.com // need to do a replacement 39911051Sandreas.hansson@arm.com blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks); 40011051Sandreas.hansson@arm.com if (blk == NULL) { 40111051Sandreas.hansson@arm.com // no replaceable block available: give up, fwd to next level. 40211051Sandreas.hansson@arm.com incMissCount(pkt); 40311051Sandreas.hansson@arm.com return false; 40411051Sandreas.hansson@arm.com } 40511051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 40611051Sandreas.hansson@arm.com 40711051Sandreas.hansson@arm.com blk->status = (BlkValid | BlkReadable); 40811051Sandreas.hansson@arm.com if (pkt->isSecure()) { 40911051Sandreas.hansson@arm.com blk->status |= BlkSecure; 41011051Sandreas.hansson@arm.com } 41111051Sandreas.hansson@arm.com } 41211199Sandreas.hansson@arm.com // only mark the block dirty if we got a writeback command, 41311199Sandreas.hansson@arm.com // and leave it as is for a clean writeback 41411199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackDirty) { 41511199Sandreas.hansson@arm.com blk->status |= BlkDirty; 41611199Sandreas.hansson@arm.com } 41711284Sandreas.hansson@arm.com // if the packet does not have sharers, it is passing 41811284Sandreas.hansson@arm.com // writable, and we got the writeback in Modified or Exclusive 41911284Sandreas.hansson@arm.com // state, if not we are in the Owned or Shared state 42011284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 42111051Sandreas.hansson@arm.com blk->status |= BlkWritable; 42211051Sandreas.hansson@arm.com } 42311051Sandreas.hansson@arm.com // nothing else to do; writeback doesn't expect response 42411051Sandreas.hansson@arm.com assert(!pkt->needsResponse()); 42511051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 42611051Sandreas.hansson@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 42711051Sandreas.hansson@arm.com incHitCount(pkt); 42811051Sandreas.hansson@arm.com return true; 42911051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::CleanEvict) { 43011051Sandreas.hansson@arm.com if (blk != NULL) { 43111051Sandreas.hansson@arm.com // Found the block in the tags, need to stop CleanEvict from 43211051Sandreas.hansson@arm.com // propagating further down the hierarchy. Returning true will 43311051Sandreas.hansson@arm.com // treat the CleanEvict like a satisfied write request and delete 43411051Sandreas.hansson@arm.com // it. 43511051Sandreas.hansson@arm.com return true; 43611051Sandreas.hansson@arm.com } 43711051Sandreas.hansson@arm.com // We didn't find the block here, propagate the CleanEvict further 43811051Sandreas.hansson@arm.com // down the memory hierarchy. Returning false will treat the CleanEvict 43911051Sandreas.hansson@arm.com // like a Writeback which could not find a replaceable block so has to 44011051Sandreas.hansson@arm.com // go to next level. 44111051Sandreas.hansson@arm.com return false; 44211051Sandreas.hansson@arm.com } else if ((blk != NULL) && 44311284Sandreas.hansson@arm.com (pkt->needsWritable() ? blk->isWritable() : blk->isReadable())) { 44411051Sandreas.hansson@arm.com // OK to satisfy access 44511051Sandreas.hansson@arm.com incHitCount(pkt); 44611051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 44711051Sandreas.hansson@arm.com return true; 44811051Sandreas.hansson@arm.com } 44911051Sandreas.hansson@arm.com 45011051Sandreas.hansson@arm.com // Can't satisfy access normally... either no block (blk == NULL) 45111284Sandreas.hansson@arm.com // or have block but need writable 45211051Sandreas.hansson@arm.com 45311051Sandreas.hansson@arm.com incMissCount(pkt); 45411051Sandreas.hansson@arm.com 45511051Sandreas.hansson@arm.com if (blk == NULL && pkt->isLLSC() && pkt->isWrite()) { 45611051Sandreas.hansson@arm.com // complete miss on store conditional... just give up now 45711051Sandreas.hansson@arm.com pkt->req->setExtraData(0); 45811051Sandreas.hansson@arm.com return true; 45911051Sandreas.hansson@arm.com } 46011051Sandreas.hansson@arm.com 46111051Sandreas.hansson@arm.com return false; 46211051Sandreas.hansson@arm.com} 46311051Sandreas.hansson@arm.com 46411051Sandreas.hansson@arm.comvoid 46511051Sandreas.hansson@arm.comCache::doWritebacks(PacketList& writebacks, Tick forward_time) 46611051Sandreas.hansson@arm.com{ 46711051Sandreas.hansson@arm.com while (!writebacks.empty()) { 46811051Sandreas.hansson@arm.com PacketPtr wbPkt = writebacks.front(); 46911051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying writebacks to 47011051Sandreas.hansson@arm.com // write buffer. Call isCachedAbove for both Writebacks and 47111051Sandreas.hansson@arm.com // CleanEvicts. If isCachedAbove returns true we set BLOCK_CACHED flag 47211051Sandreas.hansson@arm.com // in Writebacks and discard CleanEvicts. 47311051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) { 47411051Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::CleanEvict) { 47511051Sandreas.hansson@arm.com // Delete CleanEvict because cached copies exist above. The 47611051Sandreas.hansson@arm.com // packet destructor will delete the request object because 47711051Sandreas.hansson@arm.com // this is a non-snoop request packet which does not require a 47811051Sandreas.hansson@arm.com // response. 47911051Sandreas.hansson@arm.com delete wbPkt; 48011199Sandreas.hansson@arm.com } else if (wbPkt->cmd == MemCmd::WritebackClean) { 48111199Sandreas.hansson@arm.com // clean writeback, do not send since the block is 48211199Sandreas.hansson@arm.com // still cached above 48311199Sandreas.hansson@arm.com assert(writebackClean); 48411199Sandreas.hansson@arm.com delete wbPkt; 48511051Sandreas.hansson@arm.com } else { 48611199Sandreas.hansson@arm.com assert(wbPkt->cmd == MemCmd::WritebackDirty); 48711051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag in Writeback and send below, so that 48811051Sandreas.hansson@arm.com // the Writeback does not reset the bit corresponding to this 48911051Sandreas.hansson@arm.com // address in the snoop filter below. 49011051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 49111051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 49211051Sandreas.hansson@arm.com } 49311051Sandreas.hansson@arm.com } else { 49411051Sandreas.hansson@arm.com // If the block is not cached above, send packet below. Both 49511051Sandreas.hansson@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 49611051Sandreas.hansson@arm.com // reset the bit corresponding to this address in the snoop filter 49711051Sandreas.hansson@arm.com // below. 49811051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 49911051Sandreas.hansson@arm.com } 50011051Sandreas.hansson@arm.com writebacks.pop_front(); 50111051Sandreas.hansson@arm.com } 50211051Sandreas.hansson@arm.com} 50311051Sandreas.hansson@arm.com 50411130Sali.jafri@arm.comvoid 50511130Sali.jafri@arm.comCache::doWritebacksAtomic(PacketList& writebacks) 50611130Sali.jafri@arm.com{ 50711130Sali.jafri@arm.com while (!writebacks.empty()) { 50811130Sali.jafri@arm.com PacketPtr wbPkt = writebacks.front(); 50911130Sali.jafri@arm.com // Call isCachedAbove for both Writebacks and CleanEvicts. If 51011130Sali.jafri@arm.com // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks 51111130Sali.jafri@arm.com // and discard CleanEvicts. 51211130Sali.jafri@arm.com if (isCachedAbove(wbPkt, false)) { 51311199Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::WritebackDirty) { 51411130Sali.jafri@arm.com // Set BLOCK_CACHED flag in Writeback and send below, 51511130Sali.jafri@arm.com // so that the Writeback does not reset the bit 51611130Sali.jafri@arm.com // corresponding to this address in the snoop filter 51711130Sali.jafri@arm.com // below. We can discard CleanEvicts because cached 51811130Sali.jafri@arm.com // copies exist above. Atomic mode isCachedAbove 51911130Sali.jafri@arm.com // modifies packet to set BLOCK_CACHED flag 52011130Sali.jafri@arm.com memSidePort->sendAtomic(wbPkt); 52111130Sali.jafri@arm.com } 52211130Sali.jafri@arm.com } else { 52311130Sali.jafri@arm.com // If the block is not cached above, send packet below. Both 52411130Sali.jafri@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 52511130Sali.jafri@arm.com // reset the bit corresponding to this address in the snoop filter 52611130Sali.jafri@arm.com // below. 52711130Sali.jafri@arm.com memSidePort->sendAtomic(wbPkt); 52811130Sali.jafri@arm.com } 52911130Sali.jafri@arm.com writebacks.pop_front(); 53011130Sali.jafri@arm.com // In case of CleanEvicts, the packet destructor will delete the 53111130Sali.jafri@arm.com // request object because this is a non-snoop request packet which 53211130Sali.jafri@arm.com // does not require a response. 53311130Sali.jafri@arm.com delete wbPkt; 53411130Sali.jafri@arm.com } 53511130Sali.jafri@arm.com} 53611130Sali.jafri@arm.com 53711051Sandreas.hansson@arm.com 53811051Sandreas.hansson@arm.comvoid 53911051Sandreas.hansson@arm.comCache::recvTimingSnoopResp(PacketPtr pkt) 54011051Sandreas.hansson@arm.com{ 54111051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 54211051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 54311051Sandreas.hansson@arm.com 54411051Sandreas.hansson@arm.com assert(pkt->isResponse()); 54511051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 54611051Sandreas.hansson@arm.com 54711276Sandreas.hansson@arm.com // determine if the response is from a snoop request we created 54811276Sandreas.hansson@arm.com // (in which case it should be in the outstandingSnoop), or if we 54911276Sandreas.hansson@arm.com // merely forwarded someone else's snoop request 55011276Sandreas.hansson@arm.com const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) == 55111276Sandreas.hansson@arm.com outstandingSnoop.end(); 55211276Sandreas.hansson@arm.com 55311276Sandreas.hansson@arm.com if (!forwardAsSnoop) { 55411276Sandreas.hansson@arm.com // the packet came from this cache, so sink it here and do not 55511276Sandreas.hansson@arm.com // forward it 55611051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::HardPFResp); 55711276Sandreas.hansson@arm.com 55811276Sandreas.hansson@arm.com outstandingSnoop.erase(pkt->req); 55911276Sandreas.hansson@arm.com 56011276Sandreas.hansson@arm.com DPRINTF(Cache, "Got prefetch response from above for addr " 56111276Sandreas.hansson@arm.com "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 56211051Sandreas.hansson@arm.com recvTimingResp(pkt); 56311051Sandreas.hansson@arm.com return; 56411051Sandreas.hansson@arm.com } 56511051Sandreas.hansson@arm.com 56611051Sandreas.hansson@arm.com // forwardLatency is set here because there is a response from an 56711051Sandreas.hansson@arm.com // upper level cache. 56811051Sandreas.hansson@arm.com // To pay the delay that occurs if the packet comes from the bus, 56911051Sandreas.hansson@arm.com // we charge also headerDelay. 57011051Sandreas.hansson@arm.com Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay; 57111051Sandreas.hansson@arm.com // Reset the timing of the packet. 57211051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 57311051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, snoop_resp_time); 57411051Sandreas.hansson@arm.com} 57511051Sandreas.hansson@arm.com 57611051Sandreas.hansson@arm.comvoid 57711051Sandreas.hansson@arm.comCache::promoteWholeLineWrites(PacketPtr pkt) 57811051Sandreas.hansson@arm.com{ 57911051Sandreas.hansson@arm.com // Cache line clearing instructions 58011051Sandreas.hansson@arm.com if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) && 58111051Sandreas.hansson@arm.com (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) { 58211051Sandreas.hansson@arm.com pkt->cmd = MemCmd::WriteLineReq; 58311051Sandreas.hansson@arm.com DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n"); 58411051Sandreas.hansson@arm.com } 58511051Sandreas.hansson@arm.com} 58611051Sandreas.hansson@arm.com 58711051Sandreas.hansson@arm.combool 58811051Sandreas.hansson@arm.comCache::recvTimingReq(PacketPtr pkt) 58911051Sandreas.hansson@arm.com{ 59011051Sandreas.hansson@arm.com DPRINTF(CacheTags, "%s tags: %s\n", __func__, tags->print()); 59111051Sandreas.hansson@arm.com 59211051Sandreas.hansson@arm.com assert(pkt->isRequest()); 59311051Sandreas.hansson@arm.com 59411051Sandreas.hansson@arm.com // Just forward the packet if caches are disabled. 59511051Sandreas.hansson@arm.com if (system->bypassCaches()) { 59611051Sandreas.hansson@arm.com // @todo This should really enqueue the packet rather 59711051Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt); 59811051Sandreas.hansson@arm.com assert(success); 59911051Sandreas.hansson@arm.com return true; 60011051Sandreas.hansson@arm.com } 60111051Sandreas.hansson@arm.com 60211051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 60311051Sandreas.hansson@arm.com 60411284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 60511051Sandreas.hansson@arm.com // a cache above us (but not where the packet came from) is 60611284Sandreas.hansson@arm.com // responding to the request, in other words it has the line 60711284Sandreas.hansson@arm.com // in Modified or Owned state 60811284Sandreas.hansson@arm.com DPRINTF(Cache, "Cache above responding to %#llx (%s): " 60911284Sandreas.hansson@arm.com "not responding\n", 61011051Sandreas.hansson@arm.com pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 61111051Sandreas.hansson@arm.com 61211284Sandreas.hansson@arm.com // if the packet needs the block to be writable, and the cache 61311284Sandreas.hansson@arm.com // that has promised to respond (setting the cache responding 61411284Sandreas.hansson@arm.com // flag) is not providing writable (it is in Owned rather than 61511284Sandreas.hansson@arm.com // the Modified state), we know that there may be other Shared 61611284Sandreas.hansson@arm.com // copies in the system; go out and invalidate them all 61711334Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 61811284Sandreas.hansson@arm.com 61911334Sandreas.hansson@arm.com // an upstream cache that had the line in Owned state 62011334Sandreas.hansson@arm.com // (dirty, but not writable), is responding and thus 62111334Sandreas.hansson@arm.com // transferring the dirty line from one branch of the 62211334Sandreas.hansson@arm.com // cache hierarchy to another 62311284Sandreas.hansson@arm.com 62411334Sandreas.hansson@arm.com // send out an express snoop and invalidate all other 62511334Sandreas.hansson@arm.com // copies (snooping a packet that needs writable is the 62611334Sandreas.hansson@arm.com // same as an invalidation), thus turning the Owned line 62711334Sandreas.hansson@arm.com // into a Modified line, note that we don't invalidate the 62811334Sandreas.hansson@arm.com // block in the current cache or any other cache on the 62911334Sandreas.hansson@arm.com // path to memory 63011051Sandreas.hansson@arm.com 63111334Sandreas.hansson@arm.com // create a downstream express snoop with cleared packet 63211334Sandreas.hansson@arm.com // flags, there is no need to allocate any data as the 63311334Sandreas.hansson@arm.com // packet is merely used to co-ordinate state transitions 63411334Sandreas.hansson@arm.com Packet *snoop_pkt = new Packet(pkt, true, false); 63511051Sandreas.hansson@arm.com 63611334Sandreas.hansson@arm.com // also reset the bus time that the original packet has 63711334Sandreas.hansson@arm.com // not yet paid for 63811334Sandreas.hansson@arm.com snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0; 63911051Sandreas.hansson@arm.com 64011334Sandreas.hansson@arm.com // make this an instantaneous express snoop, and let the 64111334Sandreas.hansson@arm.com // other caches in the system know that the another cache 64211334Sandreas.hansson@arm.com // is responding, because we have found the authorative 64311334Sandreas.hansson@arm.com // copy (Modified or Owned) that will supply the right 64411334Sandreas.hansson@arm.com // data 64511334Sandreas.hansson@arm.com snoop_pkt->setExpressSnoop(); 64611334Sandreas.hansson@arm.com snoop_pkt->setCacheResponding(); 64711051Sandreas.hansson@arm.com 64811334Sandreas.hansson@arm.com // this express snoop travels towards the memory, and at 64911334Sandreas.hansson@arm.com // every crossbar it is snooped upwards thus reaching 65011334Sandreas.hansson@arm.com // every cache in the system 65111334Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(snoop_pkt); 65211334Sandreas.hansson@arm.com // express snoops always succeed 65311334Sandreas.hansson@arm.com assert(success); 65411334Sandreas.hansson@arm.com 65511334Sandreas.hansson@arm.com // main memory will delete the snoop packet 65611051Sandreas.hansson@arm.com 65711284Sandreas.hansson@arm.com // queue for deletion, as opposed to immediate deletion, as 65811284Sandreas.hansson@arm.com // the sending cache is still relying on the packet 65911190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 66011051Sandreas.hansson@arm.com 66111334Sandreas.hansson@arm.com // no need to take any further action in this particular cache 66211334Sandreas.hansson@arm.com // as an upstram cache has already committed to responding, 66311334Sandreas.hansson@arm.com // and we have already sent out any express snoops in the 66411334Sandreas.hansson@arm.com // section above to ensure all other copies in the system are 66511334Sandreas.hansson@arm.com // invalidated 66611051Sandreas.hansson@arm.com return true; 66711051Sandreas.hansson@arm.com } 66811051Sandreas.hansson@arm.com 66911051Sandreas.hansson@arm.com // anything that is merely forwarded pays for the forward latency and 67011051Sandreas.hansson@arm.com // the delay provided by the crossbar 67111051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 67211051Sandreas.hansson@arm.com 67311051Sandreas.hansson@arm.com // We use lookupLatency here because it is used to specify the latency 67411051Sandreas.hansson@arm.com // to access. 67511051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 67611051Sandreas.hansson@arm.com CacheBlk *blk = NULL; 67711051Sandreas.hansson@arm.com bool satisfied = false; 67811051Sandreas.hansson@arm.com { 67911051Sandreas.hansson@arm.com PacketList writebacks; 68011051Sandreas.hansson@arm.com // Note that lat is passed by reference here. The function 68111051Sandreas.hansson@arm.com // access() calls accessBlock() which can modify lat value. 68211051Sandreas.hansson@arm.com satisfied = access(pkt, blk, lat, writebacks); 68311051Sandreas.hansson@arm.com 68411051Sandreas.hansson@arm.com // copy writebacks to write buffer here to ensure they logically 68511051Sandreas.hansson@arm.com // proceed anything happening below 68611051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 68711051Sandreas.hansson@arm.com } 68811051Sandreas.hansson@arm.com 68911051Sandreas.hansson@arm.com // Here we charge the headerDelay that takes into account the latencies 69011051Sandreas.hansson@arm.com // of the bus, if the packet comes from it. 69111051Sandreas.hansson@arm.com // The latency charged it is just lat that is the value of lookupLatency 69211051Sandreas.hansson@arm.com // modified by access() function, or if not just lookupLatency. 69311051Sandreas.hansson@arm.com // In case of a hit we are neglecting response latency. 69411051Sandreas.hansson@arm.com // In case of a miss we are neglecting forward latency. 69511051Sandreas.hansson@arm.com Tick request_time = clockEdge(lat) + pkt->headerDelay; 69611051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 69711051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 69811051Sandreas.hansson@arm.com 69911051Sandreas.hansson@arm.com // track time of availability of next prefetch, if any 70011051Sandreas.hansson@arm.com Tick next_pf_time = MaxTick; 70111051Sandreas.hansson@arm.com 70211051Sandreas.hansson@arm.com bool needsResponse = pkt->needsResponse(); 70311051Sandreas.hansson@arm.com 70411051Sandreas.hansson@arm.com if (satisfied) { 70511051Sandreas.hansson@arm.com // should never be satisfying an uncacheable access as we 70611051Sandreas.hansson@arm.com // flush and invalidate any existing block as part of the 70711051Sandreas.hansson@arm.com // lookup 70811051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 70911051Sandreas.hansson@arm.com 71011051Sandreas.hansson@arm.com // hit (for all other request types) 71111051Sandreas.hansson@arm.com 71211051Sandreas.hansson@arm.com if (prefetcher && (prefetchOnAccess || (blk && blk->wasPrefetched()))) { 71311051Sandreas.hansson@arm.com if (blk) 71411051Sandreas.hansson@arm.com blk->status &= ~BlkHWPrefetched; 71511051Sandreas.hansson@arm.com 71611051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 71711051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 71811051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 71911051Sandreas.hansson@arm.com } 72011051Sandreas.hansson@arm.com 72111051Sandreas.hansson@arm.com if (needsResponse) { 72211051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 72311051Sandreas.hansson@arm.com // @todo: Make someone pay for this 72411051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 72511051Sandreas.hansson@arm.com 72611051Sandreas.hansson@arm.com // In this case we are considering request_time that takes 72711051Sandreas.hansson@arm.com // into account the delay of the xbar, if any, and just 72811051Sandreas.hansson@arm.com // lat, neglecting responseLatency, modelling hit latency 72911051Sandreas.hansson@arm.com // just as lookupLatency or or the value of lat overriden 73011051Sandreas.hansson@arm.com // by access(), that calls accessBlock() function. 73111194Sali.jafri@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 73211051Sandreas.hansson@arm.com } else { 73311199Sandreas.hansson@arm.com DPRINTF(Cache, "%s satisfied %s addr %#llx, no response needed\n", 73411199Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), 73511199Sandreas.hansson@arm.com pkt->getSize()); 73611199Sandreas.hansson@arm.com 73711190Sandreas.hansson@arm.com // queue the packet for deletion, as the sending cache is 73811190Sandreas.hansson@arm.com // still relying on it; if the block is found in access(), 73911190Sandreas.hansson@arm.com // CleanEvict and Writeback messages will be deleted 74011190Sandreas.hansson@arm.com // here as well 74111190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 74211051Sandreas.hansson@arm.com } 74311051Sandreas.hansson@arm.com } else { 74411051Sandreas.hansson@arm.com // miss 74511051Sandreas.hansson@arm.com 74611051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 74711051Sandreas.hansson@arm.com 74811051Sandreas.hansson@arm.com // ignore any existing MSHR if we are dealing with an 74911051Sandreas.hansson@arm.com // uncacheable request 75011051Sandreas.hansson@arm.com MSHR *mshr = pkt->req->isUncacheable() ? nullptr : 75111051Sandreas.hansson@arm.com mshrQueue.findMatch(blk_addr, pkt->isSecure()); 75211051Sandreas.hansson@arm.com 75311051Sandreas.hansson@arm.com // Software prefetch handling: 75411051Sandreas.hansson@arm.com // To keep the core from waiting on data it won't look at 75511051Sandreas.hansson@arm.com // anyway, send back a response with dummy data. Miss handling 75611051Sandreas.hansson@arm.com // will continue asynchronously. Unfortunately, the core will 75711051Sandreas.hansson@arm.com // insist upon freeing original Packet/Request, so we have to 75811051Sandreas.hansson@arm.com // create a new pair with a different lifecycle. Note that this 75911051Sandreas.hansson@arm.com // processing happens before any MSHR munging on the behalf of 76011051Sandreas.hansson@arm.com // this request because this new Request will be the one stored 76111051Sandreas.hansson@arm.com // into the MSHRs, not the original. 76211051Sandreas.hansson@arm.com if (pkt->cmd.isSWPrefetch()) { 76311051Sandreas.hansson@arm.com assert(needsResponse); 76411051Sandreas.hansson@arm.com assert(pkt->req->hasPaddr()); 76511051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 76611051Sandreas.hansson@arm.com 76711051Sandreas.hansson@arm.com // There's no reason to add a prefetch as an additional target 76811051Sandreas.hansson@arm.com // to an existing MSHR. If an outstanding request is already 76911051Sandreas.hansson@arm.com // in progress, there is nothing for the prefetch to do. 77011051Sandreas.hansson@arm.com // If this is the case, we don't even create a request at all. 77111051Sandreas.hansson@arm.com PacketPtr pf = nullptr; 77211051Sandreas.hansson@arm.com 77311051Sandreas.hansson@arm.com if (!mshr) { 77411051Sandreas.hansson@arm.com // copy the request and create a new SoftPFReq packet 77511051Sandreas.hansson@arm.com RequestPtr req = new Request(pkt->req->getPaddr(), 77611051Sandreas.hansson@arm.com pkt->req->getSize(), 77711051Sandreas.hansson@arm.com pkt->req->getFlags(), 77811051Sandreas.hansson@arm.com pkt->req->masterId()); 77911051Sandreas.hansson@arm.com pf = new Packet(req, pkt->cmd); 78011051Sandreas.hansson@arm.com pf->allocate(); 78111051Sandreas.hansson@arm.com assert(pf->getAddr() == pkt->getAddr()); 78211051Sandreas.hansson@arm.com assert(pf->getSize() == pkt->getSize()); 78311051Sandreas.hansson@arm.com } 78411051Sandreas.hansson@arm.com 78511051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 78611286Sandreas.hansson@arm.com 78711051Sandreas.hansson@arm.com // request_time is used here, taking into account lat and the delay 78811051Sandreas.hansson@arm.com // charged if the packet comes from the xbar. 78911194Sali.jafri@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 79011051Sandreas.hansson@arm.com 79111051Sandreas.hansson@arm.com // If an outstanding request is in progress (we found an 79211051Sandreas.hansson@arm.com // MSHR) this is set to null 79311051Sandreas.hansson@arm.com pkt = pf; 79411051Sandreas.hansson@arm.com } 79511051Sandreas.hansson@arm.com 79611051Sandreas.hansson@arm.com if (mshr) { 79711051Sandreas.hansson@arm.com /// MSHR hit 79811051Sandreas.hansson@arm.com /// @note writebacks will be checked in getNextMSHR() 79911051Sandreas.hansson@arm.com /// for any conflicting requests to the same block 80011051Sandreas.hansson@arm.com 80111051Sandreas.hansson@arm.com //@todo remove hw_pf here 80211051Sandreas.hansson@arm.com 80311051Sandreas.hansson@arm.com // Coalesce unless it was a software prefetch (see above). 80411051Sandreas.hansson@arm.com if (pkt) { 80511199Sandreas.hansson@arm.com assert(!pkt->isWriteback()); 80611199Sandreas.hansson@arm.com // CleanEvicts corresponding to blocks which have 80711199Sandreas.hansson@arm.com // outstanding requests in MSHRs are simply sunk here 80811051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::CleanEvict) { 80911190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 81011051Sandreas.hansson@arm.com } else { 81111051Sandreas.hansson@arm.com DPRINTF(Cache, "%s coalescing MSHR for %s addr %#llx size %d\n", 81211051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), 81311051Sandreas.hansson@arm.com pkt->getSize()); 81411051Sandreas.hansson@arm.com 81511051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 81611051Sandreas.hansson@arm.com mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 81711051Sandreas.hansson@arm.com // We use forward_time here because it is the same 81811051Sandreas.hansson@arm.com // considering new targets. We have multiple 81911051Sandreas.hansson@arm.com // requests for the same address here. It 82011051Sandreas.hansson@arm.com // specifies the latency to allocate an internal 82111051Sandreas.hansson@arm.com // buffer and to schedule an event to the queued 82211051Sandreas.hansson@arm.com // port and also takes into account the additional 82311051Sandreas.hansson@arm.com // delay of the xbar. 82411197Sandreas.hansson@arm.com mshr->allocateTarget(pkt, forward_time, order++, 82511197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 82611051Sandreas.hansson@arm.com if (mshr->getNumTargets() == numTarget) { 82711051Sandreas.hansson@arm.com noTargetMSHR = mshr; 82811051Sandreas.hansson@arm.com setBlocked(Blocked_NoTargets); 82911051Sandreas.hansson@arm.com // need to be careful with this... if this mshr isn't 83011051Sandreas.hansson@arm.com // ready yet (i.e. time > curTick()), we don't want to 83111051Sandreas.hansson@arm.com // move it ahead of mshrs that are ready 83211051Sandreas.hansson@arm.com // mshrQueue.moveToFront(mshr); 83311051Sandreas.hansson@arm.com } 83411051Sandreas.hansson@arm.com } 83511051Sandreas.hansson@arm.com // We should call the prefetcher reguardless if the request is 83611051Sandreas.hansson@arm.com // satisfied or not, reguardless if the request is in the MSHR or 83711051Sandreas.hansson@arm.com // not. The request could be a ReadReq hit, but still not 83811051Sandreas.hansson@arm.com // satisfied (potentially because of a prior write to the same 83911051Sandreas.hansson@arm.com // cache line. So, even when not satisfied, tehre is an MSHR 84011051Sandreas.hansson@arm.com // already allocated for this, we need to let the prefetcher know 84111051Sandreas.hansson@arm.com // about the request 84211051Sandreas.hansson@arm.com if (prefetcher) { 84311051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 84411051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 84511051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 84611051Sandreas.hansson@arm.com } 84711051Sandreas.hansson@arm.com } 84811051Sandreas.hansson@arm.com } else { 84911051Sandreas.hansson@arm.com // no MSHR 85011051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 85111051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 85211051Sandreas.hansson@arm.com mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++; 85311051Sandreas.hansson@arm.com } else { 85411051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 85511051Sandreas.hansson@arm.com } 85611051Sandreas.hansson@arm.com 85711199Sandreas.hansson@arm.com if (pkt->isEviction() || 85811051Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 85911051Sandreas.hansson@arm.com // We use forward_time here because there is an 86011051Sandreas.hansson@arm.com // uncached memory write, forwarded to WriteBuffer. 86111051Sandreas.hansson@arm.com allocateWriteBuffer(pkt, forward_time); 86211051Sandreas.hansson@arm.com } else { 86311051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 86411051Sandreas.hansson@arm.com // should have flushed and have no valid block 86511051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 86611051Sandreas.hansson@arm.com 86711051Sandreas.hansson@arm.com // If we have a write miss to a valid block, we 86811051Sandreas.hansson@arm.com // need to mark the block non-readable. Otherwise 86911051Sandreas.hansson@arm.com // if we allow reads while there's an outstanding 87011051Sandreas.hansson@arm.com // write miss, the read could return stale data 87111051Sandreas.hansson@arm.com // out of the cache block... a more aggressive 87211051Sandreas.hansson@arm.com // system could detect the overlap (if any) and 87311051Sandreas.hansson@arm.com // forward data out of the MSHRs, but we don't do 87411051Sandreas.hansson@arm.com // that yet. Note that we do need to leave the 87511051Sandreas.hansson@arm.com // block valid so that it stays in the cache, in 87611051Sandreas.hansson@arm.com // case we get an upgrade response (and hence no 87711051Sandreas.hansson@arm.com // new data) when the write miss completes. 87811051Sandreas.hansson@arm.com // As long as CPUs do proper store/load forwarding 87911051Sandreas.hansson@arm.com // internally, and have a sufficiently weak memory 88011051Sandreas.hansson@arm.com // model, this is probably unnecessary, but at some 88111051Sandreas.hansson@arm.com // point it must have seemed like we needed it... 88211284Sandreas.hansson@arm.com assert(pkt->needsWritable()); 88311051Sandreas.hansson@arm.com assert(!blk->isWritable()); 88411051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 88511051Sandreas.hansson@arm.com } 88611051Sandreas.hansson@arm.com // Here we are using forward_time, modelling the latency of 88711051Sandreas.hansson@arm.com // a miss (outbound) just as forwardLatency, neglecting the 88811051Sandreas.hansson@arm.com // lookupLatency component. 88911051Sandreas.hansson@arm.com allocateMissBuffer(pkt, forward_time); 89011051Sandreas.hansson@arm.com } 89111051Sandreas.hansson@arm.com 89211051Sandreas.hansson@arm.com if (prefetcher) { 89311051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 89411051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 89511051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 89611051Sandreas.hansson@arm.com } 89711051Sandreas.hansson@arm.com } 89811051Sandreas.hansson@arm.com } 89911051Sandreas.hansson@arm.com 90011051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 90111051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 90211051Sandreas.hansson@arm.com 90311051Sandreas.hansson@arm.com return true; 90411051Sandreas.hansson@arm.com} 90511051Sandreas.hansson@arm.com 90611051Sandreas.hansson@arm.com 90711051Sandreas.hansson@arm.com// See comment in cache.hh. 90811051Sandreas.hansson@arm.comPacketPtr 90911051Sandreas.hansson@arm.comCache::getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk, 91011284Sandreas.hansson@arm.com bool needsWritable) const 91111051Sandreas.hansson@arm.com{ 91211051Sandreas.hansson@arm.com bool blkValid = blk && blk->isValid(); 91311051Sandreas.hansson@arm.com 91411051Sandreas.hansson@arm.com if (cpu_pkt->req->isUncacheable()) { 91511051Sandreas.hansson@arm.com // note that at the point we see the uncacheable request we 91611051Sandreas.hansson@arm.com // flush any block, but there could be an outstanding MSHR, 91711051Sandreas.hansson@arm.com // and the cache could have filled again before we actually 91811051Sandreas.hansson@arm.com // send out the forwarded uncacheable request (blk could thus 91911051Sandreas.hansson@arm.com // be non-null) 92011051Sandreas.hansson@arm.com return NULL; 92111051Sandreas.hansson@arm.com } 92211051Sandreas.hansson@arm.com 92311051Sandreas.hansson@arm.com if (!blkValid && 92411051Sandreas.hansson@arm.com (cpu_pkt->isUpgrade() || 92511199Sandreas.hansson@arm.com cpu_pkt->isEviction())) { 92611051Sandreas.hansson@arm.com // Writebacks that weren't allocated in access() and upgrades 92711051Sandreas.hansson@arm.com // from upper-level caches that missed completely just go 92811051Sandreas.hansson@arm.com // through. 92911051Sandreas.hansson@arm.com return NULL; 93011051Sandreas.hansson@arm.com } 93111051Sandreas.hansson@arm.com 93211051Sandreas.hansson@arm.com assert(cpu_pkt->needsResponse()); 93311051Sandreas.hansson@arm.com 93411051Sandreas.hansson@arm.com MemCmd cmd; 93511051Sandreas.hansson@arm.com // @TODO make useUpgrades a parameter. 93611051Sandreas.hansson@arm.com // Note that ownership protocols require upgrade, otherwise a 93711051Sandreas.hansson@arm.com // write miss on a shared owned block will generate a ReadExcl, 93811051Sandreas.hansson@arm.com // which will clobber the owned copy. 93911051Sandreas.hansson@arm.com const bool useUpgrades = true; 94011051Sandreas.hansson@arm.com if (blkValid && useUpgrades) { 94111284Sandreas.hansson@arm.com // only reason to be here is that blk is read only and we need 94211284Sandreas.hansson@arm.com // it to be writable 94311284Sandreas.hansson@arm.com assert(needsWritable); 94411051Sandreas.hansson@arm.com assert(!blk->isWritable()); 94511051Sandreas.hansson@arm.com cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq; 94611051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq || 94711051Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::StoreCondFailReq) { 94811051Sandreas.hansson@arm.com // Even though this SC will fail, we still need to send out the 94911051Sandreas.hansson@arm.com // request and get the data to supply it to other snoopers in the case 95011051Sandreas.hansson@arm.com // where the determination the StoreCond fails is delayed due to 95111051Sandreas.hansson@arm.com // all caches not being on the same local bus. 95211051Sandreas.hansson@arm.com cmd = MemCmd::SCUpgradeFailReq; 95311352Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::WriteLineReq || 95411352Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::InvalidateReq) { 95511051Sandreas.hansson@arm.com // forward as invalidate to all other caches, this gives us 95611284Sandreas.hansson@arm.com // the line in Exclusive state, and invalidates all other 95711051Sandreas.hansson@arm.com // copies 95811051Sandreas.hansson@arm.com cmd = MemCmd::InvalidateReq; 95911051Sandreas.hansson@arm.com } else { 96011051Sandreas.hansson@arm.com // block is invalid 96111284Sandreas.hansson@arm.com cmd = needsWritable ? MemCmd::ReadExReq : 96211051Sandreas.hansson@arm.com (isReadOnly ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq); 96311051Sandreas.hansson@arm.com } 96411051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize); 96511051Sandreas.hansson@arm.com 96611284Sandreas.hansson@arm.com // if there are upstream caches that have already marked the 96711284Sandreas.hansson@arm.com // packet as having sharers (not passing writable), pass that info 96811284Sandreas.hansson@arm.com // downstream 96911284Sandreas.hansson@arm.com if (cpu_pkt->hasSharers()) { 97011051Sandreas.hansson@arm.com // note that cpu_pkt may have spent a considerable time in the 97111051Sandreas.hansson@arm.com // MSHR queue and that the information could possibly be out 97211051Sandreas.hansson@arm.com // of date, however, there is no harm in conservatively 97311284Sandreas.hansson@arm.com // assuming the block has sharers 97411284Sandreas.hansson@arm.com pkt->setHasSharers(); 97511284Sandreas.hansson@arm.com DPRINTF(Cache, "%s passing hasSharers from %s to %s addr %#llx " 97611284Sandreas.hansson@arm.com "size %d\n", 97711051Sandreas.hansson@arm.com __func__, cpu_pkt->cmdString(), pkt->cmdString(), 97811051Sandreas.hansson@arm.com pkt->getAddr(), pkt->getSize()); 97911051Sandreas.hansson@arm.com } 98011051Sandreas.hansson@arm.com 98111051Sandreas.hansson@arm.com // the packet should be block aligned 98211051Sandreas.hansson@arm.com assert(pkt->getAddr() == blockAlign(pkt->getAddr())); 98311051Sandreas.hansson@arm.com 98411051Sandreas.hansson@arm.com pkt->allocate(); 98511051Sandreas.hansson@arm.com DPRINTF(Cache, "%s created %s from %s for addr %#llx size %d\n", 98611051Sandreas.hansson@arm.com __func__, pkt->cmdString(), cpu_pkt->cmdString(), pkt->getAddr(), 98711051Sandreas.hansson@arm.com pkt->getSize()); 98811051Sandreas.hansson@arm.com return pkt; 98911051Sandreas.hansson@arm.com} 99011051Sandreas.hansson@arm.com 99111051Sandreas.hansson@arm.com 99211051Sandreas.hansson@arm.comTick 99311051Sandreas.hansson@arm.comCache::recvAtomic(PacketPtr pkt) 99411051Sandreas.hansson@arm.com{ 99511051Sandreas.hansson@arm.com // We are in atomic mode so we pay just for lookupLatency here. 99611051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 99711051Sandreas.hansson@arm.com 99811051Sandreas.hansson@arm.com // Forward the request if the system is in cache bypass mode. 99911051Sandreas.hansson@arm.com if (system->bypassCaches()) 100011051Sandreas.hansson@arm.com return ticksToCycles(memSidePort->sendAtomic(pkt)); 100111051Sandreas.hansson@arm.com 100211051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 100311051Sandreas.hansson@arm.com 100411333Sandreas.hansson@arm.com // follow the same flow as in recvTimingReq, and check if a cache 100511333Sandreas.hansson@arm.com // above us is responding 100611284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 100711333Sandreas.hansson@arm.com DPRINTF(Cache, "Cache above responding to %#llx (%s): " 100811333Sandreas.hansson@arm.com "not responding\n", 100911333Sandreas.hansson@arm.com pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 101011333Sandreas.hansson@arm.com 101111333Sandreas.hansson@arm.com // if a cache is responding, and it had the line in Owned 101211333Sandreas.hansson@arm.com // rather than Modified state, we need to invalidate any 101311333Sandreas.hansson@arm.com // copies that are not on the same path to memory 101411334Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 101511334Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 101611051Sandreas.hansson@arm.com 101711051Sandreas.hansson@arm.com return lat * clockPeriod(); 101811051Sandreas.hansson@arm.com } 101911051Sandreas.hansson@arm.com 102011051Sandreas.hansson@arm.com // should assert here that there are no outstanding MSHRs or 102111051Sandreas.hansson@arm.com // writebacks... that would mean that someone used an atomic 102211051Sandreas.hansson@arm.com // access in timing mode 102311051Sandreas.hansson@arm.com 102411051Sandreas.hansson@arm.com CacheBlk *blk = NULL; 102511051Sandreas.hansson@arm.com PacketList writebacks; 102611051Sandreas.hansson@arm.com bool satisfied = access(pkt, blk, lat, writebacks); 102711051Sandreas.hansson@arm.com 102811051Sandreas.hansson@arm.com // handle writebacks resulting from the access here to ensure they 102911051Sandreas.hansson@arm.com // logically proceed anything happening below 103011130Sali.jafri@arm.com doWritebacksAtomic(writebacks); 103111051Sandreas.hansson@arm.com 103211051Sandreas.hansson@arm.com if (!satisfied) { 103311051Sandreas.hansson@arm.com // MISS 103411051Sandreas.hansson@arm.com 103511284Sandreas.hansson@arm.com PacketPtr bus_pkt = getBusPacket(pkt, blk, pkt->needsWritable()); 103611051Sandreas.hansson@arm.com 103711051Sandreas.hansson@arm.com bool is_forward = (bus_pkt == NULL); 103811051Sandreas.hansson@arm.com 103911051Sandreas.hansson@arm.com if (is_forward) { 104011051Sandreas.hansson@arm.com // just forwarding the same request to the next level 104111051Sandreas.hansson@arm.com // no local cache operation involved 104211051Sandreas.hansson@arm.com bus_pkt = pkt; 104311051Sandreas.hansson@arm.com } 104411051Sandreas.hansson@arm.com 104511051Sandreas.hansson@arm.com DPRINTF(Cache, "Sending an atomic %s for %#llx (%s)\n", 104611051Sandreas.hansson@arm.com bus_pkt->cmdString(), bus_pkt->getAddr(), 104711051Sandreas.hansson@arm.com bus_pkt->isSecure() ? "s" : "ns"); 104811051Sandreas.hansson@arm.com 104911051Sandreas.hansson@arm.com#if TRACING_ON 105011051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 105111051Sandreas.hansson@arm.com#endif 105211051Sandreas.hansson@arm.com 105311051Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt)); 105411051Sandreas.hansson@arm.com 105511051Sandreas.hansson@arm.com // We are now dealing with the response handling 105611051Sandreas.hansson@arm.com DPRINTF(Cache, "Receive response: %s for addr %#llx (%s) in state %i\n", 105711051Sandreas.hansson@arm.com bus_pkt->cmdString(), bus_pkt->getAddr(), 105811051Sandreas.hansson@arm.com bus_pkt->isSecure() ? "s" : "ns", 105911051Sandreas.hansson@arm.com old_state); 106011051Sandreas.hansson@arm.com 106111051Sandreas.hansson@arm.com // If packet was a forward, the response (if any) is already 106211051Sandreas.hansson@arm.com // in place in the bus_pkt == pkt structure, so we don't need 106311051Sandreas.hansson@arm.com // to do anything. Otherwise, use the separate bus_pkt to 106411051Sandreas.hansson@arm.com // generate response to pkt and then delete it. 106511051Sandreas.hansson@arm.com if (!is_forward) { 106611051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 106711051Sandreas.hansson@arm.com assert(bus_pkt->isResponse()); 106811051Sandreas.hansson@arm.com if (bus_pkt->isError()) { 106911051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 107011051Sandreas.hansson@arm.com pkt->copyError(bus_pkt); 107111051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::InvalidateReq) { 107211051Sandreas.hansson@arm.com if (blk) { 107311051Sandreas.hansson@arm.com // invalidate response to a cache that received 107411051Sandreas.hansson@arm.com // an invalidate request 107511051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 107611051Sandreas.hansson@arm.com } 107711051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::WriteLineReq) { 107811051Sandreas.hansson@arm.com // note the use of pkt, not bus_pkt here. 107911051Sandreas.hansson@arm.com 108011051Sandreas.hansson@arm.com // write-line request to the cache that promoted 108111051Sandreas.hansson@arm.com // the write to a whole line 108211197Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks, 108311197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 108411051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 108511051Sandreas.hansson@arm.com } else if (bus_pkt->isRead() || 108611051Sandreas.hansson@arm.com bus_pkt->cmd == MemCmd::UpgradeResp) { 108711051Sandreas.hansson@arm.com // we're updating cache state to allow us to 108811051Sandreas.hansson@arm.com // satisfy the upstream request from the cache 108911197Sandreas.hansson@arm.com blk = handleFill(bus_pkt, blk, writebacks, 109011197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 109111051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 109211051Sandreas.hansson@arm.com } else { 109311051Sandreas.hansson@arm.com // we're satisfying the upstream request without 109411051Sandreas.hansson@arm.com // modifying cache state, e.g., a write-through 109511051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 109611051Sandreas.hansson@arm.com } 109711051Sandreas.hansson@arm.com } 109811051Sandreas.hansson@arm.com delete bus_pkt; 109911051Sandreas.hansson@arm.com } 110011051Sandreas.hansson@arm.com } 110111051Sandreas.hansson@arm.com 110211051Sandreas.hansson@arm.com // Note that we don't invoke the prefetcher at all in atomic mode. 110311051Sandreas.hansson@arm.com // It's not clear how to do it properly, particularly for 110411051Sandreas.hansson@arm.com // prefetchers that aggressively generate prefetch candidates and 110511051Sandreas.hansson@arm.com // rely on bandwidth contention to throttle them; these will tend 110611051Sandreas.hansson@arm.com // to pollute the cache in atomic mode since there is no bandwidth 110711051Sandreas.hansson@arm.com // contention. If we ever do want to enable prefetching in atomic 110811051Sandreas.hansson@arm.com // mode, though, this is the place to do it... see timingAccess() 110911051Sandreas.hansson@arm.com // for an example (though we'd want to issue the prefetch(es) 111011051Sandreas.hansson@arm.com // immediately rather than calling requestMemSideBus() as we do 111111051Sandreas.hansson@arm.com // there). 111211051Sandreas.hansson@arm.com 111311197Sandreas.hansson@arm.com // do any writebacks resulting from the response handling 111411130Sali.jafri@arm.com doWritebacksAtomic(writebacks); 111511051Sandreas.hansson@arm.com 111611197Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and if so 111711197Sandreas.hansson@arm.com // clear it out, but only do so after the call to recvAtomic is 111811197Sandreas.hansson@arm.com // finished so that any downstream observers (such as a snoop 111911197Sandreas.hansson@arm.com // filter), first see the fill, and only then see the eviction 112011197Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 112111197Sandreas.hansson@arm.com // the atomic CPU calls recvAtomic for fetch and load/store 112211197Sandreas.hansson@arm.com // sequentuially, and we may already have a tempBlock 112311197Sandreas.hansson@arm.com // writeback from the fetch that we have not yet sent 112411197Sandreas.hansson@arm.com if (tempBlockWriteback) { 112511197Sandreas.hansson@arm.com // if that is the case, write the prevoius one back, and 112611197Sandreas.hansson@arm.com // do not schedule any new event 112711197Sandreas.hansson@arm.com writebackTempBlockAtomic(); 112811197Sandreas.hansson@arm.com } else { 112911197Sandreas.hansson@arm.com // the writeback/clean eviction happens after the call to 113011197Sandreas.hansson@arm.com // recvAtomic has finished (but before any successive 113111197Sandreas.hansson@arm.com // calls), so that the response handling from the fill is 113211197Sandreas.hansson@arm.com // allowed to happen first 113311197Sandreas.hansson@arm.com schedule(writebackTempBlockAtomicEvent, curTick()); 113411197Sandreas.hansson@arm.com } 113511197Sandreas.hansson@arm.com 113611199Sandreas.hansson@arm.com tempBlockWriteback = (blk->isDirty() || writebackClean) ? 113711199Sandreas.hansson@arm.com writebackBlk(blk) : cleanEvictBlk(blk); 113811197Sandreas.hansson@arm.com blk->invalidate(); 113911197Sandreas.hansson@arm.com } 114011197Sandreas.hansson@arm.com 114111051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 114211051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 114311051Sandreas.hansson@arm.com } 114411051Sandreas.hansson@arm.com 114511051Sandreas.hansson@arm.com return lat * clockPeriod(); 114611051Sandreas.hansson@arm.com} 114711051Sandreas.hansson@arm.com 114811051Sandreas.hansson@arm.com 114911051Sandreas.hansson@arm.comvoid 115011051Sandreas.hansson@arm.comCache::functionalAccess(PacketPtr pkt, bool fromCpuSide) 115111051Sandreas.hansson@arm.com{ 115211051Sandreas.hansson@arm.com if (system->bypassCaches()) { 115311051Sandreas.hansson@arm.com // Packets from the memory side are snoop request and 115411051Sandreas.hansson@arm.com // shouldn't happen in bypass mode. 115511051Sandreas.hansson@arm.com assert(fromCpuSide); 115611051Sandreas.hansson@arm.com 115711051Sandreas.hansson@arm.com // The cache should be flushed if we are in cache bypass mode, 115811051Sandreas.hansson@arm.com // so we don't need to check if we need to update anything. 115911051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 116011051Sandreas.hansson@arm.com return; 116111051Sandreas.hansson@arm.com } 116211051Sandreas.hansson@arm.com 116311051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 116411051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 116511051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 116611051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 116711051Sandreas.hansson@arm.com 116811051Sandreas.hansson@arm.com pkt->pushLabel(name()); 116911051Sandreas.hansson@arm.com 117011051Sandreas.hansson@arm.com CacheBlkPrintWrapper cbpw(blk); 117111051Sandreas.hansson@arm.com 117211051Sandreas.hansson@arm.com // Note that just because an L2/L3 has valid data doesn't mean an 117311051Sandreas.hansson@arm.com // L1 doesn't have a more up-to-date modified copy that still 117411051Sandreas.hansson@arm.com // needs to be found. As a result we always update the request if 117511051Sandreas.hansson@arm.com // we have it, but only declare it satisfied if we are the owner. 117611051Sandreas.hansson@arm.com 117711051Sandreas.hansson@arm.com // see if we have data at all (owned or otherwise) 117811051Sandreas.hansson@arm.com bool have_data = blk && blk->isValid() 117911051Sandreas.hansson@arm.com && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize, 118011051Sandreas.hansson@arm.com blk->data); 118111051Sandreas.hansson@arm.com 118211284Sandreas.hansson@arm.com // data we have is dirty if marked as such or if we have an 118311284Sandreas.hansson@arm.com // in-service MSHR that is pending a modified line 118411051Sandreas.hansson@arm.com bool have_dirty = 118511051Sandreas.hansson@arm.com have_data && (blk->isDirty() || 118611284Sandreas.hansson@arm.com (mshr && mshr->inService && mshr->isPendingModified())); 118711051Sandreas.hansson@arm.com 118811051Sandreas.hansson@arm.com bool done = have_dirty 118911051Sandreas.hansson@arm.com || cpuSidePort->checkFunctional(pkt) 119011051Sandreas.hansson@arm.com || mshrQueue.checkFunctional(pkt, blk_addr) 119111051Sandreas.hansson@arm.com || writeBuffer.checkFunctional(pkt, blk_addr) 119211051Sandreas.hansson@arm.com || memSidePort->checkFunctional(pkt); 119311051Sandreas.hansson@arm.com 119411288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "functional %s %#llx (%s) %s%s%s\n", 119511051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), is_secure ? "s" : "ns", 119611051Sandreas.hansson@arm.com (blk && blk->isValid()) ? "valid " : "", 119711051Sandreas.hansson@arm.com have_data ? "data " : "", done ? "done " : ""); 119811051Sandreas.hansson@arm.com 119911051Sandreas.hansson@arm.com // We're leaving the cache, so pop cache->name() label 120011051Sandreas.hansson@arm.com pkt->popLabel(); 120111051Sandreas.hansson@arm.com 120211051Sandreas.hansson@arm.com if (done) { 120311051Sandreas.hansson@arm.com pkt->makeResponse(); 120411051Sandreas.hansson@arm.com } else { 120511051Sandreas.hansson@arm.com // if it came as a request from the CPU side then make sure it 120611051Sandreas.hansson@arm.com // continues towards the memory side 120711051Sandreas.hansson@arm.com if (fromCpuSide) { 120811051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 120911051Sandreas.hansson@arm.com } else if (forwardSnoops && cpuSidePort->isSnooping()) { 121011051Sandreas.hansson@arm.com // if it came from the memory side, it must be a snoop request 121111051Sandreas.hansson@arm.com // and we should only forward it if we are forwarding snoops 121211051Sandreas.hansson@arm.com cpuSidePort->sendFunctionalSnoop(pkt); 121311051Sandreas.hansson@arm.com } 121411051Sandreas.hansson@arm.com } 121511051Sandreas.hansson@arm.com} 121611051Sandreas.hansson@arm.com 121711051Sandreas.hansson@arm.com 121811051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 121911051Sandreas.hansson@arm.com// 122011051Sandreas.hansson@arm.com// Response handling: responses from the memory side 122111051Sandreas.hansson@arm.com// 122211051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 122311051Sandreas.hansson@arm.com 122411051Sandreas.hansson@arm.com 122511051Sandreas.hansson@arm.comvoid 122611375Sandreas.hansson@arm.comCache::handleUncacheableWriteResp(PacketPtr pkt) 122711375Sandreas.hansson@arm.com{ 122811375Sandreas.hansson@arm.com WriteQueueEntry *wq_entry = 122911375Sandreas.hansson@arm.com dynamic_cast<WriteQueueEntry*>(pkt->senderState); 123011375Sandreas.hansson@arm.com assert(wq_entry); 123111375Sandreas.hansson@arm.com 123211375Sandreas.hansson@arm.com WriteQueueEntry::Target *target = wq_entry->getTarget(); 123311375Sandreas.hansson@arm.com Packet *tgt_pkt = target->pkt; 123411375Sandreas.hansson@arm.com 123511375Sandreas.hansson@arm.com // we send out invalidation reqs and get invalidation 123611375Sandreas.hansson@arm.com // responses for write-line requests 123711375Sandreas.hansson@arm.com assert(tgt_pkt->cmd != MemCmd::WriteLineReq); 123811375Sandreas.hansson@arm.com 123911375Sandreas.hansson@arm.com int stats_cmd_idx = tgt_pkt->cmdToIndex(); 124011375Sandreas.hansson@arm.com Tick miss_latency = curTick() - target->recvTime; 124111375Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 124211375Sandreas.hansson@arm.com mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 124311375Sandreas.hansson@arm.com miss_latency; 124411375Sandreas.hansson@arm.com 124511375Sandreas.hansson@arm.com tgt_pkt->makeTimingResponse(); 124611375Sandreas.hansson@arm.com // if this packet is an error copy that to the new packet 124711375Sandreas.hansson@arm.com if (pkt->isError()) 124811375Sandreas.hansson@arm.com tgt_pkt->copyError(pkt); 124911375Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 125011375Sandreas.hansson@arm.com tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; 125111375Sandreas.hansson@arm.com Tick completion_time = clockEdge(responseLatency) + 125211375Sandreas.hansson@arm.com pkt->headerDelay + pkt->payloadDelay; 125311375Sandreas.hansson@arm.com 125411375Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true); 125511375Sandreas.hansson@arm.com 125611375Sandreas.hansson@arm.com wq_entry->popTarget(); 125711375Sandreas.hansson@arm.com assert(!wq_entry->hasTargets()); 125811375Sandreas.hansson@arm.com 125911375Sandreas.hansson@arm.com bool wasFull = writeBuffer.isFull(); 126011375Sandreas.hansson@arm.com writeBuffer.deallocate(wq_entry); 126111375Sandreas.hansson@arm.com 126211375Sandreas.hansson@arm.com if (wasFull && !writeBuffer.isFull()) { 126311375Sandreas.hansson@arm.com clearBlocked(Blocked_NoWBBuffers); 126411375Sandreas.hansson@arm.com } 126511375Sandreas.hansson@arm.com 126611375Sandreas.hansson@arm.com delete pkt; 126711375Sandreas.hansson@arm.com} 126811375Sandreas.hansson@arm.com 126911375Sandreas.hansson@arm.comvoid 127011051Sandreas.hansson@arm.comCache::recvTimingResp(PacketPtr pkt) 127111051Sandreas.hansson@arm.com{ 127211051Sandreas.hansson@arm.com assert(pkt->isResponse()); 127311051Sandreas.hansson@arm.com 127411051Sandreas.hansson@arm.com // all header delay should be paid for by the crossbar, unless 127511051Sandreas.hansson@arm.com // this is a prefetch response from above 127611051Sandreas.hansson@arm.com panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 127711051Sandreas.hansson@arm.com "%s saw a non-zero packet delay\n", name()); 127811051Sandreas.hansson@arm.com 127911051Sandreas.hansson@arm.com bool is_error = pkt->isError(); 128011051Sandreas.hansson@arm.com 128111051Sandreas.hansson@arm.com if (is_error) { 128211051Sandreas.hansson@arm.com DPRINTF(Cache, "Cache received packet with error for addr %#llx (%s), " 128311051Sandreas.hansson@arm.com "cmd: %s\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns", 128411051Sandreas.hansson@arm.com pkt->cmdString()); 128511051Sandreas.hansson@arm.com } 128611051Sandreas.hansson@arm.com 128711051Sandreas.hansson@arm.com DPRINTF(Cache, "Handling response %s for addr %#llx size %d (%s)\n", 128811051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize(), 128911051Sandreas.hansson@arm.com pkt->isSecure() ? "s" : "ns"); 129011051Sandreas.hansson@arm.com 129111375Sandreas.hansson@arm.com // if this is a write, we should be looking at an uncacheable 129211375Sandreas.hansson@arm.com // write 129311375Sandreas.hansson@arm.com if (pkt->isWrite()) { 129411375Sandreas.hansson@arm.com assert(pkt->req->isUncacheable()); 129511375Sandreas.hansson@arm.com handleUncacheableWriteResp(pkt); 129611375Sandreas.hansson@arm.com return; 129711375Sandreas.hansson@arm.com } 129811375Sandreas.hansson@arm.com 129911375Sandreas.hansson@arm.com // we have dealt with any (uncacheable) writes above, from here on 130011375Sandreas.hansson@arm.com // we know we are dealing with an MSHR due to a miss or a prefetch 130111375Sandreas.hansson@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState); 130211375Sandreas.hansson@arm.com assert(mshr); 130311051Sandreas.hansson@arm.com 130411051Sandreas.hansson@arm.com if (mshr == noTargetMSHR) { 130511051Sandreas.hansson@arm.com // we always clear at least one target 130611051Sandreas.hansson@arm.com clearBlocked(Blocked_NoTargets); 130711051Sandreas.hansson@arm.com noTargetMSHR = NULL; 130811051Sandreas.hansson@arm.com } 130911051Sandreas.hansson@arm.com 131011051Sandreas.hansson@arm.com // Initial target is used just for stats 131111051Sandreas.hansson@arm.com MSHR::Target *initial_tgt = mshr->getTarget(); 131211051Sandreas.hansson@arm.com int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 131311051Sandreas.hansson@arm.com Tick miss_latency = curTick() - initial_tgt->recvTime; 131411051Sandreas.hansson@arm.com 131511051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 131611051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 131711051Sandreas.hansson@arm.com mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 131811051Sandreas.hansson@arm.com miss_latency; 131911051Sandreas.hansson@arm.com } else { 132011051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 132111051Sandreas.hansson@arm.com mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 132211051Sandreas.hansson@arm.com miss_latency; 132311051Sandreas.hansson@arm.com } 132411051Sandreas.hansson@arm.com 132511375Sandreas.hansson@arm.com bool wasFull = mshrQueue.isFull(); 132611375Sandreas.hansson@arm.com 132711375Sandreas.hansson@arm.com PacketList writebacks; 132811375Sandreas.hansson@arm.com 132911375Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 133011375Sandreas.hansson@arm.com 133111284Sandreas.hansson@arm.com // upgrade deferred targets if the response has no sharers, and is 133211284Sandreas.hansson@arm.com // thus passing writable 133311284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 133411284Sandreas.hansson@arm.com mshr->promoteWritable(); 133511177Sandreas.hansson@arm.com } 133611177Sandreas.hansson@arm.com 133711051Sandreas.hansson@arm.com bool is_fill = !mshr->isForward && 133811051Sandreas.hansson@arm.com (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp); 133911051Sandreas.hansson@arm.com 134011177Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 134111177Sandreas.hansson@arm.com 134211051Sandreas.hansson@arm.com if (is_fill && !is_error) { 134311051Sandreas.hansson@arm.com DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 134411051Sandreas.hansson@arm.com pkt->getAddr()); 134511051Sandreas.hansson@arm.com 134611197Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill); 134711051Sandreas.hansson@arm.com assert(blk != NULL); 134811051Sandreas.hansson@arm.com } 134911051Sandreas.hansson@arm.com 135011051Sandreas.hansson@arm.com // allow invalidation responses originating from write-line 135111051Sandreas.hansson@arm.com // requests to be discarded 135211136Sandreas.hansson@arm.com bool is_invalidate = pkt->isInvalidate(); 135311051Sandreas.hansson@arm.com 135411051Sandreas.hansson@arm.com // First offset for critical word first calculations 135511051Sandreas.hansson@arm.com int initial_offset = initial_tgt->pkt->getOffset(blkSize); 135611051Sandreas.hansson@arm.com 135711051Sandreas.hansson@arm.com while (mshr->hasTargets()) { 135811051Sandreas.hansson@arm.com MSHR::Target *target = mshr->getTarget(); 135911051Sandreas.hansson@arm.com Packet *tgt_pkt = target->pkt; 136011051Sandreas.hansson@arm.com 136111051Sandreas.hansson@arm.com switch (target->source) { 136211051Sandreas.hansson@arm.com case MSHR::Target::FromCPU: 136311051Sandreas.hansson@arm.com Tick completion_time; 136411051Sandreas.hansson@arm.com // Here we charge on completion_time the delay of the xbar if the 136511051Sandreas.hansson@arm.com // packet comes from it, charged on headerDelay. 136611051Sandreas.hansson@arm.com completion_time = pkt->headerDelay; 136711051Sandreas.hansson@arm.com 136811051Sandreas.hansson@arm.com // Software prefetch handling for cache closest to core 136911051Sandreas.hansson@arm.com if (tgt_pkt->cmd.isSWPrefetch()) { 137011051Sandreas.hansson@arm.com // a software prefetch would have already been ack'd immediately 137111051Sandreas.hansson@arm.com // with dummy data so the core would be able to retire it. 137211051Sandreas.hansson@arm.com // this request completes right here, so we deallocate it. 137311051Sandreas.hansson@arm.com delete tgt_pkt->req; 137411051Sandreas.hansson@arm.com delete tgt_pkt; 137511051Sandreas.hansson@arm.com break; // skip response 137611051Sandreas.hansson@arm.com } 137711051Sandreas.hansson@arm.com 137811051Sandreas.hansson@arm.com // unlike the other packet flows, where data is found in other 137911051Sandreas.hansson@arm.com // caches or memory and brought back, write-line requests always 138011051Sandreas.hansson@arm.com // have the data right away, so the above check for "is fill?" 138111051Sandreas.hansson@arm.com // cannot actually be determined until examining the stored MSHR 138211051Sandreas.hansson@arm.com // state. We "catch up" with that logic here, which is duplicated 138311051Sandreas.hansson@arm.com // from above. 138411051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::WriteLineReq) { 138511051Sandreas.hansson@arm.com assert(!is_error); 138611284Sandreas.hansson@arm.com // we got the block in a writable state, so promote 138711284Sandreas.hansson@arm.com // any deferred targets if possible 138811284Sandreas.hansson@arm.com mshr->promoteWritable(); 138911051Sandreas.hansson@arm.com // NB: we use the original packet here and not the response! 139011197Sandreas.hansson@arm.com blk = handleFill(tgt_pkt, blk, writebacks, mshr->allocOnFill); 139111051Sandreas.hansson@arm.com assert(blk != NULL); 139211051Sandreas.hansson@arm.com 139311051Sandreas.hansson@arm.com // treat as a fill, and discard the invalidation 139411051Sandreas.hansson@arm.com // response 139511051Sandreas.hansson@arm.com is_fill = true; 139611136Sandreas.hansson@arm.com is_invalidate = false; 139711051Sandreas.hansson@arm.com } 139811051Sandreas.hansson@arm.com 139911051Sandreas.hansson@arm.com if (is_fill) { 140011051Sandreas.hansson@arm.com satisfyCpuSideRequest(tgt_pkt, blk, 140111051Sandreas.hansson@arm.com true, mshr->hasPostDowngrade()); 140211051Sandreas.hansson@arm.com 140311051Sandreas.hansson@arm.com // How many bytes past the first request is this one 140411051Sandreas.hansson@arm.com int transfer_offset = 140511051Sandreas.hansson@arm.com tgt_pkt->getOffset(blkSize) - initial_offset; 140611051Sandreas.hansson@arm.com if (transfer_offset < 0) { 140711051Sandreas.hansson@arm.com transfer_offset += blkSize; 140811051Sandreas.hansson@arm.com } 140911051Sandreas.hansson@arm.com 141011051Sandreas.hansson@arm.com // If not critical word (offset) return payloadDelay. 141111051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 141211051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 141311051Sandreas.hansson@arm.com // the core. 141411051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 141511051Sandreas.hansson@arm.com (transfer_offset ? pkt->payloadDelay : 0); 141611051Sandreas.hansson@arm.com 141711051Sandreas.hansson@arm.com assert(!tgt_pkt->req->isUncacheable()); 141811051Sandreas.hansson@arm.com 141911051Sandreas.hansson@arm.com assert(tgt_pkt->req->masterId() < system->maxMasters()); 142011051Sandreas.hansson@arm.com missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] += 142111051Sandreas.hansson@arm.com completion_time - target->recvTime; 142211051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::UpgradeFailResp) { 142311051Sandreas.hansson@arm.com // failed StoreCond upgrade 142411051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::StoreCondReq || 142511051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::StoreCondFailReq || 142611051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::SCUpgradeFailReq); 142711051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 142811051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 142911051Sandreas.hansson@arm.com // the core. 143011051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 143111051Sandreas.hansson@arm.com pkt->payloadDelay; 143211051Sandreas.hansson@arm.com tgt_pkt->req->setExtraData(0); 143311051Sandreas.hansson@arm.com } else { 143411051Sandreas.hansson@arm.com // not a cache fill, just forwarding response 143511051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 143611051Sandreas.hansson@arm.com // from lower level cahces/memory to the core. 143711051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 143811051Sandreas.hansson@arm.com pkt->payloadDelay; 143911051Sandreas.hansson@arm.com if (pkt->isRead() && !is_error) { 144011051Sandreas.hansson@arm.com // sanity check 144111051Sandreas.hansson@arm.com assert(pkt->getAddr() == tgt_pkt->getAddr()); 144211051Sandreas.hansson@arm.com assert(pkt->getSize() >= tgt_pkt->getSize()); 144311051Sandreas.hansson@arm.com 144411051Sandreas.hansson@arm.com tgt_pkt->setData(pkt->getConstPtr<uint8_t>()); 144511051Sandreas.hansson@arm.com } 144611051Sandreas.hansson@arm.com } 144711051Sandreas.hansson@arm.com tgt_pkt->makeTimingResponse(); 144811051Sandreas.hansson@arm.com // if this packet is an error copy that to the new packet 144911051Sandreas.hansson@arm.com if (is_error) 145011051Sandreas.hansson@arm.com tgt_pkt->copyError(pkt); 145111051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::ReadResp && 145211136Sandreas.hansson@arm.com (is_invalidate || mshr->hasPostInvalidate())) { 145311051Sandreas.hansson@arm.com // If intermediate cache got ReadRespWithInvalidate, 145411051Sandreas.hansson@arm.com // propagate that. Response should not have 145511051Sandreas.hansson@arm.com // isInvalidate() set otherwise. 145611051Sandreas.hansson@arm.com tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate; 145711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s updated cmd to %s for addr %#llx\n", 145811051Sandreas.hansson@arm.com __func__, tgt_pkt->cmdString(), tgt_pkt->getAddr()); 145911051Sandreas.hansson@arm.com } 146011051Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 146111051Sandreas.hansson@arm.com tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; 146211194Sali.jafri@arm.com cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true); 146311051Sandreas.hansson@arm.com break; 146411051Sandreas.hansson@arm.com 146511051Sandreas.hansson@arm.com case MSHR::Target::FromPrefetcher: 146611051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::HardPFReq); 146711051Sandreas.hansson@arm.com if (blk) 146811051Sandreas.hansson@arm.com blk->status |= BlkHWPrefetched; 146911051Sandreas.hansson@arm.com delete tgt_pkt->req; 147011051Sandreas.hansson@arm.com delete tgt_pkt; 147111051Sandreas.hansson@arm.com break; 147211051Sandreas.hansson@arm.com 147311051Sandreas.hansson@arm.com case MSHR::Target::FromSnoop: 147411051Sandreas.hansson@arm.com // I don't believe that a snoop can be in an error state 147511051Sandreas.hansson@arm.com assert(!is_error); 147611051Sandreas.hansson@arm.com // response to snoop request 147711051Sandreas.hansson@arm.com DPRINTF(Cache, "processing deferred snoop...\n"); 147811136Sandreas.hansson@arm.com assert(!(is_invalidate && !mshr->hasPostInvalidate())); 147911051Sandreas.hansson@arm.com handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate()); 148011051Sandreas.hansson@arm.com break; 148111051Sandreas.hansson@arm.com 148211051Sandreas.hansson@arm.com default: 148311051Sandreas.hansson@arm.com panic("Illegal target->source enum %d\n", target->source); 148411051Sandreas.hansson@arm.com } 148511051Sandreas.hansson@arm.com 148611051Sandreas.hansson@arm.com mshr->popTarget(); 148711051Sandreas.hansson@arm.com } 148811051Sandreas.hansson@arm.com 148911051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 149011051Sandreas.hansson@arm.com // an invalidate response stemming from a write line request 149111051Sandreas.hansson@arm.com // should not invalidate the block, so check if the 149211051Sandreas.hansson@arm.com // invalidation should be discarded 149311136Sandreas.hansson@arm.com if (is_invalidate || mshr->hasPostInvalidate()) { 149411197Sandreas.hansson@arm.com invalidateBlock(blk); 149511051Sandreas.hansson@arm.com } else if (mshr->hasPostDowngrade()) { 149611051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 149711051Sandreas.hansson@arm.com } 149811051Sandreas.hansson@arm.com } 149911051Sandreas.hansson@arm.com 150011051Sandreas.hansson@arm.com if (mshr->promoteDeferredTargets()) { 150111051Sandreas.hansson@arm.com // avoid later read getting stale data while write miss is 150211051Sandreas.hansson@arm.com // outstanding.. see comment in timingAccess() 150311051Sandreas.hansson@arm.com if (blk) { 150411051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 150511051Sandreas.hansson@arm.com } 150611375Sandreas.hansson@arm.com mshrQueue.markPending(mshr); 150711051Sandreas.hansson@arm.com schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 150811051Sandreas.hansson@arm.com } else { 150911375Sandreas.hansson@arm.com mshrQueue.deallocate(mshr); 151011375Sandreas.hansson@arm.com if (wasFull && !mshrQueue.isFull()) { 151111375Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 151211051Sandreas.hansson@arm.com } 151311051Sandreas.hansson@arm.com 151411051Sandreas.hansson@arm.com // Request the bus for a prefetch if this deallocation freed enough 151511051Sandreas.hansson@arm.com // MSHRs for a prefetch to take place 151611375Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 151711051Sandreas.hansson@arm.com Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 151811051Sandreas.hansson@arm.com clockEdge()); 151911051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 152011051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 152111051Sandreas.hansson@arm.com } 152211051Sandreas.hansson@arm.com } 152311051Sandreas.hansson@arm.com // reset the xbar additional timinig as it is now accounted for 152411051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 152511051Sandreas.hansson@arm.com 152611051Sandreas.hansson@arm.com // copy writebacks to write buffer 152711051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 152811051Sandreas.hansson@arm.com 152911051Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and then clear it out 153011051Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 153111051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying 153211051Sandreas.hansson@arm.com // Writebacks/CleanEvicts to write buffer. It specifies the latency to 153311051Sandreas.hansson@arm.com // allocate an internal buffer and to schedule an event to the 153411051Sandreas.hansson@arm.com // queued port. 153511199Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 153611051Sandreas.hansson@arm.com PacketPtr wbPkt = writebackBlk(blk); 153711051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 153811051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag if cached above. 153911051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) 154011051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 154111051Sandreas.hansson@arm.com } else { 154211051Sandreas.hansson@arm.com PacketPtr wcPkt = cleanEvictBlk(blk); 154311051Sandreas.hansson@arm.com // Check to see if block is cached above. If not allocate 154411051Sandreas.hansson@arm.com // write buffer 154511051Sandreas.hansson@arm.com if (isCachedAbove(wcPkt)) 154611051Sandreas.hansson@arm.com delete wcPkt; 154711051Sandreas.hansson@arm.com else 154811051Sandreas.hansson@arm.com allocateWriteBuffer(wcPkt, forward_time); 154911051Sandreas.hansson@arm.com } 155011051Sandreas.hansson@arm.com blk->invalidate(); 155111051Sandreas.hansson@arm.com } 155211051Sandreas.hansson@arm.com 155311288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "Leaving %s with %s for addr %#llx\n", __func__, 155411051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 155511051Sandreas.hansson@arm.com delete pkt; 155611051Sandreas.hansson@arm.com} 155711051Sandreas.hansson@arm.com 155811051Sandreas.hansson@arm.comPacketPtr 155911051Sandreas.hansson@arm.comCache::writebackBlk(CacheBlk *blk) 156011051Sandreas.hansson@arm.com{ 156111199Sandreas.hansson@arm.com chatty_assert(!isReadOnly || writebackClean, 156211199Sandreas.hansson@arm.com "Writeback from read-only cache"); 156311199Sandreas.hansson@arm.com assert(blk && blk->isValid() && (blk->isDirty() || writebackClean)); 156411051Sandreas.hansson@arm.com 156511051Sandreas.hansson@arm.com writebacks[Request::wbMasterId]++; 156611051Sandreas.hansson@arm.com 156711199Sandreas.hansson@arm.com Request *req = new Request(tags->regenerateBlkAddr(blk->tag, blk->set), 156811199Sandreas.hansson@arm.com blkSize, 0, Request::wbMasterId); 156911051Sandreas.hansson@arm.com if (blk->isSecure()) 157011199Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 157111051Sandreas.hansson@arm.com 157211199Sandreas.hansson@arm.com req->taskId(blk->task_id); 157311051Sandreas.hansson@arm.com blk->task_id= ContextSwitchTaskId::Unknown; 157411051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 157511051Sandreas.hansson@arm.com 157611199Sandreas.hansson@arm.com PacketPtr pkt = 157711199Sandreas.hansson@arm.com new Packet(req, blk->isDirty() ? 157811199Sandreas.hansson@arm.com MemCmd::WritebackDirty : MemCmd::WritebackClean); 157911199Sandreas.hansson@arm.com 158011199Sandreas.hansson@arm.com DPRINTF(Cache, "Create Writeback %#llx writable: %d, dirty: %d\n", 158111199Sandreas.hansson@arm.com pkt->getAddr(), blk->isWritable(), blk->isDirty()); 158211199Sandreas.hansson@arm.com 158311051Sandreas.hansson@arm.com if (blk->isWritable()) { 158411051Sandreas.hansson@arm.com // not asserting shared means we pass the block in modified 158511051Sandreas.hansson@arm.com // state, mark our own block non-writeable 158611051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 158711051Sandreas.hansson@arm.com } else { 158811284Sandreas.hansson@arm.com // we are in the Owned state, tell the receiver 158911284Sandreas.hansson@arm.com pkt->setHasSharers(); 159011051Sandreas.hansson@arm.com } 159111051Sandreas.hansson@arm.com 159211199Sandreas.hansson@arm.com // make sure the block is not marked dirty 159311199Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 159411051Sandreas.hansson@arm.com 159511199Sandreas.hansson@arm.com pkt->allocate(); 159611199Sandreas.hansson@arm.com std::memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize); 159711199Sandreas.hansson@arm.com 159811199Sandreas.hansson@arm.com return pkt; 159911051Sandreas.hansson@arm.com} 160011051Sandreas.hansson@arm.com 160111051Sandreas.hansson@arm.comPacketPtr 160211051Sandreas.hansson@arm.comCache::cleanEvictBlk(CacheBlk *blk) 160311051Sandreas.hansson@arm.com{ 160411199Sandreas.hansson@arm.com assert(!writebackClean); 160511051Sandreas.hansson@arm.com assert(blk && blk->isValid() && !blk->isDirty()); 160611051Sandreas.hansson@arm.com // Creating a zero sized write, a message to the snoop filter 160711051Sandreas.hansson@arm.com Request *req = 160811051Sandreas.hansson@arm.com new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0, 160911051Sandreas.hansson@arm.com Request::wbMasterId); 161011051Sandreas.hansson@arm.com if (blk->isSecure()) 161111051Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 161211051Sandreas.hansson@arm.com 161311051Sandreas.hansson@arm.com req->taskId(blk->task_id); 161411051Sandreas.hansson@arm.com blk->task_id = ContextSwitchTaskId::Unknown; 161511051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 161611051Sandreas.hansson@arm.com 161711051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::CleanEvict); 161811051Sandreas.hansson@arm.com pkt->allocate(); 161911051Sandreas.hansson@arm.com DPRINTF(Cache, "%s%s %x Create CleanEvict\n", pkt->cmdString(), 162011051Sandreas.hansson@arm.com pkt->req->isInstFetch() ? " (ifetch)" : "", 162111051Sandreas.hansson@arm.com pkt->getAddr()); 162211051Sandreas.hansson@arm.com 162311051Sandreas.hansson@arm.com return pkt; 162411051Sandreas.hansson@arm.com} 162511051Sandreas.hansson@arm.com 162611051Sandreas.hansson@arm.comvoid 162711051Sandreas.hansson@arm.comCache::memWriteback() 162811051Sandreas.hansson@arm.com{ 162911051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::writebackVisitor); 163011051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 163111051Sandreas.hansson@arm.com} 163211051Sandreas.hansson@arm.com 163311051Sandreas.hansson@arm.comvoid 163411051Sandreas.hansson@arm.comCache::memInvalidate() 163511051Sandreas.hansson@arm.com{ 163611051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::invalidateVisitor); 163711051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 163811051Sandreas.hansson@arm.com} 163911051Sandreas.hansson@arm.com 164011051Sandreas.hansson@arm.combool 164111051Sandreas.hansson@arm.comCache::isDirty() const 164211051Sandreas.hansson@arm.com{ 164311051Sandreas.hansson@arm.com CacheBlkIsDirtyVisitor visitor; 164411051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 164511051Sandreas.hansson@arm.com 164611051Sandreas.hansson@arm.com return visitor.isDirty(); 164711051Sandreas.hansson@arm.com} 164811051Sandreas.hansson@arm.com 164911051Sandreas.hansson@arm.combool 165011051Sandreas.hansson@arm.comCache::writebackVisitor(CacheBlk &blk) 165111051Sandreas.hansson@arm.com{ 165211051Sandreas.hansson@arm.com if (blk.isDirty()) { 165311051Sandreas.hansson@arm.com assert(blk.isValid()); 165411051Sandreas.hansson@arm.com 165511051Sandreas.hansson@arm.com Request request(tags->regenerateBlkAddr(blk.tag, blk.set), 165611051Sandreas.hansson@arm.com blkSize, 0, Request::funcMasterId); 165711051Sandreas.hansson@arm.com request.taskId(blk.task_id); 165811051Sandreas.hansson@arm.com 165911051Sandreas.hansson@arm.com Packet packet(&request, MemCmd::WriteReq); 166011051Sandreas.hansson@arm.com packet.dataStatic(blk.data); 166111051Sandreas.hansson@arm.com 166211051Sandreas.hansson@arm.com memSidePort->sendFunctional(&packet); 166311051Sandreas.hansson@arm.com 166411051Sandreas.hansson@arm.com blk.status &= ~BlkDirty; 166511051Sandreas.hansson@arm.com } 166611051Sandreas.hansson@arm.com 166711051Sandreas.hansson@arm.com return true; 166811051Sandreas.hansson@arm.com} 166911051Sandreas.hansson@arm.com 167011051Sandreas.hansson@arm.combool 167111051Sandreas.hansson@arm.comCache::invalidateVisitor(CacheBlk &blk) 167211051Sandreas.hansson@arm.com{ 167311051Sandreas.hansson@arm.com 167411051Sandreas.hansson@arm.com if (blk.isDirty()) 167511051Sandreas.hansson@arm.com warn_once("Invalidating dirty cache lines. Expect things to break.\n"); 167611051Sandreas.hansson@arm.com 167711051Sandreas.hansson@arm.com if (blk.isValid()) { 167811051Sandreas.hansson@arm.com assert(!blk.isDirty()); 167911051Sandreas.hansson@arm.com tags->invalidate(&blk); 168011051Sandreas.hansson@arm.com blk.invalidate(); 168111051Sandreas.hansson@arm.com } 168211051Sandreas.hansson@arm.com 168311051Sandreas.hansson@arm.com return true; 168411051Sandreas.hansson@arm.com} 168511051Sandreas.hansson@arm.com 168611051Sandreas.hansson@arm.comCacheBlk* 168711051Sandreas.hansson@arm.comCache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks) 168811051Sandreas.hansson@arm.com{ 168911051Sandreas.hansson@arm.com CacheBlk *blk = tags->findVictim(addr); 169011051Sandreas.hansson@arm.com 169111051Sandreas.hansson@arm.com // It is valid to return NULL if there is no victim 169211051Sandreas.hansson@arm.com if (!blk) 169311051Sandreas.hansson@arm.com return nullptr; 169411051Sandreas.hansson@arm.com 169511051Sandreas.hansson@arm.com if (blk->isValid()) { 169611051Sandreas.hansson@arm.com Addr repl_addr = tags->regenerateBlkAddr(blk->tag, blk->set); 169711051Sandreas.hansson@arm.com MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure()); 169811051Sandreas.hansson@arm.com if (repl_mshr) { 169911051Sandreas.hansson@arm.com // must be an outstanding upgrade request 170011051Sandreas.hansson@arm.com // on a block we're about to replace... 170111051Sandreas.hansson@arm.com assert(!blk->isWritable() || blk->isDirty()); 170211284Sandreas.hansson@arm.com assert(repl_mshr->needsWritable()); 170311051Sandreas.hansson@arm.com // too hard to replace block with transient state 170411051Sandreas.hansson@arm.com // allocation failed, block not inserted 170511051Sandreas.hansson@arm.com return NULL; 170611051Sandreas.hansson@arm.com } else { 170711051Sandreas.hansson@arm.com DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx (%s): %s\n", 170811051Sandreas.hansson@arm.com repl_addr, blk->isSecure() ? "s" : "ns", 170911051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", 171011051Sandreas.hansson@arm.com blk->isDirty() ? "writeback" : "clean"); 171111051Sandreas.hansson@arm.com 171211051Sandreas.hansson@arm.com // Will send up Writeback/CleanEvict snoops via isCachedAbove 171311051Sandreas.hansson@arm.com // when pushing this writeback list into the write buffer. 171411199Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 171511051Sandreas.hansson@arm.com // Save writeback packet for handling by caller 171611051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(blk)); 171711051Sandreas.hansson@arm.com } else { 171811051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(blk)); 171911051Sandreas.hansson@arm.com } 172011051Sandreas.hansson@arm.com } 172111051Sandreas.hansson@arm.com } 172211051Sandreas.hansson@arm.com 172311051Sandreas.hansson@arm.com return blk; 172411051Sandreas.hansson@arm.com} 172511051Sandreas.hansson@arm.com 172611197Sandreas.hansson@arm.comvoid 172711197Sandreas.hansson@arm.comCache::invalidateBlock(CacheBlk *blk) 172811197Sandreas.hansson@arm.com{ 172911197Sandreas.hansson@arm.com if (blk != tempBlock) 173011197Sandreas.hansson@arm.com tags->invalidate(blk); 173111197Sandreas.hansson@arm.com blk->invalidate(); 173211197Sandreas.hansson@arm.com} 173311051Sandreas.hansson@arm.com 173411051Sandreas.hansson@arm.com// Note that the reason we return a list of writebacks rather than 173511051Sandreas.hansson@arm.com// inserting them directly in the write buffer is that this function 173611051Sandreas.hansson@arm.com// is called by both atomic and timing-mode accesses, and in atomic 173711051Sandreas.hansson@arm.com// mode we don't mess with the write buffer (we just perform the 173811051Sandreas.hansson@arm.com// writebacks atomically once the original request is complete). 173911051Sandreas.hansson@arm.comCacheBlk* 174011197Sandreas.hansson@arm.comCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, 174111197Sandreas.hansson@arm.com bool allocate) 174211051Sandreas.hansson@arm.com{ 174311051Sandreas.hansson@arm.com assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq); 174411051Sandreas.hansson@arm.com Addr addr = pkt->getAddr(); 174511051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 174611051Sandreas.hansson@arm.com#if TRACING_ON 174711051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 174811051Sandreas.hansson@arm.com#endif 174911051Sandreas.hansson@arm.com 175011375Sandreas.hansson@arm.com // When handling a fill, we should have no writes to this line. 175111375Sandreas.hansson@arm.com assert(addr == blockAlign(addr)); 175211375Sandreas.hansson@arm.com assert(!writeBuffer.findMatch(addr, is_secure)); 175311051Sandreas.hansson@arm.com 175411051Sandreas.hansson@arm.com if (blk == NULL) { 175511051Sandreas.hansson@arm.com // better have read new data... 175611051Sandreas.hansson@arm.com assert(pkt->hasData()); 175711051Sandreas.hansson@arm.com 175811051Sandreas.hansson@arm.com // only read responses and write-line requests have data; 175911051Sandreas.hansson@arm.com // note that we don't write the data here for write-line - that 176011051Sandreas.hansson@arm.com // happens in the subsequent satisfyCpuSideRequest. 176111051Sandreas.hansson@arm.com assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq); 176211051Sandreas.hansson@arm.com 176311197Sandreas.hansson@arm.com // need to do a replacement if allocating, otherwise we stick 176411197Sandreas.hansson@arm.com // with the temporary storage 176511197Sandreas.hansson@arm.com blk = allocate ? allocateBlock(addr, is_secure, writebacks) : NULL; 176611197Sandreas.hansson@arm.com 176711051Sandreas.hansson@arm.com if (blk == NULL) { 176811197Sandreas.hansson@arm.com // No replaceable block or a mostly exclusive 176911197Sandreas.hansson@arm.com // cache... just use temporary storage to complete the 177011197Sandreas.hansson@arm.com // current request and then get rid of it 177111051Sandreas.hansson@arm.com assert(!tempBlock->isValid()); 177211051Sandreas.hansson@arm.com blk = tempBlock; 177311051Sandreas.hansson@arm.com tempBlock->set = tags->extractSet(addr); 177411051Sandreas.hansson@arm.com tempBlock->tag = tags->extractTag(addr); 177511051Sandreas.hansson@arm.com // @todo: set security state as well... 177611051Sandreas.hansson@arm.com DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr, 177711051Sandreas.hansson@arm.com is_secure ? "s" : "ns"); 177811051Sandreas.hansson@arm.com } else { 177911051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 178011051Sandreas.hansson@arm.com } 178111051Sandreas.hansson@arm.com 178211051Sandreas.hansson@arm.com // we should never be overwriting a valid block 178311051Sandreas.hansson@arm.com assert(!blk->isValid()); 178411051Sandreas.hansson@arm.com } else { 178511051Sandreas.hansson@arm.com // existing block... probably an upgrade 178611051Sandreas.hansson@arm.com assert(blk->tag == tags->extractTag(addr)); 178711051Sandreas.hansson@arm.com // either we're getting new data or the block should already be valid 178811051Sandreas.hansson@arm.com assert(pkt->hasData() || blk->isValid()); 178911051Sandreas.hansson@arm.com // don't clear block status... if block is already dirty we 179011051Sandreas.hansson@arm.com // don't want to lose that 179111051Sandreas.hansson@arm.com } 179211051Sandreas.hansson@arm.com 179311051Sandreas.hansson@arm.com if (is_secure) 179411051Sandreas.hansson@arm.com blk->status |= BlkSecure; 179511051Sandreas.hansson@arm.com blk->status |= BlkValid | BlkReadable; 179611051Sandreas.hansson@arm.com 179711137Sandreas.hansson@arm.com // sanity check for whole-line writes, which should always be 179811137Sandreas.hansson@arm.com // marked as writable as part of the fill, and then later marked 179911137Sandreas.hansson@arm.com // dirty as part of satisfyCpuSideRequest 180011137Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WriteLineReq) { 180111284Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 180211137Sandreas.hansson@arm.com // at the moment other caches do not respond to the 180311137Sandreas.hansson@arm.com // invalidation requests corresponding to a whole-line write 180411284Sandreas.hansson@arm.com assert(!pkt->cacheResponding()); 180511137Sandreas.hansson@arm.com } 180611137Sandreas.hansson@arm.com 180711284Sandreas.hansson@arm.com // here we deal with setting the appropriate state of the line, 180811284Sandreas.hansson@arm.com // and we start by looking at the hasSharers flag, and ignore the 180911284Sandreas.hansson@arm.com // cacheResponding flag (normally signalling dirty data) if the 181011284Sandreas.hansson@arm.com // packet has sharers, thus the line is never allocated as Owned 181111284Sandreas.hansson@arm.com // (dirty but not writable), and always ends up being either 181211284Sandreas.hansson@arm.com // Shared, Exclusive or Modified, see Packet::setCacheResponding 181311284Sandreas.hansson@arm.com // for more details 181411284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 181511284Sandreas.hansson@arm.com // we could get a writable line from memory (rather than a 181611284Sandreas.hansson@arm.com // cache) even in a read-only cache, note that we set this bit 181711284Sandreas.hansson@arm.com // even for a read-only cache, possibly revisit this decision 181811051Sandreas.hansson@arm.com blk->status |= BlkWritable; 181911051Sandreas.hansson@arm.com 182011284Sandreas.hansson@arm.com // check if we got this via cache-to-cache transfer (i.e., from a 182111284Sandreas.hansson@arm.com // cache that had the block in Modified or Owned state) 182211284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 182311284Sandreas.hansson@arm.com // we got the block in Modified state, and invalidated the 182411284Sandreas.hansson@arm.com // owners copy 182511051Sandreas.hansson@arm.com blk->status |= BlkDirty; 182611051Sandreas.hansson@arm.com 182711051Sandreas.hansson@arm.com chatty_assert(!isReadOnly, "Should never see dirty snoop response " 182811051Sandreas.hansson@arm.com "in read-only cache %s\n", name()); 182911051Sandreas.hansson@arm.com } 183011051Sandreas.hansson@arm.com } 183111051Sandreas.hansson@arm.com 183211051Sandreas.hansson@arm.com DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n", 183311051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", old_state, blk->print()); 183411051Sandreas.hansson@arm.com 183511051Sandreas.hansson@arm.com // if we got new data, copy it in (checking for a read response 183611051Sandreas.hansson@arm.com // and a response that has data is the same in the end) 183711051Sandreas.hansson@arm.com if (pkt->isRead()) { 183811051Sandreas.hansson@arm.com // sanity checks 183911051Sandreas.hansson@arm.com assert(pkt->hasData()); 184011051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 184111051Sandreas.hansson@arm.com 184211051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 184311051Sandreas.hansson@arm.com } 184411051Sandreas.hansson@arm.com // We pay for fillLatency here. 184511051Sandreas.hansson@arm.com blk->whenReady = clockEdge() + fillLatency * clockPeriod() + 184611051Sandreas.hansson@arm.com pkt->payloadDelay; 184711051Sandreas.hansson@arm.com 184811051Sandreas.hansson@arm.com return blk; 184911051Sandreas.hansson@arm.com} 185011051Sandreas.hansson@arm.com 185111051Sandreas.hansson@arm.com 185211051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 185311051Sandreas.hansson@arm.com// 185411051Sandreas.hansson@arm.com// Snoop path: requests coming in from the memory side 185511051Sandreas.hansson@arm.com// 185611051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 185711051Sandreas.hansson@arm.com 185811051Sandreas.hansson@arm.comvoid 185911051Sandreas.hansson@arm.comCache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 186011051Sandreas.hansson@arm.com bool already_copied, bool pending_inval) 186111051Sandreas.hansson@arm.com{ 186211051Sandreas.hansson@arm.com // sanity check 186311051Sandreas.hansson@arm.com assert(req_pkt->isRequest()); 186411051Sandreas.hansson@arm.com assert(req_pkt->needsResponse()); 186511051Sandreas.hansson@arm.com 186611051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 186711051Sandreas.hansson@arm.com req_pkt->cmdString(), req_pkt->getAddr(), req_pkt->getSize()); 186811051Sandreas.hansson@arm.com // timing-mode snoop responses require a new packet, unless we 186911051Sandreas.hansson@arm.com // already made a copy... 187011051Sandreas.hansson@arm.com PacketPtr pkt = req_pkt; 187111051Sandreas.hansson@arm.com if (!already_copied) 187211051Sandreas.hansson@arm.com // do not clear flags, and allocate space for data if the 187311051Sandreas.hansson@arm.com // packet needs it (the only packets that carry data are read 187411051Sandreas.hansson@arm.com // responses) 187511051Sandreas.hansson@arm.com pkt = new Packet(req_pkt, false, req_pkt->isRead()); 187611051Sandreas.hansson@arm.com 187711051Sandreas.hansson@arm.com assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() || 187811284Sandreas.hansson@arm.com pkt->hasSharers()); 187911051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 188011051Sandreas.hansson@arm.com if (pkt->isRead()) { 188111051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk_data, blkSize); 188211051Sandreas.hansson@arm.com } 188311051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadResp && pending_inval) { 188411051Sandreas.hansson@arm.com // Assume we defer a response to a read from a far-away cache 188511051Sandreas.hansson@arm.com // A, then later defer a ReadExcl from a cache B on the same 188611284Sandreas.hansson@arm.com // bus as us. We'll assert cacheResponding in both cases, but 188711284Sandreas.hansson@arm.com // in the latter case cacheResponding will keep the 188811284Sandreas.hansson@arm.com // invalidation from reaching cache A. This special response 188911284Sandreas.hansson@arm.com // tells cache A that it gets the block to satisfy its read, 189011284Sandreas.hansson@arm.com // but must immediately invalidate it. 189111051Sandreas.hansson@arm.com pkt->cmd = MemCmd::ReadRespWithInvalidate; 189211051Sandreas.hansson@arm.com } 189311051Sandreas.hansson@arm.com // Here we consider forward_time, paying for just forward latency and 189411051Sandreas.hansson@arm.com // also charging the delay provided by the xbar. 189511051Sandreas.hansson@arm.com // forward_time is used as send_time in next allocateWriteBuffer(). 189611051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 189711051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 189811051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 189911288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, 190011288Ssteve.reinhardt@amd.com "%s created response: %s addr %#llx size %d tick: %lu\n", 190111051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize(), 190211051Sandreas.hansson@arm.com forward_time); 190311051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, forward_time, true); 190411051Sandreas.hansson@arm.com} 190511051Sandreas.hansson@arm.com 190611127Sandreas.hansson@arm.comuint32_t 190711051Sandreas.hansson@arm.comCache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, 190811051Sandreas.hansson@arm.com bool is_deferred, bool pending_inval) 190911051Sandreas.hansson@arm.com{ 191011288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d\n", __func__, 191111051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 191211051Sandreas.hansson@arm.com // deferred snoops can only happen in timing mode 191311051Sandreas.hansson@arm.com assert(!(is_deferred && !is_timing)); 191411051Sandreas.hansson@arm.com // pending_inval only makes sense on deferred snoops 191511051Sandreas.hansson@arm.com assert(!(pending_inval && !is_deferred)); 191611051Sandreas.hansson@arm.com assert(pkt->isRequest()); 191711051Sandreas.hansson@arm.com 191811051Sandreas.hansson@arm.com // the packet may get modified if we or a forwarded snooper 191911051Sandreas.hansson@arm.com // responds in atomic mode, so remember a few things about the 192011051Sandreas.hansson@arm.com // original packet up front 192111051Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 192211284Sandreas.hansson@arm.com bool M5_VAR_USED needs_writable = pkt->needsWritable(); 192311051Sandreas.hansson@arm.com 192411285Sandreas.hansson@arm.com // at the moment we could get an uncacheable write which does not 192511285Sandreas.hansson@arm.com // have the invalidate flag, and we need a suitable way of dealing 192611285Sandreas.hansson@arm.com // with this case 192711285Sandreas.hansson@arm.com panic_if(invalidate && pkt->req->isUncacheable(), 192811285Sandreas.hansson@arm.com "%s got an invalidating uncacheable snoop request %s to %#llx", 192911285Sandreas.hansson@arm.com name(), pkt->cmdString(), pkt->getAddr()); 193011285Sandreas.hansson@arm.com 193111127Sandreas.hansson@arm.com uint32_t snoop_delay = 0; 193211127Sandreas.hansson@arm.com 193311051Sandreas.hansson@arm.com if (forwardSnoops) { 193411051Sandreas.hansson@arm.com // first propagate snoop upward to see if anyone above us wants to 193511051Sandreas.hansson@arm.com // handle it. save & restore packet src since it will get 193611051Sandreas.hansson@arm.com // rewritten to be relative to cpu-side bus (if any) 193711284Sandreas.hansson@arm.com bool alreadyResponded = pkt->cacheResponding(); 193811051Sandreas.hansson@arm.com if (is_timing) { 193911051Sandreas.hansson@arm.com // copy the packet so that we can clear any flags before 194011051Sandreas.hansson@arm.com // forwarding it upwards, we also allocate data (passing 194111051Sandreas.hansson@arm.com // the pointer along in case of static data), in case 194211051Sandreas.hansson@arm.com // there is a snoop hit in upper levels 194311051Sandreas.hansson@arm.com Packet snoopPkt(pkt, true, true); 194411051Sandreas.hansson@arm.com snoopPkt.setExpressSnoop(); 194511051Sandreas.hansson@arm.com // the snoop packet does not need to wait any additional 194611051Sandreas.hansson@arm.com // time 194711051Sandreas.hansson@arm.com snoopPkt.headerDelay = snoopPkt.payloadDelay = 0; 194811051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoopPkt); 194911127Sandreas.hansson@arm.com 195011127Sandreas.hansson@arm.com // add the header delay (including crossbar and snoop 195111127Sandreas.hansson@arm.com // delays) of the upward snoop to the snoop delay for this 195211127Sandreas.hansson@arm.com // cache 195311127Sandreas.hansson@arm.com snoop_delay += snoopPkt.headerDelay; 195411127Sandreas.hansson@arm.com 195511284Sandreas.hansson@arm.com if (snoopPkt.cacheResponding()) { 195611051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache 195711051Sandreas.hansson@arm.com assert(!alreadyResponded); 195811284Sandreas.hansson@arm.com pkt->setCacheResponding(); 195911051Sandreas.hansson@arm.com } 196011284Sandreas.hansson@arm.com // upstream cache has the block, or has an outstanding 196111284Sandreas.hansson@arm.com // MSHR, pass the flag on 196211284Sandreas.hansson@arm.com if (snoopPkt.hasSharers()) { 196311284Sandreas.hansson@arm.com pkt->setHasSharers(); 196411051Sandreas.hansson@arm.com } 196511051Sandreas.hansson@arm.com // If this request is a prefetch or clean evict and an upper level 196611051Sandreas.hansson@arm.com // signals block present, make sure to propagate the block 196711051Sandreas.hansson@arm.com // presence to the requester. 196811051Sandreas.hansson@arm.com if (snoopPkt.isBlockCached()) { 196911051Sandreas.hansson@arm.com pkt->setBlockCached(); 197011051Sandreas.hansson@arm.com } 197111051Sandreas.hansson@arm.com } else { 197211051Sandreas.hansson@arm.com cpuSidePort->sendAtomicSnoop(pkt); 197311284Sandreas.hansson@arm.com if (!alreadyResponded && pkt->cacheResponding()) { 197411051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache: 197511051Sandreas.hansson@arm.com // forward response to original requester 197611051Sandreas.hansson@arm.com assert(pkt->isResponse()); 197711051Sandreas.hansson@arm.com } 197811051Sandreas.hansson@arm.com } 197911051Sandreas.hansson@arm.com } 198011051Sandreas.hansson@arm.com 198111051Sandreas.hansson@arm.com if (!blk || !blk->isValid()) { 198211288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "%s snoop miss for %s addr %#llx size %d\n", 198311051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 198411127Sandreas.hansson@arm.com return snoop_delay; 198511051Sandreas.hansson@arm.com } else { 198611288Ssteve.reinhardt@amd.com DPRINTF(Cache, "%s snoop hit for %s addr %#llx size %d, " 198711288Ssteve.reinhardt@amd.com "old state is %s\n", __func__, pkt->cmdString(), 198811288Ssteve.reinhardt@amd.com pkt->getAddr(), pkt->getSize(), blk->print()); 198911051Sandreas.hansson@arm.com } 199011051Sandreas.hansson@arm.com 199111051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && blk->isDirty()), 199211051Sandreas.hansson@arm.com "Should never have a dirty block in a read-only cache %s\n", 199311051Sandreas.hansson@arm.com name()); 199411051Sandreas.hansson@arm.com 199511051Sandreas.hansson@arm.com // We may end up modifying both the block state and the packet (if 199611051Sandreas.hansson@arm.com // we respond in atomic mode), so just figure out what to do now 199711051Sandreas.hansson@arm.com // and then do it later. If we find dirty data while snooping for 199811051Sandreas.hansson@arm.com // an invalidate, we don't need to send a response. The 199911051Sandreas.hansson@arm.com // invalidation itself is taken care of below. 200011051Sandreas.hansson@arm.com bool respond = blk->isDirty() && pkt->needsResponse() && 200111051Sandreas.hansson@arm.com pkt->cmd != MemCmd::InvalidateReq; 200211284Sandreas.hansson@arm.com bool have_writable = blk->isWritable(); 200311051Sandreas.hansson@arm.com 200411051Sandreas.hansson@arm.com // Invalidate any prefetch's from below that would strip write permissions 200511051Sandreas.hansson@arm.com // MemCmd::HardPFReq is only observed by upstream caches. After missing 200611051Sandreas.hansson@arm.com // above and in it's own cache, a new MemCmd::ReadReq is created that 200711051Sandreas.hansson@arm.com // downstream caches observe. 200811051Sandreas.hansson@arm.com if (pkt->mustCheckAbove()) { 200911051Sandreas.hansson@arm.com DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s from" 201011051Sandreas.hansson@arm.com " lower cache\n", pkt->getAddr(), pkt->cmdString()); 201111051Sandreas.hansson@arm.com pkt->setBlockCached(); 201211127Sandreas.hansson@arm.com return snoop_delay; 201311051Sandreas.hansson@arm.com } 201411051Sandreas.hansson@arm.com 201511285Sandreas.hansson@arm.com if (pkt->isRead() && !invalidate) { 201611285Sandreas.hansson@arm.com // reading without requiring the line in a writable state 201711284Sandreas.hansson@arm.com assert(!needs_writable); 201811284Sandreas.hansson@arm.com pkt->setHasSharers(); 201911285Sandreas.hansson@arm.com 202011285Sandreas.hansson@arm.com // if the requesting packet is uncacheable, retain the line in 202111285Sandreas.hansson@arm.com // the current state, otherwhise unset the writable flag, 202211285Sandreas.hansson@arm.com // which means we go from Modified to Owned (and will respond 202311285Sandreas.hansson@arm.com // below), remain in Owned (and will respond below), from 202411285Sandreas.hansson@arm.com // Exclusive to Shared, or remain in Shared 202511285Sandreas.hansson@arm.com if (!pkt->req->isUncacheable()) 202611285Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 202711051Sandreas.hansson@arm.com } 202811051Sandreas.hansson@arm.com 202911051Sandreas.hansson@arm.com if (respond) { 203011051Sandreas.hansson@arm.com // prevent anyone else from responding, cache as well as 203111051Sandreas.hansson@arm.com // memory, and also prevent any memory from even seeing the 203211284Sandreas.hansson@arm.com // request 203311284Sandreas.hansson@arm.com pkt->setCacheResponding(); 203411284Sandreas.hansson@arm.com if (have_writable) { 203511284Sandreas.hansson@arm.com // inform the cache hierarchy that this cache had the line 203611284Sandreas.hansson@arm.com // in the Modified state so that we avoid unnecessary 203711284Sandreas.hansson@arm.com // invalidations (see Packet::setResponderHadWritable) 203811284Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 203911284Sandreas.hansson@arm.com 204011081Sandreas.hansson@arm.com // in the case of an uncacheable request there is no point 204111284Sandreas.hansson@arm.com // in setting the responderHadWritable flag, but since the 204211284Sandreas.hansson@arm.com // recipient does not care there is no harm in doing so 204311284Sandreas.hansson@arm.com } else { 204411284Sandreas.hansson@arm.com // if the packet has needsWritable set we invalidate our 204511284Sandreas.hansson@arm.com // copy below and all other copies will be invalidates 204611284Sandreas.hansson@arm.com // through express snoops, and if needsWritable is not set 204711284Sandreas.hansson@arm.com // we already called setHasSharers above 204811051Sandreas.hansson@arm.com } 204911284Sandreas.hansson@arm.com 205011285Sandreas.hansson@arm.com // if we are returning a writable and dirty (Modified) line, 205111285Sandreas.hansson@arm.com // we should be invalidating the line 205211285Sandreas.hansson@arm.com panic_if(!invalidate && !pkt->hasSharers(), 205311285Sandreas.hansson@arm.com "%s is passing a Modified line through %s to %#llx, " 205411285Sandreas.hansson@arm.com "but keeping the block", 205511285Sandreas.hansson@arm.com name(), pkt->cmdString(), pkt->getAddr()); 205611285Sandreas.hansson@arm.com 205711051Sandreas.hansson@arm.com if (is_timing) { 205811051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval); 205911051Sandreas.hansson@arm.com } else { 206011051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 206111286Sandreas.hansson@arm.com // packets such as upgrades do not actually have any data 206211286Sandreas.hansson@arm.com // payload 206311286Sandreas.hansson@arm.com if (pkt->hasData()) 206411286Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 206511051Sandreas.hansson@arm.com } 206611051Sandreas.hansson@arm.com } 206711051Sandreas.hansson@arm.com 206811051Sandreas.hansson@arm.com if (!respond && is_timing && is_deferred) { 206911271Sandreas.hansson@arm.com // if it's a deferred timing snoop to which we are not 207011271Sandreas.hansson@arm.com // responding, then we've made a copy of both the request and 207111271Sandreas.hansson@arm.com // the packet, delete them here 207211051Sandreas.hansson@arm.com assert(pkt->needsResponse()); 207311051Sandreas.hansson@arm.com delete pkt->req; 207411051Sandreas.hansson@arm.com delete pkt; 207511051Sandreas.hansson@arm.com } 207611051Sandreas.hansson@arm.com 207711051Sandreas.hansson@arm.com // Do this last in case it deallocates block data or something 207811051Sandreas.hansson@arm.com // like that 207911051Sandreas.hansson@arm.com if (invalidate) { 208011197Sandreas.hansson@arm.com invalidateBlock(blk); 208111051Sandreas.hansson@arm.com } 208211051Sandreas.hansson@arm.com 208311051Sandreas.hansson@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 208411127Sandreas.hansson@arm.com 208511127Sandreas.hansson@arm.com return snoop_delay; 208611051Sandreas.hansson@arm.com} 208711051Sandreas.hansson@arm.com 208811051Sandreas.hansson@arm.com 208911051Sandreas.hansson@arm.comvoid 209011051Sandreas.hansson@arm.comCache::recvTimingSnoopReq(PacketPtr pkt) 209111051Sandreas.hansson@arm.com{ 209211288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d\n", __func__, 209311051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 209411051Sandreas.hansson@arm.com 209511051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 209611051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 209711051Sandreas.hansson@arm.com 209811130Sali.jafri@arm.com // no need to snoop requests that are not in range 209911051Sandreas.hansson@arm.com if (!inRange(pkt->getAddr())) { 210011051Sandreas.hansson@arm.com return; 210111051Sandreas.hansson@arm.com } 210211051Sandreas.hansson@arm.com 210311051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 210411051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 210511051Sandreas.hansson@arm.com 210611051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 210711051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 210811051Sandreas.hansson@arm.com 210911127Sandreas.hansson@arm.com // Update the latency cost of the snoop so that the crossbar can 211011127Sandreas.hansson@arm.com // account for it. Do not overwrite what other neighbouring caches 211111127Sandreas.hansson@arm.com // have already done, rather take the maximum. The update is 211211127Sandreas.hansson@arm.com // tentative, for cases where we return before an upward snoop 211311127Sandreas.hansson@arm.com // happens below. 211411127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, 211511127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 211611127Sandreas.hansson@arm.com 211711051Sandreas.hansson@arm.com // Inform request(Prefetch, CleanEvict or Writeback) from below of 211811051Sandreas.hansson@arm.com // MSHR hit, set setBlockCached. 211911051Sandreas.hansson@arm.com if (mshr && pkt->mustCheckAbove()) { 212011051Sandreas.hansson@arm.com DPRINTF(Cache, "Setting block cached for %s from" 212111051Sandreas.hansson@arm.com "lower cache on mshr hit %#x\n", 212211051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 212311051Sandreas.hansson@arm.com pkt->setBlockCached(); 212411051Sandreas.hansson@arm.com return; 212511051Sandreas.hansson@arm.com } 212611051Sandreas.hansson@arm.com 212711051Sandreas.hansson@arm.com // Let the MSHR itself track the snoop and decide whether we want 212811051Sandreas.hansson@arm.com // to go ahead and do the regular cache snoop 212911051Sandreas.hansson@arm.com if (mshr && mshr->handleSnoop(pkt, order++)) { 213011051Sandreas.hansson@arm.com DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)." 213111051Sandreas.hansson@arm.com "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns", 213211051Sandreas.hansson@arm.com mshr->print()); 213311051Sandreas.hansson@arm.com 213411051Sandreas.hansson@arm.com if (mshr->getNumTargets() > numTarget) 213511051Sandreas.hansson@arm.com warn("allocating bonus target for snoop"); //handle later 213611051Sandreas.hansson@arm.com return; 213711051Sandreas.hansson@arm.com } 213811051Sandreas.hansson@arm.com 213911051Sandreas.hansson@arm.com //We also need to check the writeback buffers and handle those 214011375Sandreas.hansson@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(blk_addr, is_secure); 214111375Sandreas.hansson@arm.com if (wb_entry) { 214211051Sandreas.hansson@arm.com DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n", 214311051Sandreas.hansson@arm.com pkt->getAddr(), is_secure ? "s" : "ns"); 214411051Sandreas.hansson@arm.com // Expect to see only Writebacks and/or CleanEvicts here, both of 214511051Sandreas.hansson@arm.com // which should not be generated for uncacheable data. 214611051Sandreas.hansson@arm.com assert(!wb_entry->isUncacheable()); 214711051Sandreas.hansson@arm.com // There should only be a single request responsible for generating 214811051Sandreas.hansson@arm.com // Writebacks/CleanEvicts. 214911051Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 215011051Sandreas.hansson@arm.com PacketPtr wb_pkt = wb_entry->getTarget()->pkt; 215111199Sandreas.hansson@arm.com assert(wb_pkt->isEviction()); 215211051Sandreas.hansson@arm.com 215311199Sandreas.hansson@arm.com if (pkt->isEviction()) { 215411051Sandreas.hansson@arm.com // if the block is found in the write queue, set the BLOCK_CACHED 215511051Sandreas.hansson@arm.com // flag for Writeback/CleanEvict snoop. On return the snoop will 215611051Sandreas.hansson@arm.com // propagate the BLOCK_CACHED flag in Writeback packets and prevent 215711051Sandreas.hansson@arm.com // any CleanEvicts from travelling down the memory hierarchy. 215811051Sandreas.hansson@arm.com pkt->setBlockCached(); 215911051Sandreas.hansson@arm.com DPRINTF(Cache, "Squashing %s from lower cache on writequeue hit" 216011051Sandreas.hansson@arm.com " %#x\n", pkt->cmdString(), pkt->getAddr()); 216111051Sandreas.hansson@arm.com return; 216211051Sandreas.hansson@arm.com } 216311051Sandreas.hansson@arm.com 216411332Sandreas.hansson@arm.com // conceptually writebacks are no different to other blocks in 216511332Sandreas.hansson@arm.com // this cache, so the behaviour is modelled after handleSnoop, 216611332Sandreas.hansson@arm.com // the difference being that instead of querying the block 216711332Sandreas.hansson@arm.com // state to determine if it is dirty and writable, we use the 216811332Sandreas.hansson@arm.com // command and fields of the writeback packet 216911332Sandreas.hansson@arm.com bool respond = wb_pkt->cmd == MemCmd::WritebackDirty && 217011332Sandreas.hansson@arm.com pkt->needsResponse() && pkt->cmd != MemCmd::InvalidateReq; 217111332Sandreas.hansson@arm.com bool have_writable = !wb_pkt->hasSharers(); 217211332Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 217311332Sandreas.hansson@arm.com 217411332Sandreas.hansson@arm.com if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) { 217511332Sandreas.hansson@arm.com assert(!pkt->needsWritable()); 217611332Sandreas.hansson@arm.com pkt->setHasSharers(); 217711332Sandreas.hansson@arm.com wb_pkt->setHasSharers(); 217811332Sandreas.hansson@arm.com } 217911332Sandreas.hansson@arm.com 218011332Sandreas.hansson@arm.com if (respond) { 218111284Sandreas.hansson@arm.com pkt->setCacheResponding(); 218211332Sandreas.hansson@arm.com 218311332Sandreas.hansson@arm.com if (have_writable) { 218411332Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 218511051Sandreas.hansson@arm.com } 218611332Sandreas.hansson@arm.com 218711051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(), 218811051Sandreas.hansson@arm.com false, false); 218911051Sandreas.hansson@arm.com } 219011051Sandreas.hansson@arm.com 219111332Sandreas.hansson@arm.com if (invalidate) { 219211051Sandreas.hansson@arm.com // Invalidation trumps our writeback... discard here 219311051Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 219411375Sandreas.hansson@arm.com markInService(wb_entry); 219511051Sandreas.hansson@arm.com delete wb_pkt; 219611051Sandreas.hansson@arm.com } 219711051Sandreas.hansson@arm.com } 219811051Sandreas.hansson@arm.com 219911051Sandreas.hansson@arm.com // If this was a shared writeback, there may still be 220011051Sandreas.hansson@arm.com // other shared copies above that require invalidation. 220111051Sandreas.hansson@arm.com // We could be more selective and return here if the 220211051Sandreas.hansson@arm.com // request is non-exclusive or if the writeback is 220311051Sandreas.hansson@arm.com // exclusive. 220411127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false); 220511127Sandreas.hansson@arm.com 220611127Sandreas.hansson@arm.com // Override what we did when we first saw the snoop, as we now 220711127Sandreas.hansson@arm.com // also have the cost of the upwards snoops to account for 220811127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay + 220911127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 221011051Sandreas.hansson@arm.com} 221111051Sandreas.hansson@arm.com 221211051Sandreas.hansson@arm.combool 221311051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 221411051Sandreas.hansson@arm.com{ 221511051Sandreas.hansson@arm.com // Express snoop responses from master to slave, e.g., from L1 to L2 221611051Sandreas.hansson@arm.com cache->recvTimingSnoopResp(pkt); 221711051Sandreas.hansson@arm.com return true; 221811051Sandreas.hansson@arm.com} 221911051Sandreas.hansson@arm.com 222011051Sandreas.hansson@arm.comTick 222111051Sandreas.hansson@arm.comCache::recvAtomicSnoop(PacketPtr pkt) 222211051Sandreas.hansson@arm.com{ 222311051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 222411051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 222511051Sandreas.hansson@arm.com 222611130Sali.jafri@arm.com // no need to snoop requests that are not in range. 222711130Sali.jafri@arm.com if (!inRange(pkt->getAddr())) { 222811051Sandreas.hansson@arm.com return 0; 222911051Sandreas.hansson@arm.com } 223011051Sandreas.hansson@arm.com 223111051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 223211127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false); 223311127Sandreas.hansson@arm.com return snoop_delay + lookupLatency * clockPeriod(); 223411051Sandreas.hansson@arm.com} 223511051Sandreas.hansson@arm.com 223611051Sandreas.hansson@arm.com 223711375Sandreas.hansson@arm.comQueueEntry* 223811375Sandreas.hansson@arm.comCache::getNextQueueEntry() 223911051Sandreas.hansson@arm.com{ 224011051Sandreas.hansson@arm.com // Check both MSHR queue and write buffer for potential requests, 224111051Sandreas.hansson@arm.com // note that null does not mean there is no request, it could 224211051Sandreas.hansson@arm.com // simply be that it is not ready 224311375Sandreas.hansson@arm.com MSHR *miss_mshr = mshrQueue.getNext(); 224411375Sandreas.hansson@arm.com WriteQueueEntry *wq_entry = writeBuffer.getNext(); 224511051Sandreas.hansson@arm.com 224611051Sandreas.hansson@arm.com // If we got a write buffer request ready, first priority is a 224711375Sandreas.hansson@arm.com // full write buffer (but only if we have no uncacheable write 224811375Sandreas.hansson@arm.com // responses outstanding, possibly revisit this last part), 224911375Sandreas.hansson@arm.com // otherwhise we favour the miss requests 225011375Sandreas.hansson@arm.com if (wq_entry && 225111375Sandreas.hansson@arm.com ((writeBuffer.isFull() && writeBuffer.numInService() == 0) || 225211051Sandreas.hansson@arm.com !miss_mshr)) { 225311051Sandreas.hansson@arm.com // need to search MSHR queue for conflicting earlier miss. 225411051Sandreas.hansson@arm.com MSHR *conflict_mshr = 225511375Sandreas.hansson@arm.com mshrQueue.findPending(wq_entry->blkAddr, 225611375Sandreas.hansson@arm.com wq_entry->isSecure); 225711375Sandreas.hansson@arm.com 225811375Sandreas.hansson@arm.com if (conflict_mshr && conflict_mshr->order < wq_entry->order) { 225911051Sandreas.hansson@arm.com // Service misses in order until conflict is cleared. 226011051Sandreas.hansson@arm.com return conflict_mshr; 226111051Sandreas.hansson@arm.com 226211051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 226311051Sandreas.hansson@arm.com } 226411051Sandreas.hansson@arm.com 226511051Sandreas.hansson@arm.com // No conflicts; issue write 226611375Sandreas.hansson@arm.com return wq_entry; 226711051Sandreas.hansson@arm.com } else if (miss_mshr) { 226811051Sandreas.hansson@arm.com // need to check for conflicting earlier writeback 226911375Sandreas.hansson@arm.com WriteQueueEntry *conflict_mshr = 227011051Sandreas.hansson@arm.com writeBuffer.findPending(miss_mshr->blkAddr, 227111051Sandreas.hansson@arm.com miss_mshr->isSecure); 227211051Sandreas.hansson@arm.com if (conflict_mshr) { 227311051Sandreas.hansson@arm.com // not sure why we don't check order here... it was in the 227411051Sandreas.hansson@arm.com // original code but commented out. 227511051Sandreas.hansson@arm.com 227611051Sandreas.hansson@arm.com // The only way this happens is if we are 227711051Sandreas.hansson@arm.com // doing a write and we didn't have permissions 227811051Sandreas.hansson@arm.com // then subsequently saw a writeback (owned got evicted) 227911051Sandreas.hansson@arm.com // We need to make sure to perform the writeback first 228011051Sandreas.hansson@arm.com // To preserve the dirty data, then we can issue the write 228111051Sandreas.hansson@arm.com 228211375Sandreas.hansson@arm.com // should we return wq_entry here instead? I.e. do we 228311051Sandreas.hansson@arm.com // have to flush writes in order? I don't think so... not 228411051Sandreas.hansson@arm.com // for Alpha anyway. Maybe for x86? 228511051Sandreas.hansson@arm.com return conflict_mshr; 228611051Sandreas.hansson@arm.com 228711051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 228811051Sandreas.hansson@arm.com } 228911051Sandreas.hansson@arm.com 229011051Sandreas.hansson@arm.com // No conflicts; issue read 229111051Sandreas.hansson@arm.com return miss_mshr; 229211051Sandreas.hansson@arm.com } 229311051Sandreas.hansson@arm.com 229411051Sandreas.hansson@arm.com // fall through... no pending requests. Try a prefetch. 229511375Sandreas.hansson@arm.com assert(!miss_mshr && !wq_entry); 229611051Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 229711051Sandreas.hansson@arm.com // If we have a miss queue slot, we can try a prefetch 229811051Sandreas.hansson@arm.com PacketPtr pkt = prefetcher->getPacket(); 229911051Sandreas.hansson@arm.com if (pkt) { 230011051Sandreas.hansson@arm.com Addr pf_addr = blockAlign(pkt->getAddr()); 230111051Sandreas.hansson@arm.com if (!tags->findBlock(pf_addr, pkt->isSecure()) && 230211051Sandreas.hansson@arm.com !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 230311051Sandreas.hansson@arm.com !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 230411051Sandreas.hansson@arm.com // Update statistic on number of prefetches issued 230511051Sandreas.hansson@arm.com // (hwpf_mshr_misses) 230611051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 230711051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 230811051Sandreas.hansson@arm.com 230911051Sandreas.hansson@arm.com // allocate an MSHR and return it, note 231011051Sandreas.hansson@arm.com // that we send the packet straight away, so do not 231111051Sandreas.hansson@arm.com // schedule the send 231211051Sandreas.hansson@arm.com return allocateMissBuffer(pkt, curTick(), false); 231311051Sandreas.hansson@arm.com } else { 231411051Sandreas.hansson@arm.com // free the request and packet 231511051Sandreas.hansson@arm.com delete pkt->req; 231611051Sandreas.hansson@arm.com delete pkt; 231711051Sandreas.hansson@arm.com } 231811051Sandreas.hansson@arm.com } 231911051Sandreas.hansson@arm.com } 232011051Sandreas.hansson@arm.com 232111375Sandreas.hansson@arm.com return nullptr; 232211051Sandreas.hansson@arm.com} 232311051Sandreas.hansson@arm.com 232411051Sandreas.hansson@arm.combool 232511130Sali.jafri@arm.comCache::isCachedAbove(PacketPtr pkt, bool is_timing) const 232611051Sandreas.hansson@arm.com{ 232711051Sandreas.hansson@arm.com if (!forwardSnoops) 232811051Sandreas.hansson@arm.com return false; 232911051Sandreas.hansson@arm.com // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and 233011051Sandreas.hansson@arm.com // Writeback snoops into upper level caches to check for copies of the 233111051Sandreas.hansson@arm.com // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict 233211051Sandreas.hansson@arm.com // packet, the cache can inform the crossbar below of presence or absence 233311051Sandreas.hansson@arm.com // of the block. 233411130Sali.jafri@arm.com if (is_timing) { 233511130Sali.jafri@arm.com Packet snoop_pkt(pkt, true, false); 233611130Sali.jafri@arm.com snoop_pkt.setExpressSnoop(); 233711130Sali.jafri@arm.com // Assert that packet is either Writeback or CleanEvict and not a 233811130Sali.jafri@arm.com // prefetch request because prefetch requests need an MSHR and may 233911130Sali.jafri@arm.com // generate a snoop response. 234011199Sandreas.hansson@arm.com assert(pkt->isEviction()); 234111130Sali.jafri@arm.com snoop_pkt.senderState = NULL; 234211130Sali.jafri@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 234311130Sali.jafri@arm.com // Writeback/CleanEvict snoops do not generate a snoop response. 234411284Sandreas.hansson@arm.com assert(!(snoop_pkt.cacheResponding())); 234511130Sali.jafri@arm.com return snoop_pkt.isBlockCached(); 234611130Sali.jafri@arm.com } else { 234711130Sali.jafri@arm.com cpuSidePort->sendAtomicSnoop(pkt); 234811130Sali.jafri@arm.com return pkt->isBlockCached(); 234911130Sali.jafri@arm.com } 235011051Sandreas.hansson@arm.com} 235111051Sandreas.hansson@arm.com 235211375Sandreas.hansson@arm.comTick 235311375Sandreas.hansson@arm.comCache::nextQueueReadyTime() const 235411051Sandreas.hansson@arm.com{ 235511375Sandreas.hansson@arm.com Tick nextReady = std::min(mshrQueue.nextReadyTime(), 235611375Sandreas.hansson@arm.com writeBuffer.nextReadyTime()); 235711375Sandreas.hansson@arm.com 235811375Sandreas.hansson@arm.com // Don't signal prefetch ready time if no MSHRs available 235911375Sandreas.hansson@arm.com // Will signal once enoguh MSHRs are deallocated 236011375Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 236111375Sandreas.hansson@arm.com nextReady = std::min(nextReady, 236211375Sandreas.hansson@arm.com prefetcher->nextPrefetchReadyTime()); 236311051Sandreas.hansson@arm.com } 236411051Sandreas.hansson@arm.com 236511375Sandreas.hansson@arm.com return nextReady; 236611375Sandreas.hansson@arm.com} 236711375Sandreas.hansson@arm.com 236811375Sandreas.hansson@arm.combool 236911375Sandreas.hansson@arm.comCache::sendMSHRQueuePacket(MSHR* mshr) 237011375Sandreas.hansson@arm.com{ 237111375Sandreas.hansson@arm.com assert(mshr); 237211375Sandreas.hansson@arm.com 237311051Sandreas.hansson@arm.com // use request from 1st target 237411051Sandreas.hansson@arm.com PacketPtr tgt_pkt = mshr->getTarget()->pkt; 237511375Sandreas.hansson@arm.com 237611375Sandreas.hansson@arm.com DPRINTF(Cache, "%s MSHR %s for addr %#llx size %d\n", __func__, 237711375Sandreas.hansson@arm.com tgt_pkt->cmdString(), tgt_pkt->getAddr(), 237811375Sandreas.hansson@arm.com tgt_pkt->getSize()); 237911051Sandreas.hansson@arm.com 238011051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 238111051Sandreas.hansson@arm.com 238211051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) { 238311375Sandreas.hansson@arm.com // we should never have hardware prefetches to allocated 238411375Sandreas.hansson@arm.com // blocks 238511375Sandreas.hansson@arm.com assert(blk == NULL); 238611375Sandreas.hansson@arm.com 238711051Sandreas.hansson@arm.com // We need to check the caches above us to verify that 238811051Sandreas.hansson@arm.com // they don't have a copy of this block in the dirty state 238911051Sandreas.hansson@arm.com // at the moment. Without this check we could get a stale 239011051Sandreas.hansson@arm.com // copy from memory that might get used in place of the 239111051Sandreas.hansson@arm.com // dirty one. 239211051Sandreas.hansson@arm.com Packet snoop_pkt(tgt_pkt, true, false); 239311051Sandreas.hansson@arm.com snoop_pkt.setExpressSnoop(); 239411275Sandreas.hansson@arm.com // We are sending this packet upwards, but if it hits we will 239511275Sandreas.hansson@arm.com // get a snoop response that we end up treating just like a 239611275Sandreas.hansson@arm.com // normal response, hence it needs the MSHR as its sender 239711275Sandreas.hansson@arm.com // state 239811051Sandreas.hansson@arm.com snoop_pkt.senderState = mshr; 239911051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 240011051Sandreas.hansson@arm.com 240111051Sandreas.hansson@arm.com // Check to see if the prefetch was squashed by an upper cache (to 240211051Sandreas.hansson@arm.com // prevent us from grabbing the line) or if a Check to see if a 240311051Sandreas.hansson@arm.com // writeback arrived between the time the prefetch was placed in 240411051Sandreas.hansson@arm.com // the MSHRs and when it was selected to be sent or if the 240511051Sandreas.hansson@arm.com // prefetch was squashed by an upper cache. 240611051Sandreas.hansson@arm.com 240711284Sandreas.hansson@arm.com // It is important to check cacheResponding before 240811284Sandreas.hansson@arm.com // prefetchSquashed. If another cache has committed to 240911284Sandreas.hansson@arm.com // responding, it will be sending a dirty response which will 241011284Sandreas.hansson@arm.com // arrive at the MSHR allocated for this request. Checking the 241111284Sandreas.hansson@arm.com // prefetchSquash first may result in the MSHR being 241211284Sandreas.hansson@arm.com // prematurely deallocated. 241311284Sandreas.hansson@arm.com if (snoop_pkt.cacheResponding()) { 241411276Sandreas.hansson@arm.com auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req); 241511276Sandreas.hansson@arm.com assert(r.second); 241611284Sandreas.hansson@arm.com 241711284Sandreas.hansson@arm.com // if we are getting a snoop response with no sharers it 241811284Sandreas.hansson@arm.com // will be allocated as Modified 241911284Sandreas.hansson@arm.com bool pending_modified_resp = !snoop_pkt.hasSharers(); 242011284Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 242111284Sandreas.hansson@arm.com 242211051Sandreas.hansson@arm.com DPRINTF(Cache, "Upward snoop of prefetch for addr" 242311051Sandreas.hansson@arm.com " %#x (%s) hit\n", 242411051Sandreas.hansson@arm.com tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns"); 242511375Sandreas.hansson@arm.com return false; 242611051Sandreas.hansson@arm.com } 242711051Sandreas.hansson@arm.com 242811375Sandreas.hansson@arm.com if (snoop_pkt.isBlockCached()) { 242911051Sandreas.hansson@arm.com DPRINTF(Cache, "Block present, prefetch squashed by cache. " 243011051Sandreas.hansson@arm.com "Deallocating mshr target %#x.\n", 243111051Sandreas.hansson@arm.com mshr->blkAddr); 243211375Sandreas.hansson@arm.com 243311051Sandreas.hansson@arm.com // Deallocate the mshr target 243411375Sandreas.hansson@arm.com if (mshrQueue.forceDeallocateTarget(mshr)) { 243511277Sandreas.hansson@arm.com // Clear block if this deallocation resulted freed an 243611277Sandreas.hansson@arm.com // mshr when all had previously been utilized 243711375Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 243811051Sandreas.hansson@arm.com } 243911375Sandreas.hansson@arm.com return false; 244011051Sandreas.hansson@arm.com } 244111051Sandreas.hansson@arm.com } 244211051Sandreas.hansson@arm.com 244311375Sandreas.hansson@arm.com // either a prefetch that is not present upstream, or a normal 244411375Sandreas.hansson@arm.com // MSHR request, proceed to get the packet to send downstream 244511375Sandreas.hansson@arm.com PacketPtr pkt = getBusPacket(tgt_pkt, blk, mshr->needsWritable()); 244611375Sandreas.hansson@arm.com 244711375Sandreas.hansson@arm.com mshr->isForward = (pkt == NULL); 244811375Sandreas.hansson@arm.com 244911375Sandreas.hansson@arm.com if (mshr->isForward) { 245011375Sandreas.hansson@arm.com // not a cache block request, but a response is expected 245111375Sandreas.hansson@arm.com // make copy of current packet to forward, keep current 245211375Sandreas.hansson@arm.com // copy for response handling 245311375Sandreas.hansson@arm.com pkt = new Packet(tgt_pkt, false, true); 245411375Sandreas.hansson@arm.com assert(!pkt->isWrite()); 245511375Sandreas.hansson@arm.com } 245611375Sandreas.hansson@arm.com 245711375Sandreas.hansson@arm.com // play it safe and append (rather than set) the sender state, 245811375Sandreas.hansson@arm.com // as forwarded packets may already have existing state 245911375Sandreas.hansson@arm.com pkt->pushSenderState(mshr); 246011375Sandreas.hansson@arm.com 246111375Sandreas.hansson@arm.com if (!memSidePort->sendTimingReq(pkt)) { 246211375Sandreas.hansson@arm.com // we are awaiting a retry, but we 246311375Sandreas.hansson@arm.com // delete the packet and will be creating a new packet 246411375Sandreas.hansson@arm.com // when we get the opportunity 246511375Sandreas.hansson@arm.com delete pkt; 246611375Sandreas.hansson@arm.com 246711375Sandreas.hansson@arm.com // note that we have now masked any requestBus and 246811375Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 246911375Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 247011375Sandreas.hansson@arm.com // care about this packet and might override it before 247111375Sandreas.hansson@arm.com // it gets retried 247211375Sandreas.hansson@arm.com return true; 247311375Sandreas.hansson@arm.com } else { 247411375Sandreas.hansson@arm.com // As part of the call to sendTimingReq the packet is 247511375Sandreas.hansson@arm.com // forwarded to all neighbouring caches (and any caches 247611375Sandreas.hansson@arm.com // above them) as a snoop. Thus at this point we know if 247711375Sandreas.hansson@arm.com // any of the neighbouring caches are responding, and if 247811375Sandreas.hansson@arm.com // so, we know it is dirty, and we can determine if it is 247911375Sandreas.hansson@arm.com // being passed as Modified, making our MSHR the ordering 248011375Sandreas.hansson@arm.com // point 248111375Sandreas.hansson@arm.com bool pending_modified_resp = !pkt->hasSharers() && 248211375Sandreas.hansson@arm.com pkt->cacheResponding(); 248311375Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 248411375Sandreas.hansson@arm.com return false; 248511375Sandreas.hansson@arm.com } 248611375Sandreas.hansson@arm.com} 248711375Sandreas.hansson@arm.com 248811375Sandreas.hansson@arm.combool 248911375Sandreas.hansson@arm.comCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry) 249011375Sandreas.hansson@arm.com{ 249111375Sandreas.hansson@arm.com assert(wq_entry); 249211375Sandreas.hansson@arm.com 249311375Sandreas.hansson@arm.com // always a single target for write queue entries 249411375Sandreas.hansson@arm.com PacketPtr tgt_pkt = wq_entry->getTarget()->pkt; 249511375Sandreas.hansson@arm.com 249611375Sandreas.hansson@arm.com DPRINTF(Cache, "%s write %s for addr %#llx size %d\n", __func__, 249711375Sandreas.hansson@arm.com tgt_pkt->cmdString(), tgt_pkt->getAddr(), 249811375Sandreas.hansson@arm.com tgt_pkt->getSize()); 249911375Sandreas.hansson@arm.com 250011375Sandreas.hansson@arm.com PacketPtr pkt = nullptr; 250111375Sandreas.hansson@arm.com bool delete_pkt = false; 250211375Sandreas.hansson@arm.com 250311375Sandreas.hansson@arm.com if (tgt_pkt->isEviction()) { 250411375Sandreas.hansson@arm.com assert(!wq_entry->isUncacheable()); 250511051Sandreas.hansson@arm.com // no response expected, just forward packet as it is 250611051Sandreas.hansson@arm.com pkt = tgt_pkt; 250711051Sandreas.hansson@arm.com } else { 250811375Sandreas.hansson@arm.com // the only thing we deal with besides eviction commands 250911375Sandreas.hansson@arm.com // are uncacheable writes 251011375Sandreas.hansson@arm.com assert(tgt_pkt->req->isUncacheable() && tgt_pkt->isWrite()); 251111375Sandreas.hansson@arm.com // not a cache block request, but a response is expected 251211375Sandreas.hansson@arm.com // make copy of current packet to forward, keep current 251311375Sandreas.hansson@arm.com // copy for response handling 251411375Sandreas.hansson@arm.com pkt = new Packet(tgt_pkt, false, true); 251511375Sandreas.hansson@arm.com pkt->setData(tgt_pkt->getConstPtr<uint8_t>()); 251611375Sandreas.hansson@arm.com delete_pkt = true; 251711375Sandreas.hansson@arm.com } 251811375Sandreas.hansson@arm.com 251911375Sandreas.hansson@arm.com pkt->pushSenderState(wq_entry); 252011375Sandreas.hansson@arm.com 252111375Sandreas.hansson@arm.com if (!memSidePort->sendTimingReq(pkt)) { 252211375Sandreas.hansson@arm.com if (delete_pkt) { 252311375Sandreas.hansson@arm.com // we are awaiting a retry, but we 252411375Sandreas.hansson@arm.com // delete the packet and will be creating a new packet 252511375Sandreas.hansson@arm.com // when we get the opportunity 252611375Sandreas.hansson@arm.com delete pkt; 252711051Sandreas.hansson@arm.com } 252811375Sandreas.hansson@arm.com // note that we have now masked any requestBus and 252911375Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 253011375Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 253111375Sandreas.hansson@arm.com // care about this packet and might override it before 253211375Sandreas.hansson@arm.com // it gets retried 253311375Sandreas.hansson@arm.com return true; 253411375Sandreas.hansson@arm.com } else { 253511375Sandreas.hansson@arm.com markInService(wq_entry); 253611375Sandreas.hansson@arm.com return false; 253711051Sandreas.hansson@arm.com } 253811051Sandreas.hansson@arm.com} 253911051Sandreas.hansson@arm.com 254011051Sandreas.hansson@arm.comvoid 254111051Sandreas.hansson@arm.comCache::serialize(CheckpointOut &cp) const 254211051Sandreas.hansson@arm.com{ 254311051Sandreas.hansson@arm.com bool dirty(isDirty()); 254411051Sandreas.hansson@arm.com 254511051Sandreas.hansson@arm.com if (dirty) { 254611051Sandreas.hansson@arm.com warn("*** The cache still contains dirty data. ***\n"); 254711051Sandreas.hansson@arm.com warn(" Make sure to drain the system using the correct flags.\n"); 254811051Sandreas.hansson@arm.com warn(" This checkpoint will not restore correctly and dirty data in " 254911051Sandreas.hansson@arm.com "the cache will be lost!\n"); 255011051Sandreas.hansson@arm.com } 255111051Sandreas.hansson@arm.com 255211051Sandreas.hansson@arm.com // Since we don't checkpoint the data in the cache, any dirty data 255311051Sandreas.hansson@arm.com // will be lost when restoring from a checkpoint of a system that 255411051Sandreas.hansson@arm.com // wasn't drained properly. Flag the checkpoint as invalid if the 255511051Sandreas.hansson@arm.com // cache contains dirty data. 255611051Sandreas.hansson@arm.com bool bad_checkpoint(dirty); 255711051Sandreas.hansson@arm.com SERIALIZE_SCALAR(bad_checkpoint); 255811051Sandreas.hansson@arm.com} 255911051Sandreas.hansson@arm.com 256011051Sandreas.hansson@arm.comvoid 256111051Sandreas.hansson@arm.comCache::unserialize(CheckpointIn &cp) 256211051Sandreas.hansson@arm.com{ 256311051Sandreas.hansson@arm.com bool bad_checkpoint; 256411051Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(bad_checkpoint); 256511051Sandreas.hansson@arm.com if (bad_checkpoint) { 256611051Sandreas.hansson@arm.com fatal("Restoring from checkpoints with dirty caches is not supported " 256711051Sandreas.hansson@arm.com "in the classic memory system. Please remove any caches or " 256811051Sandreas.hansson@arm.com " drain them properly before taking checkpoints.\n"); 256911051Sandreas.hansson@arm.com } 257011051Sandreas.hansson@arm.com} 257111051Sandreas.hansson@arm.com 257211051Sandreas.hansson@arm.com/////////////// 257311051Sandreas.hansson@arm.com// 257411051Sandreas.hansson@arm.com// CpuSidePort 257511051Sandreas.hansson@arm.com// 257611051Sandreas.hansson@arm.com/////////////// 257711051Sandreas.hansson@arm.com 257811051Sandreas.hansson@arm.comAddrRangeList 257911051Sandreas.hansson@arm.comCache::CpuSidePort::getAddrRanges() const 258011051Sandreas.hansson@arm.com{ 258111051Sandreas.hansson@arm.com return cache->getAddrRanges(); 258211051Sandreas.hansson@arm.com} 258311051Sandreas.hansson@arm.com 258411051Sandreas.hansson@arm.combool 258511051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingReq(PacketPtr pkt) 258611051Sandreas.hansson@arm.com{ 258711051Sandreas.hansson@arm.com assert(!cache->system->bypassCaches()); 258811051Sandreas.hansson@arm.com 258911051Sandreas.hansson@arm.com bool success = false; 259011051Sandreas.hansson@arm.com 259111334Sandreas.hansson@arm.com // always let express snoop packets through if even if blocked 259211334Sandreas.hansson@arm.com if (pkt->isExpressSnoop()) { 259311051Sandreas.hansson@arm.com // do not change the current retry state 259411051Sandreas.hansson@arm.com bool M5_VAR_USED bypass_success = cache->recvTimingReq(pkt); 259511051Sandreas.hansson@arm.com assert(bypass_success); 259611051Sandreas.hansson@arm.com return true; 259711051Sandreas.hansson@arm.com } else if (blocked || mustSendRetry) { 259811051Sandreas.hansson@arm.com // either already committed to send a retry, or blocked 259911051Sandreas.hansson@arm.com success = false; 260011051Sandreas.hansson@arm.com } else { 260111051Sandreas.hansson@arm.com // pass it on to the cache, and let the cache decide if we 260211051Sandreas.hansson@arm.com // have to retry or not 260311051Sandreas.hansson@arm.com success = cache->recvTimingReq(pkt); 260411051Sandreas.hansson@arm.com } 260511051Sandreas.hansson@arm.com 260611051Sandreas.hansson@arm.com // remember if we have to retry 260711051Sandreas.hansson@arm.com mustSendRetry = !success; 260811051Sandreas.hansson@arm.com return success; 260911051Sandreas.hansson@arm.com} 261011051Sandreas.hansson@arm.com 261111051Sandreas.hansson@arm.comTick 261211051Sandreas.hansson@arm.comCache::CpuSidePort::recvAtomic(PacketPtr pkt) 261311051Sandreas.hansson@arm.com{ 261411051Sandreas.hansson@arm.com return cache->recvAtomic(pkt); 261511051Sandreas.hansson@arm.com} 261611051Sandreas.hansson@arm.com 261711051Sandreas.hansson@arm.comvoid 261811051Sandreas.hansson@arm.comCache::CpuSidePort::recvFunctional(PacketPtr pkt) 261911051Sandreas.hansson@arm.com{ 262011051Sandreas.hansson@arm.com // functional request 262111051Sandreas.hansson@arm.com cache->functionalAccess(pkt, true); 262211051Sandreas.hansson@arm.com} 262311051Sandreas.hansson@arm.com 262411051Sandreas.hansson@arm.comCache:: 262511051Sandreas.hansson@arm.comCpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache, 262611051Sandreas.hansson@arm.com const std::string &_label) 262711051Sandreas.hansson@arm.com : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache) 262811051Sandreas.hansson@arm.com{ 262911051Sandreas.hansson@arm.com} 263011051Sandreas.hansson@arm.com 263111053Sandreas.hansson@arm.comCache* 263211053Sandreas.hansson@arm.comCacheParams::create() 263311053Sandreas.hansson@arm.com{ 263411053Sandreas.hansson@arm.com assert(tags); 263511053Sandreas.hansson@arm.com 263611053Sandreas.hansson@arm.com return new Cache(this); 263711053Sandreas.hansson@arm.com} 263811051Sandreas.hansson@arm.com/////////////// 263911051Sandreas.hansson@arm.com// 264011051Sandreas.hansson@arm.com// MemSidePort 264111051Sandreas.hansson@arm.com// 264211051Sandreas.hansson@arm.com/////////////// 264311051Sandreas.hansson@arm.com 264411051Sandreas.hansson@arm.combool 264511051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingResp(PacketPtr pkt) 264611051Sandreas.hansson@arm.com{ 264711051Sandreas.hansson@arm.com cache->recvTimingResp(pkt); 264811051Sandreas.hansson@arm.com return true; 264911051Sandreas.hansson@arm.com} 265011051Sandreas.hansson@arm.com 265111051Sandreas.hansson@arm.com// Express snooping requests to memside port 265211051Sandreas.hansson@arm.comvoid 265311051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 265411051Sandreas.hansson@arm.com{ 265511051Sandreas.hansson@arm.com // handle snooping requests 265611051Sandreas.hansson@arm.com cache->recvTimingSnoopReq(pkt); 265711051Sandreas.hansson@arm.com} 265811051Sandreas.hansson@arm.com 265911051Sandreas.hansson@arm.comTick 266011051Sandreas.hansson@arm.comCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 266111051Sandreas.hansson@arm.com{ 266211051Sandreas.hansson@arm.com return cache->recvAtomicSnoop(pkt); 266311051Sandreas.hansson@arm.com} 266411051Sandreas.hansson@arm.com 266511051Sandreas.hansson@arm.comvoid 266611051Sandreas.hansson@arm.comCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 266711051Sandreas.hansson@arm.com{ 266811051Sandreas.hansson@arm.com // functional snoop (note that in contrast to atomic we don't have 266911051Sandreas.hansson@arm.com // a specific functionalSnoop method, as they have the same 267011051Sandreas.hansson@arm.com // behaviour regardless) 267111051Sandreas.hansson@arm.com cache->functionalAccess(pkt, false); 267211051Sandreas.hansson@arm.com} 267311051Sandreas.hansson@arm.com 267411051Sandreas.hansson@arm.comvoid 267511051Sandreas.hansson@arm.comCache::CacheReqPacketQueue::sendDeferredPacket() 267611051Sandreas.hansson@arm.com{ 267711051Sandreas.hansson@arm.com // sanity check 267811051Sandreas.hansson@arm.com assert(!waitingOnRetry); 267911051Sandreas.hansson@arm.com 268011051Sandreas.hansson@arm.com // there should never be any deferred request packets in the 268111051Sandreas.hansson@arm.com // queue, instead we resly on the cache to provide the packets 268211051Sandreas.hansson@arm.com // from the MSHR queue or write queue 268311051Sandreas.hansson@arm.com assert(deferredPacketReadyTime() == MaxTick); 268411051Sandreas.hansson@arm.com 268511051Sandreas.hansson@arm.com // check for request packets (requests & writebacks) 268611375Sandreas.hansson@arm.com QueueEntry* entry = cache.getNextQueueEntry(); 268711375Sandreas.hansson@arm.com 268811375Sandreas.hansson@arm.com if (!entry) { 268911051Sandreas.hansson@arm.com // can happen if e.g. we attempt a writeback and fail, but 269011051Sandreas.hansson@arm.com // before the retry, the writeback is eliminated because 269111051Sandreas.hansson@arm.com // we snoop another cache's ReadEx. 269211051Sandreas.hansson@arm.com } else { 269311051Sandreas.hansson@arm.com // let our snoop responses go first if there are responses to 269411375Sandreas.hansson@arm.com // the same addresses 269511375Sandreas.hansson@arm.com if (checkConflictingSnoop(entry->blkAddr)) { 269611051Sandreas.hansson@arm.com return; 269711051Sandreas.hansson@arm.com } 269811375Sandreas.hansson@arm.com waitingOnRetry = entry->sendPacket(cache); 269911051Sandreas.hansson@arm.com } 270011051Sandreas.hansson@arm.com 270111051Sandreas.hansson@arm.com // if we succeeded and are not waiting for a retry, schedule the 270211375Sandreas.hansson@arm.com // next send considering when the next queue is ready, note that 270311051Sandreas.hansson@arm.com // snoop responses have their own packet queue and thus schedule 270411051Sandreas.hansson@arm.com // their own events 270511051Sandreas.hansson@arm.com if (!waitingOnRetry) { 270611375Sandreas.hansson@arm.com schedSendEvent(cache.nextQueueReadyTime()); 270711051Sandreas.hansson@arm.com } 270811051Sandreas.hansson@arm.com} 270911051Sandreas.hansson@arm.com 271011051Sandreas.hansson@arm.comCache:: 271111051Sandreas.hansson@arm.comMemSidePort::MemSidePort(const std::string &_name, Cache *_cache, 271211051Sandreas.hansson@arm.com const std::string &_label) 271311051Sandreas.hansson@arm.com : BaseCache::CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 271411051Sandreas.hansson@arm.com _reqQueue(*_cache, *this, _snoopRespQueue, _label), 271511051Sandreas.hansson@arm.com _snoopRespQueue(*_cache, *this, _label), cache(_cache) 271611051Sandreas.hansson@arm.com{ 271711051Sandreas.hansson@arm.com} 2718