cache.cc revision 11332
12810Srdreslin@umich.edu/* 211051Sandreas.hansson@arm.com * Copyright (c) 2010-2015 ARM Limited 311051Sandreas.hansson@arm.com * All rights reserved. 411051Sandreas.hansson@arm.com * 511051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911051Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311051Sandreas.hansson@arm.com * 1411051Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511051Sandreas.hansson@arm.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 162810Srdreslin@umich.edu * All rights reserved. 172810Srdreslin@umich.edu * 182810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 192810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 202810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 212810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 222810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 232810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 242810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 252810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 262810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 272810Srdreslin@umich.edu * this software without specific prior written permission. 282810Srdreslin@umich.edu * 292810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810Srdreslin@umich.edu * 412810Srdreslin@umich.edu * Authors: Erik Hallnor 4211051Sandreas.hansson@arm.com * Dave Greene 4311051Sandreas.hansson@arm.com * Nathan Binkert 442810Srdreslin@umich.edu * Steve Reinhardt 4511051Sandreas.hansson@arm.com * Ron Dreslinski 4611051Sandreas.hansson@arm.com * Andreas Sandberg 472810Srdreslin@umich.edu */ 482810Srdreslin@umich.edu 492810Srdreslin@umich.edu/** 502810Srdreslin@umich.edu * @file 5111051Sandreas.hansson@arm.com * Cache definitions. 522810Srdreslin@umich.edu */ 532810Srdreslin@umich.edu 5411051Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 552810Srdreslin@umich.edu 5611051Sandreas.hansson@arm.com#include "base/misc.hh" 5711051Sandreas.hansson@arm.com#include "base/types.hh" 5811051Sandreas.hansson@arm.com#include "debug/Cache.hh" 5911051Sandreas.hansson@arm.com#include "debug/CachePort.hh" 6011051Sandreas.hansson@arm.com#include "debug/CacheTags.hh" 6111288Ssteve.reinhardt@amd.com#include "debug/CacheVerbose.hh" 6211051Sandreas.hansson@arm.com#include "mem/cache/blk.hh" 6311051Sandreas.hansson@arm.com#include "mem/cache/mshr.hh" 6411051Sandreas.hansson@arm.com#include "mem/cache/prefetch/base.hh" 6511051Sandreas.hansson@arm.com#include "sim/sim_exit.hh" 6611051Sandreas.hansson@arm.com 6711053Sandreas.hansson@arm.comCache::Cache(const CacheParams *p) 6811053Sandreas.hansson@arm.com : BaseCache(p, p->system->cacheLineSize()), 6911051Sandreas.hansson@arm.com tags(p->tags), 7011051Sandreas.hansson@arm.com prefetcher(p->prefetcher), 7111051Sandreas.hansson@arm.com doFastWrites(true), 7211197Sandreas.hansson@arm.com prefetchOnAccess(p->prefetch_on_access), 7311197Sandreas.hansson@arm.com clusivity(p->clusivity), 7411199Sandreas.hansson@arm.com writebackClean(p->writeback_clean), 7511197Sandreas.hansson@arm.com tempBlockWriteback(nullptr), 7611197Sandreas.hansson@arm.com writebackTempBlockAtomicEvent(this, false, 7711197Sandreas.hansson@arm.com EventBase::Delayed_Writeback_Pri) 7811051Sandreas.hansson@arm.com{ 7911051Sandreas.hansson@arm.com tempBlock = new CacheBlk(); 8011051Sandreas.hansson@arm.com tempBlock->data = new uint8_t[blkSize]; 8111051Sandreas.hansson@arm.com 8211051Sandreas.hansson@arm.com cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this, 8311051Sandreas.hansson@arm.com "CpuSidePort"); 8411051Sandreas.hansson@arm.com memSidePort = new MemSidePort(p->name + ".mem_side", this, 8511051Sandreas.hansson@arm.com "MemSidePort"); 8611051Sandreas.hansson@arm.com 8711051Sandreas.hansson@arm.com tags->setCache(this); 8811051Sandreas.hansson@arm.com if (prefetcher) 8911051Sandreas.hansson@arm.com prefetcher->setCache(this); 9011051Sandreas.hansson@arm.com} 9111051Sandreas.hansson@arm.com 9211051Sandreas.hansson@arm.comCache::~Cache() 9311051Sandreas.hansson@arm.com{ 9411051Sandreas.hansson@arm.com delete [] tempBlock->data; 9511051Sandreas.hansson@arm.com delete tempBlock; 9611051Sandreas.hansson@arm.com 9711051Sandreas.hansson@arm.com delete cpuSidePort; 9811051Sandreas.hansson@arm.com delete memSidePort; 9911051Sandreas.hansson@arm.com} 10011051Sandreas.hansson@arm.com 10111051Sandreas.hansson@arm.comvoid 10211051Sandreas.hansson@arm.comCache::regStats() 10311051Sandreas.hansson@arm.com{ 10411051Sandreas.hansson@arm.com BaseCache::regStats(); 10511051Sandreas.hansson@arm.com} 10611051Sandreas.hansson@arm.com 10711051Sandreas.hansson@arm.comvoid 10811051Sandreas.hansson@arm.comCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 10911051Sandreas.hansson@arm.com{ 11011051Sandreas.hansson@arm.com assert(pkt->isRequest()); 11111051Sandreas.hansson@arm.com 11211051Sandreas.hansson@arm.com uint64_t overwrite_val; 11311051Sandreas.hansson@arm.com bool overwrite_mem; 11411051Sandreas.hansson@arm.com uint64_t condition_val64; 11511051Sandreas.hansson@arm.com uint32_t condition_val32; 11611051Sandreas.hansson@arm.com 11711051Sandreas.hansson@arm.com int offset = tags->extractBlkOffset(pkt->getAddr()); 11811051Sandreas.hansson@arm.com uint8_t *blk_data = blk->data + offset; 11911051Sandreas.hansson@arm.com 12011051Sandreas.hansson@arm.com assert(sizeof(uint64_t) >= pkt->getSize()); 12111051Sandreas.hansson@arm.com 12211051Sandreas.hansson@arm.com overwrite_mem = true; 12311051Sandreas.hansson@arm.com // keep a copy of our possible write value, and copy what is at the 12411051Sandreas.hansson@arm.com // memory address into the packet 12511051Sandreas.hansson@arm.com pkt->writeData((uint8_t *)&overwrite_val); 12611051Sandreas.hansson@arm.com pkt->setData(blk_data); 12711051Sandreas.hansson@arm.com 12811051Sandreas.hansson@arm.com if (pkt->req->isCondSwap()) { 12911051Sandreas.hansson@arm.com if (pkt->getSize() == sizeof(uint64_t)) { 13011051Sandreas.hansson@arm.com condition_val64 = pkt->req->getExtraData(); 13111051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val64, blk_data, 13211051Sandreas.hansson@arm.com sizeof(uint64_t)); 13311051Sandreas.hansson@arm.com } else if (pkt->getSize() == sizeof(uint32_t)) { 13411051Sandreas.hansson@arm.com condition_val32 = (uint32_t)pkt->req->getExtraData(); 13511051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val32, blk_data, 13611051Sandreas.hansson@arm.com sizeof(uint32_t)); 13711051Sandreas.hansson@arm.com } else 13811051Sandreas.hansson@arm.com panic("Invalid size for conditional read/write\n"); 13911051Sandreas.hansson@arm.com } 14011051Sandreas.hansson@arm.com 14111051Sandreas.hansson@arm.com if (overwrite_mem) { 14211051Sandreas.hansson@arm.com std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 14311051Sandreas.hansson@arm.com blk->status |= BlkDirty; 14411051Sandreas.hansson@arm.com } 14511051Sandreas.hansson@arm.com} 14611051Sandreas.hansson@arm.com 14711051Sandreas.hansson@arm.com 14811051Sandreas.hansson@arm.comvoid 14911051Sandreas.hansson@arm.comCache::satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk, 15011051Sandreas.hansson@arm.com bool deferred_response, bool pending_downgrade) 15111051Sandreas.hansson@arm.com{ 15211051Sandreas.hansson@arm.com assert(pkt->isRequest()); 15311051Sandreas.hansson@arm.com 15411051Sandreas.hansson@arm.com assert(blk && blk->isValid()); 15511051Sandreas.hansson@arm.com // Occasionally this is not true... if we are a lower-level cache 15611051Sandreas.hansson@arm.com // satisfying a string of Read and ReadEx requests from 15711051Sandreas.hansson@arm.com // upper-level caches, a Read will mark the block as shared but we 15811051Sandreas.hansson@arm.com // can satisfy a following ReadEx anyway since we can rely on the 15911051Sandreas.hansson@arm.com // Read requester(s) to have buffered the ReadEx snoop and to 16011051Sandreas.hansson@arm.com // invalidate their blocks after receiving them. 16111284Sandreas.hansson@arm.com // assert(!pkt->needsWritable() || blk->isWritable()); 16211051Sandreas.hansson@arm.com assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 16311051Sandreas.hansson@arm.com 16411051Sandreas.hansson@arm.com // Check RMW operations first since both isRead() and 16511051Sandreas.hansson@arm.com // isWrite() will be true for them 16611051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::SwapReq) { 16711051Sandreas.hansson@arm.com cmpAndSwap(blk, pkt); 16811051Sandreas.hansson@arm.com } else if (pkt->isWrite()) { 16911284Sandreas.hansson@arm.com // we have the block in a writable state and can go ahead, 17011284Sandreas.hansson@arm.com // note that the line may be also be considered writable in 17111284Sandreas.hansson@arm.com // downstream caches along the path to memory, but always 17211284Sandreas.hansson@arm.com // Exclusive, and never Modified 17311051Sandreas.hansson@arm.com assert(blk->isWritable()); 17411284Sandreas.hansson@arm.com // Write or WriteLine at the first cache with block in writable state 17511051Sandreas.hansson@arm.com if (blk->checkWrite(pkt)) { 17611051Sandreas.hansson@arm.com pkt->writeDataToBlock(blk->data, blkSize); 17711051Sandreas.hansson@arm.com } 17811284Sandreas.hansson@arm.com // Always mark the line as dirty (and thus transition to the 17911284Sandreas.hansson@arm.com // Modified state) even if we are a failed StoreCond so we 18011284Sandreas.hansson@arm.com // supply data to any snoops that have appended themselves to 18111284Sandreas.hansson@arm.com // this cache before knowing the store will fail. 18211051Sandreas.hansson@arm.com blk->status |= BlkDirty; 18311288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d (write)\n", 18411288Ssteve.reinhardt@amd.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 18511051Sandreas.hansson@arm.com } else if (pkt->isRead()) { 18611051Sandreas.hansson@arm.com if (pkt->isLLSC()) { 18711051Sandreas.hansson@arm.com blk->trackLoadLocked(pkt); 18811051Sandreas.hansson@arm.com } 18911286Sandreas.hansson@arm.com 19011286Sandreas.hansson@arm.com // all read responses have a data payload 19111286Sandreas.hansson@arm.com assert(pkt->hasRespData()); 19211051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 19311286Sandreas.hansson@arm.com 19411051Sandreas.hansson@arm.com // determine if this read is from a (coherent) cache, or not 19511051Sandreas.hansson@arm.com // by looking at the command type; we could potentially add a 19611051Sandreas.hansson@arm.com // packet attribute such as 'FromCache' to make this check a 19711051Sandreas.hansson@arm.com // bit cleaner 19811051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadExReq || 19911051Sandreas.hansson@arm.com pkt->cmd == MemCmd::ReadSharedReq || 20011051Sandreas.hansson@arm.com pkt->cmd == MemCmd::ReadCleanReq || 20111051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq) { 20211051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 20311051Sandreas.hansson@arm.com // special handling for coherent block requests from 20411051Sandreas.hansson@arm.com // upper-level caches 20511284Sandreas.hansson@arm.com if (pkt->needsWritable()) { 20611051Sandreas.hansson@arm.com // sanity check 20711051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::ReadExReq || 20811051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq); 20911051Sandreas.hansson@arm.com 21011051Sandreas.hansson@arm.com // if we have a dirty copy, make sure the recipient 21111284Sandreas.hansson@arm.com // keeps it marked dirty (in the modified state) 21211051Sandreas.hansson@arm.com if (blk->isDirty()) { 21311284Sandreas.hansson@arm.com pkt->setCacheResponding(); 21411051Sandreas.hansson@arm.com } 21511197Sandreas.hansson@arm.com // on ReadExReq we give up our copy unconditionally, 21611197Sandreas.hansson@arm.com // even if this cache is mostly inclusive, we may want 21711197Sandreas.hansson@arm.com // to revisit this 21811197Sandreas.hansson@arm.com invalidateBlock(blk); 21911051Sandreas.hansson@arm.com } else if (blk->isWritable() && !pending_downgrade && 22011284Sandreas.hansson@arm.com !pkt->hasSharers() && 22111051Sandreas.hansson@arm.com pkt->cmd != MemCmd::ReadCleanReq) { 22211284Sandreas.hansson@arm.com // we can give the requester a writable copy on a read 22311284Sandreas.hansson@arm.com // request if: 22411284Sandreas.hansson@arm.com // - we have a writable copy at this level (& below) 22511051Sandreas.hansson@arm.com // - we don't have a pending snoop from below 22611051Sandreas.hansson@arm.com // signaling another read request 22711051Sandreas.hansson@arm.com // - no other cache above has a copy (otherwise it 22811284Sandreas.hansson@arm.com // would have set hasSharers flag when 22911284Sandreas.hansson@arm.com // snooping the packet) 23011284Sandreas.hansson@arm.com // - the read has explicitly asked for a clean 23111284Sandreas.hansson@arm.com // copy of the line 23211051Sandreas.hansson@arm.com if (blk->isDirty()) { 23311051Sandreas.hansson@arm.com // special considerations if we're owner: 23411051Sandreas.hansson@arm.com if (!deferred_response) { 23511284Sandreas.hansson@arm.com // respond with the line in Modified state 23611284Sandreas.hansson@arm.com // (cacheResponding set, hasSharers not set) 23711284Sandreas.hansson@arm.com pkt->setCacheResponding(); 23811197Sandreas.hansson@arm.com 23911284Sandreas.hansson@arm.com if (clusivity == Enums::mostly_excl) { 24011284Sandreas.hansson@arm.com // if this cache is mostly exclusive with 24111284Sandreas.hansson@arm.com // respect to the cache above, drop the 24211284Sandreas.hansson@arm.com // block, no need to first unset the dirty 24311284Sandreas.hansson@arm.com // bit 24411284Sandreas.hansson@arm.com invalidateBlock(blk); 24511284Sandreas.hansson@arm.com } else { 24611284Sandreas.hansson@arm.com // if this cache is mostly inclusive, we 24711284Sandreas.hansson@arm.com // keep the block in the Exclusive state, 24811284Sandreas.hansson@arm.com // and pass it upwards as Modified 24911284Sandreas.hansson@arm.com // (writable and dirty), hence we have 25011284Sandreas.hansson@arm.com // multiple caches, all on the same path 25111284Sandreas.hansson@arm.com // towards memory, all considering the 25211284Sandreas.hansson@arm.com // same block writable, but only one 25311284Sandreas.hansson@arm.com // considering it Modified 25411197Sandreas.hansson@arm.com 25511284Sandreas.hansson@arm.com // we get away with multiple caches (on 25611284Sandreas.hansson@arm.com // the same path to memory) considering 25711284Sandreas.hansson@arm.com // the block writeable as we always enter 25811284Sandreas.hansson@arm.com // the cache hierarchy through a cache, 25911284Sandreas.hansson@arm.com // and first snoop upwards in all other 26011284Sandreas.hansson@arm.com // branches 26111284Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 26211197Sandreas.hansson@arm.com } 26311051Sandreas.hansson@arm.com } else { 26411051Sandreas.hansson@arm.com // if we're responding after our own miss, 26511051Sandreas.hansson@arm.com // there's a window where the recipient didn't 26611051Sandreas.hansson@arm.com // know it was getting ownership and may not 26711051Sandreas.hansson@arm.com // have responded to snoops correctly, so we 26811284Sandreas.hansson@arm.com // have to respond with a shared line 26911284Sandreas.hansson@arm.com pkt->setHasSharers(); 27011051Sandreas.hansson@arm.com } 27111051Sandreas.hansson@arm.com } 27211051Sandreas.hansson@arm.com } else { 27311051Sandreas.hansson@arm.com // otherwise only respond with a shared copy 27411284Sandreas.hansson@arm.com pkt->setHasSharers(); 27511051Sandreas.hansson@arm.com } 27611051Sandreas.hansson@arm.com } 27711051Sandreas.hansson@arm.com } else { 27811284Sandreas.hansson@arm.com // Upgrade or Invalidate 27911051Sandreas.hansson@arm.com assert(pkt->isUpgrade() || pkt->isInvalidate()); 28011197Sandreas.hansson@arm.com 28111197Sandreas.hansson@arm.com // for invalidations we could be looking at the temp block 28211197Sandreas.hansson@arm.com // (for upgrades we always allocate) 28311197Sandreas.hansson@arm.com invalidateBlock(blk); 28411288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d (invalidation)\n", 28511051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 28611051Sandreas.hansson@arm.com } 28711051Sandreas.hansson@arm.com} 28811051Sandreas.hansson@arm.com 28911051Sandreas.hansson@arm.com 29011051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 29111051Sandreas.hansson@arm.com// 29211051Sandreas.hansson@arm.com// MSHR helper functions 29311051Sandreas.hansson@arm.com// 29411051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 29511051Sandreas.hansson@arm.com 29611051Sandreas.hansson@arm.com 29711051Sandreas.hansson@arm.comvoid 29811284Sandreas.hansson@arm.comCache::markInService(MSHR *mshr, bool pending_modified_resp) 29911051Sandreas.hansson@arm.com{ 30011284Sandreas.hansson@arm.com markInServiceInternal(mshr, pending_modified_resp); 30111051Sandreas.hansson@arm.com} 30211051Sandreas.hansson@arm.com 30311051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 30411051Sandreas.hansson@arm.com// 30511051Sandreas.hansson@arm.com// Access path: requests coming in from the CPU side 30611051Sandreas.hansson@arm.com// 30711051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 30811051Sandreas.hansson@arm.com 30911051Sandreas.hansson@arm.combool 31011051Sandreas.hansson@arm.comCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 31111051Sandreas.hansson@arm.com PacketList &writebacks) 31211051Sandreas.hansson@arm.com{ 31311051Sandreas.hansson@arm.com // sanity check 31411051Sandreas.hansson@arm.com assert(pkt->isRequest()); 31511051Sandreas.hansson@arm.com 31611051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 31711051Sandreas.hansson@arm.com "Should never see a write in a read-only cache %s\n", 31811051Sandreas.hansson@arm.com name()); 31911051Sandreas.hansson@arm.com 32011288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d\n", __func__, 32111051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 32211051Sandreas.hansson@arm.com 32311051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 32411051Sandreas.hansson@arm.com DPRINTF(Cache, "%s%s addr %#llx uncacheable\n", pkt->cmdString(), 32511051Sandreas.hansson@arm.com pkt->req->isInstFetch() ? " (ifetch)" : "", 32611051Sandreas.hansson@arm.com pkt->getAddr()); 32711051Sandreas.hansson@arm.com 32811051Sandreas.hansson@arm.com // flush and invalidate any existing block 32911051Sandreas.hansson@arm.com CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure())); 33011051Sandreas.hansson@arm.com if (old_blk && old_blk->isValid()) { 33111199Sandreas.hansson@arm.com if (old_blk->isDirty() || writebackClean) 33211051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(old_blk)); 33311051Sandreas.hansson@arm.com else 33411051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(old_blk)); 33511051Sandreas.hansson@arm.com tags->invalidate(old_blk); 33611051Sandreas.hansson@arm.com old_blk->invalidate(); 33711051Sandreas.hansson@arm.com } 33811051Sandreas.hansson@arm.com 33911051Sandreas.hansson@arm.com blk = NULL; 34011051Sandreas.hansson@arm.com // lookupLatency is the latency in case the request is uncacheable. 34111051Sandreas.hansson@arm.com lat = lookupLatency; 34211051Sandreas.hansson@arm.com return false; 34311051Sandreas.hansson@arm.com } 34411051Sandreas.hansson@arm.com 34511051Sandreas.hansson@arm.com ContextID id = pkt->req->hasContextId() ? 34611051Sandreas.hansson@arm.com pkt->req->contextId() : InvalidContextID; 34711051Sandreas.hansson@arm.com // Here lat is the value passed as parameter to accessBlock() function 34811051Sandreas.hansson@arm.com // that can modify its value. 34911051Sandreas.hansson@arm.com blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat, id); 35011051Sandreas.hansson@arm.com 35111051Sandreas.hansson@arm.com DPRINTF(Cache, "%s%s addr %#llx size %d (%s) %s\n", pkt->cmdString(), 35211051Sandreas.hansson@arm.com pkt->req->isInstFetch() ? " (ifetch)" : "", 35311051Sandreas.hansson@arm.com pkt->getAddr(), pkt->getSize(), pkt->isSecure() ? "s" : "ns", 35411051Sandreas.hansson@arm.com blk ? "hit " + blk->print() : "miss"); 35511051Sandreas.hansson@arm.com 35611051Sandreas.hansson@arm.com 35711199Sandreas.hansson@arm.com if (pkt->isEviction()) { 35811051Sandreas.hansson@arm.com // We check for presence of block in above caches before issuing 35911051Sandreas.hansson@arm.com // Writeback or CleanEvict to write buffer. Therefore the only 36011051Sandreas.hansson@arm.com // possible cases can be of a CleanEvict packet coming from above 36111051Sandreas.hansson@arm.com // encountering a Writeback generated in this cache peer cache and 36211051Sandreas.hansson@arm.com // waiting in the write buffer. Cases of upper level peer caches 36311051Sandreas.hansson@arm.com // generating CleanEvict and Writeback or simply CleanEvict and 36411051Sandreas.hansson@arm.com // CleanEvict almost simultaneously will be caught by snoops sent out 36511051Sandreas.hansson@arm.com // by crossbar. 36611051Sandreas.hansson@arm.com std::vector<MSHR *> outgoing; 36711051Sandreas.hansson@arm.com if (writeBuffer.findMatches(pkt->getAddr(), pkt->isSecure(), 36811051Sandreas.hansson@arm.com outgoing)) { 36911051Sandreas.hansson@arm.com assert(outgoing.size() == 1); 37011199Sandreas.hansson@arm.com MSHR *wb_entry = outgoing[0]; 37111199Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 37211199Sandreas.hansson@arm.com PacketPtr wbPkt = wb_entry->getTarget()->pkt; 37311199Sandreas.hansson@arm.com assert(wbPkt->isWriteback()); 37411199Sandreas.hansson@arm.com 37511199Sandreas.hansson@arm.com if (pkt->isCleanEviction()) { 37611199Sandreas.hansson@arm.com // The CleanEvict and WritebackClean snoops into other 37711199Sandreas.hansson@arm.com // peer caches of the same level while traversing the 37811199Sandreas.hansson@arm.com // crossbar. If a copy of the block is found, the 37911199Sandreas.hansson@arm.com // packet is deleted in the crossbar. Hence, none of 38011199Sandreas.hansson@arm.com // the other upper level caches connected to this 38111199Sandreas.hansson@arm.com // cache have the block, so we can clear the 38211199Sandreas.hansson@arm.com // BLOCK_CACHED flag in the Writeback if set and 38311199Sandreas.hansson@arm.com // discard the CleanEvict by returning true. 38411199Sandreas.hansson@arm.com wbPkt->clearBlockCached(); 38511199Sandreas.hansson@arm.com return true; 38611199Sandreas.hansson@arm.com } else { 38711199Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::WritebackDirty); 38811199Sandreas.hansson@arm.com // Dirty writeback from above trumps our clean 38911199Sandreas.hansson@arm.com // writeback... discard here 39011199Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 39111199Sandreas.hansson@arm.com markInService(wb_entry, false); 39211199Sandreas.hansson@arm.com delete wbPkt; 39311199Sandreas.hansson@arm.com } 39411051Sandreas.hansson@arm.com } 39511051Sandreas.hansson@arm.com } 39611051Sandreas.hansson@arm.com 39711051Sandreas.hansson@arm.com // Writeback handling is special case. We can write the block into 39811051Sandreas.hansson@arm.com // the cache without having a writeable copy (or any copy at all). 39911199Sandreas.hansson@arm.com if (pkt->isWriteback()) { 40011051Sandreas.hansson@arm.com assert(blkSize == pkt->getSize()); 40111199Sandreas.hansson@arm.com 40211199Sandreas.hansson@arm.com // we could get a clean writeback while we are having 40311199Sandreas.hansson@arm.com // outstanding accesses to a block, do the simple thing for 40411199Sandreas.hansson@arm.com // now and drop the clean writeback so that we do not upset 40511199Sandreas.hansson@arm.com // any ordering/decisions about ownership already taken 40611199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackClean && 40711199Sandreas.hansson@arm.com mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) { 40811199Sandreas.hansson@arm.com DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, " 40911199Sandreas.hansson@arm.com "dropping\n", pkt->getAddr()); 41011199Sandreas.hansson@arm.com return true; 41111199Sandreas.hansson@arm.com } 41211199Sandreas.hansson@arm.com 41311051Sandreas.hansson@arm.com if (blk == NULL) { 41411051Sandreas.hansson@arm.com // need to do a replacement 41511051Sandreas.hansson@arm.com blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks); 41611051Sandreas.hansson@arm.com if (blk == NULL) { 41711051Sandreas.hansson@arm.com // no replaceable block available: give up, fwd to next level. 41811051Sandreas.hansson@arm.com incMissCount(pkt); 41911051Sandreas.hansson@arm.com return false; 42011051Sandreas.hansson@arm.com } 42111051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 42211051Sandreas.hansson@arm.com 42311051Sandreas.hansson@arm.com blk->status = (BlkValid | BlkReadable); 42411051Sandreas.hansson@arm.com if (pkt->isSecure()) { 42511051Sandreas.hansson@arm.com blk->status |= BlkSecure; 42611051Sandreas.hansson@arm.com } 42711051Sandreas.hansson@arm.com } 42811199Sandreas.hansson@arm.com // only mark the block dirty if we got a writeback command, 42911199Sandreas.hansson@arm.com // and leave it as is for a clean writeback 43011199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackDirty) { 43111199Sandreas.hansson@arm.com blk->status |= BlkDirty; 43211199Sandreas.hansson@arm.com } 43311284Sandreas.hansson@arm.com // if the packet does not have sharers, it is passing 43411284Sandreas.hansson@arm.com // writable, and we got the writeback in Modified or Exclusive 43511284Sandreas.hansson@arm.com // state, if not we are in the Owned or Shared state 43611284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 43711051Sandreas.hansson@arm.com blk->status |= BlkWritable; 43811051Sandreas.hansson@arm.com } 43911051Sandreas.hansson@arm.com // nothing else to do; writeback doesn't expect response 44011051Sandreas.hansson@arm.com assert(!pkt->needsResponse()); 44111051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 44211051Sandreas.hansson@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 44311051Sandreas.hansson@arm.com incHitCount(pkt); 44411051Sandreas.hansson@arm.com return true; 44511051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::CleanEvict) { 44611051Sandreas.hansson@arm.com if (blk != NULL) { 44711051Sandreas.hansson@arm.com // Found the block in the tags, need to stop CleanEvict from 44811051Sandreas.hansson@arm.com // propagating further down the hierarchy. Returning true will 44911051Sandreas.hansson@arm.com // treat the CleanEvict like a satisfied write request and delete 45011051Sandreas.hansson@arm.com // it. 45111051Sandreas.hansson@arm.com return true; 45211051Sandreas.hansson@arm.com } 45311051Sandreas.hansson@arm.com // We didn't find the block here, propagate the CleanEvict further 45411051Sandreas.hansson@arm.com // down the memory hierarchy. Returning false will treat the CleanEvict 45511051Sandreas.hansson@arm.com // like a Writeback which could not find a replaceable block so has to 45611051Sandreas.hansson@arm.com // go to next level. 45711051Sandreas.hansson@arm.com return false; 45811051Sandreas.hansson@arm.com } else if ((blk != NULL) && 45911284Sandreas.hansson@arm.com (pkt->needsWritable() ? blk->isWritable() : blk->isReadable())) { 46011051Sandreas.hansson@arm.com // OK to satisfy access 46111051Sandreas.hansson@arm.com incHitCount(pkt); 46211051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 46311051Sandreas.hansson@arm.com return true; 46411051Sandreas.hansson@arm.com } 46511051Sandreas.hansson@arm.com 46611051Sandreas.hansson@arm.com // Can't satisfy access normally... either no block (blk == NULL) 46711284Sandreas.hansson@arm.com // or have block but need writable 46811051Sandreas.hansson@arm.com 46911051Sandreas.hansson@arm.com incMissCount(pkt); 47011051Sandreas.hansson@arm.com 47111051Sandreas.hansson@arm.com if (blk == NULL && pkt->isLLSC() && pkt->isWrite()) { 47211051Sandreas.hansson@arm.com // complete miss on store conditional... just give up now 47311051Sandreas.hansson@arm.com pkt->req->setExtraData(0); 47411051Sandreas.hansson@arm.com return true; 47511051Sandreas.hansson@arm.com } 47611051Sandreas.hansson@arm.com 47711051Sandreas.hansson@arm.com return false; 47811051Sandreas.hansson@arm.com} 47911051Sandreas.hansson@arm.com 48011051Sandreas.hansson@arm.comvoid 48111051Sandreas.hansson@arm.comCache::doWritebacks(PacketList& writebacks, Tick forward_time) 48211051Sandreas.hansson@arm.com{ 48311051Sandreas.hansson@arm.com while (!writebacks.empty()) { 48411051Sandreas.hansson@arm.com PacketPtr wbPkt = writebacks.front(); 48511051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying writebacks to 48611051Sandreas.hansson@arm.com // write buffer. Call isCachedAbove for both Writebacks and 48711051Sandreas.hansson@arm.com // CleanEvicts. If isCachedAbove returns true we set BLOCK_CACHED flag 48811051Sandreas.hansson@arm.com // in Writebacks and discard CleanEvicts. 48911051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) { 49011051Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::CleanEvict) { 49111051Sandreas.hansson@arm.com // Delete CleanEvict because cached copies exist above. The 49211051Sandreas.hansson@arm.com // packet destructor will delete the request object because 49311051Sandreas.hansson@arm.com // this is a non-snoop request packet which does not require a 49411051Sandreas.hansson@arm.com // response. 49511051Sandreas.hansson@arm.com delete wbPkt; 49611199Sandreas.hansson@arm.com } else if (wbPkt->cmd == MemCmd::WritebackClean) { 49711199Sandreas.hansson@arm.com // clean writeback, do not send since the block is 49811199Sandreas.hansson@arm.com // still cached above 49911199Sandreas.hansson@arm.com assert(writebackClean); 50011199Sandreas.hansson@arm.com delete wbPkt; 50111051Sandreas.hansson@arm.com } else { 50211199Sandreas.hansson@arm.com assert(wbPkt->cmd == MemCmd::WritebackDirty); 50311051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag in Writeback and send below, so that 50411051Sandreas.hansson@arm.com // the Writeback does not reset the bit corresponding to this 50511051Sandreas.hansson@arm.com // address in the snoop filter below. 50611051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 50711051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 50811051Sandreas.hansson@arm.com } 50911051Sandreas.hansson@arm.com } else { 51011051Sandreas.hansson@arm.com // If the block is not cached above, send packet below. Both 51111051Sandreas.hansson@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 51211051Sandreas.hansson@arm.com // reset the bit corresponding to this address in the snoop filter 51311051Sandreas.hansson@arm.com // below. 51411051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 51511051Sandreas.hansson@arm.com } 51611051Sandreas.hansson@arm.com writebacks.pop_front(); 51711051Sandreas.hansson@arm.com } 51811051Sandreas.hansson@arm.com} 51911051Sandreas.hansson@arm.com 52011130Sali.jafri@arm.comvoid 52111130Sali.jafri@arm.comCache::doWritebacksAtomic(PacketList& writebacks) 52211130Sali.jafri@arm.com{ 52311130Sali.jafri@arm.com while (!writebacks.empty()) { 52411130Sali.jafri@arm.com PacketPtr wbPkt = writebacks.front(); 52511130Sali.jafri@arm.com // Call isCachedAbove for both Writebacks and CleanEvicts. If 52611130Sali.jafri@arm.com // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks 52711130Sali.jafri@arm.com // and discard CleanEvicts. 52811130Sali.jafri@arm.com if (isCachedAbove(wbPkt, false)) { 52911199Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::WritebackDirty) { 53011130Sali.jafri@arm.com // Set BLOCK_CACHED flag in Writeback and send below, 53111130Sali.jafri@arm.com // so that the Writeback does not reset the bit 53211130Sali.jafri@arm.com // corresponding to this address in the snoop filter 53311130Sali.jafri@arm.com // below. We can discard CleanEvicts because cached 53411130Sali.jafri@arm.com // copies exist above. Atomic mode isCachedAbove 53511130Sali.jafri@arm.com // modifies packet to set BLOCK_CACHED flag 53611130Sali.jafri@arm.com memSidePort->sendAtomic(wbPkt); 53711130Sali.jafri@arm.com } 53811130Sali.jafri@arm.com } else { 53911130Sali.jafri@arm.com // If the block is not cached above, send packet below. Both 54011130Sali.jafri@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 54111130Sali.jafri@arm.com // reset the bit corresponding to this address in the snoop filter 54211130Sali.jafri@arm.com // below. 54311130Sali.jafri@arm.com memSidePort->sendAtomic(wbPkt); 54411130Sali.jafri@arm.com } 54511130Sali.jafri@arm.com writebacks.pop_front(); 54611130Sali.jafri@arm.com // In case of CleanEvicts, the packet destructor will delete the 54711130Sali.jafri@arm.com // request object because this is a non-snoop request packet which 54811130Sali.jafri@arm.com // does not require a response. 54911130Sali.jafri@arm.com delete wbPkt; 55011130Sali.jafri@arm.com } 55111130Sali.jafri@arm.com} 55211130Sali.jafri@arm.com 55311051Sandreas.hansson@arm.com 55411051Sandreas.hansson@arm.comvoid 55511051Sandreas.hansson@arm.comCache::recvTimingSnoopResp(PacketPtr pkt) 55611051Sandreas.hansson@arm.com{ 55711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 55811051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 55911051Sandreas.hansson@arm.com 56011051Sandreas.hansson@arm.com assert(pkt->isResponse()); 56111051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 56211051Sandreas.hansson@arm.com 56311276Sandreas.hansson@arm.com // determine if the response is from a snoop request we created 56411276Sandreas.hansson@arm.com // (in which case it should be in the outstandingSnoop), or if we 56511276Sandreas.hansson@arm.com // merely forwarded someone else's snoop request 56611276Sandreas.hansson@arm.com const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) == 56711276Sandreas.hansson@arm.com outstandingSnoop.end(); 56811276Sandreas.hansson@arm.com 56911276Sandreas.hansson@arm.com if (!forwardAsSnoop) { 57011276Sandreas.hansson@arm.com // the packet came from this cache, so sink it here and do not 57111276Sandreas.hansson@arm.com // forward it 57211051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::HardPFResp); 57311276Sandreas.hansson@arm.com 57411276Sandreas.hansson@arm.com outstandingSnoop.erase(pkt->req); 57511276Sandreas.hansson@arm.com 57611276Sandreas.hansson@arm.com DPRINTF(Cache, "Got prefetch response from above for addr " 57711276Sandreas.hansson@arm.com "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 57811051Sandreas.hansson@arm.com recvTimingResp(pkt); 57911051Sandreas.hansson@arm.com return; 58011051Sandreas.hansson@arm.com } 58111051Sandreas.hansson@arm.com 58211051Sandreas.hansson@arm.com // forwardLatency is set here because there is a response from an 58311051Sandreas.hansson@arm.com // upper level cache. 58411051Sandreas.hansson@arm.com // To pay the delay that occurs if the packet comes from the bus, 58511051Sandreas.hansson@arm.com // we charge also headerDelay. 58611051Sandreas.hansson@arm.com Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay; 58711051Sandreas.hansson@arm.com // Reset the timing of the packet. 58811051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 58911051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, snoop_resp_time); 59011051Sandreas.hansson@arm.com} 59111051Sandreas.hansson@arm.com 59211051Sandreas.hansson@arm.comvoid 59311051Sandreas.hansson@arm.comCache::promoteWholeLineWrites(PacketPtr pkt) 59411051Sandreas.hansson@arm.com{ 59511051Sandreas.hansson@arm.com // Cache line clearing instructions 59611051Sandreas.hansson@arm.com if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) && 59711051Sandreas.hansson@arm.com (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) { 59811051Sandreas.hansson@arm.com pkt->cmd = MemCmd::WriteLineReq; 59911051Sandreas.hansson@arm.com DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n"); 60011051Sandreas.hansson@arm.com } 60111051Sandreas.hansson@arm.com} 60211051Sandreas.hansson@arm.com 60311051Sandreas.hansson@arm.combool 60411051Sandreas.hansson@arm.comCache::recvTimingReq(PacketPtr pkt) 60511051Sandreas.hansson@arm.com{ 60611051Sandreas.hansson@arm.com DPRINTF(CacheTags, "%s tags: %s\n", __func__, tags->print()); 60711051Sandreas.hansson@arm.com 60811051Sandreas.hansson@arm.com assert(pkt->isRequest()); 60911051Sandreas.hansson@arm.com 61011051Sandreas.hansson@arm.com // Just forward the packet if caches are disabled. 61111051Sandreas.hansson@arm.com if (system->bypassCaches()) { 61211051Sandreas.hansson@arm.com // @todo This should really enqueue the packet rather 61311051Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt); 61411051Sandreas.hansson@arm.com assert(success); 61511051Sandreas.hansson@arm.com return true; 61611051Sandreas.hansson@arm.com } 61711051Sandreas.hansson@arm.com 61811051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 61911051Sandreas.hansson@arm.com 62011284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 62111051Sandreas.hansson@arm.com // a cache above us (but not where the packet came from) is 62211284Sandreas.hansson@arm.com // responding to the request, in other words it has the line 62311284Sandreas.hansson@arm.com // in Modified or Owned state 62411284Sandreas.hansson@arm.com DPRINTF(Cache, "Cache above responding to %#llx (%s): " 62511284Sandreas.hansson@arm.com "not responding\n", 62611051Sandreas.hansson@arm.com pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 62711051Sandreas.hansson@arm.com 62811284Sandreas.hansson@arm.com // if the packet needs the block to be writable, and the cache 62911284Sandreas.hansson@arm.com // that has promised to respond (setting the cache responding 63011284Sandreas.hansson@arm.com // flag) is not providing writable (it is in Owned rather than 63111284Sandreas.hansson@arm.com // the Modified state), we know that there may be other Shared 63211284Sandreas.hansson@arm.com // copies in the system; go out and invalidate them all 63311284Sandreas.hansson@arm.com if (pkt->needsWritable() && !pkt->responderHadWritable()) { 63411284Sandreas.hansson@arm.com // an upstream cache that had the line in Owned state 63511284Sandreas.hansson@arm.com // (dirty, but not writable), is responding and thus 63611284Sandreas.hansson@arm.com // transferring the dirty line from one branch of the 63711284Sandreas.hansson@arm.com // cache hierarchy to another 63811284Sandreas.hansson@arm.com 63911284Sandreas.hansson@arm.com // send out an express snoop and invalidate all other 64011284Sandreas.hansson@arm.com // copies (snooping a packet that needs writable is the 64111284Sandreas.hansson@arm.com // same as an invalidation), thus turning the Owned line 64211284Sandreas.hansson@arm.com // into a Modified line, note that we don't invalidate the 64311284Sandreas.hansson@arm.com // block in the current cache or any other cache on the 64411284Sandreas.hansson@arm.com // path to memory 64511284Sandreas.hansson@arm.com 64611051Sandreas.hansson@arm.com // create a downstream express snoop with cleared packet 64711051Sandreas.hansson@arm.com // flags, there is no need to allocate any data as the 64811051Sandreas.hansson@arm.com // packet is merely used to co-ordinate state transitions 64911051Sandreas.hansson@arm.com Packet *snoop_pkt = new Packet(pkt, true, false); 65011051Sandreas.hansson@arm.com 65111051Sandreas.hansson@arm.com // also reset the bus time that the original packet has 65211051Sandreas.hansson@arm.com // not yet paid for 65311051Sandreas.hansson@arm.com snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0; 65411051Sandreas.hansson@arm.com 65511051Sandreas.hansson@arm.com // make this an instantaneous express snoop, and let the 65611284Sandreas.hansson@arm.com // other caches in the system know that the another cache 65711284Sandreas.hansson@arm.com // is responding, because we have found the authorative 65811284Sandreas.hansson@arm.com // copy (Modified or Owned) that will supply the right 65911284Sandreas.hansson@arm.com // data 66011051Sandreas.hansson@arm.com snoop_pkt->setExpressSnoop(); 66111284Sandreas.hansson@arm.com snoop_pkt->setCacheResponding(); 66211051Sandreas.hansson@arm.com 66311051Sandreas.hansson@arm.com // this express snoop travels towards the memory, and at 66411051Sandreas.hansson@arm.com // every crossbar it is snooped upwards thus reaching 66511051Sandreas.hansson@arm.com // every cache in the system 66611051Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(snoop_pkt); 66711051Sandreas.hansson@arm.com // express snoops always succeed 66811051Sandreas.hansson@arm.com assert(success); 66911051Sandreas.hansson@arm.com 67011284Sandreas.hansson@arm.com // main memory will delete the snoop packet 67111051Sandreas.hansson@arm.com } 67211051Sandreas.hansson@arm.com 67311284Sandreas.hansson@arm.com // queue for deletion, as opposed to immediate deletion, as 67411284Sandreas.hansson@arm.com // the sending cache is still relying on the packet 67511190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 67611051Sandreas.hansson@arm.com 67711284Sandreas.hansson@arm.com // no need to take any action in this particular cache as an 67811284Sandreas.hansson@arm.com // upstream cache has already committed to responding, and 67911284Sandreas.hansson@arm.com // either the packet does not need writable (and we can let 68011284Sandreas.hansson@arm.com // the cache that set the cache responding flag pass on the 68111284Sandreas.hansson@arm.com // line without any need for intervention), or if the packet 68211284Sandreas.hansson@arm.com // needs writable it is provided, or we have already sent out 68311284Sandreas.hansson@arm.com // any express snoops in the section above 68411051Sandreas.hansson@arm.com return true; 68511051Sandreas.hansson@arm.com } 68611051Sandreas.hansson@arm.com 68711051Sandreas.hansson@arm.com // anything that is merely forwarded pays for the forward latency and 68811051Sandreas.hansson@arm.com // the delay provided by the crossbar 68911051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 69011051Sandreas.hansson@arm.com 69111051Sandreas.hansson@arm.com // We use lookupLatency here because it is used to specify the latency 69211051Sandreas.hansson@arm.com // to access. 69311051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 69411051Sandreas.hansson@arm.com CacheBlk *blk = NULL; 69511051Sandreas.hansson@arm.com bool satisfied = false; 69611051Sandreas.hansson@arm.com { 69711051Sandreas.hansson@arm.com PacketList writebacks; 69811051Sandreas.hansson@arm.com // Note that lat is passed by reference here. The function 69911051Sandreas.hansson@arm.com // access() calls accessBlock() which can modify lat value. 70011051Sandreas.hansson@arm.com satisfied = access(pkt, blk, lat, writebacks); 70111051Sandreas.hansson@arm.com 70211051Sandreas.hansson@arm.com // copy writebacks to write buffer here to ensure they logically 70311051Sandreas.hansson@arm.com // proceed anything happening below 70411051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 70511051Sandreas.hansson@arm.com } 70611051Sandreas.hansson@arm.com 70711051Sandreas.hansson@arm.com // Here we charge the headerDelay that takes into account the latencies 70811051Sandreas.hansson@arm.com // of the bus, if the packet comes from it. 70911051Sandreas.hansson@arm.com // The latency charged it is just lat that is the value of lookupLatency 71011051Sandreas.hansson@arm.com // modified by access() function, or if not just lookupLatency. 71111051Sandreas.hansson@arm.com // In case of a hit we are neglecting response latency. 71211051Sandreas.hansson@arm.com // In case of a miss we are neglecting forward latency. 71311051Sandreas.hansson@arm.com Tick request_time = clockEdge(lat) + pkt->headerDelay; 71411051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 71511051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 71611051Sandreas.hansson@arm.com 71711051Sandreas.hansson@arm.com // track time of availability of next prefetch, if any 71811051Sandreas.hansson@arm.com Tick next_pf_time = MaxTick; 71911051Sandreas.hansson@arm.com 72011051Sandreas.hansson@arm.com bool needsResponse = pkt->needsResponse(); 72111051Sandreas.hansson@arm.com 72211051Sandreas.hansson@arm.com if (satisfied) { 72311051Sandreas.hansson@arm.com // should never be satisfying an uncacheable access as we 72411051Sandreas.hansson@arm.com // flush and invalidate any existing block as part of the 72511051Sandreas.hansson@arm.com // lookup 72611051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 72711051Sandreas.hansson@arm.com 72811051Sandreas.hansson@arm.com // hit (for all other request types) 72911051Sandreas.hansson@arm.com 73011051Sandreas.hansson@arm.com if (prefetcher && (prefetchOnAccess || (blk && blk->wasPrefetched()))) { 73111051Sandreas.hansson@arm.com if (blk) 73211051Sandreas.hansson@arm.com blk->status &= ~BlkHWPrefetched; 73311051Sandreas.hansson@arm.com 73411051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 73511051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 73611051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 73711051Sandreas.hansson@arm.com } 73811051Sandreas.hansson@arm.com 73911051Sandreas.hansson@arm.com if (needsResponse) { 74011051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 74111051Sandreas.hansson@arm.com // @todo: Make someone pay for this 74211051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 74311051Sandreas.hansson@arm.com 74411051Sandreas.hansson@arm.com // In this case we are considering request_time that takes 74511051Sandreas.hansson@arm.com // into account the delay of the xbar, if any, and just 74611051Sandreas.hansson@arm.com // lat, neglecting responseLatency, modelling hit latency 74711051Sandreas.hansson@arm.com // just as lookupLatency or or the value of lat overriden 74811051Sandreas.hansson@arm.com // by access(), that calls accessBlock() function. 74911194Sali.jafri@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 75011051Sandreas.hansson@arm.com } else { 75111199Sandreas.hansson@arm.com DPRINTF(Cache, "%s satisfied %s addr %#llx, no response needed\n", 75211199Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), 75311199Sandreas.hansson@arm.com pkt->getSize()); 75411199Sandreas.hansson@arm.com 75511190Sandreas.hansson@arm.com // queue the packet for deletion, as the sending cache is 75611190Sandreas.hansson@arm.com // still relying on it; if the block is found in access(), 75711190Sandreas.hansson@arm.com // CleanEvict and Writeback messages will be deleted 75811190Sandreas.hansson@arm.com // here as well 75911190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 76011051Sandreas.hansson@arm.com } 76111051Sandreas.hansson@arm.com } else { 76211051Sandreas.hansson@arm.com // miss 76311051Sandreas.hansson@arm.com 76411051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 76511051Sandreas.hansson@arm.com 76611051Sandreas.hansson@arm.com // ignore any existing MSHR if we are dealing with an 76711051Sandreas.hansson@arm.com // uncacheable request 76811051Sandreas.hansson@arm.com MSHR *mshr = pkt->req->isUncacheable() ? nullptr : 76911051Sandreas.hansson@arm.com mshrQueue.findMatch(blk_addr, pkt->isSecure()); 77011051Sandreas.hansson@arm.com 77111051Sandreas.hansson@arm.com // Software prefetch handling: 77211051Sandreas.hansson@arm.com // To keep the core from waiting on data it won't look at 77311051Sandreas.hansson@arm.com // anyway, send back a response with dummy data. Miss handling 77411051Sandreas.hansson@arm.com // will continue asynchronously. Unfortunately, the core will 77511051Sandreas.hansson@arm.com // insist upon freeing original Packet/Request, so we have to 77611051Sandreas.hansson@arm.com // create a new pair with a different lifecycle. Note that this 77711051Sandreas.hansson@arm.com // processing happens before any MSHR munging on the behalf of 77811051Sandreas.hansson@arm.com // this request because this new Request will be the one stored 77911051Sandreas.hansson@arm.com // into the MSHRs, not the original. 78011051Sandreas.hansson@arm.com if (pkt->cmd.isSWPrefetch()) { 78111051Sandreas.hansson@arm.com assert(needsResponse); 78211051Sandreas.hansson@arm.com assert(pkt->req->hasPaddr()); 78311051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 78411051Sandreas.hansson@arm.com 78511051Sandreas.hansson@arm.com // There's no reason to add a prefetch as an additional target 78611051Sandreas.hansson@arm.com // to an existing MSHR. If an outstanding request is already 78711051Sandreas.hansson@arm.com // in progress, there is nothing for the prefetch to do. 78811051Sandreas.hansson@arm.com // If this is the case, we don't even create a request at all. 78911051Sandreas.hansson@arm.com PacketPtr pf = nullptr; 79011051Sandreas.hansson@arm.com 79111051Sandreas.hansson@arm.com if (!mshr) { 79211051Sandreas.hansson@arm.com // copy the request and create a new SoftPFReq packet 79311051Sandreas.hansson@arm.com RequestPtr req = new Request(pkt->req->getPaddr(), 79411051Sandreas.hansson@arm.com pkt->req->getSize(), 79511051Sandreas.hansson@arm.com pkt->req->getFlags(), 79611051Sandreas.hansson@arm.com pkt->req->masterId()); 79711051Sandreas.hansson@arm.com pf = new Packet(req, pkt->cmd); 79811051Sandreas.hansson@arm.com pf->allocate(); 79911051Sandreas.hansson@arm.com assert(pf->getAddr() == pkt->getAddr()); 80011051Sandreas.hansson@arm.com assert(pf->getSize() == pkt->getSize()); 80111051Sandreas.hansson@arm.com } 80211051Sandreas.hansson@arm.com 80311051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 80411286Sandreas.hansson@arm.com 80511051Sandreas.hansson@arm.com // request_time is used here, taking into account lat and the delay 80611051Sandreas.hansson@arm.com // charged if the packet comes from the xbar. 80711194Sali.jafri@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 80811051Sandreas.hansson@arm.com 80911051Sandreas.hansson@arm.com // If an outstanding request is in progress (we found an 81011051Sandreas.hansson@arm.com // MSHR) this is set to null 81111051Sandreas.hansson@arm.com pkt = pf; 81211051Sandreas.hansson@arm.com } 81311051Sandreas.hansson@arm.com 81411051Sandreas.hansson@arm.com if (mshr) { 81511051Sandreas.hansson@arm.com /// MSHR hit 81611051Sandreas.hansson@arm.com /// @note writebacks will be checked in getNextMSHR() 81711051Sandreas.hansson@arm.com /// for any conflicting requests to the same block 81811051Sandreas.hansson@arm.com 81911051Sandreas.hansson@arm.com //@todo remove hw_pf here 82011051Sandreas.hansson@arm.com 82111051Sandreas.hansson@arm.com // Coalesce unless it was a software prefetch (see above). 82211051Sandreas.hansson@arm.com if (pkt) { 82311199Sandreas.hansson@arm.com assert(!pkt->isWriteback()); 82411199Sandreas.hansson@arm.com // CleanEvicts corresponding to blocks which have 82511199Sandreas.hansson@arm.com // outstanding requests in MSHRs are simply sunk here 82611051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::CleanEvict) { 82711190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 82811051Sandreas.hansson@arm.com } else { 82911051Sandreas.hansson@arm.com DPRINTF(Cache, "%s coalescing MSHR for %s addr %#llx size %d\n", 83011051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), 83111051Sandreas.hansson@arm.com pkt->getSize()); 83211051Sandreas.hansson@arm.com 83311051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 83411051Sandreas.hansson@arm.com mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 83511051Sandreas.hansson@arm.com // We use forward_time here because it is the same 83611051Sandreas.hansson@arm.com // considering new targets. We have multiple 83711051Sandreas.hansson@arm.com // requests for the same address here. It 83811051Sandreas.hansson@arm.com // specifies the latency to allocate an internal 83911051Sandreas.hansson@arm.com // buffer and to schedule an event to the queued 84011051Sandreas.hansson@arm.com // port and also takes into account the additional 84111051Sandreas.hansson@arm.com // delay of the xbar. 84211197Sandreas.hansson@arm.com mshr->allocateTarget(pkt, forward_time, order++, 84311197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 84411051Sandreas.hansson@arm.com if (mshr->getNumTargets() == numTarget) { 84511051Sandreas.hansson@arm.com noTargetMSHR = mshr; 84611051Sandreas.hansson@arm.com setBlocked(Blocked_NoTargets); 84711051Sandreas.hansson@arm.com // need to be careful with this... if this mshr isn't 84811051Sandreas.hansson@arm.com // ready yet (i.e. time > curTick()), we don't want to 84911051Sandreas.hansson@arm.com // move it ahead of mshrs that are ready 85011051Sandreas.hansson@arm.com // mshrQueue.moveToFront(mshr); 85111051Sandreas.hansson@arm.com } 85211051Sandreas.hansson@arm.com } 85311051Sandreas.hansson@arm.com // We should call the prefetcher reguardless if the request is 85411051Sandreas.hansson@arm.com // satisfied or not, reguardless if the request is in the MSHR or 85511051Sandreas.hansson@arm.com // not. The request could be a ReadReq hit, but still not 85611051Sandreas.hansson@arm.com // satisfied (potentially because of a prior write to the same 85711051Sandreas.hansson@arm.com // cache line. So, even when not satisfied, tehre is an MSHR 85811051Sandreas.hansson@arm.com // already allocated for this, we need to let the prefetcher know 85911051Sandreas.hansson@arm.com // about the request 86011051Sandreas.hansson@arm.com if (prefetcher) { 86111051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 86211051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 86311051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 86411051Sandreas.hansson@arm.com } 86511051Sandreas.hansson@arm.com } 86611051Sandreas.hansson@arm.com } else { 86711051Sandreas.hansson@arm.com // no MSHR 86811051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 86911051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 87011051Sandreas.hansson@arm.com mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++; 87111051Sandreas.hansson@arm.com } else { 87211051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 87311051Sandreas.hansson@arm.com } 87411051Sandreas.hansson@arm.com 87511199Sandreas.hansson@arm.com if (pkt->isEviction() || 87611051Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 87711051Sandreas.hansson@arm.com // We use forward_time here because there is an 87811051Sandreas.hansson@arm.com // uncached memory write, forwarded to WriteBuffer. 87911051Sandreas.hansson@arm.com allocateWriteBuffer(pkt, forward_time); 88011051Sandreas.hansson@arm.com } else { 88111051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 88211051Sandreas.hansson@arm.com // should have flushed and have no valid block 88311051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 88411051Sandreas.hansson@arm.com 88511051Sandreas.hansson@arm.com // If we have a write miss to a valid block, we 88611051Sandreas.hansson@arm.com // need to mark the block non-readable. Otherwise 88711051Sandreas.hansson@arm.com // if we allow reads while there's an outstanding 88811051Sandreas.hansson@arm.com // write miss, the read could return stale data 88911051Sandreas.hansson@arm.com // out of the cache block... a more aggressive 89011051Sandreas.hansson@arm.com // system could detect the overlap (if any) and 89111051Sandreas.hansson@arm.com // forward data out of the MSHRs, but we don't do 89211051Sandreas.hansson@arm.com // that yet. Note that we do need to leave the 89311051Sandreas.hansson@arm.com // block valid so that it stays in the cache, in 89411051Sandreas.hansson@arm.com // case we get an upgrade response (and hence no 89511051Sandreas.hansson@arm.com // new data) when the write miss completes. 89611051Sandreas.hansson@arm.com // As long as CPUs do proper store/load forwarding 89711051Sandreas.hansson@arm.com // internally, and have a sufficiently weak memory 89811051Sandreas.hansson@arm.com // model, this is probably unnecessary, but at some 89911051Sandreas.hansson@arm.com // point it must have seemed like we needed it... 90011284Sandreas.hansson@arm.com assert(pkt->needsWritable()); 90111051Sandreas.hansson@arm.com assert(!blk->isWritable()); 90211051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 90311051Sandreas.hansson@arm.com } 90411051Sandreas.hansson@arm.com // Here we are using forward_time, modelling the latency of 90511051Sandreas.hansson@arm.com // a miss (outbound) just as forwardLatency, neglecting the 90611051Sandreas.hansson@arm.com // lookupLatency component. 90711051Sandreas.hansson@arm.com allocateMissBuffer(pkt, forward_time); 90811051Sandreas.hansson@arm.com } 90911051Sandreas.hansson@arm.com 91011051Sandreas.hansson@arm.com if (prefetcher) { 91111051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 91211051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 91311051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 91411051Sandreas.hansson@arm.com } 91511051Sandreas.hansson@arm.com } 91611051Sandreas.hansson@arm.com } 91711051Sandreas.hansson@arm.com 91811051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 91911051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 92011051Sandreas.hansson@arm.com 92111051Sandreas.hansson@arm.com return true; 92211051Sandreas.hansson@arm.com} 92311051Sandreas.hansson@arm.com 92411051Sandreas.hansson@arm.com 92511051Sandreas.hansson@arm.com// See comment in cache.hh. 92611051Sandreas.hansson@arm.comPacketPtr 92711051Sandreas.hansson@arm.comCache::getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk, 92811284Sandreas.hansson@arm.com bool needsWritable) const 92911051Sandreas.hansson@arm.com{ 93011051Sandreas.hansson@arm.com bool blkValid = blk && blk->isValid(); 93111051Sandreas.hansson@arm.com 93211051Sandreas.hansson@arm.com if (cpu_pkt->req->isUncacheable()) { 93311051Sandreas.hansson@arm.com // note that at the point we see the uncacheable request we 93411051Sandreas.hansson@arm.com // flush any block, but there could be an outstanding MSHR, 93511051Sandreas.hansson@arm.com // and the cache could have filled again before we actually 93611051Sandreas.hansson@arm.com // send out the forwarded uncacheable request (blk could thus 93711051Sandreas.hansson@arm.com // be non-null) 93811051Sandreas.hansson@arm.com return NULL; 93911051Sandreas.hansson@arm.com } 94011051Sandreas.hansson@arm.com 94111051Sandreas.hansson@arm.com if (!blkValid && 94211051Sandreas.hansson@arm.com (cpu_pkt->isUpgrade() || 94311199Sandreas.hansson@arm.com cpu_pkt->isEviction())) { 94411051Sandreas.hansson@arm.com // Writebacks that weren't allocated in access() and upgrades 94511051Sandreas.hansson@arm.com // from upper-level caches that missed completely just go 94611051Sandreas.hansson@arm.com // through. 94711051Sandreas.hansson@arm.com return NULL; 94811051Sandreas.hansson@arm.com } 94911051Sandreas.hansson@arm.com 95011051Sandreas.hansson@arm.com assert(cpu_pkt->needsResponse()); 95111051Sandreas.hansson@arm.com 95211051Sandreas.hansson@arm.com MemCmd cmd; 95311051Sandreas.hansson@arm.com // @TODO make useUpgrades a parameter. 95411051Sandreas.hansson@arm.com // Note that ownership protocols require upgrade, otherwise a 95511051Sandreas.hansson@arm.com // write miss on a shared owned block will generate a ReadExcl, 95611051Sandreas.hansson@arm.com // which will clobber the owned copy. 95711051Sandreas.hansson@arm.com const bool useUpgrades = true; 95811051Sandreas.hansson@arm.com if (blkValid && useUpgrades) { 95911284Sandreas.hansson@arm.com // only reason to be here is that blk is read only and we need 96011284Sandreas.hansson@arm.com // it to be writable 96111284Sandreas.hansson@arm.com assert(needsWritable); 96211051Sandreas.hansson@arm.com assert(!blk->isWritable()); 96311051Sandreas.hansson@arm.com cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq; 96411051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq || 96511051Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::StoreCondFailReq) { 96611051Sandreas.hansson@arm.com // Even though this SC will fail, we still need to send out the 96711051Sandreas.hansson@arm.com // request and get the data to supply it to other snoopers in the case 96811051Sandreas.hansson@arm.com // where the determination the StoreCond fails is delayed due to 96911051Sandreas.hansson@arm.com // all caches not being on the same local bus. 97011051Sandreas.hansson@arm.com cmd = MemCmd::SCUpgradeFailReq; 97111051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::WriteLineReq) { 97211051Sandreas.hansson@arm.com // forward as invalidate to all other caches, this gives us 97311284Sandreas.hansson@arm.com // the line in Exclusive state, and invalidates all other 97411051Sandreas.hansson@arm.com // copies 97511051Sandreas.hansson@arm.com cmd = MemCmd::InvalidateReq; 97611051Sandreas.hansson@arm.com } else { 97711051Sandreas.hansson@arm.com // block is invalid 97811284Sandreas.hansson@arm.com cmd = needsWritable ? MemCmd::ReadExReq : 97911051Sandreas.hansson@arm.com (isReadOnly ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq); 98011051Sandreas.hansson@arm.com } 98111051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize); 98211051Sandreas.hansson@arm.com 98311284Sandreas.hansson@arm.com // if there are upstream caches that have already marked the 98411284Sandreas.hansson@arm.com // packet as having sharers (not passing writable), pass that info 98511284Sandreas.hansson@arm.com // downstream 98611284Sandreas.hansson@arm.com if (cpu_pkt->hasSharers()) { 98711051Sandreas.hansson@arm.com // note that cpu_pkt may have spent a considerable time in the 98811051Sandreas.hansson@arm.com // MSHR queue and that the information could possibly be out 98911051Sandreas.hansson@arm.com // of date, however, there is no harm in conservatively 99011284Sandreas.hansson@arm.com // assuming the block has sharers 99111284Sandreas.hansson@arm.com pkt->setHasSharers(); 99211284Sandreas.hansson@arm.com DPRINTF(Cache, "%s passing hasSharers from %s to %s addr %#llx " 99311284Sandreas.hansson@arm.com "size %d\n", 99411051Sandreas.hansson@arm.com __func__, cpu_pkt->cmdString(), pkt->cmdString(), 99511051Sandreas.hansson@arm.com pkt->getAddr(), pkt->getSize()); 99611051Sandreas.hansson@arm.com } 99711051Sandreas.hansson@arm.com 99811051Sandreas.hansson@arm.com // the packet should be block aligned 99911051Sandreas.hansson@arm.com assert(pkt->getAddr() == blockAlign(pkt->getAddr())); 100011051Sandreas.hansson@arm.com 100111051Sandreas.hansson@arm.com pkt->allocate(); 100211051Sandreas.hansson@arm.com DPRINTF(Cache, "%s created %s from %s for addr %#llx size %d\n", 100311051Sandreas.hansson@arm.com __func__, pkt->cmdString(), cpu_pkt->cmdString(), pkt->getAddr(), 100411051Sandreas.hansson@arm.com pkt->getSize()); 100511051Sandreas.hansson@arm.com return pkt; 100611051Sandreas.hansson@arm.com} 100711051Sandreas.hansson@arm.com 100811051Sandreas.hansson@arm.com 100911051Sandreas.hansson@arm.comTick 101011051Sandreas.hansson@arm.comCache::recvAtomic(PacketPtr pkt) 101111051Sandreas.hansson@arm.com{ 101211051Sandreas.hansson@arm.com // We are in atomic mode so we pay just for lookupLatency here. 101311051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 101411051Sandreas.hansson@arm.com // @TODO: make this a parameter 101511051Sandreas.hansson@arm.com bool last_level_cache = false; 101611051Sandreas.hansson@arm.com 101711051Sandreas.hansson@arm.com // Forward the request if the system is in cache bypass mode. 101811051Sandreas.hansson@arm.com if (system->bypassCaches()) 101911051Sandreas.hansson@arm.com return ticksToCycles(memSidePort->sendAtomic(pkt)); 102011051Sandreas.hansson@arm.com 102111051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 102211051Sandreas.hansson@arm.com 102311284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 102411051Sandreas.hansson@arm.com // have to invalidate ourselves and any lower caches even if 102511051Sandreas.hansson@arm.com // upper cache will be responding 102611051Sandreas.hansson@arm.com if (pkt->isInvalidate()) { 102711051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 102811051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 102911051Sandreas.hansson@arm.com tags->invalidate(blk); 103011051Sandreas.hansson@arm.com blk->invalidate(); 103111284Sandreas.hansson@arm.com DPRINTF(Cache, "Other cache responding to %s on %#llx (%s):" 103211051Sandreas.hansson@arm.com " invalidating\n", 103311051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), 103411051Sandreas.hansson@arm.com pkt->isSecure() ? "s" : "ns"); 103511051Sandreas.hansson@arm.com } 103611051Sandreas.hansson@arm.com if (!last_level_cache) { 103711284Sandreas.hansson@arm.com DPRINTF(Cache, "Other cache responding to %s on %#llx (%s):" 103811284Sandreas.hansson@arm.com " forwarding\n", 103911051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), 104011051Sandreas.hansson@arm.com pkt->isSecure() ? "s" : "ns"); 104111051Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 104211051Sandreas.hansson@arm.com } 104311051Sandreas.hansson@arm.com } else { 104411284Sandreas.hansson@arm.com DPRINTF(Cache, "Other cache responding to %s on %#llx: " 104511284Sandreas.hansson@arm.com "not responding\n", 104611051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 104711051Sandreas.hansson@arm.com } 104811051Sandreas.hansson@arm.com 104911051Sandreas.hansson@arm.com return lat * clockPeriod(); 105011051Sandreas.hansson@arm.com } 105111051Sandreas.hansson@arm.com 105211051Sandreas.hansson@arm.com // should assert here that there are no outstanding MSHRs or 105311051Sandreas.hansson@arm.com // writebacks... that would mean that someone used an atomic 105411051Sandreas.hansson@arm.com // access in timing mode 105511051Sandreas.hansson@arm.com 105611051Sandreas.hansson@arm.com CacheBlk *blk = NULL; 105711051Sandreas.hansson@arm.com PacketList writebacks; 105811051Sandreas.hansson@arm.com bool satisfied = access(pkt, blk, lat, writebacks); 105911051Sandreas.hansson@arm.com 106011051Sandreas.hansson@arm.com // handle writebacks resulting from the access here to ensure they 106111051Sandreas.hansson@arm.com // logically proceed anything happening below 106211130Sali.jafri@arm.com doWritebacksAtomic(writebacks); 106311051Sandreas.hansson@arm.com 106411051Sandreas.hansson@arm.com if (!satisfied) { 106511051Sandreas.hansson@arm.com // MISS 106611051Sandreas.hansson@arm.com 106711284Sandreas.hansson@arm.com PacketPtr bus_pkt = getBusPacket(pkt, blk, pkt->needsWritable()); 106811051Sandreas.hansson@arm.com 106911051Sandreas.hansson@arm.com bool is_forward = (bus_pkt == NULL); 107011051Sandreas.hansson@arm.com 107111051Sandreas.hansson@arm.com if (is_forward) { 107211051Sandreas.hansson@arm.com // just forwarding the same request to the next level 107311051Sandreas.hansson@arm.com // no local cache operation involved 107411051Sandreas.hansson@arm.com bus_pkt = pkt; 107511051Sandreas.hansson@arm.com } 107611051Sandreas.hansson@arm.com 107711051Sandreas.hansson@arm.com DPRINTF(Cache, "Sending an atomic %s for %#llx (%s)\n", 107811051Sandreas.hansson@arm.com bus_pkt->cmdString(), bus_pkt->getAddr(), 107911051Sandreas.hansson@arm.com bus_pkt->isSecure() ? "s" : "ns"); 108011051Sandreas.hansson@arm.com 108111051Sandreas.hansson@arm.com#if TRACING_ON 108211051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 108311051Sandreas.hansson@arm.com#endif 108411051Sandreas.hansson@arm.com 108511051Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt)); 108611051Sandreas.hansson@arm.com 108711051Sandreas.hansson@arm.com // We are now dealing with the response handling 108811051Sandreas.hansson@arm.com DPRINTF(Cache, "Receive response: %s for addr %#llx (%s) in state %i\n", 108911051Sandreas.hansson@arm.com bus_pkt->cmdString(), bus_pkt->getAddr(), 109011051Sandreas.hansson@arm.com bus_pkt->isSecure() ? "s" : "ns", 109111051Sandreas.hansson@arm.com old_state); 109211051Sandreas.hansson@arm.com 109311051Sandreas.hansson@arm.com // If packet was a forward, the response (if any) is already 109411051Sandreas.hansson@arm.com // in place in the bus_pkt == pkt structure, so we don't need 109511051Sandreas.hansson@arm.com // to do anything. Otherwise, use the separate bus_pkt to 109611051Sandreas.hansson@arm.com // generate response to pkt and then delete it. 109711051Sandreas.hansson@arm.com if (!is_forward) { 109811051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 109911051Sandreas.hansson@arm.com assert(bus_pkt->isResponse()); 110011051Sandreas.hansson@arm.com if (bus_pkt->isError()) { 110111051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 110211051Sandreas.hansson@arm.com pkt->copyError(bus_pkt); 110311051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::InvalidateReq) { 110411051Sandreas.hansson@arm.com if (blk) { 110511051Sandreas.hansson@arm.com // invalidate response to a cache that received 110611051Sandreas.hansson@arm.com // an invalidate request 110711051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 110811051Sandreas.hansson@arm.com } 110911051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::WriteLineReq) { 111011051Sandreas.hansson@arm.com // note the use of pkt, not bus_pkt here. 111111051Sandreas.hansson@arm.com 111211051Sandreas.hansson@arm.com // write-line request to the cache that promoted 111311051Sandreas.hansson@arm.com // the write to a whole line 111411197Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks, 111511197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 111611051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 111711051Sandreas.hansson@arm.com } else if (bus_pkt->isRead() || 111811051Sandreas.hansson@arm.com bus_pkt->cmd == MemCmd::UpgradeResp) { 111911051Sandreas.hansson@arm.com // we're updating cache state to allow us to 112011051Sandreas.hansson@arm.com // satisfy the upstream request from the cache 112111197Sandreas.hansson@arm.com blk = handleFill(bus_pkt, blk, writebacks, 112211197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 112311051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 112411051Sandreas.hansson@arm.com } else { 112511051Sandreas.hansson@arm.com // we're satisfying the upstream request without 112611051Sandreas.hansson@arm.com // modifying cache state, e.g., a write-through 112711051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 112811051Sandreas.hansson@arm.com } 112911051Sandreas.hansson@arm.com } 113011051Sandreas.hansson@arm.com delete bus_pkt; 113111051Sandreas.hansson@arm.com } 113211051Sandreas.hansson@arm.com } 113311051Sandreas.hansson@arm.com 113411051Sandreas.hansson@arm.com // Note that we don't invoke the prefetcher at all in atomic mode. 113511051Sandreas.hansson@arm.com // It's not clear how to do it properly, particularly for 113611051Sandreas.hansson@arm.com // prefetchers that aggressively generate prefetch candidates and 113711051Sandreas.hansson@arm.com // rely on bandwidth contention to throttle them; these will tend 113811051Sandreas.hansson@arm.com // to pollute the cache in atomic mode since there is no bandwidth 113911051Sandreas.hansson@arm.com // contention. If we ever do want to enable prefetching in atomic 114011051Sandreas.hansson@arm.com // mode, though, this is the place to do it... see timingAccess() 114111051Sandreas.hansson@arm.com // for an example (though we'd want to issue the prefetch(es) 114211051Sandreas.hansson@arm.com // immediately rather than calling requestMemSideBus() as we do 114311051Sandreas.hansson@arm.com // there). 114411051Sandreas.hansson@arm.com 114511197Sandreas.hansson@arm.com // do any writebacks resulting from the response handling 114611130Sali.jafri@arm.com doWritebacksAtomic(writebacks); 114711051Sandreas.hansson@arm.com 114811197Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and if so 114911197Sandreas.hansson@arm.com // clear it out, but only do so after the call to recvAtomic is 115011197Sandreas.hansson@arm.com // finished so that any downstream observers (such as a snoop 115111197Sandreas.hansson@arm.com // filter), first see the fill, and only then see the eviction 115211197Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 115311197Sandreas.hansson@arm.com // the atomic CPU calls recvAtomic for fetch and load/store 115411197Sandreas.hansson@arm.com // sequentuially, and we may already have a tempBlock 115511197Sandreas.hansson@arm.com // writeback from the fetch that we have not yet sent 115611197Sandreas.hansson@arm.com if (tempBlockWriteback) { 115711197Sandreas.hansson@arm.com // if that is the case, write the prevoius one back, and 115811197Sandreas.hansson@arm.com // do not schedule any new event 115911197Sandreas.hansson@arm.com writebackTempBlockAtomic(); 116011197Sandreas.hansson@arm.com } else { 116111197Sandreas.hansson@arm.com // the writeback/clean eviction happens after the call to 116211197Sandreas.hansson@arm.com // recvAtomic has finished (but before any successive 116311197Sandreas.hansson@arm.com // calls), so that the response handling from the fill is 116411197Sandreas.hansson@arm.com // allowed to happen first 116511197Sandreas.hansson@arm.com schedule(writebackTempBlockAtomicEvent, curTick()); 116611197Sandreas.hansson@arm.com } 116711197Sandreas.hansson@arm.com 116811199Sandreas.hansson@arm.com tempBlockWriteback = (blk->isDirty() || writebackClean) ? 116911199Sandreas.hansson@arm.com writebackBlk(blk) : cleanEvictBlk(blk); 117011197Sandreas.hansson@arm.com blk->invalidate(); 117111197Sandreas.hansson@arm.com } 117211197Sandreas.hansson@arm.com 117311051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 117411051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 117511051Sandreas.hansson@arm.com } 117611051Sandreas.hansson@arm.com 117711051Sandreas.hansson@arm.com return lat * clockPeriod(); 117811051Sandreas.hansson@arm.com} 117911051Sandreas.hansson@arm.com 118011051Sandreas.hansson@arm.com 118111051Sandreas.hansson@arm.comvoid 118211051Sandreas.hansson@arm.comCache::functionalAccess(PacketPtr pkt, bool fromCpuSide) 118311051Sandreas.hansson@arm.com{ 118411051Sandreas.hansson@arm.com if (system->bypassCaches()) { 118511051Sandreas.hansson@arm.com // Packets from the memory side are snoop request and 118611051Sandreas.hansson@arm.com // shouldn't happen in bypass mode. 118711051Sandreas.hansson@arm.com assert(fromCpuSide); 118811051Sandreas.hansson@arm.com 118911051Sandreas.hansson@arm.com // The cache should be flushed if we are in cache bypass mode, 119011051Sandreas.hansson@arm.com // so we don't need to check if we need to update anything. 119111051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 119211051Sandreas.hansson@arm.com return; 119311051Sandreas.hansson@arm.com } 119411051Sandreas.hansson@arm.com 119511051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 119611051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 119711051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 119811051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 119911051Sandreas.hansson@arm.com 120011051Sandreas.hansson@arm.com pkt->pushLabel(name()); 120111051Sandreas.hansson@arm.com 120211051Sandreas.hansson@arm.com CacheBlkPrintWrapper cbpw(blk); 120311051Sandreas.hansson@arm.com 120411051Sandreas.hansson@arm.com // Note that just because an L2/L3 has valid data doesn't mean an 120511051Sandreas.hansson@arm.com // L1 doesn't have a more up-to-date modified copy that still 120611051Sandreas.hansson@arm.com // needs to be found. As a result we always update the request if 120711051Sandreas.hansson@arm.com // we have it, but only declare it satisfied if we are the owner. 120811051Sandreas.hansson@arm.com 120911051Sandreas.hansson@arm.com // see if we have data at all (owned or otherwise) 121011051Sandreas.hansson@arm.com bool have_data = blk && blk->isValid() 121111051Sandreas.hansson@arm.com && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize, 121211051Sandreas.hansson@arm.com blk->data); 121311051Sandreas.hansson@arm.com 121411284Sandreas.hansson@arm.com // data we have is dirty if marked as such or if we have an 121511284Sandreas.hansson@arm.com // in-service MSHR that is pending a modified line 121611051Sandreas.hansson@arm.com bool have_dirty = 121711051Sandreas.hansson@arm.com have_data && (blk->isDirty() || 121811284Sandreas.hansson@arm.com (mshr && mshr->inService && mshr->isPendingModified())); 121911051Sandreas.hansson@arm.com 122011051Sandreas.hansson@arm.com bool done = have_dirty 122111051Sandreas.hansson@arm.com || cpuSidePort->checkFunctional(pkt) 122211051Sandreas.hansson@arm.com || mshrQueue.checkFunctional(pkt, blk_addr) 122311051Sandreas.hansson@arm.com || writeBuffer.checkFunctional(pkt, blk_addr) 122411051Sandreas.hansson@arm.com || memSidePort->checkFunctional(pkt); 122511051Sandreas.hansson@arm.com 122611288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "functional %s %#llx (%s) %s%s%s\n", 122711051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), is_secure ? "s" : "ns", 122811051Sandreas.hansson@arm.com (blk && blk->isValid()) ? "valid " : "", 122911051Sandreas.hansson@arm.com have_data ? "data " : "", done ? "done " : ""); 123011051Sandreas.hansson@arm.com 123111051Sandreas.hansson@arm.com // We're leaving the cache, so pop cache->name() label 123211051Sandreas.hansson@arm.com pkt->popLabel(); 123311051Sandreas.hansson@arm.com 123411051Sandreas.hansson@arm.com if (done) { 123511051Sandreas.hansson@arm.com pkt->makeResponse(); 123611051Sandreas.hansson@arm.com } else { 123711051Sandreas.hansson@arm.com // if it came as a request from the CPU side then make sure it 123811051Sandreas.hansson@arm.com // continues towards the memory side 123911051Sandreas.hansson@arm.com if (fromCpuSide) { 124011051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 124111051Sandreas.hansson@arm.com } else if (forwardSnoops && cpuSidePort->isSnooping()) { 124211051Sandreas.hansson@arm.com // if it came from the memory side, it must be a snoop request 124311051Sandreas.hansson@arm.com // and we should only forward it if we are forwarding snoops 124411051Sandreas.hansson@arm.com cpuSidePort->sendFunctionalSnoop(pkt); 124511051Sandreas.hansson@arm.com } 124611051Sandreas.hansson@arm.com } 124711051Sandreas.hansson@arm.com} 124811051Sandreas.hansson@arm.com 124911051Sandreas.hansson@arm.com 125011051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 125111051Sandreas.hansson@arm.com// 125211051Sandreas.hansson@arm.com// Response handling: responses from the memory side 125311051Sandreas.hansson@arm.com// 125411051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 125511051Sandreas.hansson@arm.com 125611051Sandreas.hansson@arm.com 125711051Sandreas.hansson@arm.comvoid 125811051Sandreas.hansson@arm.comCache::recvTimingResp(PacketPtr pkt) 125911051Sandreas.hansson@arm.com{ 126011051Sandreas.hansson@arm.com assert(pkt->isResponse()); 126111051Sandreas.hansson@arm.com 126211051Sandreas.hansson@arm.com // all header delay should be paid for by the crossbar, unless 126311051Sandreas.hansson@arm.com // this is a prefetch response from above 126411051Sandreas.hansson@arm.com panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 126511051Sandreas.hansson@arm.com "%s saw a non-zero packet delay\n", name()); 126611051Sandreas.hansson@arm.com 126711051Sandreas.hansson@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState); 126811051Sandreas.hansson@arm.com bool is_error = pkt->isError(); 126911051Sandreas.hansson@arm.com 127011051Sandreas.hansson@arm.com assert(mshr); 127111051Sandreas.hansson@arm.com 127211051Sandreas.hansson@arm.com if (is_error) { 127311051Sandreas.hansson@arm.com DPRINTF(Cache, "Cache received packet with error for addr %#llx (%s), " 127411051Sandreas.hansson@arm.com "cmd: %s\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns", 127511051Sandreas.hansson@arm.com pkt->cmdString()); 127611051Sandreas.hansson@arm.com } 127711051Sandreas.hansson@arm.com 127811051Sandreas.hansson@arm.com DPRINTF(Cache, "Handling response %s for addr %#llx size %d (%s)\n", 127911051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize(), 128011051Sandreas.hansson@arm.com pkt->isSecure() ? "s" : "ns"); 128111051Sandreas.hansson@arm.com 128211051Sandreas.hansson@arm.com MSHRQueue *mq = mshr->queue; 128311051Sandreas.hansson@arm.com bool wasFull = mq->isFull(); 128411051Sandreas.hansson@arm.com 128511051Sandreas.hansson@arm.com if (mshr == noTargetMSHR) { 128611051Sandreas.hansson@arm.com // we always clear at least one target 128711051Sandreas.hansson@arm.com clearBlocked(Blocked_NoTargets); 128811051Sandreas.hansson@arm.com noTargetMSHR = NULL; 128911051Sandreas.hansson@arm.com } 129011051Sandreas.hansson@arm.com 129111051Sandreas.hansson@arm.com // Initial target is used just for stats 129211051Sandreas.hansson@arm.com MSHR::Target *initial_tgt = mshr->getTarget(); 129311051Sandreas.hansson@arm.com int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 129411051Sandreas.hansson@arm.com Tick miss_latency = curTick() - initial_tgt->recvTime; 129511051Sandreas.hansson@arm.com PacketList writebacks; 129611051Sandreas.hansson@arm.com // We need forward_time here because we have a call of 129711051Sandreas.hansson@arm.com // allocateWriteBuffer() that need this parameter to specify the 129811051Sandreas.hansson@arm.com // time to request the bus. In this case we use forward latency 129911051Sandreas.hansson@arm.com // because there is a writeback. We pay also here for headerDelay 130011051Sandreas.hansson@arm.com // that is charged of bus latencies if the packet comes from the 130111051Sandreas.hansson@arm.com // bus. 130211051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 130311051Sandreas.hansson@arm.com 130411051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 130511051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 130611051Sandreas.hansson@arm.com mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 130711051Sandreas.hansson@arm.com miss_latency; 130811051Sandreas.hansson@arm.com } else { 130911051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 131011051Sandreas.hansson@arm.com mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 131111051Sandreas.hansson@arm.com miss_latency; 131211051Sandreas.hansson@arm.com } 131311051Sandreas.hansson@arm.com 131411284Sandreas.hansson@arm.com // upgrade deferred targets if the response has no sharers, and is 131511284Sandreas.hansson@arm.com // thus passing writable 131611284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 131711284Sandreas.hansson@arm.com mshr->promoteWritable(); 131811177Sandreas.hansson@arm.com } 131911177Sandreas.hansson@arm.com 132011051Sandreas.hansson@arm.com bool is_fill = !mshr->isForward && 132111051Sandreas.hansson@arm.com (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp); 132211051Sandreas.hansson@arm.com 132311177Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 132411177Sandreas.hansson@arm.com 132511051Sandreas.hansson@arm.com if (is_fill && !is_error) { 132611051Sandreas.hansson@arm.com DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 132711051Sandreas.hansson@arm.com pkt->getAddr()); 132811051Sandreas.hansson@arm.com 132911197Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill); 133011051Sandreas.hansson@arm.com assert(blk != NULL); 133111051Sandreas.hansson@arm.com } 133211051Sandreas.hansson@arm.com 133311051Sandreas.hansson@arm.com // allow invalidation responses originating from write-line 133411051Sandreas.hansson@arm.com // requests to be discarded 133511136Sandreas.hansson@arm.com bool is_invalidate = pkt->isInvalidate(); 133611051Sandreas.hansson@arm.com 133711051Sandreas.hansson@arm.com // First offset for critical word first calculations 133811051Sandreas.hansson@arm.com int initial_offset = initial_tgt->pkt->getOffset(blkSize); 133911051Sandreas.hansson@arm.com 134011051Sandreas.hansson@arm.com while (mshr->hasTargets()) { 134111051Sandreas.hansson@arm.com MSHR::Target *target = mshr->getTarget(); 134211051Sandreas.hansson@arm.com Packet *tgt_pkt = target->pkt; 134311051Sandreas.hansson@arm.com 134411051Sandreas.hansson@arm.com switch (target->source) { 134511051Sandreas.hansson@arm.com case MSHR::Target::FromCPU: 134611051Sandreas.hansson@arm.com Tick completion_time; 134711051Sandreas.hansson@arm.com // Here we charge on completion_time the delay of the xbar if the 134811051Sandreas.hansson@arm.com // packet comes from it, charged on headerDelay. 134911051Sandreas.hansson@arm.com completion_time = pkt->headerDelay; 135011051Sandreas.hansson@arm.com 135111051Sandreas.hansson@arm.com // Software prefetch handling for cache closest to core 135211051Sandreas.hansson@arm.com if (tgt_pkt->cmd.isSWPrefetch()) { 135311051Sandreas.hansson@arm.com // a software prefetch would have already been ack'd immediately 135411051Sandreas.hansson@arm.com // with dummy data so the core would be able to retire it. 135511051Sandreas.hansson@arm.com // this request completes right here, so we deallocate it. 135611051Sandreas.hansson@arm.com delete tgt_pkt->req; 135711051Sandreas.hansson@arm.com delete tgt_pkt; 135811051Sandreas.hansson@arm.com break; // skip response 135911051Sandreas.hansson@arm.com } 136011051Sandreas.hansson@arm.com 136111051Sandreas.hansson@arm.com // unlike the other packet flows, where data is found in other 136211051Sandreas.hansson@arm.com // caches or memory and brought back, write-line requests always 136311051Sandreas.hansson@arm.com // have the data right away, so the above check for "is fill?" 136411051Sandreas.hansson@arm.com // cannot actually be determined until examining the stored MSHR 136511051Sandreas.hansson@arm.com // state. We "catch up" with that logic here, which is duplicated 136611051Sandreas.hansson@arm.com // from above. 136711051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::WriteLineReq) { 136811051Sandreas.hansson@arm.com assert(!is_error); 136911284Sandreas.hansson@arm.com // we got the block in a writable state, so promote 137011284Sandreas.hansson@arm.com // any deferred targets if possible 137111284Sandreas.hansson@arm.com mshr->promoteWritable(); 137211051Sandreas.hansson@arm.com // NB: we use the original packet here and not the response! 137311197Sandreas.hansson@arm.com blk = handleFill(tgt_pkt, blk, writebacks, mshr->allocOnFill); 137411051Sandreas.hansson@arm.com assert(blk != NULL); 137511051Sandreas.hansson@arm.com 137611051Sandreas.hansson@arm.com // treat as a fill, and discard the invalidation 137711051Sandreas.hansson@arm.com // response 137811051Sandreas.hansson@arm.com is_fill = true; 137911136Sandreas.hansson@arm.com is_invalidate = false; 138011051Sandreas.hansson@arm.com } 138111051Sandreas.hansson@arm.com 138211051Sandreas.hansson@arm.com if (is_fill) { 138311051Sandreas.hansson@arm.com satisfyCpuSideRequest(tgt_pkt, blk, 138411051Sandreas.hansson@arm.com true, mshr->hasPostDowngrade()); 138511051Sandreas.hansson@arm.com 138611051Sandreas.hansson@arm.com // How many bytes past the first request is this one 138711051Sandreas.hansson@arm.com int transfer_offset = 138811051Sandreas.hansson@arm.com tgt_pkt->getOffset(blkSize) - initial_offset; 138911051Sandreas.hansson@arm.com if (transfer_offset < 0) { 139011051Sandreas.hansson@arm.com transfer_offset += blkSize; 139111051Sandreas.hansson@arm.com } 139211051Sandreas.hansson@arm.com 139311051Sandreas.hansson@arm.com // If not critical word (offset) return payloadDelay. 139411051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 139511051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 139611051Sandreas.hansson@arm.com // the core. 139711051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 139811051Sandreas.hansson@arm.com (transfer_offset ? pkt->payloadDelay : 0); 139911051Sandreas.hansson@arm.com 140011051Sandreas.hansson@arm.com assert(!tgt_pkt->req->isUncacheable()); 140111051Sandreas.hansson@arm.com 140211051Sandreas.hansson@arm.com assert(tgt_pkt->req->masterId() < system->maxMasters()); 140311051Sandreas.hansson@arm.com missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] += 140411051Sandreas.hansson@arm.com completion_time - target->recvTime; 140511051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::UpgradeFailResp) { 140611051Sandreas.hansson@arm.com // failed StoreCond upgrade 140711051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::StoreCondReq || 140811051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::StoreCondFailReq || 140911051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::SCUpgradeFailReq); 141011051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 141111051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 141211051Sandreas.hansson@arm.com // the core. 141311051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 141411051Sandreas.hansson@arm.com pkt->payloadDelay; 141511051Sandreas.hansson@arm.com tgt_pkt->req->setExtraData(0); 141611051Sandreas.hansson@arm.com } else { 141711051Sandreas.hansson@arm.com // not a cache fill, just forwarding response 141811051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 141911051Sandreas.hansson@arm.com // from lower level cahces/memory to the core. 142011051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 142111051Sandreas.hansson@arm.com pkt->payloadDelay; 142211051Sandreas.hansson@arm.com if (pkt->isRead() && !is_error) { 142311051Sandreas.hansson@arm.com // sanity check 142411051Sandreas.hansson@arm.com assert(pkt->getAddr() == tgt_pkt->getAddr()); 142511051Sandreas.hansson@arm.com assert(pkt->getSize() >= tgt_pkt->getSize()); 142611051Sandreas.hansson@arm.com 142711051Sandreas.hansson@arm.com tgt_pkt->setData(pkt->getConstPtr<uint8_t>()); 142811051Sandreas.hansson@arm.com } 142911051Sandreas.hansson@arm.com } 143011051Sandreas.hansson@arm.com tgt_pkt->makeTimingResponse(); 143111051Sandreas.hansson@arm.com // if this packet is an error copy that to the new packet 143211051Sandreas.hansson@arm.com if (is_error) 143311051Sandreas.hansson@arm.com tgt_pkt->copyError(pkt); 143411051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::ReadResp && 143511136Sandreas.hansson@arm.com (is_invalidate || mshr->hasPostInvalidate())) { 143611051Sandreas.hansson@arm.com // If intermediate cache got ReadRespWithInvalidate, 143711051Sandreas.hansson@arm.com // propagate that. Response should not have 143811051Sandreas.hansson@arm.com // isInvalidate() set otherwise. 143911051Sandreas.hansson@arm.com tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate; 144011051Sandreas.hansson@arm.com DPRINTF(Cache, "%s updated cmd to %s for addr %#llx\n", 144111051Sandreas.hansson@arm.com __func__, tgt_pkt->cmdString(), tgt_pkt->getAddr()); 144211051Sandreas.hansson@arm.com } 144311051Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 144411051Sandreas.hansson@arm.com tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; 144511194Sali.jafri@arm.com cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true); 144611051Sandreas.hansson@arm.com break; 144711051Sandreas.hansson@arm.com 144811051Sandreas.hansson@arm.com case MSHR::Target::FromPrefetcher: 144911051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::HardPFReq); 145011051Sandreas.hansson@arm.com if (blk) 145111051Sandreas.hansson@arm.com blk->status |= BlkHWPrefetched; 145211051Sandreas.hansson@arm.com delete tgt_pkt->req; 145311051Sandreas.hansson@arm.com delete tgt_pkt; 145411051Sandreas.hansson@arm.com break; 145511051Sandreas.hansson@arm.com 145611051Sandreas.hansson@arm.com case MSHR::Target::FromSnoop: 145711051Sandreas.hansson@arm.com // I don't believe that a snoop can be in an error state 145811051Sandreas.hansson@arm.com assert(!is_error); 145911051Sandreas.hansson@arm.com // response to snoop request 146011051Sandreas.hansson@arm.com DPRINTF(Cache, "processing deferred snoop...\n"); 146111136Sandreas.hansson@arm.com assert(!(is_invalidate && !mshr->hasPostInvalidate())); 146211051Sandreas.hansson@arm.com handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate()); 146311051Sandreas.hansson@arm.com break; 146411051Sandreas.hansson@arm.com 146511051Sandreas.hansson@arm.com default: 146611051Sandreas.hansson@arm.com panic("Illegal target->source enum %d\n", target->source); 146711051Sandreas.hansson@arm.com } 146811051Sandreas.hansson@arm.com 146911051Sandreas.hansson@arm.com mshr->popTarget(); 147011051Sandreas.hansson@arm.com } 147111051Sandreas.hansson@arm.com 147211051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 147311051Sandreas.hansson@arm.com // an invalidate response stemming from a write line request 147411051Sandreas.hansson@arm.com // should not invalidate the block, so check if the 147511051Sandreas.hansson@arm.com // invalidation should be discarded 147611136Sandreas.hansson@arm.com if (is_invalidate || mshr->hasPostInvalidate()) { 147711197Sandreas.hansson@arm.com invalidateBlock(blk); 147811051Sandreas.hansson@arm.com } else if (mshr->hasPostDowngrade()) { 147911051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 148011051Sandreas.hansson@arm.com } 148111051Sandreas.hansson@arm.com } 148211051Sandreas.hansson@arm.com 148311051Sandreas.hansson@arm.com if (mshr->promoteDeferredTargets()) { 148411051Sandreas.hansson@arm.com // avoid later read getting stale data while write miss is 148511051Sandreas.hansson@arm.com // outstanding.. see comment in timingAccess() 148611051Sandreas.hansson@arm.com if (blk) { 148711051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 148811051Sandreas.hansson@arm.com } 148911051Sandreas.hansson@arm.com mq = mshr->queue; 149011051Sandreas.hansson@arm.com mq->markPending(mshr); 149111051Sandreas.hansson@arm.com schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 149211051Sandreas.hansson@arm.com } else { 149311051Sandreas.hansson@arm.com mq->deallocate(mshr); 149411051Sandreas.hansson@arm.com if (wasFull && !mq->isFull()) { 149511051Sandreas.hansson@arm.com clearBlocked((BlockedCause)mq->index); 149611051Sandreas.hansson@arm.com } 149711051Sandreas.hansson@arm.com 149811051Sandreas.hansson@arm.com // Request the bus for a prefetch if this deallocation freed enough 149911051Sandreas.hansson@arm.com // MSHRs for a prefetch to take place 150011051Sandreas.hansson@arm.com if (prefetcher && mq == &mshrQueue && mshrQueue.canPrefetch()) { 150111051Sandreas.hansson@arm.com Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 150211051Sandreas.hansson@arm.com clockEdge()); 150311051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 150411051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 150511051Sandreas.hansson@arm.com } 150611051Sandreas.hansson@arm.com } 150711051Sandreas.hansson@arm.com // reset the xbar additional timinig as it is now accounted for 150811051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 150911051Sandreas.hansson@arm.com 151011051Sandreas.hansson@arm.com // copy writebacks to write buffer 151111051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 151211051Sandreas.hansson@arm.com 151311051Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and then clear it out 151411051Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 151511051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying 151611051Sandreas.hansson@arm.com // Writebacks/CleanEvicts to write buffer. It specifies the latency to 151711051Sandreas.hansson@arm.com // allocate an internal buffer and to schedule an event to the 151811051Sandreas.hansson@arm.com // queued port. 151911199Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 152011051Sandreas.hansson@arm.com PacketPtr wbPkt = writebackBlk(blk); 152111051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 152211051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag if cached above. 152311051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) 152411051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 152511051Sandreas.hansson@arm.com } else { 152611051Sandreas.hansson@arm.com PacketPtr wcPkt = cleanEvictBlk(blk); 152711051Sandreas.hansson@arm.com // Check to see if block is cached above. If not allocate 152811051Sandreas.hansson@arm.com // write buffer 152911051Sandreas.hansson@arm.com if (isCachedAbove(wcPkt)) 153011051Sandreas.hansson@arm.com delete wcPkt; 153111051Sandreas.hansson@arm.com else 153211051Sandreas.hansson@arm.com allocateWriteBuffer(wcPkt, forward_time); 153311051Sandreas.hansson@arm.com } 153411051Sandreas.hansson@arm.com blk->invalidate(); 153511051Sandreas.hansson@arm.com } 153611051Sandreas.hansson@arm.com 153711288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "Leaving %s with %s for addr %#llx\n", __func__, 153811051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 153911051Sandreas.hansson@arm.com delete pkt; 154011051Sandreas.hansson@arm.com} 154111051Sandreas.hansson@arm.com 154211051Sandreas.hansson@arm.comPacketPtr 154311051Sandreas.hansson@arm.comCache::writebackBlk(CacheBlk *blk) 154411051Sandreas.hansson@arm.com{ 154511199Sandreas.hansson@arm.com chatty_assert(!isReadOnly || writebackClean, 154611199Sandreas.hansson@arm.com "Writeback from read-only cache"); 154711199Sandreas.hansson@arm.com assert(blk && blk->isValid() && (blk->isDirty() || writebackClean)); 154811051Sandreas.hansson@arm.com 154911051Sandreas.hansson@arm.com writebacks[Request::wbMasterId]++; 155011051Sandreas.hansson@arm.com 155111199Sandreas.hansson@arm.com Request *req = new Request(tags->regenerateBlkAddr(blk->tag, blk->set), 155211199Sandreas.hansson@arm.com blkSize, 0, Request::wbMasterId); 155311051Sandreas.hansson@arm.com if (blk->isSecure()) 155411199Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 155511051Sandreas.hansson@arm.com 155611199Sandreas.hansson@arm.com req->taskId(blk->task_id); 155711051Sandreas.hansson@arm.com blk->task_id= ContextSwitchTaskId::Unknown; 155811051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 155911051Sandreas.hansson@arm.com 156011199Sandreas.hansson@arm.com PacketPtr pkt = 156111199Sandreas.hansson@arm.com new Packet(req, blk->isDirty() ? 156211199Sandreas.hansson@arm.com MemCmd::WritebackDirty : MemCmd::WritebackClean); 156311199Sandreas.hansson@arm.com 156411199Sandreas.hansson@arm.com DPRINTF(Cache, "Create Writeback %#llx writable: %d, dirty: %d\n", 156511199Sandreas.hansson@arm.com pkt->getAddr(), blk->isWritable(), blk->isDirty()); 156611199Sandreas.hansson@arm.com 156711051Sandreas.hansson@arm.com if (blk->isWritable()) { 156811051Sandreas.hansson@arm.com // not asserting shared means we pass the block in modified 156911051Sandreas.hansson@arm.com // state, mark our own block non-writeable 157011051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 157111051Sandreas.hansson@arm.com } else { 157211284Sandreas.hansson@arm.com // we are in the Owned state, tell the receiver 157311284Sandreas.hansson@arm.com pkt->setHasSharers(); 157411051Sandreas.hansson@arm.com } 157511051Sandreas.hansson@arm.com 157611199Sandreas.hansson@arm.com // make sure the block is not marked dirty 157711199Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 157811051Sandreas.hansson@arm.com 157911199Sandreas.hansson@arm.com pkt->allocate(); 158011199Sandreas.hansson@arm.com std::memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize); 158111199Sandreas.hansson@arm.com 158211199Sandreas.hansson@arm.com return pkt; 158311051Sandreas.hansson@arm.com} 158411051Sandreas.hansson@arm.com 158511051Sandreas.hansson@arm.comPacketPtr 158611051Sandreas.hansson@arm.comCache::cleanEvictBlk(CacheBlk *blk) 158711051Sandreas.hansson@arm.com{ 158811199Sandreas.hansson@arm.com assert(!writebackClean); 158911051Sandreas.hansson@arm.com assert(blk && blk->isValid() && !blk->isDirty()); 159011051Sandreas.hansson@arm.com // Creating a zero sized write, a message to the snoop filter 159111051Sandreas.hansson@arm.com Request *req = 159211051Sandreas.hansson@arm.com new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0, 159311051Sandreas.hansson@arm.com Request::wbMasterId); 159411051Sandreas.hansson@arm.com if (blk->isSecure()) 159511051Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 159611051Sandreas.hansson@arm.com 159711051Sandreas.hansson@arm.com req->taskId(blk->task_id); 159811051Sandreas.hansson@arm.com blk->task_id = ContextSwitchTaskId::Unknown; 159911051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 160011051Sandreas.hansson@arm.com 160111051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::CleanEvict); 160211051Sandreas.hansson@arm.com pkt->allocate(); 160311051Sandreas.hansson@arm.com DPRINTF(Cache, "%s%s %x Create CleanEvict\n", pkt->cmdString(), 160411051Sandreas.hansson@arm.com pkt->req->isInstFetch() ? " (ifetch)" : "", 160511051Sandreas.hansson@arm.com pkt->getAddr()); 160611051Sandreas.hansson@arm.com 160711051Sandreas.hansson@arm.com return pkt; 160811051Sandreas.hansson@arm.com} 160911051Sandreas.hansson@arm.com 161011051Sandreas.hansson@arm.comvoid 161111051Sandreas.hansson@arm.comCache::memWriteback() 161211051Sandreas.hansson@arm.com{ 161311051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::writebackVisitor); 161411051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 161511051Sandreas.hansson@arm.com} 161611051Sandreas.hansson@arm.com 161711051Sandreas.hansson@arm.comvoid 161811051Sandreas.hansson@arm.comCache::memInvalidate() 161911051Sandreas.hansson@arm.com{ 162011051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::invalidateVisitor); 162111051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 162211051Sandreas.hansson@arm.com} 162311051Sandreas.hansson@arm.com 162411051Sandreas.hansson@arm.combool 162511051Sandreas.hansson@arm.comCache::isDirty() const 162611051Sandreas.hansson@arm.com{ 162711051Sandreas.hansson@arm.com CacheBlkIsDirtyVisitor visitor; 162811051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 162911051Sandreas.hansson@arm.com 163011051Sandreas.hansson@arm.com return visitor.isDirty(); 163111051Sandreas.hansson@arm.com} 163211051Sandreas.hansson@arm.com 163311051Sandreas.hansson@arm.combool 163411051Sandreas.hansson@arm.comCache::writebackVisitor(CacheBlk &blk) 163511051Sandreas.hansson@arm.com{ 163611051Sandreas.hansson@arm.com if (blk.isDirty()) { 163711051Sandreas.hansson@arm.com assert(blk.isValid()); 163811051Sandreas.hansson@arm.com 163911051Sandreas.hansson@arm.com Request request(tags->regenerateBlkAddr(blk.tag, blk.set), 164011051Sandreas.hansson@arm.com blkSize, 0, Request::funcMasterId); 164111051Sandreas.hansson@arm.com request.taskId(blk.task_id); 164211051Sandreas.hansson@arm.com 164311051Sandreas.hansson@arm.com Packet packet(&request, MemCmd::WriteReq); 164411051Sandreas.hansson@arm.com packet.dataStatic(blk.data); 164511051Sandreas.hansson@arm.com 164611051Sandreas.hansson@arm.com memSidePort->sendFunctional(&packet); 164711051Sandreas.hansson@arm.com 164811051Sandreas.hansson@arm.com blk.status &= ~BlkDirty; 164911051Sandreas.hansson@arm.com } 165011051Sandreas.hansson@arm.com 165111051Sandreas.hansson@arm.com return true; 165211051Sandreas.hansson@arm.com} 165311051Sandreas.hansson@arm.com 165411051Sandreas.hansson@arm.combool 165511051Sandreas.hansson@arm.comCache::invalidateVisitor(CacheBlk &blk) 165611051Sandreas.hansson@arm.com{ 165711051Sandreas.hansson@arm.com 165811051Sandreas.hansson@arm.com if (blk.isDirty()) 165911051Sandreas.hansson@arm.com warn_once("Invalidating dirty cache lines. Expect things to break.\n"); 166011051Sandreas.hansson@arm.com 166111051Sandreas.hansson@arm.com if (blk.isValid()) { 166211051Sandreas.hansson@arm.com assert(!blk.isDirty()); 166311051Sandreas.hansson@arm.com tags->invalidate(&blk); 166411051Sandreas.hansson@arm.com blk.invalidate(); 166511051Sandreas.hansson@arm.com } 166611051Sandreas.hansson@arm.com 166711051Sandreas.hansson@arm.com return true; 166811051Sandreas.hansson@arm.com} 166911051Sandreas.hansson@arm.com 167011051Sandreas.hansson@arm.comCacheBlk* 167111051Sandreas.hansson@arm.comCache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks) 167211051Sandreas.hansson@arm.com{ 167311051Sandreas.hansson@arm.com CacheBlk *blk = tags->findVictim(addr); 167411051Sandreas.hansson@arm.com 167511051Sandreas.hansson@arm.com // It is valid to return NULL if there is no victim 167611051Sandreas.hansson@arm.com if (!blk) 167711051Sandreas.hansson@arm.com return nullptr; 167811051Sandreas.hansson@arm.com 167911051Sandreas.hansson@arm.com if (blk->isValid()) { 168011051Sandreas.hansson@arm.com Addr repl_addr = tags->regenerateBlkAddr(blk->tag, blk->set); 168111051Sandreas.hansson@arm.com MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure()); 168211051Sandreas.hansson@arm.com if (repl_mshr) { 168311051Sandreas.hansson@arm.com // must be an outstanding upgrade request 168411051Sandreas.hansson@arm.com // on a block we're about to replace... 168511051Sandreas.hansson@arm.com assert(!blk->isWritable() || blk->isDirty()); 168611284Sandreas.hansson@arm.com assert(repl_mshr->needsWritable()); 168711051Sandreas.hansson@arm.com // too hard to replace block with transient state 168811051Sandreas.hansson@arm.com // allocation failed, block not inserted 168911051Sandreas.hansson@arm.com return NULL; 169011051Sandreas.hansson@arm.com } else { 169111051Sandreas.hansson@arm.com DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx (%s): %s\n", 169211051Sandreas.hansson@arm.com repl_addr, blk->isSecure() ? "s" : "ns", 169311051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", 169411051Sandreas.hansson@arm.com blk->isDirty() ? "writeback" : "clean"); 169511051Sandreas.hansson@arm.com 169611051Sandreas.hansson@arm.com // Will send up Writeback/CleanEvict snoops via isCachedAbove 169711051Sandreas.hansson@arm.com // when pushing this writeback list into the write buffer. 169811199Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 169911051Sandreas.hansson@arm.com // Save writeback packet for handling by caller 170011051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(blk)); 170111051Sandreas.hansson@arm.com } else { 170211051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(blk)); 170311051Sandreas.hansson@arm.com } 170411051Sandreas.hansson@arm.com } 170511051Sandreas.hansson@arm.com } 170611051Sandreas.hansson@arm.com 170711051Sandreas.hansson@arm.com return blk; 170811051Sandreas.hansson@arm.com} 170911051Sandreas.hansson@arm.com 171011197Sandreas.hansson@arm.comvoid 171111197Sandreas.hansson@arm.comCache::invalidateBlock(CacheBlk *blk) 171211197Sandreas.hansson@arm.com{ 171311197Sandreas.hansson@arm.com if (blk != tempBlock) 171411197Sandreas.hansson@arm.com tags->invalidate(blk); 171511197Sandreas.hansson@arm.com blk->invalidate(); 171611197Sandreas.hansson@arm.com} 171711051Sandreas.hansson@arm.com 171811051Sandreas.hansson@arm.com// Note that the reason we return a list of writebacks rather than 171911051Sandreas.hansson@arm.com// inserting them directly in the write buffer is that this function 172011051Sandreas.hansson@arm.com// is called by both atomic and timing-mode accesses, and in atomic 172111051Sandreas.hansson@arm.com// mode we don't mess with the write buffer (we just perform the 172211051Sandreas.hansson@arm.com// writebacks atomically once the original request is complete). 172311051Sandreas.hansson@arm.comCacheBlk* 172411197Sandreas.hansson@arm.comCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, 172511197Sandreas.hansson@arm.com bool allocate) 172611051Sandreas.hansson@arm.com{ 172711051Sandreas.hansson@arm.com assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq); 172811051Sandreas.hansson@arm.com Addr addr = pkt->getAddr(); 172911051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 173011051Sandreas.hansson@arm.com#if TRACING_ON 173111051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 173211051Sandreas.hansson@arm.com#endif 173311051Sandreas.hansson@arm.com 173411051Sandreas.hansson@arm.com // When handling a fill, discard any CleanEvicts for the 173511051Sandreas.hansson@arm.com // same address in write buffer. 173611051Sandreas.hansson@arm.com Addr M5_VAR_USED blk_addr = blockAlign(pkt->getAddr()); 173711051Sandreas.hansson@arm.com std::vector<MSHR *> M5_VAR_USED wbs; 173811051Sandreas.hansson@arm.com assert (!writeBuffer.findMatches(blk_addr, is_secure, wbs)); 173911051Sandreas.hansson@arm.com 174011051Sandreas.hansson@arm.com if (blk == NULL) { 174111051Sandreas.hansson@arm.com // better have read new data... 174211051Sandreas.hansson@arm.com assert(pkt->hasData()); 174311051Sandreas.hansson@arm.com 174411051Sandreas.hansson@arm.com // only read responses and write-line requests have data; 174511051Sandreas.hansson@arm.com // note that we don't write the data here for write-line - that 174611051Sandreas.hansson@arm.com // happens in the subsequent satisfyCpuSideRequest. 174711051Sandreas.hansson@arm.com assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq); 174811051Sandreas.hansson@arm.com 174911197Sandreas.hansson@arm.com // need to do a replacement if allocating, otherwise we stick 175011197Sandreas.hansson@arm.com // with the temporary storage 175111197Sandreas.hansson@arm.com blk = allocate ? allocateBlock(addr, is_secure, writebacks) : NULL; 175211197Sandreas.hansson@arm.com 175311051Sandreas.hansson@arm.com if (blk == NULL) { 175411197Sandreas.hansson@arm.com // No replaceable block or a mostly exclusive 175511197Sandreas.hansson@arm.com // cache... just use temporary storage to complete the 175611197Sandreas.hansson@arm.com // current request and then get rid of it 175711051Sandreas.hansson@arm.com assert(!tempBlock->isValid()); 175811051Sandreas.hansson@arm.com blk = tempBlock; 175911051Sandreas.hansson@arm.com tempBlock->set = tags->extractSet(addr); 176011051Sandreas.hansson@arm.com tempBlock->tag = tags->extractTag(addr); 176111051Sandreas.hansson@arm.com // @todo: set security state as well... 176211051Sandreas.hansson@arm.com DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr, 176311051Sandreas.hansson@arm.com is_secure ? "s" : "ns"); 176411051Sandreas.hansson@arm.com } else { 176511051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 176611051Sandreas.hansson@arm.com } 176711051Sandreas.hansson@arm.com 176811051Sandreas.hansson@arm.com // we should never be overwriting a valid block 176911051Sandreas.hansson@arm.com assert(!blk->isValid()); 177011051Sandreas.hansson@arm.com } else { 177111051Sandreas.hansson@arm.com // existing block... probably an upgrade 177211051Sandreas.hansson@arm.com assert(blk->tag == tags->extractTag(addr)); 177311051Sandreas.hansson@arm.com // either we're getting new data or the block should already be valid 177411051Sandreas.hansson@arm.com assert(pkt->hasData() || blk->isValid()); 177511051Sandreas.hansson@arm.com // don't clear block status... if block is already dirty we 177611051Sandreas.hansson@arm.com // don't want to lose that 177711051Sandreas.hansson@arm.com } 177811051Sandreas.hansson@arm.com 177911051Sandreas.hansson@arm.com if (is_secure) 178011051Sandreas.hansson@arm.com blk->status |= BlkSecure; 178111051Sandreas.hansson@arm.com blk->status |= BlkValid | BlkReadable; 178211051Sandreas.hansson@arm.com 178311137Sandreas.hansson@arm.com // sanity check for whole-line writes, which should always be 178411137Sandreas.hansson@arm.com // marked as writable as part of the fill, and then later marked 178511137Sandreas.hansson@arm.com // dirty as part of satisfyCpuSideRequest 178611137Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WriteLineReq) { 178711284Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 178811137Sandreas.hansson@arm.com // at the moment other caches do not respond to the 178911137Sandreas.hansson@arm.com // invalidation requests corresponding to a whole-line write 179011284Sandreas.hansson@arm.com assert(!pkt->cacheResponding()); 179111137Sandreas.hansson@arm.com } 179211137Sandreas.hansson@arm.com 179311284Sandreas.hansson@arm.com // here we deal with setting the appropriate state of the line, 179411284Sandreas.hansson@arm.com // and we start by looking at the hasSharers flag, and ignore the 179511284Sandreas.hansson@arm.com // cacheResponding flag (normally signalling dirty data) if the 179611284Sandreas.hansson@arm.com // packet has sharers, thus the line is never allocated as Owned 179711284Sandreas.hansson@arm.com // (dirty but not writable), and always ends up being either 179811284Sandreas.hansson@arm.com // Shared, Exclusive or Modified, see Packet::setCacheResponding 179911284Sandreas.hansson@arm.com // for more details 180011284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 180111284Sandreas.hansson@arm.com // we could get a writable line from memory (rather than a 180211284Sandreas.hansson@arm.com // cache) even in a read-only cache, note that we set this bit 180311284Sandreas.hansson@arm.com // even for a read-only cache, possibly revisit this decision 180411051Sandreas.hansson@arm.com blk->status |= BlkWritable; 180511051Sandreas.hansson@arm.com 180611284Sandreas.hansson@arm.com // check if we got this via cache-to-cache transfer (i.e., from a 180711284Sandreas.hansson@arm.com // cache that had the block in Modified or Owned state) 180811284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 180911284Sandreas.hansson@arm.com // we got the block in Modified state, and invalidated the 181011284Sandreas.hansson@arm.com // owners copy 181111051Sandreas.hansson@arm.com blk->status |= BlkDirty; 181211051Sandreas.hansson@arm.com 181311051Sandreas.hansson@arm.com chatty_assert(!isReadOnly, "Should never see dirty snoop response " 181411051Sandreas.hansson@arm.com "in read-only cache %s\n", name()); 181511051Sandreas.hansson@arm.com } 181611051Sandreas.hansson@arm.com } 181711051Sandreas.hansson@arm.com 181811051Sandreas.hansson@arm.com DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n", 181911051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", old_state, blk->print()); 182011051Sandreas.hansson@arm.com 182111051Sandreas.hansson@arm.com // if we got new data, copy it in (checking for a read response 182211051Sandreas.hansson@arm.com // and a response that has data is the same in the end) 182311051Sandreas.hansson@arm.com if (pkt->isRead()) { 182411051Sandreas.hansson@arm.com // sanity checks 182511051Sandreas.hansson@arm.com assert(pkt->hasData()); 182611051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 182711051Sandreas.hansson@arm.com 182811051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 182911051Sandreas.hansson@arm.com } 183011051Sandreas.hansson@arm.com // We pay for fillLatency here. 183111051Sandreas.hansson@arm.com blk->whenReady = clockEdge() + fillLatency * clockPeriod() + 183211051Sandreas.hansson@arm.com pkt->payloadDelay; 183311051Sandreas.hansson@arm.com 183411051Sandreas.hansson@arm.com return blk; 183511051Sandreas.hansson@arm.com} 183611051Sandreas.hansson@arm.com 183711051Sandreas.hansson@arm.com 183811051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 183911051Sandreas.hansson@arm.com// 184011051Sandreas.hansson@arm.com// Snoop path: requests coming in from the memory side 184111051Sandreas.hansson@arm.com// 184211051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 184311051Sandreas.hansson@arm.com 184411051Sandreas.hansson@arm.comvoid 184511051Sandreas.hansson@arm.comCache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 184611051Sandreas.hansson@arm.com bool already_copied, bool pending_inval) 184711051Sandreas.hansson@arm.com{ 184811051Sandreas.hansson@arm.com // sanity check 184911051Sandreas.hansson@arm.com assert(req_pkt->isRequest()); 185011051Sandreas.hansson@arm.com assert(req_pkt->needsResponse()); 185111051Sandreas.hansson@arm.com 185211051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 185311051Sandreas.hansson@arm.com req_pkt->cmdString(), req_pkt->getAddr(), req_pkt->getSize()); 185411051Sandreas.hansson@arm.com // timing-mode snoop responses require a new packet, unless we 185511051Sandreas.hansson@arm.com // already made a copy... 185611051Sandreas.hansson@arm.com PacketPtr pkt = req_pkt; 185711051Sandreas.hansson@arm.com if (!already_copied) 185811051Sandreas.hansson@arm.com // do not clear flags, and allocate space for data if the 185911051Sandreas.hansson@arm.com // packet needs it (the only packets that carry data are read 186011051Sandreas.hansson@arm.com // responses) 186111051Sandreas.hansson@arm.com pkt = new Packet(req_pkt, false, req_pkt->isRead()); 186211051Sandreas.hansson@arm.com 186311051Sandreas.hansson@arm.com assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() || 186411284Sandreas.hansson@arm.com pkt->hasSharers()); 186511051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 186611051Sandreas.hansson@arm.com if (pkt->isRead()) { 186711051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk_data, blkSize); 186811051Sandreas.hansson@arm.com } 186911051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadResp && pending_inval) { 187011051Sandreas.hansson@arm.com // Assume we defer a response to a read from a far-away cache 187111051Sandreas.hansson@arm.com // A, then later defer a ReadExcl from a cache B on the same 187211284Sandreas.hansson@arm.com // bus as us. We'll assert cacheResponding in both cases, but 187311284Sandreas.hansson@arm.com // in the latter case cacheResponding will keep the 187411284Sandreas.hansson@arm.com // invalidation from reaching cache A. This special response 187511284Sandreas.hansson@arm.com // tells cache A that it gets the block to satisfy its read, 187611284Sandreas.hansson@arm.com // but must immediately invalidate it. 187711051Sandreas.hansson@arm.com pkt->cmd = MemCmd::ReadRespWithInvalidate; 187811051Sandreas.hansson@arm.com } 187911051Sandreas.hansson@arm.com // Here we consider forward_time, paying for just forward latency and 188011051Sandreas.hansson@arm.com // also charging the delay provided by the xbar. 188111051Sandreas.hansson@arm.com // forward_time is used as send_time in next allocateWriteBuffer(). 188211051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 188311051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 188411051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 188511288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, 188611288Ssteve.reinhardt@amd.com "%s created response: %s addr %#llx size %d tick: %lu\n", 188711051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize(), 188811051Sandreas.hansson@arm.com forward_time); 188911051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, forward_time, true); 189011051Sandreas.hansson@arm.com} 189111051Sandreas.hansson@arm.com 189211127Sandreas.hansson@arm.comuint32_t 189311051Sandreas.hansson@arm.comCache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, 189411051Sandreas.hansson@arm.com bool is_deferred, bool pending_inval) 189511051Sandreas.hansson@arm.com{ 189611288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d\n", __func__, 189711051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 189811051Sandreas.hansson@arm.com // deferred snoops can only happen in timing mode 189911051Sandreas.hansson@arm.com assert(!(is_deferred && !is_timing)); 190011051Sandreas.hansson@arm.com // pending_inval only makes sense on deferred snoops 190111051Sandreas.hansson@arm.com assert(!(pending_inval && !is_deferred)); 190211051Sandreas.hansson@arm.com assert(pkt->isRequest()); 190311051Sandreas.hansson@arm.com 190411051Sandreas.hansson@arm.com // the packet may get modified if we or a forwarded snooper 190511051Sandreas.hansson@arm.com // responds in atomic mode, so remember a few things about the 190611051Sandreas.hansson@arm.com // original packet up front 190711051Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 190811284Sandreas.hansson@arm.com bool M5_VAR_USED needs_writable = pkt->needsWritable(); 190911051Sandreas.hansson@arm.com 191011285Sandreas.hansson@arm.com // at the moment we could get an uncacheable write which does not 191111285Sandreas.hansson@arm.com // have the invalidate flag, and we need a suitable way of dealing 191211285Sandreas.hansson@arm.com // with this case 191311285Sandreas.hansson@arm.com panic_if(invalidate && pkt->req->isUncacheable(), 191411285Sandreas.hansson@arm.com "%s got an invalidating uncacheable snoop request %s to %#llx", 191511285Sandreas.hansson@arm.com name(), pkt->cmdString(), pkt->getAddr()); 191611285Sandreas.hansson@arm.com 191711127Sandreas.hansson@arm.com uint32_t snoop_delay = 0; 191811127Sandreas.hansson@arm.com 191911051Sandreas.hansson@arm.com if (forwardSnoops) { 192011051Sandreas.hansson@arm.com // first propagate snoop upward to see if anyone above us wants to 192111051Sandreas.hansson@arm.com // handle it. save & restore packet src since it will get 192211051Sandreas.hansson@arm.com // rewritten to be relative to cpu-side bus (if any) 192311284Sandreas.hansson@arm.com bool alreadyResponded = pkt->cacheResponding(); 192411051Sandreas.hansson@arm.com if (is_timing) { 192511051Sandreas.hansson@arm.com // copy the packet so that we can clear any flags before 192611051Sandreas.hansson@arm.com // forwarding it upwards, we also allocate data (passing 192711051Sandreas.hansson@arm.com // the pointer along in case of static data), in case 192811051Sandreas.hansson@arm.com // there is a snoop hit in upper levels 192911051Sandreas.hansson@arm.com Packet snoopPkt(pkt, true, true); 193011051Sandreas.hansson@arm.com snoopPkt.setExpressSnoop(); 193111051Sandreas.hansson@arm.com // the snoop packet does not need to wait any additional 193211051Sandreas.hansson@arm.com // time 193311051Sandreas.hansson@arm.com snoopPkt.headerDelay = snoopPkt.payloadDelay = 0; 193411051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoopPkt); 193511127Sandreas.hansson@arm.com 193611127Sandreas.hansson@arm.com // add the header delay (including crossbar and snoop 193711127Sandreas.hansson@arm.com // delays) of the upward snoop to the snoop delay for this 193811127Sandreas.hansson@arm.com // cache 193911127Sandreas.hansson@arm.com snoop_delay += snoopPkt.headerDelay; 194011127Sandreas.hansson@arm.com 194111284Sandreas.hansson@arm.com if (snoopPkt.cacheResponding()) { 194211051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache 194311051Sandreas.hansson@arm.com assert(!alreadyResponded); 194411284Sandreas.hansson@arm.com pkt->setCacheResponding(); 194511051Sandreas.hansson@arm.com } 194611284Sandreas.hansson@arm.com // upstream cache has the block, or has an outstanding 194711284Sandreas.hansson@arm.com // MSHR, pass the flag on 194811284Sandreas.hansson@arm.com if (snoopPkt.hasSharers()) { 194911284Sandreas.hansson@arm.com pkt->setHasSharers(); 195011051Sandreas.hansson@arm.com } 195111051Sandreas.hansson@arm.com // If this request is a prefetch or clean evict and an upper level 195211051Sandreas.hansson@arm.com // signals block present, make sure to propagate the block 195311051Sandreas.hansson@arm.com // presence to the requester. 195411051Sandreas.hansson@arm.com if (snoopPkt.isBlockCached()) { 195511051Sandreas.hansson@arm.com pkt->setBlockCached(); 195611051Sandreas.hansson@arm.com } 195711051Sandreas.hansson@arm.com } else { 195811051Sandreas.hansson@arm.com cpuSidePort->sendAtomicSnoop(pkt); 195911284Sandreas.hansson@arm.com if (!alreadyResponded && pkt->cacheResponding()) { 196011051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache: 196111051Sandreas.hansson@arm.com // forward response to original requester 196211051Sandreas.hansson@arm.com assert(pkt->isResponse()); 196311051Sandreas.hansson@arm.com } 196411051Sandreas.hansson@arm.com } 196511051Sandreas.hansson@arm.com } 196611051Sandreas.hansson@arm.com 196711051Sandreas.hansson@arm.com if (!blk || !blk->isValid()) { 196811288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "%s snoop miss for %s addr %#llx size %d\n", 196911051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 197011127Sandreas.hansson@arm.com return snoop_delay; 197111051Sandreas.hansson@arm.com } else { 197211288Ssteve.reinhardt@amd.com DPRINTF(Cache, "%s snoop hit for %s addr %#llx size %d, " 197311288Ssteve.reinhardt@amd.com "old state is %s\n", __func__, pkt->cmdString(), 197411288Ssteve.reinhardt@amd.com pkt->getAddr(), pkt->getSize(), blk->print()); 197511051Sandreas.hansson@arm.com } 197611051Sandreas.hansson@arm.com 197711051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && blk->isDirty()), 197811051Sandreas.hansson@arm.com "Should never have a dirty block in a read-only cache %s\n", 197911051Sandreas.hansson@arm.com name()); 198011051Sandreas.hansson@arm.com 198111051Sandreas.hansson@arm.com // We may end up modifying both the block state and the packet (if 198211051Sandreas.hansson@arm.com // we respond in atomic mode), so just figure out what to do now 198311051Sandreas.hansson@arm.com // and then do it later. If we find dirty data while snooping for 198411051Sandreas.hansson@arm.com // an invalidate, we don't need to send a response. The 198511051Sandreas.hansson@arm.com // invalidation itself is taken care of below. 198611051Sandreas.hansson@arm.com bool respond = blk->isDirty() && pkt->needsResponse() && 198711051Sandreas.hansson@arm.com pkt->cmd != MemCmd::InvalidateReq; 198811284Sandreas.hansson@arm.com bool have_writable = blk->isWritable(); 198911051Sandreas.hansson@arm.com 199011051Sandreas.hansson@arm.com // Invalidate any prefetch's from below that would strip write permissions 199111051Sandreas.hansson@arm.com // MemCmd::HardPFReq is only observed by upstream caches. After missing 199211051Sandreas.hansson@arm.com // above and in it's own cache, a new MemCmd::ReadReq is created that 199311051Sandreas.hansson@arm.com // downstream caches observe. 199411051Sandreas.hansson@arm.com if (pkt->mustCheckAbove()) { 199511051Sandreas.hansson@arm.com DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s from" 199611051Sandreas.hansson@arm.com " lower cache\n", pkt->getAddr(), pkt->cmdString()); 199711051Sandreas.hansson@arm.com pkt->setBlockCached(); 199811127Sandreas.hansson@arm.com return snoop_delay; 199911051Sandreas.hansson@arm.com } 200011051Sandreas.hansson@arm.com 200111285Sandreas.hansson@arm.com if (pkt->isRead() && !invalidate) { 200211285Sandreas.hansson@arm.com // reading without requiring the line in a writable state 200311284Sandreas.hansson@arm.com assert(!needs_writable); 200411284Sandreas.hansson@arm.com pkt->setHasSharers(); 200511285Sandreas.hansson@arm.com 200611285Sandreas.hansson@arm.com // if the requesting packet is uncacheable, retain the line in 200711285Sandreas.hansson@arm.com // the current state, otherwhise unset the writable flag, 200811285Sandreas.hansson@arm.com // which means we go from Modified to Owned (and will respond 200911285Sandreas.hansson@arm.com // below), remain in Owned (and will respond below), from 201011285Sandreas.hansson@arm.com // Exclusive to Shared, or remain in Shared 201111285Sandreas.hansson@arm.com if (!pkt->req->isUncacheable()) 201211285Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 201311051Sandreas.hansson@arm.com } 201411051Sandreas.hansson@arm.com 201511051Sandreas.hansson@arm.com if (respond) { 201611051Sandreas.hansson@arm.com // prevent anyone else from responding, cache as well as 201711051Sandreas.hansson@arm.com // memory, and also prevent any memory from even seeing the 201811284Sandreas.hansson@arm.com // request 201911284Sandreas.hansson@arm.com pkt->setCacheResponding(); 202011284Sandreas.hansson@arm.com if (have_writable) { 202111284Sandreas.hansson@arm.com // inform the cache hierarchy that this cache had the line 202211284Sandreas.hansson@arm.com // in the Modified state so that we avoid unnecessary 202311284Sandreas.hansson@arm.com // invalidations (see Packet::setResponderHadWritable) 202411284Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 202511284Sandreas.hansson@arm.com 202611081Sandreas.hansson@arm.com // in the case of an uncacheable request there is no point 202711284Sandreas.hansson@arm.com // in setting the responderHadWritable flag, but since the 202811284Sandreas.hansson@arm.com // recipient does not care there is no harm in doing so 202911284Sandreas.hansson@arm.com } else { 203011284Sandreas.hansson@arm.com // if the packet has needsWritable set we invalidate our 203111284Sandreas.hansson@arm.com // copy below and all other copies will be invalidates 203211284Sandreas.hansson@arm.com // through express snoops, and if needsWritable is not set 203311284Sandreas.hansson@arm.com // we already called setHasSharers above 203411051Sandreas.hansson@arm.com } 203511284Sandreas.hansson@arm.com 203611285Sandreas.hansson@arm.com // if we are returning a writable and dirty (Modified) line, 203711285Sandreas.hansson@arm.com // we should be invalidating the line 203811285Sandreas.hansson@arm.com panic_if(!invalidate && !pkt->hasSharers(), 203911285Sandreas.hansson@arm.com "%s is passing a Modified line through %s to %#llx, " 204011285Sandreas.hansson@arm.com "but keeping the block", 204111285Sandreas.hansson@arm.com name(), pkt->cmdString(), pkt->getAddr()); 204211285Sandreas.hansson@arm.com 204311051Sandreas.hansson@arm.com if (is_timing) { 204411051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval); 204511051Sandreas.hansson@arm.com } else { 204611051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 204711286Sandreas.hansson@arm.com // packets such as upgrades do not actually have any data 204811286Sandreas.hansson@arm.com // payload 204911286Sandreas.hansson@arm.com if (pkt->hasData()) 205011286Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 205111051Sandreas.hansson@arm.com } 205211051Sandreas.hansson@arm.com } 205311051Sandreas.hansson@arm.com 205411051Sandreas.hansson@arm.com if (!respond && is_timing && is_deferred) { 205511271Sandreas.hansson@arm.com // if it's a deferred timing snoop to which we are not 205611271Sandreas.hansson@arm.com // responding, then we've made a copy of both the request and 205711271Sandreas.hansson@arm.com // the packet, delete them here 205811051Sandreas.hansson@arm.com assert(pkt->needsResponse()); 205911051Sandreas.hansson@arm.com delete pkt->req; 206011051Sandreas.hansson@arm.com delete pkt; 206111051Sandreas.hansson@arm.com } 206211051Sandreas.hansson@arm.com 206311051Sandreas.hansson@arm.com // Do this last in case it deallocates block data or something 206411051Sandreas.hansson@arm.com // like that 206511051Sandreas.hansson@arm.com if (invalidate) { 206611197Sandreas.hansson@arm.com invalidateBlock(blk); 206711051Sandreas.hansson@arm.com } 206811051Sandreas.hansson@arm.com 206911051Sandreas.hansson@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 207011127Sandreas.hansson@arm.com 207111127Sandreas.hansson@arm.com return snoop_delay; 207211051Sandreas.hansson@arm.com} 207311051Sandreas.hansson@arm.com 207411051Sandreas.hansson@arm.com 207511051Sandreas.hansson@arm.comvoid 207611051Sandreas.hansson@arm.comCache::recvTimingSnoopReq(PacketPtr pkt) 207711051Sandreas.hansson@arm.com{ 207811288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d\n", __func__, 207911051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 208011051Sandreas.hansson@arm.com 208111051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 208211051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 208311051Sandreas.hansson@arm.com 208411130Sali.jafri@arm.com // no need to snoop requests that are not in range 208511051Sandreas.hansson@arm.com if (!inRange(pkt->getAddr())) { 208611051Sandreas.hansson@arm.com return; 208711051Sandreas.hansson@arm.com } 208811051Sandreas.hansson@arm.com 208911051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 209011051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 209111051Sandreas.hansson@arm.com 209211051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 209311051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 209411051Sandreas.hansson@arm.com 209511127Sandreas.hansson@arm.com // Update the latency cost of the snoop so that the crossbar can 209611127Sandreas.hansson@arm.com // account for it. Do not overwrite what other neighbouring caches 209711127Sandreas.hansson@arm.com // have already done, rather take the maximum. The update is 209811127Sandreas.hansson@arm.com // tentative, for cases where we return before an upward snoop 209911127Sandreas.hansson@arm.com // happens below. 210011127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, 210111127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 210211127Sandreas.hansson@arm.com 210311051Sandreas.hansson@arm.com // Inform request(Prefetch, CleanEvict or Writeback) from below of 210411051Sandreas.hansson@arm.com // MSHR hit, set setBlockCached. 210511051Sandreas.hansson@arm.com if (mshr && pkt->mustCheckAbove()) { 210611051Sandreas.hansson@arm.com DPRINTF(Cache, "Setting block cached for %s from" 210711051Sandreas.hansson@arm.com "lower cache on mshr hit %#x\n", 210811051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 210911051Sandreas.hansson@arm.com pkt->setBlockCached(); 211011051Sandreas.hansson@arm.com return; 211111051Sandreas.hansson@arm.com } 211211051Sandreas.hansson@arm.com 211311051Sandreas.hansson@arm.com // Let the MSHR itself track the snoop and decide whether we want 211411051Sandreas.hansson@arm.com // to go ahead and do the regular cache snoop 211511051Sandreas.hansson@arm.com if (mshr && mshr->handleSnoop(pkt, order++)) { 211611051Sandreas.hansson@arm.com DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)." 211711051Sandreas.hansson@arm.com "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns", 211811051Sandreas.hansson@arm.com mshr->print()); 211911051Sandreas.hansson@arm.com 212011051Sandreas.hansson@arm.com if (mshr->getNumTargets() > numTarget) 212111051Sandreas.hansson@arm.com warn("allocating bonus target for snoop"); //handle later 212211051Sandreas.hansson@arm.com return; 212311051Sandreas.hansson@arm.com } 212411051Sandreas.hansson@arm.com 212511051Sandreas.hansson@arm.com //We also need to check the writeback buffers and handle those 212611051Sandreas.hansson@arm.com std::vector<MSHR *> writebacks; 212711051Sandreas.hansson@arm.com if (writeBuffer.findMatches(blk_addr, is_secure, writebacks)) { 212811051Sandreas.hansson@arm.com DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n", 212911051Sandreas.hansson@arm.com pkt->getAddr(), is_secure ? "s" : "ns"); 213011051Sandreas.hansson@arm.com 213111051Sandreas.hansson@arm.com // Look through writebacks for any cachable writes. 213211051Sandreas.hansson@arm.com // We should only ever find a single match 213311051Sandreas.hansson@arm.com assert(writebacks.size() == 1); 213411051Sandreas.hansson@arm.com MSHR *wb_entry = writebacks[0]; 213511051Sandreas.hansson@arm.com // Expect to see only Writebacks and/or CleanEvicts here, both of 213611051Sandreas.hansson@arm.com // which should not be generated for uncacheable data. 213711051Sandreas.hansson@arm.com assert(!wb_entry->isUncacheable()); 213811051Sandreas.hansson@arm.com // There should only be a single request responsible for generating 213911051Sandreas.hansson@arm.com // Writebacks/CleanEvicts. 214011051Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 214111051Sandreas.hansson@arm.com PacketPtr wb_pkt = wb_entry->getTarget()->pkt; 214211199Sandreas.hansson@arm.com assert(wb_pkt->isEviction()); 214311051Sandreas.hansson@arm.com 214411199Sandreas.hansson@arm.com if (pkt->isEviction()) { 214511051Sandreas.hansson@arm.com // if the block is found in the write queue, set the BLOCK_CACHED 214611051Sandreas.hansson@arm.com // flag for Writeback/CleanEvict snoop. On return the snoop will 214711051Sandreas.hansson@arm.com // propagate the BLOCK_CACHED flag in Writeback packets and prevent 214811051Sandreas.hansson@arm.com // any CleanEvicts from travelling down the memory hierarchy. 214911051Sandreas.hansson@arm.com pkt->setBlockCached(); 215011051Sandreas.hansson@arm.com DPRINTF(Cache, "Squashing %s from lower cache on writequeue hit" 215111051Sandreas.hansson@arm.com " %#x\n", pkt->cmdString(), pkt->getAddr()); 215211051Sandreas.hansson@arm.com return; 215311051Sandreas.hansson@arm.com } 215411051Sandreas.hansson@arm.com 215511332Sandreas.hansson@arm.com // conceptually writebacks are no different to other blocks in 215611332Sandreas.hansson@arm.com // this cache, so the behaviour is modelled after handleSnoop, 215711332Sandreas.hansson@arm.com // the difference being that instead of querying the block 215811332Sandreas.hansson@arm.com // state to determine if it is dirty and writable, we use the 215911332Sandreas.hansson@arm.com // command and fields of the writeback packet 216011332Sandreas.hansson@arm.com bool respond = wb_pkt->cmd == MemCmd::WritebackDirty && 216111332Sandreas.hansson@arm.com pkt->needsResponse() && pkt->cmd != MemCmd::InvalidateReq; 216211332Sandreas.hansson@arm.com bool have_writable = !wb_pkt->hasSharers(); 216311332Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 216411332Sandreas.hansson@arm.com 216511332Sandreas.hansson@arm.com if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) { 216611332Sandreas.hansson@arm.com assert(!pkt->needsWritable()); 216711332Sandreas.hansson@arm.com pkt->setHasSharers(); 216811332Sandreas.hansson@arm.com wb_pkt->setHasSharers(); 216911332Sandreas.hansson@arm.com } 217011332Sandreas.hansson@arm.com 217111332Sandreas.hansson@arm.com if (respond) { 217211284Sandreas.hansson@arm.com pkt->setCacheResponding(); 217311332Sandreas.hansson@arm.com 217411332Sandreas.hansson@arm.com if (have_writable) { 217511332Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 217611051Sandreas.hansson@arm.com } 217711332Sandreas.hansson@arm.com 217811051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(), 217911051Sandreas.hansson@arm.com false, false); 218011051Sandreas.hansson@arm.com } 218111051Sandreas.hansson@arm.com 218211332Sandreas.hansson@arm.com if (invalidate) { 218311051Sandreas.hansson@arm.com // Invalidation trumps our writeback... discard here 218411051Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 218511051Sandreas.hansson@arm.com markInService(wb_entry, false); 218611051Sandreas.hansson@arm.com delete wb_pkt; 218711051Sandreas.hansson@arm.com } 218811051Sandreas.hansson@arm.com } 218911051Sandreas.hansson@arm.com 219011051Sandreas.hansson@arm.com // If this was a shared writeback, there may still be 219111051Sandreas.hansson@arm.com // other shared copies above that require invalidation. 219211051Sandreas.hansson@arm.com // We could be more selective and return here if the 219311051Sandreas.hansson@arm.com // request is non-exclusive or if the writeback is 219411051Sandreas.hansson@arm.com // exclusive. 219511127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false); 219611127Sandreas.hansson@arm.com 219711127Sandreas.hansson@arm.com // Override what we did when we first saw the snoop, as we now 219811127Sandreas.hansson@arm.com // also have the cost of the upwards snoops to account for 219911127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay + 220011127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 220111051Sandreas.hansson@arm.com} 220211051Sandreas.hansson@arm.com 220311051Sandreas.hansson@arm.combool 220411051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 220511051Sandreas.hansson@arm.com{ 220611051Sandreas.hansson@arm.com // Express snoop responses from master to slave, e.g., from L1 to L2 220711051Sandreas.hansson@arm.com cache->recvTimingSnoopResp(pkt); 220811051Sandreas.hansson@arm.com return true; 220911051Sandreas.hansson@arm.com} 221011051Sandreas.hansson@arm.com 221111051Sandreas.hansson@arm.comTick 221211051Sandreas.hansson@arm.comCache::recvAtomicSnoop(PacketPtr pkt) 221311051Sandreas.hansson@arm.com{ 221411051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 221511051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 221611051Sandreas.hansson@arm.com 221711130Sali.jafri@arm.com // no need to snoop requests that are not in range. 221811130Sali.jafri@arm.com if (!inRange(pkt->getAddr())) { 221911051Sandreas.hansson@arm.com return 0; 222011051Sandreas.hansson@arm.com } 222111051Sandreas.hansson@arm.com 222211051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 222311127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false); 222411127Sandreas.hansson@arm.com return snoop_delay + lookupLatency * clockPeriod(); 222511051Sandreas.hansson@arm.com} 222611051Sandreas.hansson@arm.com 222711051Sandreas.hansson@arm.com 222811051Sandreas.hansson@arm.comMSHR * 222911051Sandreas.hansson@arm.comCache::getNextMSHR() 223011051Sandreas.hansson@arm.com{ 223111051Sandreas.hansson@arm.com // Check both MSHR queue and write buffer for potential requests, 223211051Sandreas.hansson@arm.com // note that null does not mean there is no request, it could 223311051Sandreas.hansson@arm.com // simply be that it is not ready 223411051Sandreas.hansson@arm.com MSHR *miss_mshr = mshrQueue.getNextMSHR(); 223511051Sandreas.hansson@arm.com MSHR *write_mshr = writeBuffer.getNextMSHR(); 223611051Sandreas.hansson@arm.com 223711051Sandreas.hansson@arm.com // If we got a write buffer request ready, first priority is a 223811051Sandreas.hansson@arm.com // full write buffer, otherwhise we favour the miss requests 223911051Sandreas.hansson@arm.com if (write_mshr && 224011051Sandreas.hansson@arm.com ((writeBuffer.isFull() && writeBuffer.inServiceEntries == 0) || 224111051Sandreas.hansson@arm.com !miss_mshr)) { 224211051Sandreas.hansson@arm.com // need to search MSHR queue for conflicting earlier miss. 224311051Sandreas.hansson@arm.com MSHR *conflict_mshr = 224411051Sandreas.hansson@arm.com mshrQueue.findPending(write_mshr->blkAddr, 224511051Sandreas.hansson@arm.com write_mshr->isSecure); 224611051Sandreas.hansson@arm.com 224711051Sandreas.hansson@arm.com if (conflict_mshr && conflict_mshr->order < write_mshr->order) { 224811051Sandreas.hansson@arm.com // Service misses in order until conflict is cleared. 224911051Sandreas.hansson@arm.com return conflict_mshr; 225011051Sandreas.hansson@arm.com 225111051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 225211051Sandreas.hansson@arm.com } 225311051Sandreas.hansson@arm.com 225411051Sandreas.hansson@arm.com // No conflicts; issue write 225511051Sandreas.hansson@arm.com return write_mshr; 225611051Sandreas.hansson@arm.com } else if (miss_mshr) { 225711051Sandreas.hansson@arm.com // need to check for conflicting earlier writeback 225811051Sandreas.hansson@arm.com MSHR *conflict_mshr = 225911051Sandreas.hansson@arm.com writeBuffer.findPending(miss_mshr->blkAddr, 226011051Sandreas.hansson@arm.com miss_mshr->isSecure); 226111051Sandreas.hansson@arm.com if (conflict_mshr) { 226211051Sandreas.hansson@arm.com // not sure why we don't check order here... it was in the 226311051Sandreas.hansson@arm.com // original code but commented out. 226411051Sandreas.hansson@arm.com 226511051Sandreas.hansson@arm.com // The only way this happens is if we are 226611051Sandreas.hansson@arm.com // doing a write and we didn't have permissions 226711051Sandreas.hansson@arm.com // then subsequently saw a writeback (owned got evicted) 226811051Sandreas.hansson@arm.com // We need to make sure to perform the writeback first 226911051Sandreas.hansson@arm.com // To preserve the dirty data, then we can issue the write 227011051Sandreas.hansson@arm.com 227111051Sandreas.hansson@arm.com // should we return write_mshr here instead? I.e. do we 227211051Sandreas.hansson@arm.com // have to flush writes in order? I don't think so... not 227311051Sandreas.hansson@arm.com // for Alpha anyway. Maybe for x86? 227411051Sandreas.hansson@arm.com return conflict_mshr; 227511051Sandreas.hansson@arm.com 227611051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 227711051Sandreas.hansson@arm.com } 227811051Sandreas.hansson@arm.com 227911051Sandreas.hansson@arm.com // No conflicts; issue read 228011051Sandreas.hansson@arm.com return miss_mshr; 228111051Sandreas.hansson@arm.com } 228211051Sandreas.hansson@arm.com 228311051Sandreas.hansson@arm.com // fall through... no pending requests. Try a prefetch. 228411051Sandreas.hansson@arm.com assert(!miss_mshr && !write_mshr); 228511051Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 228611051Sandreas.hansson@arm.com // If we have a miss queue slot, we can try a prefetch 228711051Sandreas.hansson@arm.com PacketPtr pkt = prefetcher->getPacket(); 228811051Sandreas.hansson@arm.com if (pkt) { 228911051Sandreas.hansson@arm.com Addr pf_addr = blockAlign(pkt->getAddr()); 229011051Sandreas.hansson@arm.com if (!tags->findBlock(pf_addr, pkt->isSecure()) && 229111051Sandreas.hansson@arm.com !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 229211051Sandreas.hansson@arm.com !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 229311051Sandreas.hansson@arm.com // Update statistic on number of prefetches issued 229411051Sandreas.hansson@arm.com // (hwpf_mshr_misses) 229511051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 229611051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 229711051Sandreas.hansson@arm.com 229811051Sandreas.hansson@arm.com // allocate an MSHR and return it, note 229911051Sandreas.hansson@arm.com // that we send the packet straight away, so do not 230011051Sandreas.hansson@arm.com // schedule the send 230111051Sandreas.hansson@arm.com return allocateMissBuffer(pkt, curTick(), false); 230211051Sandreas.hansson@arm.com } else { 230311051Sandreas.hansson@arm.com // free the request and packet 230411051Sandreas.hansson@arm.com delete pkt->req; 230511051Sandreas.hansson@arm.com delete pkt; 230611051Sandreas.hansson@arm.com } 230711051Sandreas.hansson@arm.com } 230811051Sandreas.hansson@arm.com } 230911051Sandreas.hansson@arm.com 231011051Sandreas.hansson@arm.com return NULL; 231111051Sandreas.hansson@arm.com} 231211051Sandreas.hansson@arm.com 231311051Sandreas.hansson@arm.combool 231411130Sali.jafri@arm.comCache::isCachedAbove(PacketPtr pkt, bool is_timing) const 231511051Sandreas.hansson@arm.com{ 231611051Sandreas.hansson@arm.com if (!forwardSnoops) 231711051Sandreas.hansson@arm.com return false; 231811051Sandreas.hansson@arm.com // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and 231911051Sandreas.hansson@arm.com // Writeback snoops into upper level caches to check for copies of the 232011051Sandreas.hansson@arm.com // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict 232111051Sandreas.hansson@arm.com // packet, the cache can inform the crossbar below of presence or absence 232211051Sandreas.hansson@arm.com // of the block. 232311130Sali.jafri@arm.com if (is_timing) { 232411130Sali.jafri@arm.com Packet snoop_pkt(pkt, true, false); 232511130Sali.jafri@arm.com snoop_pkt.setExpressSnoop(); 232611130Sali.jafri@arm.com // Assert that packet is either Writeback or CleanEvict and not a 232711130Sali.jafri@arm.com // prefetch request because prefetch requests need an MSHR and may 232811130Sali.jafri@arm.com // generate a snoop response. 232911199Sandreas.hansson@arm.com assert(pkt->isEviction()); 233011130Sali.jafri@arm.com snoop_pkt.senderState = NULL; 233111130Sali.jafri@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 233211130Sali.jafri@arm.com // Writeback/CleanEvict snoops do not generate a snoop response. 233311284Sandreas.hansson@arm.com assert(!(snoop_pkt.cacheResponding())); 233411130Sali.jafri@arm.com return snoop_pkt.isBlockCached(); 233511130Sali.jafri@arm.com } else { 233611130Sali.jafri@arm.com cpuSidePort->sendAtomicSnoop(pkt); 233711130Sali.jafri@arm.com return pkt->isBlockCached(); 233811130Sali.jafri@arm.com } 233911051Sandreas.hansson@arm.com} 234011051Sandreas.hansson@arm.com 234111051Sandreas.hansson@arm.comPacketPtr 234211051Sandreas.hansson@arm.comCache::getTimingPacket() 234311051Sandreas.hansson@arm.com{ 234411051Sandreas.hansson@arm.com MSHR *mshr = getNextMSHR(); 234511051Sandreas.hansson@arm.com 234611051Sandreas.hansson@arm.com if (mshr == NULL) { 234711051Sandreas.hansson@arm.com return NULL; 234811051Sandreas.hansson@arm.com } 234911051Sandreas.hansson@arm.com 235011051Sandreas.hansson@arm.com // use request from 1st target 235111051Sandreas.hansson@arm.com PacketPtr tgt_pkt = mshr->getTarget()->pkt; 235211051Sandreas.hansson@arm.com PacketPtr pkt = NULL; 235311051Sandreas.hansson@arm.com 235411051Sandreas.hansson@arm.com DPRINTF(CachePort, "%s %s for addr %#llx size %d\n", __func__, 235511051Sandreas.hansson@arm.com tgt_pkt->cmdString(), tgt_pkt->getAddr(), tgt_pkt->getSize()); 235611051Sandreas.hansson@arm.com 235711051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 235811051Sandreas.hansson@arm.com 235911051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) { 236011051Sandreas.hansson@arm.com // We need to check the caches above us to verify that 236111051Sandreas.hansson@arm.com // they don't have a copy of this block in the dirty state 236211051Sandreas.hansson@arm.com // at the moment. Without this check we could get a stale 236311051Sandreas.hansson@arm.com // copy from memory that might get used in place of the 236411051Sandreas.hansson@arm.com // dirty one. 236511051Sandreas.hansson@arm.com Packet snoop_pkt(tgt_pkt, true, false); 236611051Sandreas.hansson@arm.com snoop_pkt.setExpressSnoop(); 236711275Sandreas.hansson@arm.com // We are sending this packet upwards, but if it hits we will 236811275Sandreas.hansson@arm.com // get a snoop response that we end up treating just like a 236911275Sandreas.hansson@arm.com // normal response, hence it needs the MSHR as its sender 237011275Sandreas.hansson@arm.com // state 237111051Sandreas.hansson@arm.com snoop_pkt.senderState = mshr; 237211051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 237311051Sandreas.hansson@arm.com 237411051Sandreas.hansson@arm.com // Check to see if the prefetch was squashed by an upper cache (to 237511051Sandreas.hansson@arm.com // prevent us from grabbing the line) or if a Check to see if a 237611051Sandreas.hansson@arm.com // writeback arrived between the time the prefetch was placed in 237711051Sandreas.hansson@arm.com // the MSHRs and when it was selected to be sent or if the 237811051Sandreas.hansson@arm.com // prefetch was squashed by an upper cache. 237911051Sandreas.hansson@arm.com 238011284Sandreas.hansson@arm.com // It is important to check cacheResponding before 238111284Sandreas.hansson@arm.com // prefetchSquashed. If another cache has committed to 238211284Sandreas.hansson@arm.com // responding, it will be sending a dirty response which will 238311284Sandreas.hansson@arm.com // arrive at the MSHR allocated for this request. Checking the 238411284Sandreas.hansson@arm.com // prefetchSquash first may result in the MSHR being 238511284Sandreas.hansson@arm.com // prematurely deallocated. 238611284Sandreas.hansson@arm.com if (snoop_pkt.cacheResponding()) { 238711276Sandreas.hansson@arm.com auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req); 238811276Sandreas.hansson@arm.com assert(r.second); 238911284Sandreas.hansson@arm.com 239011284Sandreas.hansson@arm.com // if we are getting a snoop response with no sharers it 239111284Sandreas.hansson@arm.com // will be allocated as Modified 239211284Sandreas.hansson@arm.com bool pending_modified_resp = !snoop_pkt.hasSharers(); 239311284Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 239411284Sandreas.hansson@arm.com 239511051Sandreas.hansson@arm.com DPRINTF(Cache, "Upward snoop of prefetch for addr" 239611051Sandreas.hansson@arm.com " %#x (%s) hit\n", 239711051Sandreas.hansson@arm.com tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns"); 239811051Sandreas.hansson@arm.com return NULL; 239911051Sandreas.hansson@arm.com } 240011051Sandreas.hansson@arm.com 240111051Sandreas.hansson@arm.com if (snoop_pkt.isBlockCached() || blk != NULL) { 240211051Sandreas.hansson@arm.com DPRINTF(Cache, "Block present, prefetch squashed by cache. " 240311051Sandreas.hansson@arm.com "Deallocating mshr target %#x.\n", 240411051Sandreas.hansson@arm.com mshr->blkAddr); 240511051Sandreas.hansson@arm.com // Deallocate the mshr target 240611277Sandreas.hansson@arm.com if (mshr->queue->forceDeallocateTarget(mshr)) { 240711277Sandreas.hansson@arm.com // Clear block if this deallocation resulted freed an 240811277Sandreas.hansson@arm.com // mshr when all had previously been utilized 240911277Sandreas.hansson@arm.com clearBlocked((BlockedCause)(mshr->queue->index)); 241011051Sandreas.hansson@arm.com } 241111277Sandreas.hansson@arm.com return NULL; 241211051Sandreas.hansson@arm.com } 241311051Sandreas.hansson@arm.com } 241411051Sandreas.hansson@arm.com 241511051Sandreas.hansson@arm.com if (mshr->isForwardNoResponse()) { 241611051Sandreas.hansson@arm.com // no response expected, just forward packet as it is 241711051Sandreas.hansson@arm.com assert(tags->findBlock(mshr->blkAddr, mshr->isSecure) == NULL); 241811051Sandreas.hansson@arm.com pkt = tgt_pkt; 241911051Sandreas.hansson@arm.com } else { 242011284Sandreas.hansson@arm.com pkt = getBusPacket(tgt_pkt, blk, mshr->needsWritable()); 242111051Sandreas.hansson@arm.com 242211051Sandreas.hansson@arm.com mshr->isForward = (pkt == NULL); 242311051Sandreas.hansson@arm.com 242411051Sandreas.hansson@arm.com if (mshr->isForward) { 242511051Sandreas.hansson@arm.com // not a cache block request, but a response is expected 242611051Sandreas.hansson@arm.com // make copy of current packet to forward, keep current 242711051Sandreas.hansson@arm.com // copy for response handling 242811051Sandreas.hansson@arm.com pkt = new Packet(tgt_pkt, false, true); 242911051Sandreas.hansson@arm.com if (pkt->isWrite()) { 243011051Sandreas.hansson@arm.com pkt->setData(tgt_pkt->getConstPtr<uint8_t>()); 243111051Sandreas.hansson@arm.com } 243211051Sandreas.hansson@arm.com } 243311051Sandreas.hansson@arm.com } 243411051Sandreas.hansson@arm.com 243511051Sandreas.hansson@arm.com assert(pkt != NULL); 243611275Sandreas.hansson@arm.com // play it safe and append (rather than set) the sender state, as 243711275Sandreas.hansson@arm.com // forwarded packets may already have existing state 243811275Sandreas.hansson@arm.com pkt->pushSenderState(mshr); 243911051Sandreas.hansson@arm.com return pkt; 244011051Sandreas.hansson@arm.com} 244111051Sandreas.hansson@arm.com 244211051Sandreas.hansson@arm.com 244311051Sandreas.hansson@arm.comTick 244411051Sandreas.hansson@arm.comCache::nextMSHRReadyTime() const 244511051Sandreas.hansson@arm.com{ 244611051Sandreas.hansson@arm.com Tick nextReady = std::min(mshrQueue.nextMSHRReadyTime(), 244711051Sandreas.hansson@arm.com writeBuffer.nextMSHRReadyTime()); 244811051Sandreas.hansson@arm.com 244911051Sandreas.hansson@arm.com // Don't signal prefetch ready time if no MSHRs available 245011051Sandreas.hansson@arm.com // Will signal once enoguh MSHRs are deallocated 245111051Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 245211051Sandreas.hansson@arm.com nextReady = std::min(nextReady, 245311051Sandreas.hansson@arm.com prefetcher->nextPrefetchReadyTime()); 245411051Sandreas.hansson@arm.com } 245511051Sandreas.hansson@arm.com 245611051Sandreas.hansson@arm.com return nextReady; 245711051Sandreas.hansson@arm.com} 245811051Sandreas.hansson@arm.com 245911051Sandreas.hansson@arm.comvoid 246011051Sandreas.hansson@arm.comCache::serialize(CheckpointOut &cp) const 246111051Sandreas.hansson@arm.com{ 246211051Sandreas.hansson@arm.com bool dirty(isDirty()); 246311051Sandreas.hansson@arm.com 246411051Sandreas.hansson@arm.com if (dirty) { 246511051Sandreas.hansson@arm.com warn("*** The cache still contains dirty data. ***\n"); 246611051Sandreas.hansson@arm.com warn(" Make sure to drain the system using the correct flags.\n"); 246711051Sandreas.hansson@arm.com warn(" This checkpoint will not restore correctly and dirty data in " 246811051Sandreas.hansson@arm.com "the cache will be lost!\n"); 246911051Sandreas.hansson@arm.com } 247011051Sandreas.hansson@arm.com 247111051Sandreas.hansson@arm.com // Since we don't checkpoint the data in the cache, any dirty data 247211051Sandreas.hansson@arm.com // will be lost when restoring from a checkpoint of a system that 247311051Sandreas.hansson@arm.com // wasn't drained properly. Flag the checkpoint as invalid if the 247411051Sandreas.hansson@arm.com // cache contains dirty data. 247511051Sandreas.hansson@arm.com bool bad_checkpoint(dirty); 247611051Sandreas.hansson@arm.com SERIALIZE_SCALAR(bad_checkpoint); 247711051Sandreas.hansson@arm.com} 247811051Sandreas.hansson@arm.com 247911051Sandreas.hansson@arm.comvoid 248011051Sandreas.hansson@arm.comCache::unserialize(CheckpointIn &cp) 248111051Sandreas.hansson@arm.com{ 248211051Sandreas.hansson@arm.com bool bad_checkpoint; 248311051Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(bad_checkpoint); 248411051Sandreas.hansson@arm.com if (bad_checkpoint) { 248511051Sandreas.hansson@arm.com fatal("Restoring from checkpoints with dirty caches is not supported " 248611051Sandreas.hansson@arm.com "in the classic memory system. Please remove any caches or " 248711051Sandreas.hansson@arm.com " drain them properly before taking checkpoints.\n"); 248811051Sandreas.hansson@arm.com } 248911051Sandreas.hansson@arm.com} 249011051Sandreas.hansson@arm.com 249111051Sandreas.hansson@arm.com/////////////// 249211051Sandreas.hansson@arm.com// 249311051Sandreas.hansson@arm.com// CpuSidePort 249411051Sandreas.hansson@arm.com// 249511051Sandreas.hansson@arm.com/////////////// 249611051Sandreas.hansson@arm.com 249711051Sandreas.hansson@arm.comAddrRangeList 249811051Sandreas.hansson@arm.comCache::CpuSidePort::getAddrRanges() const 249911051Sandreas.hansson@arm.com{ 250011051Sandreas.hansson@arm.com return cache->getAddrRanges(); 250111051Sandreas.hansson@arm.com} 250211051Sandreas.hansson@arm.com 250311051Sandreas.hansson@arm.combool 250411051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingReq(PacketPtr pkt) 250511051Sandreas.hansson@arm.com{ 250611051Sandreas.hansson@arm.com assert(!cache->system->bypassCaches()); 250711051Sandreas.hansson@arm.com 250811051Sandreas.hansson@arm.com bool success = false; 250911051Sandreas.hansson@arm.com 251011284Sandreas.hansson@arm.com // always let packets through if an upstream cache has committed 251111284Sandreas.hansson@arm.com // to responding, even if blocked (we should technically look at 251211284Sandreas.hansson@arm.com // the isExpressSnoop flag, but it is set by the cache itself, and 251311284Sandreas.hansson@arm.com // consequently we have to rely on the cacheResponding flag) 251411284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 251511051Sandreas.hansson@arm.com // do not change the current retry state 251611051Sandreas.hansson@arm.com bool M5_VAR_USED bypass_success = cache->recvTimingReq(pkt); 251711051Sandreas.hansson@arm.com assert(bypass_success); 251811051Sandreas.hansson@arm.com return true; 251911051Sandreas.hansson@arm.com } else if (blocked || mustSendRetry) { 252011051Sandreas.hansson@arm.com // either already committed to send a retry, or blocked 252111051Sandreas.hansson@arm.com success = false; 252211051Sandreas.hansson@arm.com } else { 252311051Sandreas.hansson@arm.com // pass it on to the cache, and let the cache decide if we 252411051Sandreas.hansson@arm.com // have to retry or not 252511051Sandreas.hansson@arm.com success = cache->recvTimingReq(pkt); 252611051Sandreas.hansson@arm.com } 252711051Sandreas.hansson@arm.com 252811051Sandreas.hansson@arm.com // remember if we have to retry 252911051Sandreas.hansson@arm.com mustSendRetry = !success; 253011051Sandreas.hansson@arm.com return success; 253111051Sandreas.hansson@arm.com} 253211051Sandreas.hansson@arm.com 253311051Sandreas.hansson@arm.comTick 253411051Sandreas.hansson@arm.comCache::CpuSidePort::recvAtomic(PacketPtr pkt) 253511051Sandreas.hansson@arm.com{ 253611051Sandreas.hansson@arm.com return cache->recvAtomic(pkt); 253711051Sandreas.hansson@arm.com} 253811051Sandreas.hansson@arm.com 253911051Sandreas.hansson@arm.comvoid 254011051Sandreas.hansson@arm.comCache::CpuSidePort::recvFunctional(PacketPtr pkt) 254111051Sandreas.hansson@arm.com{ 254211051Sandreas.hansson@arm.com // functional request 254311051Sandreas.hansson@arm.com cache->functionalAccess(pkt, true); 254411051Sandreas.hansson@arm.com} 254511051Sandreas.hansson@arm.com 254611051Sandreas.hansson@arm.comCache:: 254711051Sandreas.hansson@arm.comCpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache, 254811051Sandreas.hansson@arm.com const std::string &_label) 254911051Sandreas.hansson@arm.com : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache) 255011051Sandreas.hansson@arm.com{ 255111051Sandreas.hansson@arm.com} 255211051Sandreas.hansson@arm.com 255311053Sandreas.hansson@arm.comCache* 255411053Sandreas.hansson@arm.comCacheParams::create() 255511053Sandreas.hansson@arm.com{ 255611053Sandreas.hansson@arm.com assert(tags); 255711053Sandreas.hansson@arm.com 255811053Sandreas.hansson@arm.com return new Cache(this); 255911053Sandreas.hansson@arm.com} 256011051Sandreas.hansson@arm.com/////////////// 256111051Sandreas.hansson@arm.com// 256211051Sandreas.hansson@arm.com// MemSidePort 256311051Sandreas.hansson@arm.com// 256411051Sandreas.hansson@arm.com/////////////// 256511051Sandreas.hansson@arm.com 256611051Sandreas.hansson@arm.combool 256711051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingResp(PacketPtr pkt) 256811051Sandreas.hansson@arm.com{ 256911051Sandreas.hansson@arm.com cache->recvTimingResp(pkt); 257011051Sandreas.hansson@arm.com return true; 257111051Sandreas.hansson@arm.com} 257211051Sandreas.hansson@arm.com 257311051Sandreas.hansson@arm.com// Express snooping requests to memside port 257411051Sandreas.hansson@arm.comvoid 257511051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 257611051Sandreas.hansson@arm.com{ 257711051Sandreas.hansson@arm.com // handle snooping requests 257811051Sandreas.hansson@arm.com cache->recvTimingSnoopReq(pkt); 257911051Sandreas.hansson@arm.com} 258011051Sandreas.hansson@arm.com 258111051Sandreas.hansson@arm.comTick 258211051Sandreas.hansson@arm.comCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 258311051Sandreas.hansson@arm.com{ 258411051Sandreas.hansson@arm.com return cache->recvAtomicSnoop(pkt); 258511051Sandreas.hansson@arm.com} 258611051Sandreas.hansson@arm.com 258711051Sandreas.hansson@arm.comvoid 258811051Sandreas.hansson@arm.comCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 258911051Sandreas.hansson@arm.com{ 259011051Sandreas.hansson@arm.com // functional snoop (note that in contrast to atomic we don't have 259111051Sandreas.hansson@arm.com // a specific functionalSnoop method, as they have the same 259211051Sandreas.hansson@arm.com // behaviour regardless) 259311051Sandreas.hansson@arm.com cache->functionalAccess(pkt, false); 259411051Sandreas.hansson@arm.com} 259511051Sandreas.hansson@arm.com 259611051Sandreas.hansson@arm.comvoid 259711051Sandreas.hansson@arm.comCache::CacheReqPacketQueue::sendDeferredPacket() 259811051Sandreas.hansson@arm.com{ 259911051Sandreas.hansson@arm.com // sanity check 260011051Sandreas.hansson@arm.com assert(!waitingOnRetry); 260111051Sandreas.hansson@arm.com 260211051Sandreas.hansson@arm.com // there should never be any deferred request packets in the 260311051Sandreas.hansson@arm.com // queue, instead we resly on the cache to provide the packets 260411051Sandreas.hansson@arm.com // from the MSHR queue or write queue 260511051Sandreas.hansson@arm.com assert(deferredPacketReadyTime() == MaxTick); 260611051Sandreas.hansson@arm.com 260711051Sandreas.hansson@arm.com // check for request packets (requests & writebacks) 260811051Sandreas.hansson@arm.com PacketPtr pkt = cache.getTimingPacket(); 260911051Sandreas.hansson@arm.com if (pkt == NULL) { 261011051Sandreas.hansson@arm.com // can happen if e.g. we attempt a writeback and fail, but 261111051Sandreas.hansson@arm.com // before the retry, the writeback is eliminated because 261211051Sandreas.hansson@arm.com // we snoop another cache's ReadEx. 261311051Sandreas.hansson@arm.com } else { 261411051Sandreas.hansson@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState); 261511051Sandreas.hansson@arm.com // in most cases getTimingPacket allocates a new packet, and 261611051Sandreas.hansson@arm.com // we must delete it unless it is successfully sent 261711051Sandreas.hansson@arm.com bool delete_pkt = !mshr->isForwardNoResponse(); 261811051Sandreas.hansson@arm.com 261911051Sandreas.hansson@arm.com // let our snoop responses go first if there are responses to 262011051Sandreas.hansson@arm.com // the same addresses we are about to writeback, note that 262111051Sandreas.hansson@arm.com // this creates a dependency between requests and snoop 262211051Sandreas.hansson@arm.com // responses, but that should not be a problem since there is 262311051Sandreas.hansson@arm.com // a chain already and the key is that the snoop responses can 262411051Sandreas.hansson@arm.com // sink unconditionally 262511051Sandreas.hansson@arm.com if (snoopRespQueue.hasAddr(pkt->getAddr())) { 262611051Sandreas.hansson@arm.com DPRINTF(CachePort, "Waiting for snoop response to be sent\n"); 262711051Sandreas.hansson@arm.com Tick when = snoopRespQueue.deferredPacketReadyTime(); 262811051Sandreas.hansson@arm.com schedSendEvent(when); 262911051Sandreas.hansson@arm.com 263011051Sandreas.hansson@arm.com if (delete_pkt) 263111051Sandreas.hansson@arm.com delete pkt; 263211051Sandreas.hansson@arm.com 263311051Sandreas.hansson@arm.com return; 263411051Sandreas.hansson@arm.com } 263511051Sandreas.hansson@arm.com 263611051Sandreas.hansson@arm.com 263711051Sandreas.hansson@arm.com waitingOnRetry = !masterPort.sendTimingReq(pkt); 263811051Sandreas.hansson@arm.com 263911051Sandreas.hansson@arm.com if (waitingOnRetry) { 264011051Sandreas.hansson@arm.com DPRINTF(CachePort, "now waiting on a retry\n"); 264111051Sandreas.hansson@arm.com if (delete_pkt) { 264211051Sandreas.hansson@arm.com // we are awaiting a retry, but we 264311051Sandreas.hansson@arm.com // delete the packet and will be creating a new packet 264411051Sandreas.hansson@arm.com // when we get the opportunity 264511051Sandreas.hansson@arm.com delete pkt; 264611051Sandreas.hansson@arm.com } 264711051Sandreas.hansson@arm.com // note that we have now masked any requestBus and 264811051Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 264911051Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 265011051Sandreas.hansson@arm.com // care about this packet and might override it before 265111051Sandreas.hansson@arm.com // it gets retried 265211051Sandreas.hansson@arm.com } else { 265311051Sandreas.hansson@arm.com // As part of the call to sendTimingReq the packet is 265411284Sandreas.hansson@arm.com // forwarded to all neighbouring caches (and any caches 265511284Sandreas.hansson@arm.com // above them) as a snoop. Thus at this point we know if 265611284Sandreas.hansson@arm.com // any of the neighbouring caches are responding, and if 265711284Sandreas.hansson@arm.com // so, we know it is dirty, and we can determine if it is 265811284Sandreas.hansson@arm.com // being passed as Modified, making our MSHR the ordering 265911284Sandreas.hansson@arm.com // point 266011284Sandreas.hansson@arm.com bool pending_modified_resp = !pkt->hasSharers() && 266111284Sandreas.hansson@arm.com pkt->cacheResponding(); 266211051Sandreas.hansson@arm.com 266311284Sandreas.hansson@arm.com cache.markInService(mshr, pending_modified_resp); 266411051Sandreas.hansson@arm.com } 266511051Sandreas.hansson@arm.com } 266611051Sandreas.hansson@arm.com 266711051Sandreas.hansson@arm.com // if we succeeded and are not waiting for a retry, schedule the 266811051Sandreas.hansson@arm.com // next send considering when the next MSHR is ready, note that 266911051Sandreas.hansson@arm.com // snoop responses have their own packet queue and thus schedule 267011051Sandreas.hansson@arm.com // their own events 267111051Sandreas.hansson@arm.com if (!waitingOnRetry) { 267211051Sandreas.hansson@arm.com schedSendEvent(cache.nextMSHRReadyTime()); 267311051Sandreas.hansson@arm.com } 267411051Sandreas.hansson@arm.com} 267511051Sandreas.hansson@arm.com 267611051Sandreas.hansson@arm.comCache:: 267711051Sandreas.hansson@arm.comMemSidePort::MemSidePort(const std::string &_name, Cache *_cache, 267811051Sandreas.hansson@arm.com const std::string &_label) 267911051Sandreas.hansson@arm.com : BaseCache::CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 268011051Sandreas.hansson@arm.com _reqQueue(*_cache, *this, _snoopRespQueue, _label), 268111051Sandreas.hansson@arm.com _snoopRespQueue(*_cache, *this, _label), cache(_cache) 268211051Sandreas.hansson@arm.com{ 268311051Sandreas.hansson@arm.com} 2684