cache.cc revision 11277
12810Srdreslin@umich.edu/* 211051Sandreas.hansson@arm.com * Copyright (c) 2010-2015 ARM Limited 311051Sandreas.hansson@arm.com * All rights reserved. 411051Sandreas.hansson@arm.com * 511051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911051Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311051Sandreas.hansson@arm.com * 1411051Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511051Sandreas.hansson@arm.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 162810Srdreslin@umich.edu * All rights reserved. 172810Srdreslin@umich.edu * 182810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 192810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 202810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 212810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 222810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 232810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 242810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 252810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 262810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 272810Srdreslin@umich.edu * this software without specific prior written permission. 282810Srdreslin@umich.edu * 292810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810Srdreslin@umich.edu * 412810Srdreslin@umich.edu * Authors: Erik Hallnor 4211051Sandreas.hansson@arm.com * Dave Greene 4311051Sandreas.hansson@arm.com * Nathan Binkert 442810Srdreslin@umich.edu * Steve Reinhardt 4511051Sandreas.hansson@arm.com * Ron Dreslinski 4611051Sandreas.hansson@arm.com * Andreas Sandberg 472810Srdreslin@umich.edu */ 482810Srdreslin@umich.edu 492810Srdreslin@umich.edu/** 502810Srdreslin@umich.edu * @file 5111051Sandreas.hansson@arm.com * Cache definitions. 522810Srdreslin@umich.edu */ 532810Srdreslin@umich.edu 5411051Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 552810Srdreslin@umich.edu 5611051Sandreas.hansson@arm.com#include "base/misc.hh" 5711051Sandreas.hansson@arm.com#include "base/types.hh" 5811051Sandreas.hansson@arm.com#include "debug/Cache.hh" 5911051Sandreas.hansson@arm.com#include "debug/CachePort.hh" 6011051Sandreas.hansson@arm.com#include "debug/CacheTags.hh" 6111051Sandreas.hansson@arm.com#include "mem/cache/blk.hh" 6211051Sandreas.hansson@arm.com#include "mem/cache/mshr.hh" 6311051Sandreas.hansson@arm.com#include "mem/cache/prefetch/base.hh" 6411051Sandreas.hansson@arm.com#include "sim/sim_exit.hh" 6511051Sandreas.hansson@arm.com 6611053Sandreas.hansson@arm.comCache::Cache(const CacheParams *p) 6711053Sandreas.hansson@arm.com : BaseCache(p, p->system->cacheLineSize()), 6811051Sandreas.hansson@arm.com tags(p->tags), 6911051Sandreas.hansson@arm.com prefetcher(p->prefetcher), 7011051Sandreas.hansson@arm.com doFastWrites(true), 7111197Sandreas.hansson@arm.com prefetchOnAccess(p->prefetch_on_access), 7211197Sandreas.hansson@arm.com clusivity(p->clusivity), 7311199Sandreas.hansson@arm.com writebackClean(p->writeback_clean), 7411197Sandreas.hansson@arm.com tempBlockWriteback(nullptr), 7511197Sandreas.hansson@arm.com writebackTempBlockAtomicEvent(this, false, 7611197Sandreas.hansson@arm.com EventBase::Delayed_Writeback_Pri) 7711051Sandreas.hansson@arm.com{ 7811051Sandreas.hansson@arm.com tempBlock = new CacheBlk(); 7911051Sandreas.hansson@arm.com tempBlock->data = new uint8_t[blkSize]; 8011051Sandreas.hansson@arm.com 8111051Sandreas.hansson@arm.com cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this, 8211051Sandreas.hansson@arm.com "CpuSidePort"); 8311051Sandreas.hansson@arm.com memSidePort = new MemSidePort(p->name + ".mem_side", this, 8411051Sandreas.hansson@arm.com "MemSidePort"); 8511051Sandreas.hansson@arm.com 8611051Sandreas.hansson@arm.com tags->setCache(this); 8711051Sandreas.hansson@arm.com if (prefetcher) 8811051Sandreas.hansson@arm.com prefetcher->setCache(this); 8911051Sandreas.hansson@arm.com} 9011051Sandreas.hansson@arm.com 9111051Sandreas.hansson@arm.comCache::~Cache() 9211051Sandreas.hansson@arm.com{ 9311051Sandreas.hansson@arm.com delete [] tempBlock->data; 9411051Sandreas.hansson@arm.com delete tempBlock; 9511051Sandreas.hansson@arm.com 9611051Sandreas.hansson@arm.com delete cpuSidePort; 9711051Sandreas.hansson@arm.com delete memSidePort; 9811051Sandreas.hansson@arm.com} 9911051Sandreas.hansson@arm.com 10011051Sandreas.hansson@arm.comvoid 10111051Sandreas.hansson@arm.comCache::regStats() 10211051Sandreas.hansson@arm.com{ 10311051Sandreas.hansson@arm.com BaseCache::regStats(); 10411051Sandreas.hansson@arm.com} 10511051Sandreas.hansson@arm.com 10611051Sandreas.hansson@arm.comvoid 10711051Sandreas.hansson@arm.comCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 10811051Sandreas.hansson@arm.com{ 10911051Sandreas.hansson@arm.com assert(pkt->isRequest()); 11011051Sandreas.hansson@arm.com 11111051Sandreas.hansson@arm.com uint64_t overwrite_val; 11211051Sandreas.hansson@arm.com bool overwrite_mem; 11311051Sandreas.hansson@arm.com uint64_t condition_val64; 11411051Sandreas.hansson@arm.com uint32_t condition_val32; 11511051Sandreas.hansson@arm.com 11611051Sandreas.hansson@arm.com int offset = tags->extractBlkOffset(pkt->getAddr()); 11711051Sandreas.hansson@arm.com uint8_t *blk_data = blk->data + offset; 11811051Sandreas.hansson@arm.com 11911051Sandreas.hansson@arm.com assert(sizeof(uint64_t) >= pkt->getSize()); 12011051Sandreas.hansson@arm.com 12111051Sandreas.hansson@arm.com overwrite_mem = true; 12211051Sandreas.hansson@arm.com // keep a copy of our possible write value, and copy what is at the 12311051Sandreas.hansson@arm.com // memory address into the packet 12411051Sandreas.hansson@arm.com pkt->writeData((uint8_t *)&overwrite_val); 12511051Sandreas.hansson@arm.com pkt->setData(blk_data); 12611051Sandreas.hansson@arm.com 12711051Sandreas.hansson@arm.com if (pkt->req->isCondSwap()) { 12811051Sandreas.hansson@arm.com if (pkt->getSize() == sizeof(uint64_t)) { 12911051Sandreas.hansson@arm.com condition_val64 = pkt->req->getExtraData(); 13011051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val64, blk_data, 13111051Sandreas.hansson@arm.com sizeof(uint64_t)); 13211051Sandreas.hansson@arm.com } else if (pkt->getSize() == sizeof(uint32_t)) { 13311051Sandreas.hansson@arm.com condition_val32 = (uint32_t)pkt->req->getExtraData(); 13411051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val32, blk_data, 13511051Sandreas.hansson@arm.com sizeof(uint32_t)); 13611051Sandreas.hansson@arm.com } else 13711051Sandreas.hansson@arm.com panic("Invalid size for conditional read/write\n"); 13811051Sandreas.hansson@arm.com } 13911051Sandreas.hansson@arm.com 14011051Sandreas.hansson@arm.com if (overwrite_mem) { 14111051Sandreas.hansson@arm.com std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 14211051Sandreas.hansson@arm.com blk->status |= BlkDirty; 14311051Sandreas.hansson@arm.com } 14411051Sandreas.hansson@arm.com} 14511051Sandreas.hansson@arm.com 14611051Sandreas.hansson@arm.com 14711051Sandreas.hansson@arm.comvoid 14811051Sandreas.hansson@arm.comCache::satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk, 14911051Sandreas.hansson@arm.com bool deferred_response, bool pending_downgrade) 15011051Sandreas.hansson@arm.com{ 15111051Sandreas.hansson@arm.com assert(pkt->isRequest()); 15211051Sandreas.hansson@arm.com 15311051Sandreas.hansson@arm.com assert(blk && blk->isValid()); 15411051Sandreas.hansson@arm.com // Occasionally this is not true... if we are a lower-level cache 15511051Sandreas.hansson@arm.com // satisfying a string of Read and ReadEx requests from 15611051Sandreas.hansson@arm.com // upper-level caches, a Read will mark the block as shared but we 15711051Sandreas.hansson@arm.com // can satisfy a following ReadEx anyway since we can rely on the 15811051Sandreas.hansson@arm.com // Read requester(s) to have buffered the ReadEx snoop and to 15911051Sandreas.hansson@arm.com // invalidate their blocks after receiving them. 16011051Sandreas.hansson@arm.com // assert(!pkt->needsExclusive() || blk->isWritable()); 16111051Sandreas.hansson@arm.com assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 16211051Sandreas.hansson@arm.com 16311051Sandreas.hansson@arm.com // Check RMW operations first since both isRead() and 16411051Sandreas.hansson@arm.com // isWrite() will be true for them 16511051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::SwapReq) { 16611051Sandreas.hansson@arm.com cmpAndSwap(blk, pkt); 16711051Sandreas.hansson@arm.com } else if (pkt->isWrite()) { 16811051Sandreas.hansson@arm.com assert(blk->isWritable()); 16911051Sandreas.hansson@arm.com // Write or WriteLine at the first cache with block in Exclusive 17011051Sandreas.hansson@arm.com if (blk->checkWrite(pkt)) { 17111051Sandreas.hansson@arm.com pkt->writeDataToBlock(blk->data, blkSize); 17211051Sandreas.hansson@arm.com } 17311051Sandreas.hansson@arm.com // Always mark the line as dirty even if we are a failed 17411051Sandreas.hansson@arm.com // StoreCond so we supply data to any snoops that have 17511051Sandreas.hansson@arm.com // appended themselves to this cache before knowing the store 17611051Sandreas.hansson@arm.com // will fail. 17711051Sandreas.hansson@arm.com blk->status |= BlkDirty; 17811051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d (write)\n", __func__, 17911051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 18011051Sandreas.hansson@arm.com } else if (pkt->isRead()) { 18111051Sandreas.hansson@arm.com if (pkt->isLLSC()) { 18211051Sandreas.hansson@arm.com blk->trackLoadLocked(pkt); 18311051Sandreas.hansson@arm.com } 18411051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 18511051Sandreas.hansson@arm.com // determine if this read is from a (coherent) cache, or not 18611051Sandreas.hansson@arm.com // by looking at the command type; we could potentially add a 18711051Sandreas.hansson@arm.com // packet attribute such as 'FromCache' to make this check a 18811051Sandreas.hansson@arm.com // bit cleaner 18911051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadExReq || 19011051Sandreas.hansson@arm.com pkt->cmd == MemCmd::ReadSharedReq || 19111051Sandreas.hansson@arm.com pkt->cmd == MemCmd::ReadCleanReq || 19211051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq) { 19311051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 19411051Sandreas.hansson@arm.com // special handling for coherent block requests from 19511051Sandreas.hansson@arm.com // upper-level caches 19611051Sandreas.hansson@arm.com if (pkt->needsExclusive()) { 19711051Sandreas.hansson@arm.com // sanity check 19811051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::ReadExReq || 19911051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq); 20011051Sandreas.hansson@arm.com 20111051Sandreas.hansson@arm.com // if we have a dirty copy, make sure the recipient 20211051Sandreas.hansson@arm.com // keeps it marked dirty 20311051Sandreas.hansson@arm.com if (blk->isDirty()) { 20411051Sandreas.hansson@arm.com pkt->assertMemInhibit(); 20511051Sandreas.hansson@arm.com } 20611197Sandreas.hansson@arm.com // on ReadExReq we give up our copy unconditionally, 20711197Sandreas.hansson@arm.com // even if this cache is mostly inclusive, we may want 20811197Sandreas.hansson@arm.com // to revisit this 20911197Sandreas.hansson@arm.com invalidateBlock(blk); 21011051Sandreas.hansson@arm.com } else if (blk->isWritable() && !pending_downgrade && 21111051Sandreas.hansson@arm.com !pkt->sharedAsserted() && 21211051Sandreas.hansson@arm.com pkt->cmd != MemCmd::ReadCleanReq) { 21311051Sandreas.hansson@arm.com // we can give the requester an exclusive copy (by not 21411051Sandreas.hansson@arm.com // asserting shared line) on a read request if: 21511051Sandreas.hansson@arm.com // - we have an exclusive copy at this level (& below) 21611051Sandreas.hansson@arm.com // - we don't have a pending snoop from below 21711051Sandreas.hansson@arm.com // signaling another read request 21811051Sandreas.hansson@arm.com // - no other cache above has a copy (otherwise it 21911051Sandreas.hansson@arm.com // would have asseretd shared line on request) 22011051Sandreas.hansson@arm.com // - we are not satisfying an instruction fetch (this 22111051Sandreas.hansson@arm.com // prevents dirty data in the i-cache) 22211051Sandreas.hansson@arm.com 22311051Sandreas.hansson@arm.com if (blk->isDirty()) { 22411051Sandreas.hansson@arm.com // special considerations if we're owner: 22511051Sandreas.hansson@arm.com if (!deferred_response) { 22611051Sandreas.hansson@arm.com // if we are responding immediately and can 22711051Sandreas.hansson@arm.com // signal that we're transferring ownership 22811197Sandreas.hansson@arm.com // (inhibit set) along with exclusivity 22911197Sandreas.hansson@arm.com // (shared not set), do so 23011051Sandreas.hansson@arm.com pkt->assertMemInhibit(); 23111197Sandreas.hansson@arm.com 23211197Sandreas.hansson@arm.com // if this cache is mostly inclusive, we keep 23311197Sandreas.hansson@arm.com // the block as writable (exclusive), and pass 23411197Sandreas.hansson@arm.com // it upwards as writable and dirty 23511197Sandreas.hansson@arm.com // (modified), hence we have multiple caches 23611197Sandreas.hansson@arm.com // considering the same block writable, 23711197Sandreas.hansson@arm.com // something that we get away with due to the 23811197Sandreas.hansson@arm.com // fact that: 1) this cache has been 23911197Sandreas.hansson@arm.com // considered the ordering points and 24011197Sandreas.hansson@arm.com // responded to all snoops up till now, and 2) 24111197Sandreas.hansson@arm.com // we always snoop upwards before consulting 24211197Sandreas.hansson@arm.com // the local cache, both on a normal request 24311197Sandreas.hansson@arm.com // (snooping done by the crossbar), and on a 24411197Sandreas.hansson@arm.com // snoop 24511051Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 24611197Sandreas.hansson@arm.com 24711197Sandreas.hansson@arm.com // if this cache is mostly exclusive with 24811197Sandreas.hansson@arm.com // respect to the cache above, drop the block 24911197Sandreas.hansson@arm.com if (clusivity == Enums::mostly_excl) { 25011197Sandreas.hansson@arm.com invalidateBlock(blk); 25111197Sandreas.hansson@arm.com } 25211051Sandreas.hansson@arm.com } else { 25311051Sandreas.hansson@arm.com // if we're responding after our own miss, 25411051Sandreas.hansson@arm.com // there's a window where the recipient didn't 25511051Sandreas.hansson@arm.com // know it was getting ownership and may not 25611051Sandreas.hansson@arm.com // have responded to snoops correctly, so we 25711051Sandreas.hansson@arm.com // can't pass off ownership *or* exclusivity 25811051Sandreas.hansson@arm.com pkt->assertShared(); 25911051Sandreas.hansson@arm.com } 26011051Sandreas.hansson@arm.com } 26111051Sandreas.hansson@arm.com } else { 26211051Sandreas.hansson@arm.com // otherwise only respond with a shared copy 26311051Sandreas.hansson@arm.com pkt->assertShared(); 26411051Sandreas.hansson@arm.com } 26511051Sandreas.hansson@arm.com } 26611051Sandreas.hansson@arm.com } else { 26711051Sandreas.hansson@arm.com // Upgrade or Invalidate, since we have it Exclusively (E or 26811051Sandreas.hansson@arm.com // M), we ack then invalidate. 26911051Sandreas.hansson@arm.com assert(pkt->isUpgrade() || pkt->isInvalidate()); 27011197Sandreas.hansson@arm.com 27111197Sandreas.hansson@arm.com // for invalidations we could be looking at the temp block 27211197Sandreas.hansson@arm.com // (for upgrades we always allocate) 27311197Sandreas.hansson@arm.com invalidateBlock(blk); 27411051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d (invalidation)\n", 27511051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 27611051Sandreas.hansson@arm.com } 27711051Sandreas.hansson@arm.com} 27811051Sandreas.hansson@arm.com 27911051Sandreas.hansson@arm.com 28011051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28111051Sandreas.hansson@arm.com// 28211051Sandreas.hansson@arm.com// MSHR helper functions 28311051Sandreas.hansson@arm.com// 28411051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28511051Sandreas.hansson@arm.com 28611051Sandreas.hansson@arm.com 28711051Sandreas.hansson@arm.comvoid 28811051Sandreas.hansson@arm.comCache::markInService(MSHR *mshr, bool pending_dirty_resp) 28911051Sandreas.hansson@arm.com{ 29011051Sandreas.hansson@arm.com markInServiceInternal(mshr, pending_dirty_resp); 29111051Sandreas.hansson@arm.com} 29211051Sandreas.hansson@arm.com 29311051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 29411051Sandreas.hansson@arm.com// 29511051Sandreas.hansson@arm.com// Access path: requests coming in from the CPU side 29611051Sandreas.hansson@arm.com// 29711051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 29811051Sandreas.hansson@arm.com 29911051Sandreas.hansson@arm.combool 30011051Sandreas.hansson@arm.comCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 30111051Sandreas.hansson@arm.com PacketList &writebacks) 30211051Sandreas.hansson@arm.com{ 30311051Sandreas.hansson@arm.com // sanity check 30411051Sandreas.hansson@arm.com assert(pkt->isRequest()); 30511051Sandreas.hansson@arm.com 30611051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 30711051Sandreas.hansson@arm.com "Should never see a write in a read-only cache %s\n", 30811051Sandreas.hansson@arm.com name()); 30911051Sandreas.hansson@arm.com 31011051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 31111051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 31211051Sandreas.hansson@arm.com 31311051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 31411051Sandreas.hansson@arm.com DPRINTF(Cache, "%s%s addr %#llx uncacheable\n", pkt->cmdString(), 31511051Sandreas.hansson@arm.com pkt->req->isInstFetch() ? " (ifetch)" : "", 31611051Sandreas.hansson@arm.com pkt->getAddr()); 31711051Sandreas.hansson@arm.com 31811051Sandreas.hansson@arm.com // flush and invalidate any existing block 31911051Sandreas.hansson@arm.com CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure())); 32011051Sandreas.hansson@arm.com if (old_blk && old_blk->isValid()) { 32111199Sandreas.hansson@arm.com if (old_blk->isDirty() || writebackClean) 32211051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(old_blk)); 32311051Sandreas.hansson@arm.com else 32411051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(old_blk)); 32511051Sandreas.hansson@arm.com tags->invalidate(old_blk); 32611051Sandreas.hansson@arm.com old_blk->invalidate(); 32711051Sandreas.hansson@arm.com } 32811051Sandreas.hansson@arm.com 32911051Sandreas.hansson@arm.com blk = NULL; 33011051Sandreas.hansson@arm.com // lookupLatency is the latency in case the request is uncacheable. 33111051Sandreas.hansson@arm.com lat = lookupLatency; 33211051Sandreas.hansson@arm.com return false; 33311051Sandreas.hansson@arm.com } 33411051Sandreas.hansson@arm.com 33511051Sandreas.hansson@arm.com ContextID id = pkt->req->hasContextId() ? 33611051Sandreas.hansson@arm.com pkt->req->contextId() : InvalidContextID; 33711051Sandreas.hansson@arm.com // Here lat is the value passed as parameter to accessBlock() function 33811051Sandreas.hansson@arm.com // that can modify its value. 33911051Sandreas.hansson@arm.com blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat, id); 34011051Sandreas.hansson@arm.com 34111051Sandreas.hansson@arm.com DPRINTF(Cache, "%s%s addr %#llx size %d (%s) %s\n", pkt->cmdString(), 34211051Sandreas.hansson@arm.com pkt->req->isInstFetch() ? " (ifetch)" : "", 34311051Sandreas.hansson@arm.com pkt->getAddr(), pkt->getSize(), pkt->isSecure() ? "s" : "ns", 34411051Sandreas.hansson@arm.com blk ? "hit " + blk->print() : "miss"); 34511051Sandreas.hansson@arm.com 34611051Sandreas.hansson@arm.com 34711199Sandreas.hansson@arm.com if (pkt->isEviction()) { 34811051Sandreas.hansson@arm.com // We check for presence of block in above caches before issuing 34911051Sandreas.hansson@arm.com // Writeback or CleanEvict to write buffer. Therefore the only 35011051Sandreas.hansson@arm.com // possible cases can be of a CleanEvict packet coming from above 35111051Sandreas.hansson@arm.com // encountering a Writeback generated in this cache peer cache and 35211051Sandreas.hansson@arm.com // waiting in the write buffer. Cases of upper level peer caches 35311051Sandreas.hansson@arm.com // generating CleanEvict and Writeback or simply CleanEvict and 35411051Sandreas.hansson@arm.com // CleanEvict almost simultaneously will be caught by snoops sent out 35511051Sandreas.hansson@arm.com // by crossbar. 35611051Sandreas.hansson@arm.com std::vector<MSHR *> outgoing; 35711051Sandreas.hansson@arm.com if (writeBuffer.findMatches(pkt->getAddr(), pkt->isSecure(), 35811051Sandreas.hansson@arm.com outgoing)) { 35911051Sandreas.hansson@arm.com assert(outgoing.size() == 1); 36011199Sandreas.hansson@arm.com MSHR *wb_entry = outgoing[0]; 36111199Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 36211199Sandreas.hansson@arm.com PacketPtr wbPkt = wb_entry->getTarget()->pkt; 36311199Sandreas.hansson@arm.com assert(wbPkt->isWriteback()); 36411199Sandreas.hansson@arm.com 36511199Sandreas.hansson@arm.com if (pkt->isCleanEviction()) { 36611199Sandreas.hansson@arm.com // The CleanEvict and WritebackClean snoops into other 36711199Sandreas.hansson@arm.com // peer caches of the same level while traversing the 36811199Sandreas.hansson@arm.com // crossbar. If a copy of the block is found, the 36911199Sandreas.hansson@arm.com // packet is deleted in the crossbar. Hence, none of 37011199Sandreas.hansson@arm.com // the other upper level caches connected to this 37111199Sandreas.hansson@arm.com // cache have the block, so we can clear the 37211199Sandreas.hansson@arm.com // BLOCK_CACHED flag in the Writeback if set and 37311199Sandreas.hansson@arm.com // discard the CleanEvict by returning true. 37411199Sandreas.hansson@arm.com wbPkt->clearBlockCached(); 37511199Sandreas.hansson@arm.com return true; 37611199Sandreas.hansson@arm.com } else { 37711199Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::WritebackDirty); 37811199Sandreas.hansson@arm.com // Dirty writeback from above trumps our clean 37911199Sandreas.hansson@arm.com // writeback... discard here 38011199Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 38111199Sandreas.hansson@arm.com markInService(wb_entry, false); 38211199Sandreas.hansson@arm.com delete wbPkt; 38311199Sandreas.hansson@arm.com } 38411051Sandreas.hansson@arm.com } 38511051Sandreas.hansson@arm.com } 38611051Sandreas.hansson@arm.com 38711051Sandreas.hansson@arm.com // Writeback handling is special case. We can write the block into 38811051Sandreas.hansson@arm.com // the cache without having a writeable copy (or any copy at all). 38911199Sandreas.hansson@arm.com if (pkt->isWriteback()) { 39011051Sandreas.hansson@arm.com assert(blkSize == pkt->getSize()); 39111199Sandreas.hansson@arm.com 39211199Sandreas.hansson@arm.com // we could get a clean writeback while we are having 39311199Sandreas.hansson@arm.com // outstanding accesses to a block, do the simple thing for 39411199Sandreas.hansson@arm.com // now and drop the clean writeback so that we do not upset 39511199Sandreas.hansson@arm.com // any ordering/decisions about ownership already taken 39611199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackClean && 39711199Sandreas.hansson@arm.com mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) { 39811199Sandreas.hansson@arm.com DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, " 39911199Sandreas.hansson@arm.com "dropping\n", pkt->getAddr()); 40011199Sandreas.hansson@arm.com return true; 40111199Sandreas.hansson@arm.com } 40211199Sandreas.hansson@arm.com 40311051Sandreas.hansson@arm.com if (blk == NULL) { 40411051Sandreas.hansson@arm.com // need to do a replacement 40511051Sandreas.hansson@arm.com blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks); 40611051Sandreas.hansson@arm.com if (blk == NULL) { 40711051Sandreas.hansson@arm.com // no replaceable block available: give up, fwd to next level. 40811051Sandreas.hansson@arm.com incMissCount(pkt); 40911051Sandreas.hansson@arm.com return false; 41011051Sandreas.hansson@arm.com } 41111051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 41211051Sandreas.hansson@arm.com 41311051Sandreas.hansson@arm.com blk->status = (BlkValid | BlkReadable); 41411051Sandreas.hansson@arm.com if (pkt->isSecure()) { 41511051Sandreas.hansson@arm.com blk->status |= BlkSecure; 41611051Sandreas.hansson@arm.com } 41711051Sandreas.hansson@arm.com } 41811199Sandreas.hansson@arm.com // only mark the block dirty if we got a writeback command, 41911199Sandreas.hansson@arm.com // and leave it as is for a clean writeback 42011199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackDirty) { 42111199Sandreas.hansson@arm.com blk->status |= BlkDirty; 42211199Sandreas.hansson@arm.com } 42311051Sandreas.hansson@arm.com // if shared is not asserted we got the writeback in modified 42411051Sandreas.hansson@arm.com // state, if it is asserted we are in the owned state 42511051Sandreas.hansson@arm.com if (!pkt->sharedAsserted()) { 42611051Sandreas.hansson@arm.com blk->status |= BlkWritable; 42711051Sandreas.hansson@arm.com } 42811051Sandreas.hansson@arm.com // nothing else to do; writeback doesn't expect response 42911051Sandreas.hansson@arm.com assert(!pkt->needsResponse()); 43011051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 43111051Sandreas.hansson@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 43211051Sandreas.hansson@arm.com incHitCount(pkt); 43311051Sandreas.hansson@arm.com return true; 43411051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::CleanEvict) { 43511051Sandreas.hansson@arm.com if (blk != NULL) { 43611051Sandreas.hansson@arm.com // Found the block in the tags, need to stop CleanEvict from 43711051Sandreas.hansson@arm.com // propagating further down the hierarchy. Returning true will 43811051Sandreas.hansson@arm.com // treat the CleanEvict like a satisfied write request and delete 43911051Sandreas.hansson@arm.com // it. 44011051Sandreas.hansson@arm.com return true; 44111051Sandreas.hansson@arm.com } 44211051Sandreas.hansson@arm.com // We didn't find the block here, propagate the CleanEvict further 44311051Sandreas.hansson@arm.com // down the memory hierarchy. Returning false will treat the CleanEvict 44411051Sandreas.hansson@arm.com // like a Writeback which could not find a replaceable block so has to 44511051Sandreas.hansson@arm.com // go to next level. 44611051Sandreas.hansson@arm.com return false; 44711051Sandreas.hansson@arm.com } else if ((blk != NULL) && 44811051Sandreas.hansson@arm.com (pkt->needsExclusive() ? blk->isWritable() 44911051Sandreas.hansson@arm.com : blk->isReadable())) { 45011051Sandreas.hansson@arm.com // OK to satisfy access 45111051Sandreas.hansson@arm.com incHitCount(pkt); 45211051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 45311051Sandreas.hansson@arm.com return true; 45411051Sandreas.hansson@arm.com } 45511051Sandreas.hansson@arm.com 45611051Sandreas.hansson@arm.com // Can't satisfy access normally... either no block (blk == NULL) 45711051Sandreas.hansson@arm.com // or have block but need exclusive & only have shared. 45811051Sandreas.hansson@arm.com 45911051Sandreas.hansson@arm.com incMissCount(pkt); 46011051Sandreas.hansson@arm.com 46111051Sandreas.hansson@arm.com if (blk == NULL && pkt->isLLSC() && pkt->isWrite()) { 46211051Sandreas.hansson@arm.com // complete miss on store conditional... just give up now 46311051Sandreas.hansson@arm.com pkt->req->setExtraData(0); 46411051Sandreas.hansson@arm.com return true; 46511051Sandreas.hansson@arm.com } 46611051Sandreas.hansson@arm.com 46711051Sandreas.hansson@arm.com return false; 46811051Sandreas.hansson@arm.com} 46911051Sandreas.hansson@arm.com 47011051Sandreas.hansson@arm.comvoid 47111051Sandreas.hansson@arm.comCache::doWritebacks(PacketList& writebacks, Tick forward_time) 47211051Sandreas.hansson@arm.com{ 47311051Sandreas.hansson@arm.com while (!writebacks.empty()) { 47411051Sandreas.hansson@arm.com PacketPtr wbPkt = writebacks.front(); 47511051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying writebacks to 47611051Sandreas.hansson@arm.com // write buffer. Call isCachedAbove for both Writebacks and 47711051Sandreas.hansson@arm.com // CleanEvicts. If isCachedAbove returns true we set BLOCK_CACHED flag 47811051Sandreas.hansson@arm.com // in Writebacks and discard CleanEvicts. 47911051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) { 48011051Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::CleanEvict) { 48111051Sandreas.hansson@arm.com // Delete CleanEvict because cached copies exist above. The 48211051Sandreas.hansson@arm.com // packet destructor will delete the request object because 48311051Sandreas.hansson@arm.com // this is a non-snoop request packet which does not require a 48411051Sandreas.hansson@arm.com // response. 48511051Sandreas.hansson@arm.com delete wbPkt; 48611199Sandreas.hansson@arm.com } else if (wbPkt->cmd == MemCmd::WritebackClean) { 48711199Sandreas.hansson@arm.com // clean writeback, do not send since the block is 48811199Sandreas.hansson@arm.com // still cached above 48911199Sandreas.hansson@arm.com assert(writebackClean); 49011199Sandreas.hansson@arm.com delete wbPkt; 49111051Sandreas.hansson@arm.com } else { 49211199Sandreas.hansson@arm.com assert(wbPkt->cmd == MemCmd::WritebackDirty); 49311051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag in Writeback and send below, so that 49411051Sandreas.hansson@arm.com // the Writeback does not reset the bit corresponding to this 49511051Sandreas.hansson@arm.com // address in the snoop filter below. 49611051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 49711051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 49811051Sandreas.hansson@arm.com } 49911051Sandreas.hansson@arm.com } else { 50011051Sandreas.hansson@arm.com // If the block is not cached above, send packet below. Both 50111051Sandreas.hansson@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 50211051Sandreas.hansson@arm.com // reset the bit corresponding to this address in the snoop filter 50311051Sandreas.hansson@arm.com // below. 50411051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 50511051Sandreas.hansson@arm.com } 50611051Sandreas.hansson@arm.com writebacks.pop_front(); 50711051Sandreas.hansson@arm.com } 50811051Sandreas.hansson@arm.com} 50911051Sandreas.hansson@arm.com 51011130Sali.jafri@arm.comvoid 51111130Sali.jafri@arm.comCache::doWritebacksAtomic(PacketList& writebacks) 51211130Sali.jafri@arm.com{ 51311130Sali.jafri@arm.com while (!writebacks.empty()) { 51411130Sali.jafri@arm.com PacketPtr wbPkt = writebacks.front(); 51511130Sali.jafri@arm.com // Call isCachedAbove for both Writebacks and CleanEvicts. If 51611130Sali.jafri@arm.com // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks 51711130Sali.jafri@arm.com // and discard CleanEvicts. 51811130Sali.jafri@arm.com if (isCachedAbove(wbPkt, false)) { 51911199Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::WritebackDirty) { 52011130Sali.jafri@arm.com // Set BLOCK_CACHED flag in Writeback and send below, 52111130Sali.jafri@arm.com // so that the Writeback does not reset the bit 52211130Sali.jafri@arm.com // corresponding to this address in the snoop filter 52311130Sali.jafri@arm.com // below. We can discard CleanEvicts because cached 52411130Sali.jafri@arm.com // copies exist above. Atomic mode isCachedAbove 52511130Sali.jafri@arm.com // modifies packet to set BLOCK_CACHED flag 52611130Sali.jafri@arm.com memSidePort->sendAtomic(wbPkt); 52711130Sali.jafri@arm.com } 52811130Sali.jafri@arm.com } else { 52911130Sali.jafri@arm.com // If the block is not cached above, send packet below. Both 53011130Sali.jafri@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 53111130Sali.jafri@arm.com // reset the bit corresponding to this address in the snoop filter 53211130Sali.jafri@arm.com // below. 53311130Sali.jafri@arm.com memSidePort->sendAtomic(wbPkt); 53411130Sali.jafri@arm.com } 53511130Sali.jafri@arm.com writebacks.pop_front(); 53611130Sali.jafri@arm.com // In case of CleanEvicts, the packet destructor will delete the 53711130Sali.jafri@arm.com // request object because this is a non-snoop request packet which 53811130Sali.jafri@arm.com // does not require a response. 53911130Sali.jafri@arm.com delete wbPkt; 54011130Sali.jafri@arm.com } 54111130Sali.jafri@arm.com} 54211130Sali.jafri@arm.com 54311051Sandreas.hansson@arm.com 54411051Sandreas.hansson@arm.comvoid 54511051Sandreas.hansson@arm.comCache::recvTimingSnoopResp(PacketPtr pkt) 54611051Sandreas.hansson@arm.com{ 54711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 54811051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 54911051Sandreas.hansson@arm.com 55011051Sandreas.hansson@arm.com assert(pkt->isResponse()); 55111051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 55211051Sandreas.hansson@arm.com 55311276Sandreas.hansson@arm.com // determine if the response is from a snoop request we created 55411276Sandreas.hansson@arm.com // (in which case it should be in the outstandingSnoop), or if we 55511276Sandreas.hansson@arm.com // merely forwarded someone else's snoop request 55611276Sandreas.hansson@arm.com const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) == 55711276Sandreas.hansson@arm.com outstandingSnoop.end(); 55811276Sandreas.hansson@arm.com 55911276Sandreas.hansson@arm.com if (!forwardAsSnoop) { 56011276Sandreas.hansson@arm.com // the packet came from this cache, so sink it here and do not 56111276Sandreas.hansson@arm.com // forward it 56211051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::HardPFResp); 56311276Sandreas.hansson@arm.com 56411276Sandreas.hansson@arm.com outstandingSnoop.erase(pkt->req); 56511276Sandreas.hansson@arm.com 56611276Sandreas.hansson@arm.com DPRINTF(Cache, "Got prefetch response from above for addr " 56711276Sandreas.hansson@arm.com "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 56811051Sandreas.hansson@arm.com recvTimingResp(pkt); 56911051Sandreas.hansson@arm.com return; 57011051Sandreas.hansson@arm.com } 57111051Sandreas.hansson@arm.com 57211051Sandreas.hansson@arm.com // forwardLatency is set here because there is a response from an 57311051Sandreas.hansson@arm.com // upper level cache. 57411051Sandreas.hansson@arm.com // To pay the delay that occurs if the packet comes from the bus, 57511051Sandreas.hansson@arm.com // we charge also headerDelay. 57611051Sandreas.hansson@arm.com Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay; 57711051Sandreas.hansson@arm.com // Reset the timing of the packet. 57811051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 57911051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, snoop_resp_time); 58011051Sandreas.hansson@arm.com} 58111051Sandreas.hansson@arm.com 58211051Sandreas.hansson@arm.comvoid 58311051Sandreas.hansson@arm.comCache::promoteWholeLineWrites(PacketPtr pkt) 58411051Sandreas.hansson@arm.com{ 58511051Sandreas.hansson@arm.com // Cache line clearing instructions 58611051Sandreas.hansson@arm.com if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) && 58711051Sandreas.hansson@arm.com (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) { 58811051Sandreas.hansson@arm.com pkt->cmd = MemCmd::WriteLineReq; 58911051Sandreas.hansson@arm.com DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n"); 59011051Sandreas.hansson@arm.com } 59111051Sandreas.hansson@arm.com} 59211051Sandreas.hansson@arm.com 59311051Sandreas.hansson@arm.combool 59411051Sandreas.hansson@arm.comCache::recvTimingReq(PacketPtr pkt) 59511051Sandreas.hansson@arm.com{ 59611051Sandreas.hansson@arm.com DPRINTF(CacheTags, "%s tags: %s\n", __func__, tags->print()); 59711051Sandreas.hansson@arm.com 59811051Sandreas.hansson@arm.com assert(pkt->isRequest()); 59911051Sandreas.hansson@arm.com 60011051Sandreas.hansson@arm.com // Just forward the packet if caches are disabled. 60111051Sandreas.hansson@arm.com if (system->bypassCaches()) { 60211051Sandreas.hansson@arm.com // @todo This should really enqueue the packet rather 60311051Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt); 60411051Sandreas.hansson@arm.com assert(success); 60511051Sandreas.hansson@arm.com return true; 60611051Sandreas.hansson@arm.com } 60711051Sandreas.hansson@arm.com 60811051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 60911051Sandreas.hansson@arm.com 61011051Sandreas.hansson@arm.com if (pkt->memInhibitAsserted()) { 61111051Sandreas.hansson@arm.com // a cache above us (but not where the packet came from) is 61211051Sandreas.hansson@arm.com // responding to the request 61311051Sandreas.hansson@arm.com DPRINTF(Cache, "mem inhibited on addr %#llx (%s): not responding\n", 61411051Sandreas.hansson@arm.com pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 61511051Sandreas.hansson@arm.com 61611051Sandreas.hansson@arm.com // if the packet needs exclusive, and the cache that has 61711051Sandreas.hansson@arm.com // promised to respond (setting the inhibit flag) is not 61811051Sandreas.hansson@arm.com // providing exclusive (it is in O vs M state), we know that 61911051Sandreas.hansson@arm.com // there may be other shared copies in the system; go out and 62011051Sandreas.hansson@arm.com // invalidate them all 62111051Sandreas.hansson@arm.com if (pkt->needsExclusive() && !pkt->isSupplyExclusive()) { 62211051Sandreas.hansson@arm.com // create a downstream express snoop with cleared packet 62311051Sandreas.hansson@arm.com // flags, there is no need to allocate any data as the 62411051Sandreas.hansson@arm.com // packet is merely used to co-ordinate state transitions 62511051Sandreas.hansson@arm.com Packet *snoop_pkt = new Packet(pkt, true, false); 62611051Sandreas.hansson@arm.com 62711051Sandreas.hansson@arm.com // also reset the bus time that the original packet has 62811051Sandreas.hansson@arm.com // not yet paid for 62911051Sandreas.hansson@arm.com snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0; 63011051Sandreas.hansson@arm.com 63111051Sandreas.hansson@arm.com // make this an instantaneous express snoop, and let the 63211051Sandreas.hansson@arm.com // other caches in the system know that the packet is 63311051Sandreas.hansson@arm.com // inhibited, because we have found the authorative copy 63411051Sandreas.hansson@arm.com // (O) that will supply the right data 63511051Sandreas.hansson@arm.com snoop_pkt->setExpressSnoop(); 63611051Sandreas.hansson@arm.com snoop_pkt->assertMemInhibit(); 63711051Sandreas.hansson@arm.com 63811051Sandreas.hansson@arm.com // this express snoop travels towards the memory, and at 63911051Sandreas.hansson@arm.com // every crossbar it is snooped upwards thus reaching 64011051Sandreas.hansson@arm.com // every cache in the system 64111051Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(snoop_pkt); 64211051Sandreas.hansson@arm.com // express snoops always succeed 64311051Sandreas.hansson@arm.com assert(success); 64411051Sandreas.hansson@arm.com 64511051Sandreas.hansson@arm.com // main memory will delete the packet 64611051Sandreas.hansson@arm.com } 64711051Sandreas.hansson@arm.com 64811190Sandreas.hansson@arm.com // queue for deletion, as the sending cache is still relying 64911190Sandreas.hansson@arm.com // on the packet 65011190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 65111051Sandreas.hansson@arm.com 65211051Sandreas.hansson@arm.com // no need to take any action in this particular cache as the 65311051Sandreas.hansson@arm.com // caches along the path to memory are allowed to keep lines 65411051Sandreas.hansson@arm.com // in a shared state, and a cache above us already committed 65511051Sandreas.hansson@arm.com // to responding 65611051Sandreas.hansson@arm.com return true; 65711051Sandreas.hansson@arm.com } 65811051Sandreas.hansson@arm.com 65911051Sandreas.hansson@arm.com // anything that is merely forwarded pays for the forward latency and 66011051Sandreas.hansson@arm.com // the delay provided by the crossbar 66111051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 66211051Sandreas.hansson@arm.com 66311051Sandreas.hansson@arm.com // We use lookupLatency here because it is used to specify the latency 66411051Sandreas.hansson@arm.com // to access. 66511051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 66611051Sandreas.hansson@arm.com CacheBlk *blk = NULL; 66711051Sandreas.hansson@arm.com bool satisfied = false; 66811051Sandreas.hansson@arm.com { 66911051Sandreas.hansson@arm.com PacketList writebacks; 67011051Sandreas.hansson@arm.com // Note that lat is passed by reference here. The function 67111051Sandreas.hansson@arm.com // access() calls accessBlock() which can modify lat value. 67211051Sandreas.hansson@arm.com satisfied = access(pkt, blk, lat, writebacks); 67311051Sandreas.hansson@arm.com 67411051Sandreas.hansson@arm.com // copy writebacks to write buffer here to ensure they logically 67511051Sandreas.hansson@arm.com // proceed anything happening below 67611051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 67711051Sandreas.hansson@arm.com } 67811051Sandreas.hansson@arm.com 67911051Sandreas.hansson@arm.com // Here we charge the headerDelay that takes into account the latencies 68011051Sandreas.hansson@arm.com // of the bus, if the packet comes from it. 68111051Sandreas.hansson@arm.com // The latency charged it is just lat that is the value of lookupLatency 68211051Sandreas.hansson@arm.com // modified by access() function, or if not just lookupLatency. 68311051Sandreas.hansson@arm.com // In case of a hit we are neglecting response latency. 68411051Sandreas.hansson@arm.com // In case of a miss we are neglecting forward latency. 68511051Sandreas.hansson@arm.com Tick request_time = clockEdge(lat) + pkt->headerDelay; 68611051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 68711051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 68811051Sandreas.hansson@arm.com 68911051Sandreas.hansson@arm.com // track time of availability of next prefetch, if any 69011051Sandreas.hansson@arm.com Tick next_pf_time = MaxTick; 69111051Sandreas.hansson@arm.com 69211051Sandreas.hansson@arm.com bool needsResponse = pkt->needsResponse(); 69311051Sandreas.hansson@arm.com 69411051Sandreas.hansson@arm.com if (satisfied) { 69511051Sandreas.hansson@arm.com // should never be satisfying an uncacheable access as we 69611051Sandreas.hansson@arm.com // flush and invalidate any existing block as part of the 69711051Sandreas.hansson@arm.com // lookup 69811051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 69911051Sandreas.hansson@arm.com 70011051Sandreas.hansson@arm.com // hit (for all other request types) 70111051Sandreas.hansson@arm.com 70211051Sandreas.hansson@arm.com if (prefetcher && (prefetchOnAccess || (blk && blk->wasPrefetched()))) { 70311051Sandreas.hansson@arm.com if (blk) 70411051Sandreas.hansson@arm.com blk->status &= ~BlkHWPrefetched; 70511051Sandreas.hansson@arm.com 70611051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 70711051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 70811051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 70911051Sandreas.hansson@arm.com } 71011051Sandreas.hansson@arm.com 71111051Sandreas.hansson@arm.com if (needsResponse) { 71211051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 71311051Sandreas.hansson@arm.com // @todo: Make someone pay for this 71411051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 71511051Sandreas.hansson@arm.com 71611051Sandreas.hansson@arm.com // In this case we are considering request_time that takes 71711051Sandreas.hansson@arm.com // into account the delay of the xbar, if any, and just 71811051Sandreas.hansson@arm.com // lat, neglecting responseLatency, modelling hit latency 71911051Sandreas.hansson@arm.com // just as lookupLatency or or the value of lat overriden 72011051Sandreas.hansson@arm.com // by access(), that calls accessBlock() function. 72111194Sali.jafri@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 72211051Sandreas.hansson@arm.com } else { 72311199Sandreas.hansson@arm.com DPRINTF(Cache, "%s satisfied %s addr %#llx, no response needed\n", 72411199Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), 72511199Sandreas.hansson@arm.com pkt->getSize()); 72611199Sandreas.hansson@arm.com 72711190Sandreas.hansson@arm.com // queue the packet for deletion, as the sending cache is 72811190Sandreas.hansson@arm.com // still relying on it; if the block is found in access(), 72911190Sandreas.hansson@arm.com // CleanEvict and Writeback messages will be deleted 73011190Sandreas.hansson@arm.com // here as well 73111190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 73211051Sandreas.hansson@arm.com } 73311051Sandreas.hansson@arm.com } else { 73411051Sandreas.hansson@arm.com // miss 73511051Sandreas.hansson@arm.com 73611051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 73711051Sandreas.hansson@arm.com 73811051Sandreas.hansson@arm.com // ignore any existing MSHR if we are dealing with an 73911051Sandreas.hansson@arm.com // uncacheable request 74011051Sandreas.hansson@arm.com MSHR *mshr = pkt->req->isUncacheable() ? nullptr : 74111051Sandreas.hansson@arm.com mshrQueue.findMatch(blk_addr, pkt->isSecure()); 74211051Sandreas.hansson@arm.com 74311051Sandreas.hansson@arm.com // Software prefetch handling: 74411051Sandreas.hansson@arm.com // To keep the core from waiting on data it won't look at 74511051Sandreas.hansson@arm.com // anyway, send back a response with dummy data. Miss handling 74611051Sandreas.hansson@arm.com // will continue asynchronously. Unfortunately, the core will 74711051Sandreas.hansson@arm.com // insist upon freeing original Packet/Request, so we have to 74811051Sandreas.hansson@arm.com // create a new pair with a different lifecycle. Note that this 74911051Sandreas.hansson@arm.com // processing happens before any MSHR munging on the behalf of 75011051Sandreas.hansson@arm.com // this request because this new Request will be the one stored 75111051Sandreas.hansson@arm.com // into the MSHRs, not the original. 75211051Sandreas.hansson@arm.com if (pkt->cmd.isSWPrefetch()) { 75311051Sandreas.hansson@arm.com assert(needsResponse); 75411051Sandreas.hansson@arm.com assert(pkt->req->hasPaddr()); 75511051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 75611051Sandreas.hansson@arm.com 75711051Sandreas.hansson@arm.com // There's no reason to add a prefetch as an additional target 75811051Sandreas.hansson@arm.com // to an existing MSHR. If an outstanding request is already 75911051Sandreas.hansson@arm.com // in progress, there is nothing for the prefetch to do. 76011051Sandreas.hansson@arm.com // If this is the case, we don't even create a request at all. 76111051Sandreas.hansson@arm.com PacketPtr pf = nullptr; 76211051Sandreas.hansson@arm.com 76311051Sandreas.hansson@arm.com if (!mshr) { 76411051Sandreas.hansson@arm.com // copy the request and create a new SoftPFReq packet 76511051Sandreas.hansson@arm.com RequestPtr req = new Request(pkt->req->getPaddr(), 76611051Sandreas.hansson@arm.com pkt->req->getSize(), 76711051Sandreas.hansson@arm.com pkt->req->getFlags(), 76811051Sandreas.hansson@arm.com pkt->req->masterId()); 76911051Sandreas.hansson@arm.com pf = new Packet(req, pkt->cmd); 77011051Sandreas.hansson@arm.com pf->allocate(); 77111051Sandreas.hansson@arm.com assert(pf->getAddr() == pkt->getAddr()); 77211051Sandreas.hansson@arm.com assert(pf->getSize() == pkt->getSize()); 77311051Sandreas.hansson@arm.com } 77411051Sandreas.hansson@arm.com 77511051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 77611051Sandreas.hansson@arm.com // for debugging, set all the bits in the response data 77711051Sandreas.hansson@arm.com // (also keeps valgrind from complaining when debugging settings 77811051Sandreas.hansson@arm.com // print out instruction results) 77911051Sandreas.hansson@arm.com std::memset(pkt->getPtr<uint8_t>(), 0xFF, pkt->getSize()); 78011051Sandreas.hansson@arm.com // request_time is used here, taking into account lat and the delay 78111051Sandreas.hansson@arm.com // charged if the packet comes from the xbar. 78211194Sali.jafri@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 78311051Sandreas.hansson@arm.com 78411051Sandreas.hansson@arm.com // If an outstanding request is in progress (we found an 78511051Sandreas.hansson@arm.com // MSHR) this is set to null 78611051Sandreas.hansson@arm.com pkt = pf; 78711051Sandreas.hansson@arm.com } 78811051Sandreas.hansson@arm.com 78911051Sandreas.hansson@arm.com if (mshr) { 79011051Sandreas.hansson@arm.com /// MSHR hit 79111051Sandreas.hansson@arm.com /// @note writebacks will be checked in getNextMSHR() 79211051Sandreas.hansson@arm.com /// for any conflicting requests to the same block 79311051Sandreas.hansson@arm.com 79411051Sandreas.hansson@arm.com //@todo remove hw_pf here 79511051Sandreas.hansson@arm.com 79611051Sandreas.hansson@arm.com // Coalesce unless it was a software prefetch (see above). 79711051Sandreas.hansson@arm.com if (pkt) { 79811199Sandreas.hansson@arm.com assert(!pkt->isWriteback()); 79911199Sandreas.hansson@arm.com // CleanEvicts corresponding to blocks which have 80011199Sandreas.hansson@arm.com // outstanding requests in MSHRs are simply sunk here 80111051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::CleanEvict) { 80211190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 80311051Sandreas.hansson@arm.com } else { 80411051Sandreas.hansson@arm.com DPRINTF(Cache, "%s coalescing MSHR for %s addr %#llx size %d\n", 80511051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), 80611051Sandreas.hansson@arm.com pkt->getSize()); 80711051Sandreas.hansson@arm.com 80811051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 80911051Sandreas.hansson@arm.com mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 81011051Sandreas.hansson@arm.com if (mshr->threadNum != 0/*pkt->req->threadId()*/) { 81111051Sandreas.hansson@arm.com mshr->threadNum = -1; 81211051Sandreas.hansson@arm.com } 81311051Sandreas.hansson@arm.com // We use forward_time here because it is the same 81411051Sandreas.hansson@arm.com // considering new targets. We have multiple 81511051Sandreas.hansson@arm.com // requests for the same address here. It 81611051Sandreas.hansson@arm.com // specifies the latency to allocate an internal 81711051Sandreas.hansson@arm.com // buffer and to schedule an event to the queued 81811051Sandreas.hansson@arm.com // port and also takes into account the additional 81911051Sandreas.hansson@arm.com // delay of the xbar. 82011197Sandreas.hansson@arm.com mshr->allocateTarget(pkt, forward_time, order++, 82111197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 82211051Sandreas.hansson@arm.com if (mshr->getNumTargets() == numTarget) { 82311051Sandreas.hansson@arm.com noTargetMSHR = mshr; 82411051Sandreas.hansson@arm.com setBlocked(Blocked_NoTargets); 82511051Sandreas.hansson@arm.com // need to be careful with this... if this mshr isn't 82611051Sandreas.hansson@arm.com // ready yet (i.e. time > curTick()), we don't want to 82711051Sandreas.hansson@arm.com // move it ahead of mshrs that are ready 82811051Sandreas.hansson@arm.com // mshrQueue.moveToFront(mshr); 82911051Sandreas.hansson@arm.com } 83011051Sandreas.hansson@arm.com } 83111051Sandreas.hansson@arm.com // We should call the prefetcher reguardless if the request is 83211051Sandreas.hansson@arm.com // satisfied or not, reguardless if the request is in the MSHR or 83311051Sandreas.hansson@arm.com // not. The request could be a ReadReq hit, but still not 83411051Sandreas.hansson@arm.com // satisfied (potentially because of a prior write to the same 83511051Sandreas.hansson@arm.com // cache line. So, even when not satisfied, tehre is an MSHR 83611051Sandreas.hansson@arm.com // already allocated for this, we need to let the prefetcher know 83711051Sandreas.hansson@arm.com // about the request 83811051Sandreas.hansson@arm.com if (prefetcher) { 83911051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 84011051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 84111051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 84211051Sandreas.hansson@arm.com } 84311051Sandreas.hansson@arm.com } 84411051Sandreas.hansson@arm.com } else { 84511051Sandreas.hansson@arm.com // no MSHR 84611051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 84711051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 84811051Sandreas.hansson@arm.com mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++; 84911051Sandreas.hansson@arm.com } else { 85011051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 85111051Sandreas.hansson@arm.com } 85211051Sandreas.hansson@arm.com 85311199Sandreas.hansson@arm.com if (pkt->isEviction() || 85411051Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 85511051Sandreas.hansson@arm.com // We use forward_time here because there is an 85611051Sandreas.hansson@arm.com // uncached memory write, forwarded to WriteBuffer. 85711051Sandreas.hansson@arm.com allocateWriteBuffer(pkt, forward_time); 85811051Sandreas.hansson@arm.com } else { 85911051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 86011051Sandreas.hansson@arm.com // should have flushed and have no valid block 86111051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 86211051Sandreas.hansson@arm.com 86311051Sandreas.hansson@arm.com // If we have a write miss to a valid block, we 86411051Sandreas.hansson@arm.com // need to mark the block non-readable. Otherwise 86511051Sandreas.hansson@arm.com // if we allow reads while there's an outstanding 86611051Sandreas.hansson@arm.com // write miss, the read could return stale data 86711051Sandreas.hansson@arm.com // out of the cache block... a more aggressive 86811051Sandreas.hansson@arm.com // system could detect the overlap (if any) and 86911051Sandreas.hansson@arm.com // forward data out of the MSHRs, but we don't do 87011051Sandreas.hansson@arm.com // that yet. Note that we do need to leave the 87111051Sandreas.hansson@arm.com // block valid so that it stays in the cache, in 87211051Sandreas.hansson@arm.com // case we get an upgrade response (and hence no 87311051Sandreas.hansson@arm.com // new data) when the write miss completes. 87411051Sandreas.hansson@arm.com // As long as CPUs do proper store/load forwarding 87511051Sandreas.hansson@arm.com // internally, and have a sufficiently weak memory 87611051Sandreas.hansson@arm.com // model, this is probably unnecessary, but at some 87711051Sandreas.hansson@arm.com // point it must have seemed like we needed it... 87811051Sandreas.hansson@arm.com assert(pkt->needsExclusive()); 87911051Sandreas.hansson@arm.com assert(!blk->isWritable()); 88011051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 88111051Sandreas.hansson@arm.com } 88211051Sandreas.hansson@arm.com // Here we are using forward_time, modelling the latency of 88311051Sandreas.hansson@arm.com // a miss (outbound) just as forwardLatency, neglecting the 88411051Sandreas.hansson@arm.com // lookupLatency component. 88511051Sandreas.hansson@arm.com allocateMissBuffer(pkt, forward_time); 88611051Sandreas.hansson@arm.com } 88711051Sandreas.hansson@arm.com 88811051Sandreas.hansson@arm.com if (prefetcher) { 88911051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 89011051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 89111051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 89211051Sandreas.hansson@arm.com } 89311051Sandreas.hansson@arm.com } 89411051Sandreas.hansson@arm.com } 89511051Sandreas.hansson@arm.com 89611051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 89711051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 89811051Sandreas.hansson@arm.com 89911051Sandreas.hansson@arm.com return true; 90011051Sandreas.hansson@arm.com} 90111051Sandreas.hansson@arm.com 90211051Sandreas.hansson@arm.com 90311051Sandreas.hansson@arm.com// See comment in cache.hh. 90411051Sandreas.hansson@arm.comPacketPtr 90511051Sandreas.hansson@arm.comCache::getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk, 90611051Sandreas.hansson@arm.com bool needsExclusive) const 90711051Sandreas.hansson@arm.com{ 90811051Sandreas.hansson@arm.com bool blkValid = blk && blk->isValid(); 90911051Sandreas.hansson@arm.com 91011051Sandreas.hansson@arm.com if (cpu_pkt->req->isUncacheable()) { 91111051Sandreas.hansson@arm.com // note that at the point we see the uncacheable request we 91211051Sandreas.hansson@arm.com // flush any block, but there could be an outstanding MSHR, 91311051Sandreas.hansson@arm.com // and the cache could have filled again before we actually 91411051Sandreas.hansson@arm.com // send out the forwarded uncacheable request (blk could thus 91511051Sandreas.hansson@arm.com // be non-null) 91611051Sandreas.hansson@arm.com return NULL; 91711051Sandreas.hansson@arm.com } 91811051Sandreas.hansson@arm.com 91911051Sandreas.hansson@arm.com if (!blkValid && 92011051Sandreas.hansson@arm.com (cpu_pkt->isUpgrade() || 92111199Sandreas.hansson@arm.com cpu_pkt->isEviction())) { 92211051Sandreas.hansson@arm.com // Writebacks that weren't allocated in access() and upgrades 92311051Sandreas.hansson@arm.com // from upper-level caches that missed completely just go 92411051Sandreas.hansson@arm.com // through. 92511051Sandreas.hansson@arm.com return NULL; 92611051Sandreas.hansson@arm.com } 92711051Sandreas.hansson@arm.com 92811051Sandreas.hansson@arm.com assert(cpu_pkt->needsResponse()); 92911051Sandreas.hansson@arm.com 93011051Sandreas.hansson@arm.com MemCmd cmd; 93111051Sandreas.hansson@arm.com // @TODO make useUpgrades a parameter. 93211051Sandreas.hansson@arm.com // Note that ownership protocols require upgrade, otherwise a 93311051Sandreas.hansson@arm.com // write miss on a shared owned block will generate a ReadExcl, 93411051Sandreas.hansson@arm.com // which will clobber the owned copy. 93511051Sandreas.hansson@arm.com const bool useUpgrades = true; 93611051Sandreas.hansson@arm.com if (blkValid && useUpgrades) { 93711051Sandreas.hansson@arm.com // only reason to be here is that blk is shared 93811051Sandreas.hansson@arm.com // (read-only) and we need exclusive 93911051Sandreas.hansson@arm.com assert(needsExclusive); 94011051Sandreas.hansson@arm.com assert(!blk->isWritable()); 94111051Sandreas.hansson@arm.com cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq; 94211051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq || 94311051Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::StoreCondFailReq) { 94411051Sandreas.hansson@arm.com // Even though this SC will fail, we still need to send out the 94511051Sandreas.hansson@arm.com // request and get the data to supply it to other snoopers in the case 94611051Sandreas.hansson@arm.com // where the determination the StoreCond fails is delayed due to 94711051Sandreas.hansson@arm.com // all caches not being on the same local bus. 94811051Sandreas.hansson@arm.com cmd = MemCmd::SCUpgradeFailReq; 94911051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::WriteLineReq) { 95011051Sandreas.hansson@arm.com // forward as invalidate to all other caches, this gives us 95111051Sandreas.hansson@arm.com // the line in exclusive state, and invalidates all other 95211051Sandreas.hansson@arm.com // copies 95311051Sandreas.hansson@arm.com cmd = MemCmd::InvalidateReq; 95411051Sandreas.hansson@arm.com } else { 95511051Sandreas.hansson@arm.com // block is invalid 95611051Sandreas.hansson@arm.com cmd = needsExclusive ? MemCmd::ReadExReq : 95711051Sandreas.hansson@arm.com (isReadOnly ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq); 95811051Sandreas.hansson@arm.com } 95911051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize); 96011051Sandreas.hansson@arm.com 96111051Sandreas.hansson@arm.com // if there are sharers in the upper levels, pass that info downstream 96211051Sandreas.hansson@arm.com if (cpu_pkt->sharedAsserted()) { 96311051Sandreas.hansson@arm.com // note that cpu_pkt may have spent a considerable time in the 96411051Sandreas.hansson@arm.com // MSHR queue and that the information could possibly be out 96511051Sandreas.hansson@arm.com // of date, however, there is no harm in conservatively 96611051Sandreas.hansson@arm.com // assuming the block is shared 96711051Sandreas.hansson@arm.com pkt->assertShared(); 96811051Sandreas.hansson@arm.com DPRINTF(Cache, "%s passing shared from %s to %s addr %#llx size %d\n", 96911051Sandreas.hansson@arm.com __func__, cpu_pkt->cmdString(), pkt->cmdString(), 97011051Sandreas.hansson@arm.com pkt->getAddr(), pkt->getSize()); 97111051Sandreas.hansson@arm.com } 97211051Sandreas.hansson@arm.com 97311051Sandreas.hansson@arm.com // the packet should be block aligned 97411051Sandreas.hansson@arm.com assert(pkt->getAddr() == blockAlign(pkt->getAddr())); 97511051Sandreas.hansson@arm.com 97611051Sandreas.hansson@arm.com pkt->allocate(); 97711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s created %s from %s for addr %#llx size %d\n", 97811051Sandreas.hansson@arm.com __func__, pkt->cmdString(), cpu_pkt->cmdString(), pkt->getAddr(), 97911051Sandreas.hansson@arm.com pkt->getSize()); 98011051Sandreas.hansson@arm.com return pkt; 98111051Sandreas.hansson@arm.com} 98211051Sandreas.hansson@arm.com 98311051Sandreas.hansson@arm.com 98411051Sandreas.hansson@arm.comTick 98511051Sandreas.hansson@arm.comCache::recvAtomic(PacketPtr pkt) 98611051Sandreas.hansson@arm.com{ 98711051Sandreas.hansson@arm.com // We are in atomic mode so we pay just for lookupLatency here. 98811051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 98911051Sandreas.hansson@arm.com // @TODO: make this a parameter 99011051Sandreas.hansson@arm.com bool last_level_cache = false; 99111051Sandreas.hansson@arm.com 99211051Sandreas.hansson@arm.com // Forward the request if the system is in cache bypass mode. 99311051Sandreas.hansson@arm.com if (system->bypassCaches()) 99411051Sandreas.hansson@arm.com return ticksToCycles(memSidePort->sendAtomic(pkt)); 99511051Sandreas.hansson@arm.com 99611051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 99711051Sandreas.hansson@arm.com 99811051Sandreas.hansson@arm.com if (pkt->memInhibitAsserted()) { 99911051Sandreas.hansson@arm.com // have to invalidate ourselves and any lower caches even if 100011051Sandreas.hansson@arm.com // upper cache will be responding 100111051Sandreas.hansson@arm.com if (pkt->isInvalidate()) { 100211051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 100311051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 100411051Sandreas.hansson@arm.com tags->invalidate(blk); 100511051Sandreas.hansson@arm.com blk->invalidate(); 100611051Sandreas.hansson@arm.com DPRINTF(Cache, "rcvd mem-inhibited %s on %#llx (%s):" 100711051Sandreas.hansson@arm.com " invalidating\n", 100811051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), 100911051Sandreas.hansson@arm.com pkt->isSecure() ? "s" : "ns"); 101011051Sandreas.hansson@arm.com } 101111051Sandreas.hansson@arm.com if (!last_level_cache) { 101211051Sandreas.hansson@arm.com DPRINTF(Cache, "forwarding mem-inhibited %s on %#llx (%s)\n", 101311051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), 101411051Sandreas.hansson@arm.com pkt->isSecure() ? "s" : "ns"); 101511051Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 101611051Sandreas.hansson@arm.com } 101711051Sandreas.hansson@arm.com } else { 101811051Sandreas.hansson@arm.com DPRINTF(Cache, "rcvd mem-inhibited %s on %#llx: not responding\n", 101911051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 102011051Sandreas.hansson@arm.com } 102111051Sandreas.hansson@arm.com 102211051Sandreas.hansson@arm.com return lat * clockPeriod(); 102311051Sandreas.hansson@arm.com } 102411051Sandreas.hansson@arm.com 102511051Sandreas.hansson@arm.com // should assert here that there are no outstanding MSHRs or 102611051Sandreas.hansson@arm.com // writebacks... that would mean that someone used an atomic 102711051Sandreas.hansson@arm.com // access in timing mode 102811051Sandreas.hansson@arm.com 102911051Sandreas.hansson@arm.com CacheBlk *blk = NULL; 103011051Sandreas.hansson@arm.com PacketList writebacks; 103111051Sandreas.hansson@arm.com bool satisfied = access(pkt, blk, lat, writebacks); 103211051Sandreas.hansson@arm.com 103311051Sandreas.hansson@arm.com // handle writebacks resulting from the access here to ensure they 103411051Sandreas.hansson@arm.com // logically proceed anything happening below 103511130Sali.jafri@arm.com doWritebacksAtomic(writebacks); 103611051Sandreas.hansson@arm.com 103711051Sandreas.hansson@arm.com if (!satisfied) { 103811051Sandreas.hansson@arm.com // MISS 103911051Sandreas.hansson@arm.com 104011051Sandreas.hansson@arm.com PacketPtr bus_pkt = getBusPacket(pkt, blk, pkt->needsExclusive()); 104111051Sandreas.hansson@arm.com 104211051Sandreas.hansson@arm.com bool is_forward = (bus_pkt == NULL); 104311051Sandreas.hansson@arm.com 104411051Sandreas.hansson@arm.com if (is_forward) { 104511051Sandreas.hansson@arm.com // just forwarding the same request to the next level 104611051Sandreas.hansson@arm.com // no local cache operation involved 104711051Sandreas.hansson@arm.com bus_pkt = pkt; 104811051Sandreas.hansson@arm.com } 104911051Sandreas.hansson@arm.com 105011051Sandreas.hansson@arm.com DPRINTF(Cache, "Sending an atomic %s for %#llx (%s)\n", 105111051Sandreas.hansson@arm.com bus_pkt->cmdString(), bus_pkt->getAddr(), 105211051Sandreas.hansson@arm.com bus_pkt->isSecure() ? "s" : "ns"); 105311051Sandreas.hansson@arm.com 105411051Sandreas.hansson@arm.com#if TRACING_ON 105511051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 105611051Sandreas.hansson@arm.com#endif 105711051Sandreas.hansson@arm.com 105811051Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt)); 105911051Sandreas.hansson@arm.com 106011051Sandreas.hansson@arm.com // We are now dealing with the response handling 106111051Sandreas.hansson@arm.com DPRINTF(Cache, "Receive response: %s for addr %#llx (%s) in state %i\n", 106211051Sandreas.hansson@arm.com bus_pkt->cmdString(), bus_pkt->getAddr(), 106311051Sandreas.hansson@arm.com bus_pkt->isSecure() ? "s" : "ns", 106411051Sandreas.hansson@arm.com old_state); 106511051Sandreas.hansson@arm.com 106611051Sandreas.hansson@arm.com // If packet was a forward, the response (if any) is already 106711051Sandreas.hansson@arm.com // in place in the bus_pkt == pkt structure, so we don't need 106811051Sandreas.hansson@arm.com // to do anything. Otherwise, use the separate bus_pkt to 106911051Sandreas.hansson@arm.com // generate response to pkt and then delete it. 107011051Sandreas.hansson@arm.com if (!is_forward) { 107111051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 107211051Sandreas.hansson@arm.com assert(bus_pkt->isResponse()); 107311051Sandreas.hansson@arm.com if (bus_pkt->isError()) { 107411051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 107511051Sandreas.hansson@arm.com pkt->copyError(bus_pkt); 107611051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::InvalidateReq) { 107711051Sandreas.hansson@arm.com if (blk) { 107811051Sandreas.hansson@arm.com // invalidate response to a cache that received 107911051Sandreas.hansson@arm.com // an invalidate request 108011051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 108111051Sandreas.hansson@arm.com } 108211051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::WriteLineReq) { 108311051Sandreas.hansson@arm.com // note the use of pkt, not bus_pkt here. 108411051Sandreas.hansson@arm.com 108511051Sandreas.hansson@arm.com // write-line request to the cache that promoted 108611051Sandreas.hansson@arm.com // the write to a whole line 108711197Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks, 108811197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 108911051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 109011051Sandreas.hansson@arm.com } else if (bus_pkt->isRead() || 109111051Sandreas.hansson@arm.com bus_pkt->cmd == MemCmd::UpgradeResp) { 109211051Sandreas.hansson@arm.com // we're updating cache state to allow us to 109311051Sandreas.hansson@arm.com // satisfy the upstream request from the cache 109411197Sandreas.hansson@arm.com blk = handleFill(bus_pkt, blk, writebacks, 109511197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 109611051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 109711051Sandreas.hansson@arm.com } else { 109811051Sandreas.hansson@arm.com // we're satisfying the upstream request without 109911051Sandreas.hansson@arm.com // modifying cache state, e.g., a write-through 110011051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 110111051Sandreas.hansson@arm.com } 110211051Sandreas.hansson@arm.com } 110311051Sandreas.hansson@arm.com delete bus_pkt; 110411051Sandreas.hansson@arm.com } 110511051Sandreas.hansson@arm.com } 110611051Sandreas.hansson@arm.com 110711051Sandreas.hansson@arm.com // Note that we don't invoke the prefetcher at all in atomic mode. 110811051Sandreas.hansson@arm.com // It's not clear how to do it properly, particularly for 110911051Sandreas.hansson@arm.com // prefetchers that aggressively generate prefetch candidates and 111011051Sandreas.hansson@arm.com // rely on bandwidth contention to throttle them; these will tend 111111051Sandreas.hansson@arm.com // to pollute the cache in atomic mode since there is no bandwidth 111211051Sandreas.hansson@arm.com // contention. If we ever do want to enable prefetching in atomic 111311051Sandreas.hansson@arm.com // mode, though, this is the place to do it... see timingAccess() 111411051Sandreas.hansson@arm.com // for an example (though we'd want to issue the prefetch(es) 111511051Sandreas.hansson@arm.com // immediately rather than calling requestMemSideBus() as we do 111611051Sandreas.hansson@arm.com // there). 111711051Sandreas.hansson@arm.com 111811197Sandreas.hansson@arm.com // do any writebacks resulting from the response handling 111911130Sali.jafri@arm.com doWritebacksAtomic(writebacks); 112011051Sandreas.hansson@arm.com 112111197Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and if so 112211197Sandreas.hansson@arm.com // clear it out, but only do so after the call to recvAtomic is 112311197Sandreas.hansson@arm.com // finished so that any downstream observers (such as a snoop 112411197Sandreas.hansson@arm.com // filter), first see the fill, and only then see the eviction 112511197Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 112611197Sandreas.hansson@arm.com // the atomic CPU calls recvAtomic for fetch and load/store 112711197Sandreas.hansson@arm.com // sequentuially, and we may already have a tempBlock 112811197Sandreas.hansson@arm.com // writeback from the fetch that we have not yet sent 112911197Sandreas.hansson@arm.com if (tempBlockWriteback) { 113011197Sandreas.hansson@arm.com // if that is the case, write the prevoius one back, and 113111197Sandreas.hansson@arm.com // do not schedule any new event 113211197Sandreas.hansson@arm.com writebackTempBlockAtomic(); 113311197Sandreas.hansson@arm.com } else { 113411197Sandreas.hansson@arm.com // the writeback/clean eviction happens after the call to 113511197Sandreas.hansson@arm.com // recvAtomic has finished (but before any successive 113611197Sandreas.hansson@arm.com // calls), so that the response handling from the fill is 113711197Sandreas.hansson@arm.com // allowed to happen first 113811197Sandreas.hansson@arm.com schedule(writebackTempBlockAtomicEvent, curTick()); 113911197Sandreas.hansson@arm.com } 114011197Sandreas.hansson@arm.com 114111199Sandreas.hansson@arm.com tempBlockWriteback = (blk->isDirty() || writebackClean) ? 114211199Sandreas.hansson@arm.com writebackBlk(blk) : cleanEvictBlk(blk); 114311197Sandreas.hansson@arm.com blk->invalidate(); 114411197Sandreas.hansson@arm.com } 114511197Sandreas.hansson@arm.com 114611051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 114711051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 114811051Sandreas.hansson@arm.com } 114911051Sandreas.hansson@arm.com 115011051Sandreas.hansson@arm.com return lat * clockPeriod(); 115111051Sandreas.hansson@arm.com} 115211051Sandreas.hansson@arm.com 115311051Sandreas.hansson@arm.com 115411051Sandreas.hansson@arm.comvoid 115511051Sandreas.hansson@arm.comCache::functionalAccess(PacketPtr pkt, bool fromCpuSide) 115611051Sandreas.hansson@arm.com{ 115711051Sandreas.hansson@arm.com if (system->bypassCaches()) { 115811051Sandreas.hansson@arm.com // Packets from the memory side are snoop request and 115911051Sandreas.hansson@arm.com // shouldn't happen in bypass mode. 116011051Sandreas.hansson@arm.com assert(fromCpuSide); 116111051Sandreas.hansson@arm.com 116211051Sandreas.hansson@arm.com // The cache should be flushed if we are in cache bypass mode, 116311051Sandreas.hansson@arm.com // so we don't need to check if we need to update anything. 116411051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 116511051Sandreas.hansson@arm.com return; 116611051Sandreas.hansson@arm.com } 116711051Sandreas.hansson@arm.com 116811051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 116911051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 117011051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 117111051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 117211051Sandreas.hansson@arm.com 117311051Sandreas.hansson@arm.com pkt->pushLabel(name()); 117411051Sandreas.hansson@arm.com 117511051Sandreas.hansson@arm.com CacheBlkPrintWrapper cbpw(blk); 117611051Sandreas.hansson@arm.com 117711051Sandreas.hansson@arm.com // Note that just because an L2/L3 has valid data doesn't mean an 117811051Sandreas.hansson@arm.com // L1 doesn't have a more up-to-date modified copy that still 117911051Sandreas.hansson@arm.com // needs to be found. As a result we always update the request if 118011051Sandreas.hansson@arm.com // we have it, but only declare it satisfied if we are the owner. 118111051Sandreas.hansson@arm.com 118211051Sandreas.hansson@arm.com // see if we have data at all (owned or otherwise) 118311051Sandreas.hansson@arm.com bool have_data = blk && blk->isValid() 118411051Sandreas.hansson@arm.com && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize, 118511051Sandreas.hansson@arm.com blk->data); 118611051Sandreas.hansson@arm.com 118711051Sandreas.hansson@arm.com // data we have is dirty if marked as such or if valid & ownership 118811051Sandreas.hansson@arm.com // pending due to outstanding UpgradeReq 118911051Sandreas.hansson@arm.com bool have_dirty = 119011051Sandreas.hansson@arm.com have_data && (blk->isDirty() || 119111051Sandreas.hansson@arm.com (mshr && mshr->inService && mshr->isPendingDirty())); 119211051Sandreas.hansson@arm.com 119311051Sandreas.hansson@arm.com bool done = have_dirty 119411051Sandreas.hansson@arm.com || cpuSidePort->checkFunctional(pkt) 119511051Sandreas.hansson@arm.com || mshrQueue.checkFunctional(pkt, blk_addr) 119611051Sandreas.hansson@arm.com || writeBuffer.checkFunctional(pkt, blk_addr) 119711051Sandreas.hansson@arm.com || memSidePort->checkFunctional(pkt); 119811051Sandreas.hansson@arm.com 119911051Sandreas.hansson@arm.com DPRINTF(Cache, "functional %s %#llx (%s) %s%s%s\n", 120011051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), is_secure ? "s" : "ns", 120111051Sandreas.hansson@arm.com (blk && blk->isValid()) ? "valid " : "", 120211051Sandreas.hansson@arm.com have_data ? "data " : "", done ? "done " : ""); 120311051Sandreas.hansson@arm.com 120411051Sandreas.hansson@arm.com // We're leaving the cache, so pop cache->name() label 120511051Sandreas.hansson@arm.com pkt->popLabel(); 120611051Sandreas.hansson@arm.com 120711051Sandreas.hansson@arm.com if (done) { 120811051Sandreas.hansson@arm.com pkt->makeResponse(); 120911051Sandreas.hansson@arm.com } else { 121011051Sandreas.hansson@arm.com // if it came as a request from the CPU side then make sure it 121111051Sandreas.hansson@arm.com // continues towards the memory side 121211051Sandreas.hansson@arm.com if (fromCpuSide) { 121311051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 121411051Sandreas.hansson@arm.com } else if (forwardSnoops && cpuSidePort->isSnooping()) { 121511051Sandreas.hansson@arm.com // if it came from the memory side, it must be a snoop request 121611051Sandreas.hansson@arm.com // and we should only forward it if we are forwarding snoops 121711051Sandreas.hansson@arm.com cpuSidePort->sendFunctionalSnoop(pkt); 121811051Sandreas.hansson@arm.com } 121911051Sandreas.hansson@arm.com } 122011051Sandreas.hansson@arm.com} 122111051Sandreas.hansson@arm.com 122211051Sandreas.hansson@arm.com 122311051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 122411051Sandreas.hansson@arm.com// 122511051Sandreas.hansson@arm.com// Response handling: responses from the memory side 122611051Sandreas.hansson@arm.com// 122711051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 122811051Sandreas.hansson@arm.com 122911051Sandreas.hansson@arm.com 123011051Sandreas.hansson@arm.comvoid 123111051Sandreas.hansson@arm.comCache::recvTimingResp(PacketPtr pkt) 123211051Sandreas.hansson@arm.com{ 123311051Sandreas.hansson@arm.com assert(pkt->isResponse()); 123411051Sandreas.hansson@arm.com 123511051Sandreas.hansson@arm.com // all header delay should be paid for by the crossbar, unless 123611051Sandreas.hansson@arm.com // this is a prefetch response from above 123711051Sandreas.hansson@arm.com panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 123811051Sandreas.hansson@arm.com "%s saw a non-zero packet delay\n", name()); 123911051Sandreas.hansson@arm.com 124011051Sandreas.hansson@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState); 124111051Sandreas.hansson@arm.com bool is_error = pkt->isError(); 124211051Sandreas.hansson@arm.com 124311051Sandreas.hansson@arm.com assert(mshr); 124411051Sandreas.hansson@arm.com 124511051Sandreas.hansson@arm.com if (is_error) { 124611051Sandreas.hansson@arm.com DPRINTF(Cache, "Cache received packet with error for addr %#llx (%s), " 124711051Sandreas.hansson@arm.com "cmd: %s\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns", 124811051Sandreas.hansson@arm.com pkt->cmdString()); 124911051Sandreas.hansson@arm.com } 125011051Sandreas.hansson@arm.com 125111051Sandreas.hansson@arm.com DPRINTF(Cache, "Handling response %s for addr %#llx size %d (%s)\n", 125211051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize(), 125311051Sandreas.hansson@arm.com pkt->isSecure() ? "s" : "ns"); 125411051Sandreas.hansson@arm.com 125511051Sandreas.hansson@arm.com MSHRQueue *mq = mshr->queue; 125611051Sandreas.hansson@arm.com bool wasFull = mq->isFull(); 125711051Sandreas.hansson@arm.com 125811051Sandreas.hansson@arm.com if (mshr == noTargetMSHR) { 125911051Sandreas.hansson@arm.com // we always clear at least one target 126011051Sandreas.hansson@arm.com clearBlocked(Blocked_NoTargets); 126111051Sandreas.hansson@arm.com noTargetMSHR = NULL; 126211051Sandreas.hansson@arm.com } 126311051Sandreas.hansson@arm.com 126411051Sandreas.hansson@arm.com // Initial target is used just for stats 126511051Sandreas.hansson@arm.com MSHR::Target *initial_tgt = mshr->getTarget(); 126611051Sandreas.hansson@arm.com int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 126711051Sandreas.hansson@arm.com Tick miss_latency = curTick() - initial_tgt->recvTime; 126811051Sandreas.hansson@arm.com PacketList writebacks; 126911051Sandreas.hansson@arm.com // We need forward_time here because we have a call of 127011051Sandreas.hansson@arm.com // allocateWriteBuffer() that need this parameter to specify the 127111051Sandreas.hansson@arm.com // time to request the bus. In this case we use forward latency 127211051Sandreas.hansson@arm.com // because there is a writeback. We pay also here for headerDelay 127311051Sandreas.hansson@arm.com // that is charged of bus latencies if the packet comes from the 127411051Sandreas.hansson@arm.com // bus. 127511051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 127611051Sandreas.hansson@arm.com 127711051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 127811051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 127911051Sandreas.hansson@arm.com mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 128011051Sandreas.hansson@arm.com miss_latency; 128111051Sandreas.hansson@arm.com } else { 128211051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 128311051Sandreas.hansson@arm.com mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 128411051Sandreas.hansson@arm.com miss_latency; 128511051Sandreas.hansson@arm.com } 128611051Sandreas.hansson@arm.com 128711177Sandreas.hansson@arm.com // upgrade deferred targets if we got exclusive 128811177Sandreas.hansson@arm.com if (!pkt->sharedAsserted()) { 128911177Sandreas.hansson@arm.com mshr->promoteExclusive(); 129011177Sandreas.hansson@arm.com } 129111177Sandreas.hansson@arm.com 129211051Sandreas.hansson@arm.com bool is_fill = !mshr->isForward && 129311051Sandreas.hansson@arm.com (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp); 129411051Sandreas.hansson@arm.com 129511177Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 129611177Sandreas.hansson@arm.com 129711051Sandreas.hansson@arm.com if (is_fill && !is_error) { 129811051Sandreas.hansson@arm.com DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 129911051Sandreas.hansson@arm.com pkt->getAddr()); 130011051Sandreas.hansson@arm.com 130111197Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill); 130211051Sandreas.hansson@arm.com assert(blk != NULL); 130311051Sandreas.hansson@arm.com } 130411051Sandreas.hansson@arm.com 130511051Sandreas.hansson@arm.com // allow invalidation responses originating from write-line 130611051Sandreas.hansson@arm.com // requests to be discarded 130711136Sandreas.hansson@arm.com bool is_invalidate = pkt->isInvalidate(); 130811051Sandreas.hansson@arm.com 130911051Sandreas.hansson@arm.com // First offset for critical word first calculations 131011051Sandreas.hansson@arm.com int initial_offset = initial_tgt->pkt->getOffset(blkSize); 131111051Sandreas.hansson@arm.com 131211051Sandreas.hansson@arm.com while (mshr->hasTargets()) { 131311051Sandreas.hansson@arm.com MSHR::Target *target = mshr->getTarget(); 131411051Sandreas.hansson@arm.com Packet *tgt_pkt = target->pkt; 131511051Sandreas.hansson@arm.com 131611051Sandreas.hansson@arm.com switch (target->source) { 131711051Sandreas.hansson@arm.com case MSHR::Target::FromCPU: 131811051Sandreas.hansson@arm.com Tick completion_time; 131911051Sandreas.hansson@arm.com // Here we charge on completion_time the delay of the xbar if the 132011051Sandreas.hansson@arm.com // packet comes from it, charged on headerDelay. 132111051Sandreas.hansson@arm.com completion_time = pkt->headerDelay; 132211051Sandreas.hansson@arm.com 132311051Sandreas.hansson@arm.com // Software prefetch handling for cache closest to core 132411051Sandreas.hansson@arm.com if (tgt_pkt->cmd.isSWPrefetch()) { 132511051Sandreas.hansson@arm.com // a software prefetch would have already been ack'd immediately 132611051Sandreas.hansson@arm.com // with dummy data so the core would be able to retire it. 132711051Sandreas.hansson@arm.com // this request completes right here, so we deallocate it. 132811051Sandreas.hansson@arm.com delete tgt_pkt->req; 132911051Sandreas.hansson@arm.com delete tgt_pkt; 133011051Sandreas.hansson@arm.com break; // skip response 133111051Sandreas.hansson@arm.com } 133211051Sandreas.hansson@arm.com 133311051Sandreas.hansson@arm.com // unlike the other packet flows, where data is found in other 133411051Sandreas.hansson@arm.com // caches or memory and brought back, write-line requests always 133511051Sandreas.hansson@arm.com // have the data right away, so the above check for "is fill?" 133611051Sandreas.hansson@arm.com // cannot actually be determined until examining the stored MSHR 133711051Sandreas.hansson@arm.com // state. We "catch up" with that logic here, which is duplicated 133811051Sandreas.hansson@arm.com // from above. 133911051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::WriteLineReq) { 134011051Sandreas.hansson@arm.com assert(!is_error); 134111177Sandreas.hansson@arm.com // we got the block in exclusive state, so promote any 134211177Sandreas.hansson@arm.com // deferred targets if possible 134311177Sandreas.hansson@arm.com mshr->promoteExclusive(); 134411051Sandreas.hansson@arm.com // NB: we use the original packet here and not the response! 134511197Sandreas.hansson@arm.com blk = handleFill(tgt_pkt, blk, writebacks, mshr->allocOnFill); 134611051Sandreas.hansson@arm.com assert(blk != NULL); 134711051Sandreas.hansson@arm.com 134811051Sandreas.hansson@arm.com // treat as a fill, and discard the invalidation 134911051Sandreas.hansson@arm.com // response 135011051Sandreas.hansson@arm.com is_fill = true; 135111136Sandreas.hansson@arm.com is_invalidate = false; 135211051Sandreas.hansson@arm.com } 135311051Sandreas.hansson@arm.com 135411051Sandreas.hansson@arm.com if (is_fill) { 135511051Sandreas.hansson@arm.com satisfyCpuSideRequest(tgt_pkt, blk, 135611051Sandreas.hansson@arm.com true, mshr->hasPostDowngrade()); 135711051Sandreas.hansson@arm.com 135811051Sandreas.hansson@arm.com // How many bytes past the first request is this one 135911051Sandreas.hansson@arm.com int transfer_offset = 136011051Sandreas.hansson@arm.com tgt_pkt->getOffset(blkSize) - initial_offset; 136111051Sandreas.hansson@arm.com if (transfer_offset < 0) { 136211051Sandreas.hansson@arm.com transfer_offset += blkSize; 136311051Sandreas.hansson@arm.com } 136411051Sandreas.hansson@arm.com 136511051Sandreas.hansson@arm.com // If not critical word (offset) return payloadDelay. 136611051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 136711051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 136811051Sandreas.hansson@arm.com // the core. 136911051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 137011051Sandreas.hansson@arm.com (transfer_offset ? pkt->payloadDelay : 0); 137111051Sandreas.hansson@arm.com 137211051Sandreas.hansson@arm.com assert(!tgt_pkt->req->isUncacheable()); 137311051Sandreas.hansson@arm.com 137411051Sandreas.hansson@arm.com assert(tgt_pkt->req->masterId() < system->maxMasters()); 137511051Sandreas.hansson@arm.com missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] += 137611051Sandreas.hansson@arm.com completion_time - target->recvTime; 137711051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::UpgradeFailResp) { 137811051Sandreas.hansson@arm.com // failed StoreCond upgrade 137911051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::StoreCondReq || 138011051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::StoreCondFailReq || 138111051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::SCUpgradeFailReq); 138211051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 138311051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 138411051Sandreas.hansson@arm.com // the core. 138511051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 138611051Sandreas.hansson@arm.com pkt->payloadDelay; 138711051Sandreas.hansson@arm.com tgt_pkt->req->setExtraData(0); 138811051Sandreas.hansson@arm.com } else { 138911051Sandreas.hansson@arm.com // not a cache fill, just forwarding response 139011051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 139111051Sandreas.hansson@arm.com // from lower level cahces/memory to the core. 139211051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 139311051Sandreas.hansson@arm.com pkt->payloadDelay; 139411051Sandreas.hansson@arm.com if (pkt->isRead() && !is_error) { 139511051Sandreas.hansson@arm.com // sanity check 139611051Sandreas.hansson@arm.com assert(pkt->getAddr() == tgt_pkt->getAddr()); 139711051Sandreas.hansson@arm.com assert(pkt->getSize() >= tgt_pkt->getSize()); 139811051Sandreas.hansson@arm.com 139911051Sandreas.hansson@arm.com tgt_pkt->setData(pkt->getConstPtr<uint8_t>()); 140011051Sandreas.hansson@arm.com } 140111051Sandreas.hansson@arm.com } 140211051Sandreas.hansson@arm.com tgt_pkt->makeTimingResponse(); 140311051Sandreas.hansson@arm.com // if this packet is an error copy that to the new packet 140411051Sandreas.hansson@arm.com if (is_error) 140511051Sandreas.hansson@arm.com tgt_pkt->copyError(pkt); 140611051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::ReadResp && 140711136Sandreas.hansson@arm.com (is_invalidate || mshr->hasPostInvalidate())) { 140811051Sandreas.hansson@arm.com // If intermediate cache got ReadRespWithInvalidate, 140911051Sandreas.hansson@arm.com // propagate that. Response should not have 141011051Sandreas.hansson@arm.com // isInvalidate() set otherwise. 141111051Sandreas.hansson@arm.com tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate; 141211051Sandreas.hansson@arm.com DPRINTF(Cache, "%s updated cmd to %s for addr %#llx\n", 141311051Sandreas.hansson@arm.com __func__, tgt_pkt->cmdString(), tgt_pkt->getAddr()); 141411051Sandreas.hansson@arm.com } 141511051Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 141611051Sandreas.hansson@arm.com tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; 141711194Sali.jafri@arm.com cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true); 141811051Sandreas.hansson@arm.com break; 141911051Sandreas.hansson@arm.com 142011051Sandreas.hansson@arm.com case MSHR::Target::FromPrefetcher: 142111051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::HardPFReq); 142211051Sandreas.hansson@arm.com if (blk) 142311051Sandreas.hansson@arm.com blk->status |= BlkHWPrefetched; 142411051Sandreas.hansson@arm.com delete tgt_pkt->req; 142511051Sandreas.hansson@arm.com delete tgt_pkt; 142611051Sandreas.hansson@arm.com break; 142711051Sandreas.hansson@arm.com 142811051Sandreas.hansson@arm.com case MSHR::Target::FromSnoop: 142911051Sandreas.hansson@arm.com // I don't believe that a snoop can be in an error state 143011051Sandreas.hansson@arm.com assert(!is_error); 143111051Sandreas.hansson@arm.com // response to snoop request 143211051Sandreas.hansson@arm.com DPRINTF(Cache, "processing deferred snoop...\n"); 143311136Sandreas.hansson@arm.com assert(!(is_invalidate && !mshr->hasPostInvalidate())); 143411051Sandreas.hansson@arm.com handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate()); 143511051Sandreas.hansson@arm.com break; 143611051Sandreas.hansson@arm.com 143711051Sandreas.hansson@arm.com default: 143811051Sandreas.hansson@arm.com panic("Illegal target->source enum %d\n", target->source); 143911051Sandreas.hansson@arm.com } 144011051Sandreas.hansson@arm.com 144111051Sandreas.hansson@arm.com mshr->popTarget(); 144211051Sandreas.hansson@arm.com } 144311051Sandreas.hansson@arm.com 144411051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 144511051Sandreas.hansson@arm.com // an invalidate response stemming from a write line request 144611051Sandreas.hansson@arm.com // should not invalidate the block, so check if the 144711051Sandreas.hansson@arm.com // invalidation should be discarded 144811136Sandreas.hansson@arm.com if (is_invalidate || mshr->hasPostInvalidate()) { 144911197Sandreas.hansson@arm.com invalidateBlock(blk); 145011051Sandreas.hansson@arm.com } else if (mshr->hasPostDowngrade()) { 145111051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 145211051Sandreas.hansson@arm.com } 145311051Sandreas.hansson@arm.com } 145411051Sandreas.hansson@arm.com 145511051Sandreas.hansson@arm.com if (mshr->promoteDeferredTargets()) { 145611051Sandreas.hansson@arm.com // avoid later read getting stale data while write miss is 145711051Sandreas.hansson@arm.com // outstanding.. see comment in timingAccess() 145811051Sandreas.hansson@arm.com if (blk) { 145911051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 146011051Sandreas.hansson@arm.com } 146111051Sandreas.hansson@arm.com mq = mshr->queue; 146211051Sandreas.hansson@arm.com mq->markPending(mshr); 146311051Sandreas.hansson@arm.com schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 146411051Sandreas.hansson@arm.com } else { 146511051Sandreas.hansson@arm.com mq->deallocate(mshr); 146611051Sandreas.hansson@arm.com if (wasFull && !mq->isFull()) { 146711051Sandreas.hansson@arm.com clearBlocked((BlockedCause)mq->index); 146811051Sandreas.hansson@arm.com } 146911051Sandreas.hansson@arm.com 147011051Sandreas.hansson@arm.com // Request the bus for a prefetch if this deallocation freed enough 147111051Sandreas.hansson@arm.com // MSHRs for a prefetch to take place 147211051Sandreas.hansson@arm.com if (prefetcher && mq == &mshrQueue && mshrQueue.canPrefetch()) { 147311051Sandreas.hansson@arm.com Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 147411051Sandreas.hansson@arm.com clockEdge()); 147511051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 147611051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 147711051Sandreas.hansson@arm.com } 147811051Sandreas.hansson@arm.com } 147911051Sandreas.hansson@arm.com // reset the xbar additional timinig as it is now accounted for 148011051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 148111051Sandreas.hansson@arm.com 148211051Sandreas.hansson@arm.com // copy writebacks to write buffer 148311051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 148411051Sandreas.hansson@arm.com 148511051Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and then clear it out 148611051Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 148711051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying 148811051Sandreas.hansson@arm.com // Writebacks/CleanEvicts to write buffer. It specifies the latency to 148911051Sandreas.hansson@arm.com // allocate an internal buffer and to schedule an event to the 149011051Sandreas.hansson@arm.com // queued port. 149111199Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 149211051Sandreas.hansson@arm.com PacketPtr wbPkt = writebackBlk(blk); 149311051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 149411051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag if cached above. 149511051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) 149611051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 149711051Sandreas.hansson@arm.com } else { 149811051Sandreas.hansson@arm.com PacketPtr wcPkt = cleanEvictBlk(blk); 149911051Sandreas.hansson@arm.com // Check to see if block is cached above. If not allocate 150011051Sandreas.hansson@arm.com // write buffer 150111051Sandreas.hansson@arm.com if (isCachedAbove(wcPkt)) 150211051Sandreas.hansson@arm.com delete wcPkt; 150311051Sandreas.hansson@arm.com else 150411051Sandreas.hansson@arm.com allocateWriteBuffer(wcPkt, forward_time); 150511051Sandreas.hansson@arm.com } 150611051Sandreas.hansson@arm.com blk->invalidate(); 150711051Sandreas.hansson@arm.com } 150811051Sandreas.hansson@arm.com 150911051Sandreas.hansson@arm.com DPRINTF(Cache, "Leaving %s with %s for addr %#llx\n", __func__, 151011051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 151111051Sandreas.hansson@arm.com delete pkt; 151211051Sandreas.hansson@arm.com} 151311051Sandreas.hansson@arm.com 151411051Sandreas.hansson@arm.comPacketPtr 151511051Sandreas.hansson@arm.comCache::writebackBlk(CacheBlk *blk) 151611051Sandreas.hansson@arm.com{ 151711199Sandreas.hansson@arm.com chatty_assert(!isReadOnly || writebackClean, 151811199Sandreas.hansson@arm.com "Writeback from read-only cache"); 151911199Sandreas.hansson@arm.com assert(blk && blk->isValid() && (blk->isDirty() || writebackClean)); 152011051Sandreas.hansson@arm.com 152111051Sandreas.hansson@arm.com writebacks[Request::wbMasterId]++; 152211051Sandreas.hansson@arm.com 152311199Sandreas.hansson@arm.com Request *req = new Request(tags->regenerateBlkAddr(blk->tag, blk->set), 152411199Sandreas.hansson@arm.com blkSize, 0, Request::wbMasterId); 152511051Sandreas.hansson@arm.com if (blk->isSecure()) 152611199Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 152711051Sandreas.hansson@arm.com 152811199Sandreas.hansson@arm.com req->taskId(blk->task_id); 152911051Sandreas.hansson@arm.com blk->task_id= ContextSwitchTaskId::Unknown; 153011051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 153111051Sandreas.hansson@arm.com 153211199Sandreas.hansson@arm.com PacketPtr pkt = 153311199Sandreas.hansson@arm.com new Packet(req, blk->isDirty() ? 153411199Sandreas.hansson@arm.com MemCmd::WritebackDirty : MemCmd::WritebackClean); 153511199Sandreas.hansson@arm.com 153611199Sandreas.hansson@arm.com DPRINTF(Cache, "Create Writeback %#llx writable: %d, dirty: %d\n", 153711199Sandreas.hansson@arm.com pkt->getAddr(), blk->isWritable(), blk->isDirty()); 153811199Sandreas.hansson@arm.com 153911051Sandreas.hansson@arm.com if (blk->isWritable()) { 154011051Sandreas.hansson@arm.com // not asserting shared means we pass the block in modified 154111051Sandreas.hansson@arm.com // state, mark our own block non-writeable 154211051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 154311051Sandreas.hansson@arm.com } else { 154411051Sandreas.hansson@arm.com // we are in the owned state, tell the receiver 154511199Sandreas.hansson@arm.com pkt->assertShared(); 154611051Sandreas.hansson@arm.com } 154711051Sandreas.hansson@arm.com 154811199Sandreas.hansson@arm.com // make sure the block is not marked dirty 154911199Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 155011051Sandreas.hansson@arm.com 155111199Sandreas.hansson@arm.com pkt->allocate(); 155211199Sandreas.hansson@arm.com std::memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize); 155311199Sandreas.hansson@arm.com 155411199Sandreas.hansson@arm.com return pkt; 155511051Sandreas.hansson@arm.com} 155611051Sandreas.hansson@arm.com 155711051Sandreas.hansson@arm.comPacketPtr 155811051Sandreas.hansson@arm.comCache::cleanEvictBlk(CacheBlk *blk) 155911051Sandreas.hansson@arm.com{ 156011199Sandreas.hansson@arm.com assert(!writebackClean); 156111051Sandreas.hansson@arm.com assert(blk && blk->isValid() && !blk->isDirty()); 156211051Sandreas.hansson@arm.com // Creating a zero sized write, a message to the snoop filter 156311051Sandreas.hansson@arm.com Request *req = 156411051Sandreas.hansson@arm.com new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0, 156511051Sandreas.hansson@arm.com Request::wbMasterId); 156611051Sandreas.hansson@arm.com if (blk->isSecure()) 156711051Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 156811051Sandreas.hansson@arm.com 156911051Sandreas.hansson@arm.com req->taskId(blk->task_id); 157011051Sandreas.hansson@arm.com blk->task_id = ContextSwitchTaskId::Unknown; 157111051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 157211051Sandreas.hansson@arm.com 157311051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::CleanEvict); 157411051Sandreas.hansson@arm.com pkt->allocate(); 157511051Sandreas.hansson@arm.com DPRINTF(Cache, "%s%s %x Create CleanEvict\n", pkt->cmdString(), 157611051Sandreas.hansson@arm.com pkt->req->isInstFetch() ? " (ifetch)" : "", 157711051Sandreas.hansson@arm.com pkt->getAddr()); 157811051Sandreas.hansson@arm.com 157911051Sandreas.hansson@arm.com return pkt; 158011051Sandreas.hansson@arm.com} 158111051Sandreas.hansson@arm.com 158211051Sandreas.hansson@arm.comvoid 158311051Sandreas.hansson@arm.comCache::memWriteback() 158411051Sandreas.hansson@arm.com{ 158511051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::writebackVisitor); 158611051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 158711051Sandreas.hansson@arm.com} 158811051Sandreas.hansson@arm.com 158911051Sandreas.hansson@arm.comvoid 159011051Sandreas.hansson@arm.comCache::memInvalidate() 159111051Sandreas.hansson@arm.com{ 159211051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::invalidateVisitor); 159311051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 159411051Sandreas.hansson@arm.com} 159511051Sandreas.hansson@arm.com 159611051Sandreas.hansson@arm.combool 159711051Sandreas.hansson@arm.comCache::isDirty() const 159811051Sandreas.hansson@arm.com{ 159911051Sandreas.hansson@arm.com CacheBlkIsDirtyVisitor visitor; 160011051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 160111051Sandreas.hansson@arm.com 160211051Sandreas.hansson@arm.com return visitor.isDirty(); 160311051Sandreas.hansson@arm.com} 160411051Sandreas.hansson@arm.com 160511051Sandreas.hansson@arm.combool 160611051Sandreas.hansson@arm.comCache::writebackVisitor(CacheBlk &blk) 160711051Sandreas.hansson@arm.com{ 160811051Sandreas.hansson@arm.com if (blk.isDirty()) { 160911051Sandreas.hansson@arm.com assert(blk.isValid()); 161011051Sandreas.hansson@arm.com 161111051Sandreas.hansson@arm.com Request request(tags->regenerateBlkAddr(blk.tag, blk.set), 161211051Sandreas.hansson@arm.com blkSize, 0, Request::funcMasterId); 161311051Sandreas.hansson@arm.com request.taskId(blk.task_id); 161411051Sandreas.hansson@arm.com 161511051Sandreas.hansson@arm.com Packet packet(&request, MemCmd::WriteReq); 161611051Sandreas.hansson@arm.com packet.dataStatic(blk.data); 161711051Sandreas.hansson@arm.com 161811051Sandreas.hansson@arm.com memSidePort->sendFunctional(&packet); 161911051Sandreas.hansson@arm.com 162011051Sandreas.hansson@arm.com blk.status &= ~BlkDirty; 162111051Sandreas.hansson@arm.com } 162211051Sandreas.hansson@arm.com 162311051Sandreas.hansson@arm.com return true; 162411051Sandreas.hansson@arm.com} 162511051Sandreas.hansson@arm.com 162611051Sandreas.hansson@arm.combool 162711051Sandreas.hansson@arm.comCache::invalidateVisitor(CacheBlk &blk) 162811051Sandreas.hansson@arm.com{ 162911051Sandreas.hansson@arm.com 163011051Sandreas.hansson@arm.com if (blk.isDirty()) 163111051Sandreas.hansson@arm.com warn_once("Invalidating dirty cache lines. Expect things to break.\n"); 163211051Sandreas.hansson@arm.com 163311051Sandreas.hansson@arm.com if (blk.isValid()) { 163411051Sandreas.hansson@arm.com assert(!blk.isDirty()); 163511051Sandreas.hansson@arm.com tags->invalidate(&blk); 163611051Sandreas.hansson@arm.com blk.invalidate(); 163711051Sandreas.hansson@arm.com } 163811051Sandreas.hansson@arm.com 163911051Sandreas.hansson@arm.com return true; 164011051Sandreas.hansson@arm.com} 164111051Sandreas.hansson@arm.com 164211051Sandreas.hansson@arm.comCacheBlk* 164311051Sandreas.hansson@arm.comCache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks) 164411051Sandreas.hansson@arm.com{ 164511051Sandreas.hansson@arm.com CacheBlk *blk = tags->findVictim(addr); 164611051Sandreas.hansson@arm.com 164711051Sandreas.hansson@arm.com // It is valid to return NULL if there is no victim 164811051Sandreas.hansson@arm.com if (!blk) 164911051Sandreas.hansson@arm.com return nullptr; 165011051Sandreas.hansson@arm.com 165111051Sandreas.hansson@arm.com if (blk->isValid()) { 165211051Sandreas.hansson@arm.com Addr repl_addr = tags->regenerateBlkAddr(blk->tag, blk->set); 165311051Sandreas.hansson@arm.com MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure()); 165411051Sandreas.hansson@arm.com if (repl_mshr) { 165511051Sandreas.hansson@arm.com // must be an outstanding upgrade request 165611051Sandreas.hansson@arm.com // on a block we're about to replace... 165711051Sandreas.hansson@arm.com assert(!blk->isWritable() || blk->isDirty()); 165811051Sandreas.hansson@arm.com assert(repl_mshr->needsExclusive()); 165911051Sandreas.hansson@arm.com // too hard to replace block with transient state 166011051Sandreas.hansson@arm.com // allocation failed, block not inserted 166111051Sandreas.hansson@arm.com return NULL; 166211051Sandreas.hansson@arm.com } else { 166311051Sandreas.hansson@arm.com DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx (%s): %s\n", 166411051Sandreas.hansson@arm.com repl_addr, blk->isSecure() ? "s" : "ns", 166511051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", 166611051Sandreas.hansson@arm.com blk->isDirty() ? "writeback" : "clean"); 166711051Sandreas.hansson@arm.com 166811051Sandreas.hansson@arm.com // Will send up Writeback/CleanEvict snoops via isCachedAbove 166911051Sandreas.hansson@arm.com // when pushing this writeback list into the write buffer. 167011199Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 167111051Sandreas.hansson@arm.com // Save writeback packet for handling by caller 167211051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(blk)); 167311051Sandreas.hansson@arm.com } else { 167411051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(blk)); 167511051Sandreas.hansson@arm.com } 167611051Sandreas.hansson@arm.com } 167711051Sandreas.hansson@arm.com } 167811051Sandreas.hansson@arm.com 167911051Sandreas.hansson@arm.com return blk; 168011051Sandreas.hansson@arm.com} 168111051Sandreas.hansson@arm.com 168211197Sandreas.hansson@arm.comvoid 168311197Sandreas.hansson@arm.comCache::invalidateBlock(CacheBlk *blk) 168411197Sandreas.hansson@arm.com{ 168511197Sandreas.hansson@arm.com if (blk != tempBlock) 168611197Sandreas.hansson@arm.com tags->invalidate(blk); 168711197Sandreas.hansson@arm.com blk->invalidate(); 168811197Sandreas.hansson@arm.com} 168911051Sandreas.hansson@arm.com 169011051Sandreas.hansson@arm.com// Note that the reason we return a list of writebacks rather than 169111051Sandreas.hansson@arm.com// inserting them directly in the write buffer is that this function 169211051Sandreas.hansson@arm.com// is called by both atomic and timing-mode accesses, and in atomic 169311051Sandreas.hansson@arm.com// mode we don't mess with the write buffer (we just perform the 169411051Sandreas.hansson@arm.com// writebacks atomically once the original request is complete). 169511051Sandreas.hansson@arm.comCacheBlk* 169611197Sandreas.hansson@arm.comCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, 169711197Sandreas.hansson@arm.com bool allocate) 169811051Sandreas.hansson@arm.com{ 169911051Sandreas.hansson@arm.com assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq); 170011051Sandreas.hansson@arm.com Addr addr = pkt->getAddr(); 170111051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 170211051Sandreas.hansson@arm.com#if TRACING_ON 170311051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 170411051Sandreas.hansson@arm.com#endif 170511051Sandreas.hansson@arm.com 170611051Sandreas.hansson@arm.com // When handling a fill, discard any CleanEvicts for the 170711051Sandreas.hansson@arm.com // same address in write buffer. 170811051Sandreas.hansson@arm.com Addr M5_VAR_USED blk_addr = blockAlign(pkt->getAddr()); 170911051Sandreas.hansson@arm.com std::vector<MSHR *> M5_VAR_USED wbs; 171011051Sandreas.hansson@arm.com assert (!writeBuffer.findMatches(blk_addr, is_secure, wbs)); 171111051Sandreas.hansson@arm.com 171211051Sandreas.hansson@arm.com if (blk == NULL) { 171311051Sandreas.hansson@arm.com // better have read new data... 171411051Sandreas.hansson@arm.com assert(pkt->hasData()); 171511051Sandreas.hansson@arm.com 171611051Sandreas.hansson@arm.com // only read responses and write-line requests have data; 171711051Sandreas.hansson@arm.com // note that we don't write the data here for write-line - that 171811051Sandreas.hansson@arm.com // happens in the subsequent satisfyCpuSideRequest. 171911051Sandreas.hansson@arm.com assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq); 172011051Sandreas.hansson@arm.com 172111197Sandreas.hansson@arm.com // need to do a replacement if allocating, otherwise we stick 172211197Sandreas.hansson@arm.com // with the temporary storage 172311197Sandreas.hansson@arm.com blk = allocate ? allocateBlock(addr, is_secure, writebacks) : NULL; 172411197Sandreas.hansson@arm.com 172511051Sandreas.hansson@arm.com if (blk == NULL) { 172611197Sandreas.hansson@arm.com // No replaceable block or a mostly exclusive 172711197Sandreas.hansson@arm.com // cache... just use temporary storage to complete the 172811197Sandreas.hansson@arm.com // current request and then get rid of it 172911051Sandreas.hansson@arm.com assert(!tempBlock->isValid()); 173011051Sandreas.hansson@arm.com blk = tempBlock; 173111051Sandreas.hansson@arm.com tempBlock->set = tags->extractSet(addr); 173211051Sandreas.hansson@arm.com tempBlock->tag = tags->extractTag(addr); 173311051Sandreas.hansson@arm.com // @todo: set security state as well... 173411051Sandreas.hansson@arm.com DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr, 173511051Sandreas.hansson@arm.com is_secure ? "s" : "ns"); 173611051Sandreas.hansson@arm.com } else { 173711051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 173811051Sandreas.hansson@arm.com } 173911051Sandreas.hansson@arm.com 174011051Sandreas.hansson@arm.com // we should never be overwriting a valid block 174111051Sandreas.hansson@arm.com assert(!blk->isValid()); 174211051Sandreas.hansson@arm.com } else { 174311051Sandreas.hansson@arm.com // existing block... probably an upgrade 174411051Sandreas.hansson@arm.com assert(blk->tag == tags->extractTag(addr)); 174511051Sandreas.hansson@arm.com // either we're getting new data or the block should already be valid 174611051Sandreas.hansson@arm.com assert(pkt->hasData() || blk->isValid()); 174711051Sandreas.hansson@arm.com // don't clear block status... if block is already dirty we 174811051Sandreas.hansson@arm.com // don't want to lose that 174911051Sandreas.hansson@arm.com } 175011051Sandreas.hansson@arm.com 175111051Sandreas.hansson@arm.com if (is_secure) 175211051Sandreas.hansson@arm.com blk->status |= BlkSecure; 175311051Sandreas.hansson@arm.com blk->status |= BlkValid | BlkReadable; 175411051Sandreas.hansson@arm.com 175511137Sandreas.hansson@arm.com // sanity check for whole-line writes, which should always be 175611137Sandreas.hansson@arm.com // marked as writable as part of the fill, and then later marked 175711137Sandreas.hansson@arm.com // dirty as part of satisfyCpuSideRequest 175811137Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WriteLineReq) { 175911137Sandreas.hansson@arm.com assert(!pkt->sharedAsserted()); 176011137Sandreas.hansson@arm.com // at the moment other caches do not respond to the 176111137Sandreas.hansson@arm.com // invalidation requests corresponding to a whole-line write 176211137Sandreas.hansson@arm.com assert(!pkt->memInhibitAsserted()); 176311137Sandreas.hansson@arm.com } 176411137Sandreas.hansson@arm.com 176511051Sandreas.hansson@arm.com if (!pkt->sharedAsserted()) { 176611051Sandreas.hansson@arm.com // we could get non-shared responses from memory (rather than 176711051Sandreas.hansson@arm.com // a cache) even in a read-only cache, note that we set this 176811051Sandreas.hansson@arm.com // bit even for a read-only cache as we use it to represent 176911051Sandreas.hansson@arm.com // the exclusive state 177011051Sandreas.hansson@arm.com blk->status |= BlkWritable; 177111051Sandreas.hansson@arm.com 177211051Sandreas.hansson@arm.com // If we got this via cache-to-cache transfer (i.e., from a 177311051Sandreas.hansson@arm.com // cache that was an owner) and took away that owner's copy, 177411051Sandreas.hansson@arm.com // then we need to write it back. Normally this happens 177511051Sandreas.hansson@arm.com // anyway as a side effect of getting a copy to write it, but 177611051Sandreas.hansson@arm.com // there are cases (such as failed store conditionals or 177711051Sandreas.hansson@arm.com // compare-and-swaps) where we'll demand an exclusive copy but 177811051Sandreas.hansson@arm.com // end up not writing it. 177911051Sandreas.hansson@arm.com if (pkt->memInhibitAsserted()) { 178011051Sandreas.hansson@arm.com blk->status |= BlkDirty; 178111051Sandreas.hansson@arm.com 178211051Sandreas.hansson@arm.com chatty_assert(!isReadOnly, "Should never see dirty snoop response " 178311051Sandreas.hansson@arm.com "in read-only cache %s\n", name()); 178411051Sandreas.hansson@arm.com } 178511051Sandreas.hansson@arm.com } 178611051Sandreas.hansson@arm.com 178711051Sandreas.hansson@arm.com DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n", 178811051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", old_state, blk->print()); 178911051Sandreas.hansson@arm.com 179011051Sandreas.hansson@arm.com // if we got new data, copy it in (checking for a read response 179111051Sandreas.hansson@arm.com // and a response that has data is the same in the end) 179211051Sandreas.hansson@arm.com if (pkt->isRead()) { 179311051Sandreas.hansson@arm.com // sanity checks 179411051Sandreas.hansson@arm.com assert(pkt->hasData()); 179511051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 179611051Sandreas.hansson@arm.com 179711051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 179811051Sandreas.hansson@arm.com } 179911051Sandreas.hansson@arm.com // We pay for fillLatency here. 180011051Sandreas.hansson@arm.com blk->whenReady = clockEdge() + fillLatency * clockPeriod() + 180111051Sandreas.hansson@arm.com pkt->payloadDelay; 180211051Sandreas.hansson@arm.com 180311051Sandreas.hansson@arm.com return blk; 180411051Sandreas.hansson@arm.com} 180511051Sandreas.hansson@arm.com 180611051Sandreas.hansson@arm.com 180711051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 180811051Sandreas.hansson@arm.com// 180911051Sandreas.hansson@arm.com// Snoop path: requests coming in from the memory side 181011051Sandreas.hansson@arm.com// 181111051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 181211051Sandreas.hansson@arm.com 181311051Sandreas.hansson@arm.comvoid 181411051Sandreas.hansson@arm.comCache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 181511051Sandreas.hansson@arm.com bool already_copied, bool pending_inval) 181611051Sandreas.hansson@arm.com{ 181711051Sandreas.hansson@arm.com // sanity check 181811051Sandreas.hansson@arm.com assert(req_pkt->isRequest()); 181911051Sandreas.hansson@arm.com assert(req_pkt->needsResponse()); 182011051Sandreas.hansson@arm.com 182111051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 182211051Sandreas.hansson@arm.com req_pkt->cmdString(), req_pkt->getAddr(), req_pkt->getSize()); 182311051Sandreas.hansson@arm.com // timing-mode snoop responses require a new packet, unless we 182411051Sandreas.hansson@arm.com // already made a copy... 182511051Sandreas.hansson@arm.com PacketPtr pkt = req_pkt; 182611051Sandreas.hansson@arm.com if (!already_copied) 182711051Sandreas.hansson@arm.com // do not clear flags, and allocate space for data if the 182811051Sandreas.hansson@arm.com // packet needs it (the only packets that carry data are read 182911051Sandreas.hansson@arm.com // responses) 183011051Sandreas.hansson@arm.com pkt = new Packet(req_pkt, false, req_pkt->isRead()); 183111051Sandreas.hansson@arm.com 183211051Sandreas.hansson@arm.com assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() || 183311051Sandreas.hansson@arm.com pkt->sharedAsserted()); 183411051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 183511051Sandreas.hansson@arm.com if (pkt->isRead()) { 183611051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk_data, blkSize); 183711051Sandreas.hansson@arm.com } 183811051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadResp && pending_inval) { 183911051Sandreas.hansson@arm.com // Assume we defer a response to a read from a far-away cache 184011051Sandreas.hansson@arm.com // A, then later defer a ReadExcl from a cache B on the same 184111051Sandreas.hansson@arm.com // bus as us. We'll assert MemInhibit in both cases, but in 184211051Sandreas.hansson@arm.com // the latter case MemInhibit will keep the invalidation from 184311051Sandreas.hansson@arm.com // reaching cache A. This special response tells cache A that 184411051Sandreas.hansson@arm.com // it gets the block to satisfy its read, but must immediately 184511051Sandreas.hansson@arm.com // invalidate it. 184611051Sandreas.hansson@arm.com pkt->cmd = MemCmd::ReadRespWithInvalidate; 184711051Sandreas.hansson@arm.com } 184811051Sandreas.hansson@arm.com // Here we consider forward_time, paying for just forward latency and 184911051Sandreas.hansson@arm.com // also charging the delay provided by the xbar. 185011051Sandreas.hansson@arm.com // forward_time is used as send_time in next allocateWriteBuffer(). 185111051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 185211051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 185311051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 185411051Sandreas.hansson@arm.com DPRINTF(Cache, "%s created response: %s addr %#llx size %d tick: %lu\n", 185511051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize(), 185611051Sandreas.hansson@arm.com forward_time); 185711051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, forward_time, true); 185811051Sandreas.hansson@arm.com} 185911051Sandreas.hansson@arm.com 186011127Sandreas.hansson@arm.comuint32_t 186111051Sandreas.hansson@arm.comCache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, 186211051Sandreas.hansson@arm.com bool is_deferred, bool pending_inval) 186311051Sandreas.hansson@arm.com{ 186411051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 186511051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 186611051Sandreas.hansson@arm.com // deferred snoops can only happen in timing mode 186711051Sandreas.hansson@arm.com assert(!(is_deferred && !is_timing)); 186811051Sandreas.hansson@arm.com // pending_inval only makes sense on deferred snoops 186911051Sandreas.hansson@arm.com assert(!(pending_inval && !is_deferred)); 187011051Sandreas.hansson@arm.com assert(pkt->isRequest()); 187111051Sandreas.hansson@arm.com 187211051Sandreas.hansson@arm.com // the packet may get modified if we or a forwarded snooper 187311051Sandreas.hansson@arm.com // responds in atomic mode, so remember a few things about the 187411051Sandreas.hansson@arm.com // original packet up front 187511051Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 187611051Sandreas.hansson@arm.com bool M5_VAR_USED needs_exclusive = pkt->needsExclusive(); 187711051Sandreas.hansson@arm.com 187811127Sandreas.hansson@arm.com uint32_t snoop_delay = 0; 187911127Sandreas.hansson@arm.com 188011051Sandreas.hansson@arm.com if (forwardSnoops) { 188111051Sandreas.hansson@arm.com // first propagate snoop upward to see if anyone above us wants to 188211051Sandreas.hansson@arm.com // handle it. save & restore packet src since it will get 188311051Sandreas.hansson@arm.com // rewritten to be relative to cpu-side bus (if any) 188411051Sandreas.hansson@arm.com bool alreadyResponded = pkt->memInhibitAsserted(); 188511051Sandreas.hansson@arm.com if (is_timing) { 188611051Sandreas.hansson@arm.com // copy the packet so that we can clear any flags before 188711051Sandreas.hansson@arm.com // forwarding it upwards, we also allocate data (passing 188811051Sandreas.hansson@arm.com // the pointer along in case of static data), in case 188911051Sandreas.hansson@arm.com // there is a snoop hit in upper levels 189011051Sandreas.hansson@arm.com Packet snoopPkt(pkt, true, true); 189111051Sandreas.hansson@arm.com snoopPkt.setExpressSnoop(); 189211051Sandreas.hansson@arm.com // the snoop packet does not need to wait any additional 189311051Sandreas.hansson@arm.com // time 189411051Sandreas.hansson@arm.com snoopPkt.headerDelay = snoopPkt.payloadDelay = 0; 189511051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoopPkt); 189611127Sandreas.hansson@arm.com 189711127Sandreas.hansson@arm.com // add the header delay (including crossbar and snoop 189811127Sandreas.hansson@arm.com // delays) of the upward snoop to the snoop delay for this 189911127Sandreas.hansson@arm.com // cache 190011127Sandreas.hansson@arm.com snoop_delay += snoopPkt.headerDelay; 190111127Sandreas.hansson@arm.com 190211051Sandreas.hansson@arm.com if (snoopPkt.memInhibitAsserted()) { 190311051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache 190411051Sandreas.hansson@arm.com assert(!alreadyResponded); 190511051Sandreas.hansson@arm.com pkt->assertMemInhibit(); 190611051Sandreas.hansson@arm.com } 190711051Sandreas.hansson@arm.com if (snoopPkt.sharedAsserted()) { 190811051Sandreas.hansson@arm.com pkt->assertShared(); 190911051Sandreas.hansson@arm.com } 191011051Sandreas.hansson@arm.com // If this request is a prefetch or clean evict and an upper level 191111051Sandreas.hansson@arm.com // signals block present, make sure to propagate the block 191211051Sandreas.hansson@arm.com // presence to the requester. 191311051Sandreas.hansson@arm.com if (snoopPkt.isBlockCached()) { 191411051Sandreas.hansson@arm.com pkt->setBlockCached(); 191511051Sandreas.hansson@arm.com } 191611051Sandreas.hansson@arm.com } else { 191711051Sandreas.hansson@arm.com cpuSidePort->sendAtomicSnoop(pkt); 191811051Sandreas.hansson@arm.com if (!alreadyResponded && pkt->memInhibitAsserted()) { 191911051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache: 192011051Sandreas.hansson@arm.com // forward response to original requester 192111051Sandreas.hansson@arm.com assert(pkt->isResponse()); 192211051Sandreas.hansson@arm.com } 192311051Sandreas.hansson@arm.com } 192411051Sandreas.hansson@arm.com } 192511051Sandreas.hansson@arm.com 192611051Sandreas.hansson@arm.com if (!blk || !blk->isValid()) { 192711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s snoop miss for %s addr %#llx size %d\n", 192811051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 192911127Sandreas.hansson@arm.com return snoop_delay; 193011051Sandreas.hansson@arm.com } else { 193111051Sandreas.hansson@arm.com DPRINTF(Cache, "%s snoop hit for %s for addr %#llx size %d, " 193211051Sandreas.hansson@arm.com "old state is %s\n", __func__, pkt->cmdString(), 193311051Sandreas.hansson@arm.com pkt->getAddr(), pkt->getSize(), blk->print()); 193411051Sandreas.hansson@arm.com } 193511051Sandreas.hansson@arm.com 193611051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && blk->isDirty()), 193711051Sandreas.hansson@arm.com "Should never have a dirty block in a read-only cache %s\n", 193811051Sandreas.hansson@arm.com name()); 193911051Sandreas.hansson@arm.com 194011051Sandreas.hansson@arm.com // We may end up modifying both the block state and the packet (if 194111051Sandreas.hansson@arm.com // we respond in atomic mode), so just figure out what to do now 194211051Sandreas.hansson@arm.com // and then do it later. If we find dirty data while snooping for 194311051Sandreas.hansson@arm.com // an invalidate, we don't need to send a response. The 194411051Sandreas.hansson@arm.com // invalidation itself is taken care of below. 194511051Sandreas.hansson@arm.com bool respond = blk->isDirty() && pkt->needsResponse() && 194611051Sandreas.hansson@arm.com pkt->cmd != MemCmd::InvalidateReq; 194711051Sandreas.hansson@arm.com bool have_exclusive = blk->isWritable(); 194811051Sandreas.hansson@arm.com 194911051Sandreas.hansson@arm.com // Invalidate any prefetch's from below that would strip write permissions 195011051Sandreas.hansson@arm.com // MemCmd::HardPFReq is only observed by upstream caches. After missing 195111051Sandreas.hansson@arm.com // above and in it's own cache, a new MemCmd::ReadReq is created that 195211051Sandreas.hansson@arm.com // downstream caches observe. 195311051Sandreas.hansson@arm.com if (pkt->mustCheckAbove()) { 195411051Sandreas.hansson@arm.com DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s from" 195511051Sandreas.hansson@arm.com " lower cache\n", pkt->getAddr(), pkt->cmdString()); 195611051Sandreas.hansson@arm.com pkt->setBlockCached(); 195711127Sandreas.hansson@arm.com return snoop_delay; 195811051Sandreas.hansson@arm.com } 195911051Sandreas.hansson@arm.com 196011051Sandreas.hansson@arm.com if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) { 196111081Sandreas.hansson@arm.com // reading non-exclusive shared data, note that we retain 196211081Sandreas.hansson@arm.com // the block in owned state if it is dirty, with the response 196311081Sandreas.hansson@arm.com // taken care of below, and otherwhise simply downgrade to 196411081Sandreas.hansson@arm.com // shared 196511051Sandreas.hansson@arm.com assert(!needs_exclusive); 196611051Sandreas.hansson@arm.com pkt->assertShared(); 196711081Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 196811051Sandreas.hansson@arm.com } 196911051Sandreas.hansson@arm.com 197011051Sandreas.hansson@arm.com if (respond) { 197111051Sandreas.hansson@arm.com // prevent anyone else from responding, cache as well as 197211051Sandreas.hansson@arm.com // memory, and also prevent any memory from even seeing the 197311051Sandreas.hansson@arm.com // request (with current inhibited semantics), note that this 197411051Sandreas.hansson@arm.com // applies both to reads and writes and that for writes it 197511051Sandreas.hansson@arm.com // works thanks to the fact that we still have dirty data and 197611051Sandreas.hansson@arm.com // will write it back at a later point 197711197Sandreas.hansson@arm.com assert(!pkt->memInhibitAsserted()); 197811051Sandreas.hansson@arm.com pkt->assertMemInhibit(); 197911051Sandreas.hansson@arm.com if (have_exclusive) { 198011081Sandreas.hansson@arm.com // in the case of an uncacheable request there is no point 198111081Sandreas.hansson@arm.com // in setting the exclusive flag, but since the recipient 198211081Sandreas.hansson@arm.com // does not care there is no harm in doing so, in any case 198311081Sandreas.hansson@arm.com // it is just a hint 198411051Sandreas.hansson@arm.com pkt->setSupplyExclusive(); 198511051Sandreas.hansson@arm.com } 198611051Sandreas.hansson@arm.com if (is_timing) { 198711051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval); 198811051Sandreas.hansson@arm.com } else { 198911051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 199011051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 199111051Sandreas.hansson@arm.com } 199211051Sandreas.hansson@arm.com } 199311051Sandreas.hansson@arm.com 199411051Sandreas.hansson@arm.com if (!respond && is_timing && is_deferred) { 199511271Sandreas.hansson@arm.com // if it's a deferred timing snoop to which we are not 199611271Sandreas.hansson@arm.com // responding, then we've made a copy of both the request and 199711271Sandreas.hansson@arm.com // the packet, delete them here 199811051Sandreas.hansson@arm.com assert(pkt->needsResponse()); 199911051Sandreas.hansson@arm.com delete pkt->req; 200011051Sandreas.hansson@arm.com delete pkt; 200111051Sandreas.hansson@arm.com } 200211051Sandreas.hansson@arm.com 200311051Sandreas.hansson@arm.com // Do this last in case it deallocates block data or something 200411051Sandreas.hansson@arm.com // like that 200511051Sandreas.hansson@arm.com if (invalidate) { 200611197Sandreas.hansson@arm.com invalidateBlock(blk); 200711051Sandreas.hansson@arm.com } 200811051Sandreas.hansson@arm.com 200911051Sandreas.hansson@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 201011127Sandreas.hansson@arm.com 201111127Sandreas.hansson@arm.com return snoop_delay; 201211051Sandreas.hansson@arm.com} 201311051Sandreas.hansson@arm.com 201411051Sandreas.hansson@arm.com 201511051Sandreas.hansson@arm.comvoid 201611051Sandreas.hansson@arm.comCache::recvTimingSnoopReq(PacketPtr pkt) 201711051Sandreas.hansson@arm.com{ 201811051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 201911051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 202011051Sandreas.hansson@arm.com 202111051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 202211051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 202311051Sandreas.hansson@arm.com 202411130Sali.jafri@arm.com // no need to snoop requests that are not in range 202511051Sandreas.hansson@arm.com if (!inRange(pkt->getAddr())) { 202611051Sandreas.hansson@arm.com return; 202711051Sandreas.hansson@arm.com } 202811051Sandreas.hansson@arm.com 202911051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 203011051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 203111051Sandreas.hansson@arm.com 203211051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 203311051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 203411051Sandreas.hansson@arm.com 203511127Sandreas.hansson@arm.com // Update the latency cost of the snoop so that the crossbar can 203611127Sandreas.hansson@arm.com // account for it. Do not overwrite what other neighbouring caches 203711127Sandreas.hansson@arm.com // have already done, rather take the maximum. The update is 203811127Sandreas.hansson@arm.com // tentative, for cases where we return before an upward snoop 203911127Sandreas.hansson@arm.com // happens below. 204011127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, 204111127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 204211127Sandreas.hansson@arm.com 204311051Sandreas.hansson@arm.com // Inform request(Prefetch, CleanEvict or Writeback) from below of 204411051Sandreas.hansson@arm.com // MSHR hit, set setBlockCached. 204511051Sandreas.hansson@arm.com if (mshr && pkt->mustCheckAbove()) { 204611051Sandreas.hansson@arm.com DPRINTF(Cache, "Setting block cached for %s from" 204711051Sandreas.hansson@arm.com "lower cache on mshr hit %#x\n", 204811051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 204911051Sandreas.hansson@arm.com pkt->setBlockCached(); 205011051Sandreas.hansson@arm.com return; 205111051Sandreas.hansson@arm.com } 205211051Sandreas.hansson@arm.com 205311051Sandreas.hansson@arm.com // Let the MSHR itself track the snoop and decide whether we want 205411051Sandreas.hansson@arm.com // to go ahead and do the regular cache snoop 205511051Sandreas.hansson@arm.com if (mshr && mshr->handleSnoop(pkt, order++)) { 205611051Sandreas.hansson@arm.com DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)." 205711051Sandreas.hansson@arm.com "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns", 205811051Sandreas.hansson@arm.com mshr->print()); 205911051Sandreas.hansson@arm.com 206011051Sandreas.hansson@arm.com if (mshr->getNumTargets() > numTarget) 206111051Sandreas.hansson@arm.com warn("allocating bonus target for snoop"); //handle later 206211051Sandreas.hansson@arm.com return; 206311051Sandreas.hansson@arm.com } 206411051Sandreas.hansson@arm.com 206511051Sandreas.hansson@arm.com //We also need to check the writeback buffers and handle those 206611051Sandreas.hansson@arm.com std::vector<MSHR *> writebacks; 206711051Sandreas.hansson@arm.com if (writeBuffer.findMatches(blk_addr, is_secure, writebacks)) { 206811051Sandreas.hansson@arm.com DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n", 206911051Sandreas.hansson@arm.com pkt->getAddr(), is_secure ? "s" : "ns"); 207011051Sandreas.hansson@arm.com 207111051Sandreas.hansson@arm.com // Look through writebacks for any cachable writes. 207211051Sandreas.hansson@arm.com // We should only ever find a single match 207311051Sandreas.hansson@arm.com assert(writebacks.size() == 1); 207411051Sandreas.hansson@arm.com MSHR *wb_entry = writebacks[0]; 207511051Sandreas.hansson@arm.com // Expect to see only Writebacks and/or CleanEvicts here, both of 207611051Sandreas.hansson@arm.com // which should not be generated for uncacheable data. 207711051Sandreas.hansson@arm.com assert(!wb_entry->isUncacheable()); 207811051Sandreas.hansson@arm.com // There should only be a single request responsible for generating 207911051Sandreas.hansson@arm.com // Writebacks/CleanEvicts. 208011051Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 208111051Sandreas.hansson@arm.com PacketPtr wb_pkt = wb_entry->getTarget()->pkt; 208211199Sandreas.hansson@arm.com assert(wb_pkt->isEviction()); 208311051Sandreas.hansson@arm.com 208411199Sandreas.hansson@arm.com if (pkt->isEviction()) { 208511051Sandreas.hansson@arm.com // if the block is found in the write queue, set the BLOCK_CACHED 208611051Sandreas.hansson@arm.com // flag for Writeback/CleanEvict snoop. On return the snoop will 208711051Sandreas.hansson@arm.com // propagate the BLOCK_CACHED flag in Writeback packets and prevent 208811051Sandreas.hansson@arm.com // any CleanEvicts from travelling down the memory hierarchy. 208911051Sandreas.hansson@arm.com pkt->setBlockCached(); 209011051Sandreas.hansson@arm.com DPRINTF(Cache, "Squashing %s from lower cache on writequeue hit" 209111051Sandreas.hansson@arm.com " %#x\n", pkt->cmdString(), pkt->getAddr()); 209211051Sandreas.hansson@arm.com return; 209311051Sandreas.hansson@arm.com } 209411051Sandreas.hansson@arm.com 209511199Sandreas.hansson@arm.com if (wb_pkt->cmd == MemCmd::WritebackDirty) { 209611051Sandreas.hansson@arm.com assert(!pkt->memInhibitAsserted()); 209711051Sandreas.hansson@arm.com pkt->assertMemInhibit(); 209811051Sandreas.hansson@arm.com if (!pkt->needsExclusive()) { 209911051Sandreas.hansson@arm.com pkt->assertShared(); 210011051Sandreas.hansson@arm.com // the writeback is no longer passing exclusivity (the 210111051Sandreas.hansson@arm.com // receiving cache should consider the block owned 210211051Sandreas.hansson@arm.com // rather than modified) 210311051Sandreas.hansson@arm.com wb_pkt->assertShared(); 210411051Sandreas.hansson@arm.com } else { 210511051Sandreas.hansson@arm.com // if we're not asserting the shared line, we need to 210611051Sandreas.hansson@arm.com // invalidate our copy. we'll do that below as long as 210711051Sandreas.hansson@arm.com // the packet's invalidate flag is set... 210811051Sandreas.hansson@arm.com assert(pkt->isInvalidate()); 210911051Sandreas.hansson@arm.com } 211011051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(), 211111051Sandreas.hansson@arm.com false, false); 211211051Sandreas.hansson@arm.com } else { 211311199Sandreas.hansson@arm.com // on hitting a clean writeback we play it safe and do not 211411199Sandreas.hansson@arm.com // provide a response, the block may be dirty somewhere 211511199Sandreas.hansson@arm.com // else 211611199Sandreas.hansson@arm.com assert(wb_pkt->isCleanEviction()); 211711051Sandreas.hansson@arm.com // The cache technically holds the block until the 211811199Sandreas.hansson@arm.com // corresponding message reaches the crossbar 211911051Sandreas.hansson@arm.com // below. Therefore when a snoop encounters a CleanEvict 212011199Sandreas.hansson@arm.com // or WritebackClean message we must set assertShared 212111199Sandreas.hansson@arm.com // (just like when it encounters a Writeback) to avoid the 212211199Sandreas.hansson@arm.com // snoop filter prematurely clearing the holder bit in the 212311199Sandreas.hansson@arm.com // crossbar below 212411199Sandreas.hansson@arm.com if (!pkt->needsExclusive()) { 212511051Sandreas.hansson@arm.com pkt->assertShared(); 212611199Sandreas.hansson@arm.com // the writeback is no longer passing exclusivity (the 212711199Sandreas.hansson@arm.com // receiving cache should consider the block owned 212811199Sandreas.hansson@arm.com // rather than modified) 212911199Sandreas.hansson@arm.com wb_pkt->assertShared(); 213011199Sandreas.hansson@arm.com } else { 213111051Sandreas.hansson@arm.com assert(pkt->isInvalidate()); 213211199Sandreas.hansson@arm.com } 213311051Sandreas.hansson@arm.com } 213411051Sandreas.hansson@arm.com 213511051Sandreas.hansson@arm.com if (pkt->isInvalidate()) { 213611051Sandreas.hansson@arm.com // Invalidation trumps our writeback... discard here 213711051Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 213811051Sandreas.hansson@arm.com markInService(wb_entry, false); 213911051Sandreas.hansson@arm.com delete wb_pkt; 214011051Sandreas.hansson@arm.com } 214111051Sandreas.hansson@arm.com } 214211051Sandreas.hansson@arm.com 214311051Sandreas.hansson@arm.com // If this was a shared writeback, there may still be 214411051Sandreas.hansson@arm.com // other shared copies above that require invalidation. 214511051Sandreas.hansson@arm.com // We could be more selective and return here if the 214611051Sandreas.hansson@arm.com // request is non-exclusive or if the writeback is 214711051Sandreas.hansson@arm.com // exclusive. 214811127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false); 214911127Sandreas.hansson@arm.com 215011127Sandreas.hansson@arm.com // Override what we did when we first saw the snoop, as we now 215111127Sandreas.hansson@arm.com // also have the cost of the upwards snoops to account for 215211127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay + 215311127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 215411051Sandreas.hansson@arm.com} 215511051Sandreas.hansson@arm.com 215611051Sandreas.hansson@arm.combool 215711051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 215811051Sandreas.hansson@arm.com{ 215911051Sandreas.hansson@arm.com // Express snoop responses from master to slave, e.g., from L1 to L2 216011051Sandreas.hansson@arm.com cache->recvTimingSnoopResp(pkt); 216111051Sandreas.hansson@arm.com return true; 216211051Sandreas.hansson@arm.com} 216311051Sandreas.hansson@arm.com 216411051Sandreas.hansson@arm.comTick 216511051Sandreas.hansson@arm.comCache::recvAtomicSnoop(PacketPtr pkt) 216611051Sandreas.hansson@arm.com{ 216711051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 216811051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 216911051Sandreas.hansson@arm.com 217011130Sali.jafri@arm.com // no need to snoop requests that are not in range. 217111130Sali.jafri@arm.com if (!inRange(pkt->getAddr())) { 217211051Sandreas.hansson@arm.com return 0; 217311051Sandreas.hansson@arm.com } 217411051Sandreas.hansson@arm.com 217511051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 217611127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false); 217711127Sandreas.hansson@arm.com return snoop_delay + lookupLatency * clockPeriod(); 217811051Sandreas.hansson@arm.com} 217911051Sandreas.hansson@arm.com 218011051Sandreas.hansson@arm.com 218111051Sandreas.hansson@arm.comMSHR * 218211051Sandreas.hansson@arm.comCache::getNextMSHR() 218311051Sandreas.hansson@arm.com{ 218411051Sandreas.hansson@arm.com // Check both MSHR queue and write buffer for potential requests, 218511051Sandreas.hansson@arm.com // note that null does not mean there is no request, it could 218611051Sandreas.hansson@arm.com // simply be that it is not ready 218711051Sandreas.hansson@arm.com MSHR *miss_mshr = mshrQueue.getNextMSHR(); 218811051Sandreas.hansson@arm.com MSHR *write_mshr = writeBuffer.getNextMSHR(); 218911051Sandreas.hansson@arm.com 219011051Sandreas.hansson@arm.com // If we got a write buffer request ready, first priority is a 219111051Sandreas.hansson@arm.com // full write buffer, otherwhise we favour the miss requests 219211051Sandreas.hansson@arm.com if (write_mshr && 219311051Sandreas.hansson@arm.com ((writeBuffer.isFull() && writeBuffer.inServiceEntries == 0) || 219411051Sandreas.hansson@arm.com !miss_mshr)) { 219511051Sandreas.hansson@arm.com // need to search MSHR queue for conflicting earlier miss. 219611051Sandreas.hansson@arm.com MSHR *conflict_mshr = 219711051Sandreas.hansson@arm.com mshrQueue.findPending(write_mshr->blkAddr, 219811051Sandreas.hansson@arm.com write_mshr->isSecure); 219911051Sandreas.hansson@arm.com 220011051Sandreas.hansson@arm.com if (conflict_mshr && conflict_mshr->order < write_mshr->order) { 220111051Sandreas.hansson@arm.com // Service misses in order until conflict is cleared. 220211051Sandreas.hansson@arm.com return conflict_mshr; 220311051Sandreas.hansson@arm.com 220411051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 220511051Sandreas.hansson@arm.com } 220611051Sandreas.hansson@arm.com 220711051Sandreas.hansson@arm.com // No conflicts; issue write 220811051Sandreas.hansson@arm.com return write_mshr; 220911051Sandreas.hansson@arm.com } else if (miss_mshr) { 221011051Sandreas.hansson@arm.com // need to check for conflicting earlier writeback 221111051Sandreas.hansson@arm.com MSHR *conflict_mshr = 221211051Sandreas.hansson@arm.com writeBuffer.findPending(miss_mshr->blkAddr, 221311051Sandreas.hansson@arm.com miss_mshr->isSecure); 221411051Sandreas.hansson@arm.com if (conflict_mshr) { 221511051Sandreas.hansson@arm.com // not sure why we don't check order here... it was in the 221611051Sandreas.hansson@arm.com // original code but commented out. 221711051Sandreas.hansson@arm.com 221811051Sandreas.hansson@arm.com // The only way this happens is if we are 221911051Sandreas.hansson@arm.com // doing a write and we didn't have permissions 222011051Sandreas.hansson@arm.com // then subsequently saw a writeback (owned got evicted) 222111051Sandreas.hansson@arm.com // We need to make sure to perform the writeback first 222211051Sandreas.hansson@arm.com // To preserve the dirty data, then we can issue the write 222311051Sandreas.hansson@arm.com 222411051Sandreas.hansson@arm.com // should we return write_mshr here instead? I.e. do we 222511051Sandreas.hansson@arm.com // have to flush writes in order? I don't think so... not 222611051Sandreas.hansson@arm.com // for Alpha anyway. Maybe for x86? 222711051Sandreas.hansson@arm.com return conflict_mshr; 222811051Sandreas.hansson@arm.com 222911051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 223011051Sandreas.hansson@arm.com } 223111051Sandreas.hansson@arm.com 223211051Sandreas.hansson@arm.com // No conflicts; issue read 223311051Sandreas.hansson@arm.com return miss_mshr; 223411051Sandreas.hansson@arm.com } 223511051Sandreas.hansson@arm.com 223611051Sandreas.hansson@arm.com // fall through... no pending requests. Try a prefetch. 223711051Sandreas.hansson@arm.com assert(!miss_mshr && !write_mshr); 223811051Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 223911051Sandreas.hansson@arm.com // If we have a miss queue slot, we can try a prefetch 224011051Sandreas.hansson@arm.com PacketPtr pkt = prefetcher->getPacket(); 224111051Sandreas.hansson@arm.com if (pkt) { 224211051Sandreas.hansson@arm.com Addr pf_addr = blockAlign(pkt->getAddr()); 224311051Sandreas.hansson@arm.com if (!tags->findBlock(pf_addr, pkt->isSecure()) && 224411051Sandreas.hansson@arm.com !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 224511051Sandreas.hansson@arm.com !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 224611051Sandreas.hansson@arm.com // Update statistic on number of prefetches issued 224711051Sandreas.hansson@arm.com // (hwpf_mshr_misses) 224811051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 224911051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 225011051Sandreas.hansson@arm.com 225111051Sandreas.hansson@arm.com // allocate an MSHR and return it, note 225211051Sandreas.hansson@arm.com // that we send the packet straight away, so do not 225311051Sandreas.hansson@arm.com // schedule the send 225411051Sandreas.hansson@arm.com return allocateMissBuffer(pkt, curTick(), false); 225511051Sandreas.hansson@arm.com } else { 225611051Sandreas.hansson@arm.com // free the request and packet 225711051Sandreas.hansson@arm.com delete pkt->req; 225811051Sandreas.hansson@arm.com delete pkt; 225911051Sandreas.hansson@arm.com } 226011051Sandreas.hansson@arm.com } 226111051Sandreas.hansson@arm.com } 226211051Sandreas.hansson@arm.com 226311051Sandreas.hansson@arm.com return NULL; 226411051Sandreas.hansson@arm.com} 226511051Sandreas.hansson@arm.com 226611051Sandreas.hansson@arm.combool 226711130Sali.jafri@arm.comCache::isCachedAbove(PacketPtr pkt, bool is_timing) const 226811051Sandreas.hansson@arm.com{ 226911051Sandreas.hansson@arm.com if (!forwardSnoops) 227011051Sandreas.hansson@arm.com return false; 227111051Sandreas.hansson@arm.com // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and 227211051Sandreas.hansson@arm.com // Writeback snoops into upper level caches to check for copies of the 227311051Sandreas.hansson@arm.com // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict 227411051Sandreas.hansson@arm.com // packet, the cache can inform the crossbar below of presence or absence 227511051Sandreas.hansson@arm.com // of the block. 227611130Sali.jafri@arm.com if (is_timing) { 227711130Sali.jafri@arm.com Packet snoop_pkt(pkt, true, false); 227811130Sali.jafri@arm.com snoop_pkt.setExpressSnoop(); 227911130Sali.jafri@arm.com // Assert that packet is either Writeback or CleanEvict and not a 228011130Sali.jafri@arm.com // prefetch request because prefetch requests need an MSHR and may 228111130Sali.jafri@arm.com // generate a snoop response. 228211199Sandreas.hansson@arm.com assert(pkt->isEviction()); 228311130Sali.jafri@arm.com snoop_pkt.senderState = NULL; 228411130Sali.jafri@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 228511130Sali.jafri@arm.com // Writeback/CleanEvict snoops do not generate a snoop response. 228611130Sali.jafri@arm.com assert(!(snoop_pkt.memInhibitAsserted())); 228711130Sali.jafri@arm.com return snoop_pkt.isBlockCached(); 228811130Sali.jafri@arm.com } else { 228911130Sali.jafri@arm.com cpuSidePort->sendAtomicSnoop(pkt); 229011130Sali.jafri@arm.com return pkt->isBlockCached(); 229111130Sali.jafri@arm.com } 229211051Sandreas.hansson@arm.com} 229311051Sandreas.hansson@arm.com 229411051Sandreas.hansson@arm.comPacketPtr 229511051Sandreas.hansson@arm.comCache::getTimingPacket() 229611051Sandreas.hansson@arm.com{ 229711051Sandreas.hansson@arm.com MSHR *mshr = getNextMSHR(); 229811051Sandreas.hansson@arm.com 229911051Sandreas.hansson@arm.com if (mshr == NULL) { 230011051Sandreas.hansson@arm.com return NULL; 230111051Sandreas.hansson@arm.com } 230211051Sandreas.hansson@arm.com 230311051Sandreas.hansson@arm.com // use request from 1st target 230411051Sandreas.hansson@arm.com PacketPtr tgt_pkt = mshr->getTarget()->pkt; 230511051Sandreas.hansson@arm.com PacketPtr pkt = NULL; 230611051Sandreas.hansson@arm.com 230711051Sandreas.hansson@arm.com DPRINTF(CachePort, "%s %s for addr %#llx size %d\n", __func__, 230811051Sandreas.hansson@arm.com tgt_pkt->cmdString(), tgt_pkt->getAddr(), tgt_pkt->getSize()); 230911051Sandreas.hansson@arm.com 231011051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 231111051Sandreas.hansson@arm.com 231211051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) { 231311051Sandreas.hansson@arm.com // We need to check the caches above us to verify that 231411051Sandreas.hansson@arm.com // they don't have a copy of this block in the dirty state 231511051Sandreas.hansson@arm.com // at the moment. Without this check we could get a stale 231611051Sandreas.hansson@arm.com // copy from memory that might get used in place of the 231711051Sandreas.hansson@arm.com // dirty one. 231811051Sandreas.hansson@arm.com Packet snoop_pkt(tgt_pkt, true, false); 231911051Sandreas.hansson@arm.com snoop_pkt.setExpressSnoop(); 232011275Sandreas.hansson@arm.com // We are sending this packet upwards, but if it hits we will 232111275Sandreas.hansson@arm.com // get a snoop response that we end up treating just like a 232211275Sandreas.hansson@arm.com // normal response, hence it needs the MSHR as its sender 232311275Sandreas.hansson@arm.com // state 232411051Sandreas.hansson@arm.com snoop_pkt.senderState = mshr; 232511051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 232611051Sandreas.hansson@arm.com 232711051Sandreas.hansson@arm.com // Check to see if the prefetch was squashed by an upper cache (to 232811051Sandreas.hansson@arm.com // prevent us from grabbing the line) or if a Check to see if a 232911051Sandreas.hansson@arm.com // writeback arrived between the time the prefetch was placed in 233011051Sandreas.hansson@arm.com // the MSHRs and when it was selected to be sent or if the 233111051Sandreas.hansson@arm.com // prefetch was squashed by an upper cache. 233211051Sandreas.hansson@arm.com 233311051Sandreas.hansson@arm.com // It is important to check memInhibitAsserted before 233411051Sandreas.hansson@arm.com // prefetchSquashed. If another cache has asserted MEM_INGIBIT, it 233511051Sandreas.hansson@arm.com // will be sending a response which will arrive at the MSHR 233611051Sandreas.hansson@arm.com // allocated ofr this request. Checking the prefetchSquash first 233711051Sandreas.hansson@arm.com // may result in the MSHR being prematurely deallocated. 233811051Sandreas.hansson@arm.com 233911051Sandreas.hansson@arm.com if (snoop_pkt.memInhibitAsserted()) { 234011276Sandreas.hansson@arm.com auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req); 234111276Sandreas.hansson@arm.com assert(r.second); 234211051Sandreas.hansson@arm.com // If we are getting a non-shared response it is dirty 234311051Sandreas.hansson@arm.com bool pending_dirty_resp = !snoop_pkt.sharedAsserted(); 234411051Sandreas.hansson@arm.com markInService(mshr, pending_dirty_resp); 234511051Sandreas.hansson@arm.com DPRINTF(Cache, "Upward snoop of prefetch for addr" 234611051Sandreas.hansson@arm.com " %#x (%s) hit\n", 234711051Sandreas.hansson@arm.com tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns"); 234811051Sandreas.hansson@arm.com return NULL; 234911051Sandreas.hansson@arm.com } 235011051Sandreas.hansson@arm.com 235111051Sandreas.hansson@arm.com if (snoop_pkt.isBlockCached() || blk != NULL) { 235211051Sandreas.hansson@arm.com DPRINTF(Cache, "Block present, prefetch squashed by cache. " 235311051Sandreas.hansson@arm.com "Deallocating mshr target %#x.\n", 235411051Sandreas.hansson@arm.com mshr->blkAddr); 235511051Sandreas.hansson@arm.com // Deallocate the mshr target 235611277Sandreas.hansson@arm.com if (mshr->queue->forceDeallocateTarget(mshr)) { 235711277Sandreas.hansson@arm.com // Clear block if this deallocation resulted freed an 235811277Sandreas.hansson@arm.com // mshr when all had previously been utilized 235911277Sandreas.hansson@arm.com clearBlocked((BlockedCause)(mshr->queue->index)); 236011051Sandreas.hansson@arm.com } 236111277Sandreas.hansson@arm.com return NULL; 236211051Sandreas.hansson@arm.com } 236311051Sandreas.hansson@arm.com } 236411051Sandreas.hansson@arm.com 236511051Sandreas.hansson@arm.com if (mshr->isForwardNoResponse()) { 236611051Sandreas.hansson@arm.com // no response expected, just forward packet as it is 236711051Sandreas.hansson@arm.com assert(tags->findBlock(mshr->blkAddr, mshr->isSecure) == NULL); 236811051Sandreas.hansson@arm.com pkt = tgt_pkt; 236911051Sandreas.hansson@arm.com } else { 237011051Sandreas.hansson@arm.com pkt = getBusPacket(tgt_pkt, blk, mshr->needsExclusive()); 237111051Sandreas.hansson@arm.com 237211051Sandreas.hansson@arm.com mshr->isForward = (pkt == NULL); 237311051Sandreas.hansson@arm.com 237411051Sandreas.hansson@arm.com if (mshr->isForward) { 237511051Sandreas.hansson@arm.com // not a cache block request, but a response is expected 237611051Sandreas.hansson@arm.com // make copy of current packet to forward, keep current 237711051Sandreas.hansson@arm.com // copy for response handling 237811051Sandreas.hansson@arm.com pkt = new Packet(tgt_pkt, false, true); 237911051Sandreas.hansson@arm.com if (pkt->isWrite()) { 238011051Sandreas.hansson@arm.com pkt->setData(tgt_pkt->getConstPtr<uint8_t>()); 238111051Sandreas.hansson@arm.com } 238211051Sandreas.hansson@arm.com } 238311051Sandreas.hansson@arm.com } 238411051Sandreas.hansson@arm.com 238511051Sandreas.hansson@arm.com assert(pkt != NULL); 238611275Sandreas.hansson@arm.com // play it safe and append (rather than set) the sender state, as 238711275Sandreas.hansson@arm.com // forwarded packets may already have existing state 238811275Sandreas.hansson@arm.com pkt->pushSenderState(mshr); 238911051Sandreas.hansson@arm.com return pkt; 239011051Sandreas.hansson@arm.com} 239111051Sandreas.hansson@arm.com 239211051Sandreas.hansson@arm.com 239311051Sandreas.hansson@arm.comTick 239411051Sandreas.hansson@arm.comCache::nextMSHRReadyTime() const 239511051Sandreas.hansson@arm.com{ 239611051Sandreas.hansson@arm.com Tick nextReady = std::min(mshrQueue.nextMSHRReadyTime(), 239711051Sandreas.hansson@arm.com writeBuffer.nextMSHRReadyTime()); 239811051Sandreas.hansson@arm.com 239911051Sandreas.hansson@arm.com // Don't signal prefetch ready time if no MSHRs available 240011051Sandreas.hansson@arm.com // Will signal once enoguh MSHRs are deallocated 240111051Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 240211051Sandreas.hansson@arm.com nextReady = std::min(nextReady, 240311051Sandreas.hansson@arm.com prefetcher->nextPrefetchReadyTime()); 240411051Sandreas.hansson@arm.com } 240511051Sandreas.hansson@arm.com 240611051Sandreas.hansson@arm.com return nextReady; 240711051Sandreas.hansson@arm.com} 240811051Sandreas.hansson@arm.com 240911051Sandreas.hansson@arm.comvoid 241011051Sandreas.hansson@arm.comCache::serialize(CheckpointOut &cp) const 241111051Sandreas.hansson@arm.com{ 241211051Sandreas.hansson@arm.com bool dirty(isDirty()); 241311051Sandreas.hansson@arm.com 241411051Sandreas.hansson@arm.com if (dirty) { 241511051Sandreas.hansson@arm.com warn("*** The cache still contains dirty data. ***\n"); 241611051Sandreas.hansson@arm.com warn(" Make sure to drain the system using the correct flags.\n"); 241711051Sandreas.hansson@arm.com warn(" This checkpoint will not restore correctly and dirty data in " 241811051Sandreas.hansson@arm.com "the cache will be lost!\n"); 241911051Sandreas.hansson@arm.com } 242011051Sandreas.hansson@arm.com 242111051Sandreas.hansson@arm.com // Since we don't checkpoint the data in the cache, any dirty data 242211051Sandreas.hansson@arm.com // will be lost when restoring from a checkpoint of a system that 242311051Sandreas.hansson@arm.com // wasn't drained properly. Flag the checkpoint as invalid if the 242411051Sandreas.hansson@arm.com // cache contains dirty data. 242511051Sandreas.hansson@arm.com bool bad_checkpoint(dirty); 242611051Sandreas.hansson@arm.com SERIALIZE_SCALAR(bad_checkpoint); 242711051Sandreas.hansson@arm.com} 242811051Sandreas.hansson@arm.com 242911051Sandreas.hansson@arm.comvoid 243011051Sandreas.hansson@arm.comCache::unserialize(CheckpointIn &cp) 243111051Sandreas.hansson@arm.com{ 243211051Sandreas.hansson@arm.com bool bad_checkpoint; 243311051Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(bad_checkpoint); 243411051Sandreas.hansson@arm.com if (bad_checkpoint) { 243511051Sandreas.hansson@arm.com fatal("Restoring from checkpoints with dirty caches is not supported " 243611051Sandreas.hansson@arm.com "in the classic memory system. Please remove any caches or " 243711051Sandreas.hansson@arm.com " drain them properly before taking checkpoints.\n"); 243811051Sandreas.hansson@arm.com } 243911051Sandreas.hansson@arm.com} 244011051Sandreas.hansson@arm.com 244111051Sandreas.hansson@arm.com/////////////// 244211051Sandreas.hansson@arm.com// 244311051Sandreas.hansson@arm.com// CpuSidePort 244411051Sandreas.hansson@arm.com// 244511051Sandreas.hansson@arm.com/////////////// 244611051Sandreas.hansson@arm.com 244711051Sandreas.hansson@arm.comAddrRangeList 244811051Sandreas.hansson@arm.comCache::CpuSidePort::getAddrRanges() const 244911051Sandreas.hansson@arm.com{ 245011051Sandreas.hansson@arm.com return cache->getAddrRanges(); 245111051Sandreas.hansson@arm.com} 245211051Sandreas.hansson@arm.com 245311051Sandreas.hansson@arm.combool 245411051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingReq(PacketPtr pkt) 245511051Sandreas.hansson@arm.com{ 245611051Sandreas.hansson@arm.com assert(!cache->system->bypassCaches()); 245711051Sandreas.hansson@arm.com 245811051Sandreas.hansson@arm.com bool success = false; 245911051Sandreas.hansson@arm.com 246011051Sandreas.hansson@arm.com // always let inhibited requests through, even if blocked, 246111051Sandreas.hansson@arm.com // ultimately we should check if this is an express snoop, but at 246211051Sandreas.hansson@arm.com // the moment that flag is only set in the cache itself 246311051Sandreas.hansson@arm.com if (pkt->memInhibitAsserted()) { 246411051Sandreas.hansson@arm.com // do not change the current retry state 246511051Sandreas.hansson@arm.com bool M5_VAR_USED bypass_success = cache->recvTimingReq(pkt); 246611051Sandreas.hansson@arm.com assert(bypass_success); 246711051Sandreas.hansson@arm.com return true; 246811051Sandreas.hansson@arm.com } else if (blocked || mustSendRetry) { 246911051Sandreas.hansson@arm.com // either already committed to send a retry, or blocked 247011051Sandreas.hansson@arm.com success = false; 247111051Sandreas.hansson@arm.com } else { 247211051Sandreas.hansson@arm.com // pass it on to the cache, and let the cache decide if we 247311051Sandreas.hansson@arm.com // have to retry or not 247411051Sandreas.hansson@arm.com success = cache->recvTimingReq(pkt); 247511051Sandreas.hansson@arm.com } 247611051Sandreas.hansson@arm.com 247711051Sandreas.hansson@arm.com // remember if we have to retry 247811051Sandreas.hansson@arm.com mustSendRetry = !success; 247911051Sandreas.hansson@arm.com return success; 248011051Sandreas.hansson@arm.com} 248111051Sandreas.hansson@arm.com 248211051Sandreas.hansson@arm.comTick 248311051Sandreas.hansson@arm.comCache::CpuSidePort::recvAtomic(PacketPtr pkt) 248411051Sandreas.hansson@arm.com{ 248511051Sandreas.hansson@arm.com return cache->recvAtomic(pkt); 248611051Sandreas.hansson@arm.com} 248711051Sandreas.hansson@arm.com 248811051Sandreas.hansson@arm.comvoid 248911051Sandreas.hansson@arm.comCache::CpuSidePort::recvFunctional(PacketPtr pkt) 249011051Sandreas.hansson@arm.com{ 249111051Sandreas.hansson@arm.com // functional request 249211051Sandreas.hansson@arm.com cache->functionalAccess(pkt, true); 249311051Sandreas.hansson@arm.com} 249411051Sandreas.hansson@arm.com 249511051Sandreas.hansson@arm.comCache:: 249611051Sandreas.hansson@arm.comCpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache, 249711051Sandreas.hansson@arm.com const std::string &_label) 249811051Sandreas.hansson@arm.com : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache) 249911051Sandreas.hansson@arm.com{ 250011051Sandreas.hansson@arm.com} 250111051Sandreas.hansson@arm.com 250211053Sandreas.hansson@arm.comCache* 250311053Sandreas.hansson@arm.comCacheParams::create() 250411053Sandreas.hansson@arm.com{ 250511053Sandreas.hansson@arm.com assert(tags); 250611053Sandreas.hansson@arm.com 250711053Sandreas.hansson@arm.com return new Cache(this); 250811053Sandreas.hansson@arm.com} 250911051Sandreas.hansson@arm.com/////////////// 251011051Sandreas.hansson@arm.com// 251111051Sandreas.hansson@arm.com// MemSidePort 251211051Sandreas.hansson@arm.com// 251311051Sandreas.hansson@arm.com/////////////// 251411051Sandreas.hansson@arm.com 251511051Sandreas.hansson@arm.combool 251611051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingResp(PacketPtr pkt) 251711051Sandreas.hansson@arm.com{ 251811051Sandreas.hansson@arm.com cache->recvTimingResp(pkt); 251911051Sandreas.hansson@arm.com return true; 252011051Sandreas.hansson@arm.com} 252111051Sandreas.hansson@arm.com 252211051Sandreas.hansson@arm.com// Express snooping requests to memside port 252311051Sandreas.hansson@arm.comvoid 252411051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 252511051Sandreas.hansson@arm.com{ 252611051Sandreas.hansson@arm.com // handle snooping requests 252711051Sandreas.hansson@arm.com cache->recvTimingSnoopReq(pkt); 252811051Sandreas.hansson@arm.com} 252911051Sandreas.hansson@arm.com 253011051Sandreas.hansson@arm.comTick 253111051Sandreas.hansson@arm.comCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 253211051Sandreas.hansson@arm.com{ 253311051Sandreas.hansson@arm.com return cache->recvAtomicSnoop(pkt); 253411051Sandreas.hansson@arm.com} 253511051Sandreas.hansson@arm.com 253611051Sandreas.hansson@arm.comvoid 253711051Sandreas.hansson@arm.comCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 253811051Sandreas.hansson@arm.com{ 253911051Sandreas.hansson@arm.com // functional snoop (note that in contrast to atomic we don't have 254011051Sandreas.hansson@arm.com // a specific functionalSnoop method, as they have the same 254111051Sandreas.hansson@arm.com // behaviour regardless) 254211051Sandreas.hansson@arm.com cache->functionalAccess(pkt, false); 254311051Sandreas.hansson@arm.com} 254411051Sandreas.hansson@arm.com 254511051Sandreas.hansson@arm.comvoid 254611051Sandreas.hansson@arm.comCache::CacheReqPacketQueue::sendDeferredPacket() 254711051Sandreas.hansson@arm.com{ 254811051Sandreas.hansson@arm.com // sanity check 254911051Sandreas.hansson@arm.com assert(!waitingOnRetry); 255011051Sandreas.hansson@arm.com 255111051Sandreas.hansson@arm.com // there should never be any deferred request packets in the 255211051Sandreas.hansson@arm.com // queue, instead we resly on the cache to provide the packets 255311051Sandreas.hansson@arm.com // from the MSHR queue or write queue 255411051Sandreas.hansson@arm.com assert(deferredPacketReadyTime() == MaxTick); 255511051Sandreas.hansson@arm.com 255611051Sandreas.hansson@arm.com // check for request packets (requests & writebacks) 255711051Sandreas.hansson@arm.com PacketPtr pkt = cache.getTimingPacket(); 255811051Sandreas.hansson@arm.com if (pkt == NULL) { 255911051Sandreas.hansson@arm.com // can happen if e.g. we attempt a writeback and fail, but 256011051Sandreas.hansson@arm.com // before the retry, the writeback is eliminated because 256111051Sandreas.hansson@arm.com // we snoop another cache's ReadEx. 256211051Sandreas.hansson@arm.com } else { 256311051Sandreas.hansson@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState); 256411051Sandreas.hansson@arm.com // in most cases getTimingPacket allocates a new packet, and 256511051Sandreas.hansson@arm.com // we must delete it unless it is successfully sent 256611051Sandreas.hansson@arm.com bool delete_pkt = !mshr->isForwardNoResponse(); 256711051Sandreas.hansson@arm.com 256811051Sandreas.hansson@arm.com // let our snoop responses go first if there are responses to 256911051Sandreas.hansson@arm.com // the same addresses we are about to writeback, note that 257011051Sandreas.hansson@arm.com // this creates a dependency between requests and snoop 257111051Sandreas.hansson@arm.com // responses, but that should not be a problem since there is 257211051Sandreas.hansson@arm.com // a chain already and the key is that the snoop responses can 257311051Sandreas.hansson@arm.com // sink unconditionally 257411051Sandreas.hansson@arm.com if (snoopRespQueue.hasAddr(pkt->getAddr())) { 257511051Sandreas.hansson@arm.com DPRINTF(CachePort, "Waiting for snoop response to be sent\n"); 257611051Sandreas.hansson@arm.com Tick when = snoopRespQueue.deferredPacketReadyTime(); 257711051Sandreas.hansson@arm.com schedSendEvent(when); 257811051Sandreas.hansson@arm.com 257911051Sandreas.hansson@arm.com if (delete_pkt) 258011051Sandreas.hansson@arm.com delete pkt; 258111051Sandreas.hansson@arm.com 258211051Sandreas.hansson@arm.com return; 258311051Sandreas.hansson@arm.com } 258411051Sandreas.hansson@arm.com 258511051Sandreas.hansson@arm.com 258611051Sandreas.hansson@arm.com waitingOnRetry = !masterPort.sendTimingReq(pkt); 258711051Sandreas.hansson@arm.com 258811051Sandreas.hansson@arm.com if (waitingOnRetry) { 258911051Sandreas.hansson@arm.com DPRINTF(CachePort, "now waiting on a retry\n"); 259011051Sandreas.hansson@arm.com if (delete_pkt) { 259111051Sandreas.hansson@arm.com // we are awaiting a retry, but we 259211051Sandreas.hansson@arm.com // delete the packet and will be creating a new packet 259311051Sandreas.hansson@arm.com // when we get the opportunity 259411051Sandreas.hansson@arm.com delete pkt; 259511051Sandreas.hansson@arm.com } 259611051Sandreas.hansson@arm.com // note that we have now masked any requestBus and 259711051Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 259811051Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 259911051Sandreas.hansson@arm.com // care about this packet and might override it before 260011051Sandreas.hansson@arm.com // it gets retried 260111051Sandreas.hansson@arm.com } else { 260211051Sandreas.hansson@arm.com // As part of the call to sendTimingReq the packet is 260311051Sandreas.hansson@arm.com // forwarded to all neighbouring caches (and any 260411051Sandreas.hansson@arm.com // caches above them) as a snoop. The packet is also 260511051Sandreas.hansson@arm.com // sent to any potential cache below as the 260611051Sandreas.hansson@arm.com // interconnect is not allowed to buffer the 260711051Sandreas.hansson@arm.com // packet. Thus at this point we know if any of the 260811051Sandreas.hansson@arm.com // neighbouring, or the downstream cache is 260911051Sandreas.hansson@arm.com // responding, and if so, if it is with a dirty line 261011051Sandreas.hansson@arm.com // or not. 261111051Sandreas.hansson@arm.com bool pending_dirty_resp = !pkt->sharedAsserted() && 261211051Sandreas.hansson@arm.com pkt->memInhibitAsserted(); 261311051Sandreas.hansson@arm.com 261411051Sandreas.hansson@arm.com cache.markInService(mshr, pending_dirty_resp); 261511051Sandreas.hansson@arm.com } 261611051Sandreas.hansson@arm.com } 261711051Sandreas.hansson@arm.com 261811051Sandreas.hansson@arm.com // if we succeeded and are not waiting for a retry, schedule the 261911051Sandreas.hansson@arm.com // next send considering when the next MSHR is ready, note that 262011051Sandreas.hansson@arm.com // snoop responses have their own packet queue and thus schedule 262111051Sandreas.hansson@arm.com // their own events 262211051Sandreas.hansson@arm.com if (!waitingOnRetry) { 262311051Sandreas.hansson@arm.com schedSendEvent(cache.nextMSHRReadyTime()); 262411051Sandreas.hansson@arm.com } 262511051Sandreas.hansson@arm.com} 262611051Sandreas.hansson@arm.com 262711051Sandreas.hansson@arm.comCache:: 262811051Sandreas.hansson@arm.comMemSidePort::MemSidePort(const std::string &_name, Cache *_cache, 262911051Sandreas.hansson@arm.com const std::string &_label) 263011051Sandreas.hansson@arm.com : BaseCache::CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 263111051Sandreas.hansson@arm.com _reqQueue(*_cache, *this, _snoopRespQueue, _label), 263211051Sandreas.hansson@arm.com _snoopRespQueue(*_cache, *this, _label), cache(_cache) 263311051Sandreas.hansson@arm.com{ 263411051Sandreas.hansson@arm.com} 2635