cache.cc revision 11081
12810Srdreslin@umich.edu/* 211051Sandreas.hansson@arm.com * Copyright (c) 2010-2015 ARM Limited 311051Sandreas.hansson@arm.com * All rights reserved. 411051Sandreas.hansson@arm.com * 511051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911051Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311051Sandreas.hansson@arm.com * 1411051Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511051Sandreas.hansson@arm.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 162810Srdreslin@umich.edu * All rights reserved. 172810Srdreslin@umich.edu * 182810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 192810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 202810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 212810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 222810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 232810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 242810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 252810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 262810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 272810Srdreslin@umich.edu * this software without specific prior written permission. 282810Srdreslin@umich.edu * 292810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810Srdreslin@umich.edu * 412810Srdreslin@umich.edu * Authors: Erik Hallnor 4211051Sandreas.hansson@arm.com * Dave Greene 4311051Sandreas.hansson@arm.com * Nathan Binkert 442810Srdreslin@umich.edu * Steve Reinhardt 4511051Sandreas.hansson@arm.com * Ron Dreslinski 4611051Sandreas.hansson@arm.com * Andreas Sandberg 472810Srdreslin@umich.edu */ 482810Srdreslin@umich.edu 492810Srdreslin@umich.edu/** 502810Srdreslin@umich.edu * @file 5111051Sandreas.hansson@arm.com * Cache definitions. 522810Srdreslin@umich.edu */ 532810Srdreslin@umich.edu 5411051Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 552810Srdreslin@umich.edu 5611051Sandreas.hansson@arm.com#include "base/misc.hh" 5711051Sandreas.hansson@arm.com#include "base/types.hh" 5811051Sandreas.hansson@arm.com#include "debug/Cache.hh" 5911051Sandreas.hansson@arm.com#include "debug/CachePort.hh" 6011051Sandreas.hansson@arm.com#include "debug/CacheTags.hh" 6111051Sandreas.hansson@arm.com#include "mem/cache/blk.hh" 6211051Sandreas.hansson@arm.com#include "mem/cache/mshr.hh" 6311051Sandreas.hansson@arm.com#include "mem/cache/prefetch/base.hh" 6411051Sandreas.hansson@arm.com#include "sim/sim_exit.hh" 6511051Sandreas.hansson@arm.com 6611053Sandreas.hansson@arm.comCache::Cache(const CacheParams *p) 6711053Sandreas.hansson@arm.com : BaseCache(p, p->system->cacheLineSize()), 6811051Sandreas.hansson@arm.com tags(p->tags), 6911051Sandreas.hansson@arm.com prefetcher(p->prefetcher), 7011051Sandreas.hansson@arm.com doFastWrites(true), 7111051Sandreas.hansson@arm.com prefetchOnAccess(p->prefetch_on_access) 7211051Sandreas.hansson@arm.com{ 7311051Sandreas.hansson@arm.com tempBlock = new CacheBlk(); 7411051Sandreas.hansson@arm.com tempBlock->data = new uint8_t[blkSize]; 7511051Sandreas.hansson@arm.com 7611051Sandreas.hansson@arm.com cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this, 7711051Sandreas.hansson@arm.com "CpuSidePort"); 7811051Sandreas.hansson@arm.com memSidePort = new MemSidePort(p->name + ".mem_side", this, 7911051Sandreas.hansson@arm.com "MemSidePort"); 8011051Sandreas.hansson@arm.com 8111051Sandreas.hansson@arm.com tags->setCache(this); 8211051Sandreas.hansson@arm.com if (prefetcher) 8311051Sandreas.hansson@arm.com prefetcher->setCache(this); 8411051Sandreas.hansson@arm.com} 8511051Sandreas.hansson@arm.com 8611051Sandreas.hansson@arm.comCache::~Cache() 8711051Sandreas.hansson@arm.com{ 8811051Sandreas.hansson@arm.com delete [] tempBlock->data; 8911051Sandreas.hansson@arm.com delete tempBlock; 9011051Sandreas.hansson@arm.com 9111051Sandreas.hansson@arm.com delete cpuSidePort; 9211051Sandreas.hansson@arm.com delete memSidePort; 9311051Sandreas.hansson@arm.com} 9411051Sandreas.hansson@arm.com 9511051Sandreas.hansson@arm.comvoid 9611051Sandreas.hansson@arm.comCache::regStats() 9711051Sandreas.hansson@arm.com{ 9811051Sandreas.hansson@arm.com BaseCache::regStats(); 9911051Sandreas.hansson@arm.com} 10011051Sandreas.hansson@arm.com 10111051Sandreas.hansson@arm.comvoid 10211051Sandreas.hansson@arm.comCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 10311051Sandreas.hansson@arm.com{ 10411051Sandreas.hansson@arm.com assert(pkt->isRequest()); 10511051Sandreas.hansson@arm.com 10611051Sandreas.hansson@arm.com uint64_t overwrite_val; 10711051Sandreas.hansson@arm.com bool overwrite_mem; 10811051Sandreas.hansson@arm.com uint64_t condition_val64; 10911051Sandreas.hansson@arm.com uint32_t condition_val32; 11011051Sandreas.hansson@arm.com 11111051Sandreas.hansson@arm.com int offset = tags->extractBlkOffset(pkt->getAddr()); 11211051Sandreas.hansson@arm.com uint8_t *blk_data = blk->data + offset; 11311051Sandreas.hansson@arm.com 11411051Sandreas.hansson@arm.com assert(sizeof(uint64_t) >= pkt->getSize()); 11511051Sandreas.hansson@arm.com 11611051Sandreas.hansson@arm.com overwrite_mem = true; 11711051Sandreas.hansson@arm.com // keep a copy of our possible write value, and copy what is at the 11811051Sandreas.hansson@arm.com // memory address into the packet 11911051Sandreas.hansson@arm.com pkt->writeData((uint8_t *)&overwrite_val); 12011051Sandreas.hansson@arm.com pkt->setData(blk_data); 12111051Sandreas.hansson@arm.com 12211051Sandreas.hansson@arm.com if (pkt->req->isCondSwap()) { 12311051Sandreas.hansson@arm.com if (pkt->getSize() == sizeof(uint64_t)) { 12411051Sandreas.hansson@arm.com condition_val64 = pkt->req->getExtraData(); 12511051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val64, blk_data, 12611051Sandreas.hansson@arm.com sizeof(uint64_t)); 12711051Sandreas.hansson@arm.com } else if (pkt->getSize() == sizeof(uint32_t)) { 12811051Sandreas.hansson@arm.com condition_val32 = (uint32_t)pkt->req->getExtraData(); 12911051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val32, blk_data, 13011051Sandreas.hansson@arm.com sizeof(uint32_t)); 13111051Sandreas.hansson@arm.com } else 13211051Sandreas.hansson@arm.com panic("Invalid size for conditional read/write\n"); 13311051Sandreas.hansson@arm.com } 13411051Sandreas.hansson@arm.com 13511051Sandreas.hansson@arm.com if (overwrite_mem) { 13611051Sandreas.hansson@arm.com std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 13711051Sandreas.hansson@arm.com blk->status |= BlkDirty; 13811051Sandreas.hansson@arm.com } 13911051Sandreas.hansson@arm.com} 14011051Sandreas.hansson@arm.com 14111051Sandreas.hansson@arm.com 14211051Sandreas.hansson@arm.comvoid 14311051Sandreas.hansson@arm.comCache::satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk, 14411051Sandreas.hansson@arm.com bool deferred_response, bool pending_downgrade) 14511051Sandreas.hansson@arm.com{ 14611051Sandreas.hansson@arm.com assert(pkt->isRequest()); 14711051Sandreas.hansson@arm.com 14811051Sandreas.hansson@arm.com assert(blk && blk->isValid()); 14911051Sandreas.hansson@arm.com // Occasionally this is not true... if we are a lower-level cache 15011051Sandreas.hansson@arm.com // satisfying a string of Read and ReadEx requests from 15111051Sandreas.hansson@arm.com // upper-level caches, a Read will mark the block as shared but we 15211051Sandreas.hansson@arm.com // can satisfy a following ReadEx anyway since we can rely on the 15311051Sandreas.hansson@arm.com // Read requester(s) to have buffered the ReadEx snoop and to 15411051Sandreas.hansson@arm.com // invalidate their blocks after receiving them. 15511051Sandreas.hansson@arm.com // assert(!pkt->needsExclusive() || blk->isWritable()); 15611051Sandreas.hansson@arm.com assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 15711051Sandreas.hansson@arm.com 15811051Sandreas.hansson@arm.com // Check RMW operations first since both isRead() and 15911051Sandreas.hansson@arm.com // isWrite() will be true for them 16011051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::SwapReq) { 16111051Sandreas.hansson@arm.com cmpAndSwap(blk, pkt); 16211051Sandreas.hansson@arm.com } else if (pkt->isWrite()) { 16311051Sandreas.hansson@arm.com assert(blk->isWritable()); 16411051Sandreas.hansson@arm.com // Write or WriteLine at the first cache with block in Exclusive 16511051Sandreas.hansson@arm.com if (blk->checkWrite(pkt)) { 16611051Sandreas.hansson@arm.com pkt->writeDataToBlock(blk->data, blkSize); 16711051Sandreas.hansson@arm.com } 16811051Sandreas.hansson@arm.com // Always mark the line as dirty even if we are a failed 16911051Sandreas.hansson@arm.com // StoreCond so we supply data to any snoops that have 17011051Sandreas.hansson@arm.com // appended themselves to this cache before knowing the store 17111051Sandreas.hansson@arm.com // will fail. 17211051Sandreas.hansson@arm.com blk->status |= BlkDirty; 17311051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d (write)\n", __func__, 17411051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 17511051Sandreas.hansson@arm.com } else if (pkt->isRead()) { 17611051Sandreas.hansson@arm.com if (pkt->isLLSC()) { 17711051Sandreas.hansson@arm.com blk->trackLoadLocked(pkt); 17811051Sandreas.hansson@arm.com } 17911051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 18011051Sandreas.hansson@arm.com // determine if this read is from a (coherent) cache, or not 18111051Sandreas.hansson@arm.com // by looking at the command type; we could potentially add a 18211051Sandreas.hansson@arm.com // packet attribute such as 'FromCache' to make this check a 18311051Sandreas.hansson@arm.com // bit cleaner 18411051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadExReq || 18511051Sandreas.hansson@arm.com pkt->cmd == MemCmd::ReadSharedReq || 18611051Sandreas.hansson@arm.com pkt->cmd == MemCmd::ReadCleanReq || 18711051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq) { 18811051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 18911051Sandreas.hansson@arm.com // special handling for coherent block requests from 19011051Sandreas.hansson@arm.com // upper-level caches 19111051Sandreas.hansson@arm.com if (pkt->needsExclusive()) { 19211051Sandreas.hansson@arm.com // sanity check 19311051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::ReadExReq || 19411051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq); 19511051Sandreas.hansson@arm.com 19611051Sandreas.hansson@arm.com // if we have a dirty copy, make sure the recipient 19711051Sandreas.hansson@arm.com // keeps it marked dirty 19811051Sandreas.hansson@arm.com if (blk->isDirty()) { 19911051Sandreas.hansson@arm.com pkt->assertMemInhibit(); 20011051Sandreas.hansson@arm.com } 20111051Sandreas.hansson@arm.com // on ReadExReq we give up our copy unconditionally 20211051Sandreas.hansson@arm.com if (blk != tempBlock) 20311051Sandreas.hansson@arm.com tags->invalidate(blk); 20411051Sandreas.hansson@arm.com blk->invalidate(); 20511051Sandreas.hansson@arm.com } else if (blk->isWritable() && !pending_downgrade && 20611051Sandreas.hansson@arm.com !pkt->sharedAsserted() && 20711051Sandreas.hansson@arm.com pkt->cmd != MemCmd::ReadCleanReq) { 20811051Sandreas.hansson@arm.com // we can give the requester an exclusive copy (by not 20911051Sandreas.hansson@arm.com // asserting shared line) on a read request if: 21011051Sandreas.hansson@arm.com // - we have an exclusive copy at this level (& below) 21111051Sandreas.hansson@arm.com // - we don't have a pending snoop from below 21211051Sandreas.hansson@arm.com // signaling another read request 21311051Sandreas.hansson@arm.com // - no other cache above has a copy (otherwise it 21411051Sandreas.hansson@arm.com // would have asseretd shared line on request) 21511051Sandreas.hansson@arm.com // - we are not satisfying an instruction fetch (this 21611051Sandreas.hansson@arm.com // prevents dirty data in the i-cache) 21711051Sandreas.hansson@arm.com 21811051Sandreas.hansson@arm.com if (blk->isDirty()) { 21911051Sandreas.hansson@arm.com // special considerations if we're owner: 22011051Sandreas.hansson@arm.com if (!deferred_response) { 22111051Sandreas.hansson@arm.com // if we are responding immediately and can 22211051Sandreas.hansson@arm.com // signal that we're transferring ownership 22311051Sandreas.hansson@arm.com // along with exclusivity, do so 22411051Sandreas.hansson@arm.com pkt->assertMemInhibit(); 22511051Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 22611051Sandreas.hansson@arm.com } else { 22711051Sandreas.hansson@arm.com // if we're responding after our own miss, 22811051Sandreas.hansson@arm.com // there's a window where the recipient didn't 22911051Sandreas.hansson@arm.com // know it was getting ownership and may not 23011051Sandreas.hansson@arm.com // have responded to snoops correctly, so we 23111051Sandreas.hansson@arm.com // can't pass off ownership *or* exclusivity 23211051Sandreas.hansson@arm.com pkt->assertShared(); 23311051Sandreas.hansson@arm.com } 23411051Sandreas.hansson@arm.com } 23511051Sandreas.hansson@arm.com } else { 23611051Sandreas.hansson@arm.com // otherwise only respond with a shared copy 23711051Sandreas.hansson@arm.com pkt->assertShared(); 23811051Sandreas.hansson@arm.com } 23911051Sandreas.hansson@arm.com } 24011051Sandreas.hansson@arm.com } else { 24111051Sandreas.hansson@arm.com // Upgrade or Invalidate, since we have it Exclusively (E or 24211051Sandreas.hansson@arm.com // M), we ack then invalidate. 24311051Sandreas.hansson@arm.com assert(pkt->isUpgrade() || pkt->isInvalidate()); 24411051Sandreas.hansson@arm.com assert(blk != tempBlock); 24511051Sandreas.hansson@arm.com tags->invalidate(blk); 24611051Sandreas.hansson@arm.com blk->invalidate(); 24711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d (invalidation)\n", 24811051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 24911051Sandreas.hansson@arm.com } 25011051Sandreas.hansson@arm.com} 25111051Sandreas.hansson@arm.com 25211051Sandreas.hansson@arm.com 25311051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 25411051Sandreas.hansson@arm.com// 25511051Sandreas.hansson@arm.com// MSHR helper functions 25611051Sandreas.hansson@arm.com// 25711051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 25811051Sandreas.hansson@arm.com 25911051Sandreas.hansson@arm.com 26011051Sandreas.hansson@arm.comvoid 26111051Sandreas.hansson@arm.comCache::markInService(MSHR *mshr, bool pending_dirty_resp) 26211051Sandreas.hansson@arm.com{ 26311051Sandreas.hansson@arm.com markInServiceInternal(mshr, pending_dirty_resp); 26411051Sandreas.hansson@arm.com} 26511051Sandreas.hansson@arm.com 26611051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 26711051Sandreas.hansson@arm.com// 26811051Sandreas.hansson@arm.com// Access path: requests coming in from the CPU side 26911051Sandreas.hansson@arm.com// 27011051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 27111051Sandreas.hansson@arm.com 27211051Sandreas.hansson@arm.combool 27311051Sandreas.hansson@arm.comCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 27411051Sandreas.hansson@arm.com PacketList &writebacks) 27511051Sandreas.hansson@arm.com{ 27611051Sandreas.hansson@arm.com // sanity check 27711051Sandreas.hansson@arm.com assert(pkt->isRequest()); 27811051Sandreas.hansson@arm.com 27911051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 28011051Sandreas.hansson@arm.com "Should never see a write in a read-only cache %s\n", 28111051Sandreas.hansson@arm.com name()); 28211051Sandreas.hansson@arm.com 28311051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 28411051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 28511051Sandreas.hansson@arm.com 28611051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 28711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s%s addr %#llx uncacheable\n", pkt->cmdString(), 28811051Sandreas.hansson@arm.com pkt->req->isInstFetch() ? " (ifetch)" : "", 28911051Sandreas.hansson@arm.com pkt->getAddr()); 29011051Sandreas.hansson@arm.com 29111051Sandreas.hansson@arm.com // flush and invalidate any existing block 29211051Sandreas.hansson@arm.com CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure())); 29311051Sandreas.hansson@arm.com if (old_blk && old_blk->isValid()) { 29411051Sandreas.hansson@arm.com if (old_blk->isDirty()) 29511051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(old_blk)); 29611051Sandreas.hansson@arm.com else 29711051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(old_blk)); 29811051Sandreas.hansson@arm.com tags->invalidate(old_blk); 29911051Sandreas.hansson@arm.com old_blk->invalidate(); 30011051Sandreas.hansson@arm.com } 30111051Sandreas.hansson@arm.com 30211051Sandreas.hansson@arm.com blk = NULL; 30311051Sandreas.hansson@arm.com // lookupLatency is the latency in case the request is uncacheable. 30411051Sandreas.hansson@arm.com lat = lookupLatency; 30511051Sandreas.hansson@arm.com return false; 30611051Sandreas.hansson@arm.com } 30711051Sandreas.hansson@arm.com 30811051Sandreas.hansson@arm.com ContextID id = pkt->req->hasContextId() ? 30911051Sandreas.hansson@arm.com pkt->req->contextId() : InvalidContextID; 31011051Sandreas.hansson@arm.com // Here lat is the value passed as parameter to accessBlock() function 31111051Sandreas.hansson@arm.com // that can modify its value. 31211051Sandreas.hansson@arm.com blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat, id); 31311051Sandreas.hansson@arm.com 31411051Sandreas.hansson@arm.com DPRINTF(Cache, "%s%s addr %#llx size %d (%s) %s\n", pkt->cmdString(), 31511051Sandreas.hansson@arm.com pkt->req->isInstFetch() ? " (ifetch)" : "", 31611051Sandreas.hansson@arm.com pkt->getAddr(), pkt->getSize(), pkt->isSecure() ? "s" : "ns", 31711051Sandreas.hansson@arm.com blk ? "hit " + blk->print() : "miss"); 31811051Sandreas.hansson@arm.com 31911051Sandreas.hansson@arm.com 32011051Sandreas.hansson@arm.com if (pkt->evictingBlock()) { 32111051Sandreas.hansson@arm.com // We check for presence of block in above caches before issuing 32211051Sandreas.hansson@arm.com // Writeback or CleanEvict to write buffer. Therefore the only 32311051Sandreas.hansson@arm.com // possible cases can be of a CleanEvict packet coming from above 32411051Sandreas.hansson@arm.com // encountering a Writeback generated in this cache peer cache and 32511051Sandreas.hansson@arm.com // waiting in the write buffer. Cases of upper level peer caches 32611051Sandreas.hansson@arm.com // generating CleanEvict and Writeback or simply CleanEvict and 32711051Sandreas.hansson@arm.com // CleanEvict almost simultaneously will be caught by snoops sent out 32811051Sandreas.hansson@arm.com // by crossbar. 32911051Sandreas.hansson@arm.com std::vector<MSHR *> outgoing; 33011051Sandreas.hansson@arm.com if (writeBuffer.findMatches(pkt->getAddr(), pkt->isSecure(), 33111051Sandreas.hansson@arm.com outgoing)) { 33211051Sandreas.hansson@arm.com assert(outgoing.size() == 1); 33311051Sandreas.hansson@arm.com PacketPtr wbPkt = outgoing[0]->getTarget()->pkt; 33411051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::CleanEvict && 33511051Sandreas.hansson@arm.com wbPkt->cmd == MemCmd::Writeback); 33611051Sandreas.hansson@arm.com // As the CleanEvict is coming from above, it would have snooped 33711051Sandreas.hansson@arm.com // into other peer caches of the same level while traversing the 33811051Sandreas.hansson@arm.com // crossbar. If a copy of the block had been found, the CleanEvict 33911051Sandreas.hansson@arm.com // would have been deleted in the crossbar. Now that the 34011051Sandreas.hansson@arm.com // CleanEvict is here we can be sure none of the other upper level 34111051Sandreas.hansson@arm.com // caches connected to this cache have the block, so we can clear 34211051Sandreas.hansson@arm.com // the BLOCK_CACHED flag in the Writeback if set and discard the 34311051Sandreas.hansson@arm.com // CleanEvict by returning true. 34411051Sandreas.hansson@arm.com wbPkt->clearBlockCached(); 34511051Sandreas.hansson@arm.com return true; 34611051Sandreas.hansson@arm.com } 34711051Sandreas.hansson@arm.com } 34811051Sandreas.hansson@arm.com 34911051Sandreas.hansson@arm.com // Writeback handling is special case. We can write the block into 35011051Sandreas.hansson@arm.com // the cache without having a writeable copy (or any copy at all). 35111051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::Writeback) { 35211051Sandreas.hansson@arm.com assert(blkSize == pkt->getSize()); 35311051Sandreas.hansson@arm.com if (blk == NULL) { 35411051Sandreas.hansson@arm.com // need to do a replacement 35511051Sandreas.hansson@arm.com blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks); 35611051Sandreas.hansson@arm.com if (blk == NULL) { 35711051Sandreas.hansson@arm.com // no replaceable block available: give up, fwd to next level. 35811051Sandreas.hansson@arm.com incMissCount(pkt); 35911051Sandreas.hansson@arm.com return false; 36011051Sandreas.hansson@arm.com } 36111051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 36211051Sandreas.hansson@arm.com 36311051Sandreas.hansson@arm.com blk->status = (BlkValid | BlkReadable); 36411051Sandreas.hansson@arm.com if (pkt->isSecure()) { 36511051Sandreas.hansson@arm.com blk->status |= BlkSecure; 36611051Sandreas.hansson@arm.com } 36711051Sandreas.hansson@arm.com } 36811051Sandreas.hansson@arm.com blk->status |= BlkDirty; 36911051Sandreas.hansson@arm.com // if shared is not asserted we got the writeback in modified 37011051Sandreas.hansson@arm.com // state, if it is asserted we are in the owned state 37111051Sandreas.hansson@arm.com if (!pkt->sharedAsserted()) { 37211051Sandreas.hansson@arm.com blk->status |= BlkWritable; 37311051Sandreas.hansson@arm.com } 37411051Sandreas.hansson@arm.com // nothing else to do; writeback doesn't expect response 37511051Sandreas.hansson@arm.com assert(!pkt->needsResponse()); 37611051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 37711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 37811051Sandreas.hansson@arm.com incHitCount(pkt); 37911051Sandreas.hansson@arm.com return true; 38011051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::CleanEvict) { 38111051Sandreas.hansson@arm.com if (blk != NULL) { 38211051Sandreas.hansson@arm.com // Found the block in the tags, need to stop CleanEvict from 38311051Sandreas.hansson@arm.com // propagating further down the hierarchy. Returning true will 38411051Sandreas.hansson@arm.com // treat the CleanEvict like a satisfied write request and delete 38511051Sandreas.hansson@arm.com // it. 38611051Sandreas.hansson@arm.com return true; 38711051Sandreas.hansson@arm.com } 38811051Sandreas.hansson@arm.com // We didn't find the block here, propagate the CleanEvict further 38911051Sandreas.hansson@arm.com // down the memory hierarchy. Returning false will treat the CleanEvict 39011051Sandreas.hansson@arm.com // like a Writeback which could not find a replaceable block so has to 39111051Sandreas.hansson@arm.com // go to next level. 39211051Sandreas.hansson@arm.com return false; 39311051Sandreas.hansson@arm.com } else if ((blk != NULL) && 39411051Sandreas.hansson@arm.com (pkt->needsExclusive() ? blk->isWritable() 39511051Sandreas.hansson@arm.com : blk->isReadable())) { 39611051Sandreas.hansson@arm.com // OK to satisfy access 39711051Sandreas.hansson@arm.com incHitCount(pkt); 39811051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 39911051Sandreas.hansson@arm.com return true; 40011051Sandreas.hansson@arm.com } 40111051Sandreas.hansson@arm.com 40211051Sandreas.hansson@arm.com // Can't satisfy access normally... either no block (blk == NULL) 40311051Sandreas.hansson@arm.com // or have block but need exclusive & only have shared. 40411051Sandreas.hansson@arm.com 40511051Sandreas.hansson@arm.com incMissCount(pkt); 40611051Sandreas.hansson@arm.com 40711051Sandreas.hansson@arm.com if (blk == NULL && pkt->isLLSC() && pkt->isWrite()) { 40811051Sandreas.hansson@arm.com // complete miss on store conditional... just give up now 40911051Sandreas.hansson@arm.com pkt->req->setExtraData(0); 41011051Sandreas.hansson@arm.com return true; 41111051Sandreas.hansson@arm.com } 41211051Sandreas.hansson@arm.com 41311051Sandreas.hansson@arm.com return false; 41411051Sandreas.hansson@arm.com} 41511051Sandreas.hansson@arm.com 41611051Sandreas.hansson@arm.com 41711051Sandreas.hansson@arm.comclass ForwardResponseRecord : public Packet::SenderState 41811051Sandreas.hansson@arm.com{ 41911051Sandreas.hansson@arm.com public: 42011051Sandreas.hansson@arm.com 42111051Sandreas.hansson@arm.com ForwardResponseRecord() {} 42211051Sandreas.hansson@arm.com}; 42311051Sandreas.hansson@arm.com 42411051Sandreas.hansson@arm.comvoid 42511051Sandreas.hansson@arm.comCache::doWritebacks(PacketList& writebacks, Tick forward_time) 42611051Sandreas.hansson@arm.com{ 42711051Sandreas.hansson@arm.com while (!writebacks.empty()) { 42811051Sandreas.hansson@arm.com PacketPtr wbPkt = writebacks.front(); 42911051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying writebacks to 43011051Sandreas.hansson@arm.com // write buffer. Call isCachedAbove for both Writebacks and 43111051Sandreas.hansson@arm.com // CleanEvicts. If isCachedAbove returns true we set BLOCK_CACHED flag 43211051Sandreas.hansson@arm.com // in Writebacks and discard CleanEvicts. 43311051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) { 43411051Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::CleanEvict) { 43511051Sandreas.hansson@arm.com // Delete CleanEvict because cached copies exist above. The 43611051Sandreas.hansson@arm.com // packet destructor will delete the request object because 43711051Sandreas.hansson@arm.com // this is a non-snoop request packet which does not require a 43811051Sandreas.hansson@arm.com // response. 43911051Sandreas.hansson@arm.com delete wbPkt; 44011051Sandreas.hansson@arm.com } else { 44111051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag in Writeback and send below, so that 44211051Sandreas.hansson@arm.com // the Writeback does not reset the bit corresponding to this 44311051Sandreas.hansson@arm.com // address in the snoop filter below. 44411051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 44511051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 44611051Sandreas.hansson@arm.com } 44711051Sandreas.hansson@arm.com } else { 44811051Sandreas.hansson@arm.com // If the block is not cached above, send packet below. Both 44911051Sandreas.hansson@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 45011051Sandreas.hansson@arm.com // reset the bit corresponding to this address in the snoop filter 45111051Sandreas.hansson@arm.com // below. 45211051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 45311051Sandreas.hansson@arm.com } 45411051Sandreas.hansson@arm.com writebacks.pop_front(); 45511051Sandreas.hansson@arm.com } 45611051Sandreas.hansson@arm.com} 45711051Sandreas.hansson@arm.com 45811051Sandreas.hansson@arm.com 45911051Sandreas.hansson@arm.comvoid 46011051Sandreas.hansson@arm.comCache::recvTimingSnoopResp(PacketPtr pkt) 46111051Sandreas.hansson@arm.com{ 46211051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 46311051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 46411051Sandreas.hansson@arm.com 46511051Sandreas.hansson@arm.com assert(pkt->isResponse()); 46611051Sandreas.hansson@arm.com 46711051Sandreas.hansson@arm.com // must be cache-to-cache response from upper to lower level 46811051Sandreas.hansson@arm.com ForwardResponseRecord *rec = 46911051Sandreas.hansson@arm.com dynamic_cast<ForwardResponseRecord *>(pkt->senderState); 47011051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 47111051Sandreas.hansson@arm.com 47211051Sandreas.hansson@arm.com if (rec == NULL) { 47311051Sandreas.hansson@arm.com // @todo What guarantee do we have that this HardPFResp is 47411051Sandreas.hansson@arm.com // actually for this cache, and not a cache closer to the 47511051Sandreas.hansson@arm.com // memory? 47611051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::HardPFResp); 47711051Sandreas.hansson@arm.com // Check if it's a prefetch response and handle it. We shouldn't 47811051Sandreas.hansson@arm.com // get any other kinds of responses without FRRs. 47911051Sandreas.hansson@arm.com DPRINTF(Cache, "Got prefetch response from above for addr %#llx (%s)\n", 48011051Sandreas.hansson@arm.com pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 48111051Sandreas.hansson@arm.com recvTimingResp(pkt); 48211051Sandreas.hansson@arm.com return; 48311051Sandreas.hansson@arm.com } 48411051Sandreas.hansson@arm.com 48511051Sandreas.hansson@arm.com pkt->popSenderState(); 48611051Sandreas.hansson@arm.com delete rec; 48711051Sandreas.hansson@arm.com // forwardLatency is set here because there is a response from an 48811051Sandreas.hansson@arm.com // upper level cache. 48911051Sandreas.hansson@arm.com // To pay the delay that occurs if the packet comes from the bus, 49011051Sandreas.hansson@arm.com // we charge also headerDelay. 49111051Sandreas.hansson@arm.com Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay; 49211051Sandreas.hansson@arm.com // Reset the timing of the packet. 49311051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 49411051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, snoop_resp_time); 49511051Sandreas.hansson@arm.com} 49611051Sandreas.hansson@arm.com 49711051Sandreas.hansson@arm.comvoid 49811051Sandreas.hansson@arm.comCache::promoteWholeLineWrites(PacketPtr pkt) 49911051Sandreas.hansson@arm.com{ 50011051Sandreas.hansson@arm.com // Cache line clearing instructions 50111051Sandreas.hansson@arm.com if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) && 50211051Sandreas.hansson@arm.com (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) { 50311051Sandreas.hansson@arm.com pkt->cmd = MemCmd::WriteLineReq; 50411051Sandreas.hansson@arm.com DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n"); 50511051Sandreas.hansson@arm.com } 50611051Sandreas.hansson@arm.com} 50711051Sandreas.hansson@arm.com 50811051Sandreas.hansson@arm.combool 50911051Sandreas.hansson@arm.comCache::recvTimingReq(PacketPtr pkt) 51011051Sandreas.hansson@arm.com{ 51111051Sandreas.hansson@arm.com DPRINTF(CacheTags, "%s tags: %s\n", __func__, tags->print()); 51211051Sandreas.hansson@arm.com//@todo Add back in MemDebug Calls 51311051Sandreas.hansson@arm.com// MemDebug::cacheAccess(pkt); 51411051Sandreas.hansson@arm.com 51511051Sandreas.hansson@arm.com 51611051Sandreas.hansson@arm.com /// @todo temporary hack to deal with memory corruption issue until 51711051Sandreas.hansson@arm.com /// 4-phase transactions are complete 51811051Sandreas.hansson@arm.com for (int x = 0; x < pendingDelete.size(); x++) 51911051Sandreas.hansson@arm.com delete pendingDelete[x]; 52011051Sandreas.hansson@arm.com pendingDelete.clear(); 52111051Sandreas.hansson@arm.com 52211051Sandreas.hansson@arm.com assert(pkt->isRequest()); 52311051Sandreas.hansson@arm.com 52411051Sandreas.hansson@arm.com // Just forward the packet if caches are disabled. 52511051Sandreas.hansson@arm.com if (system->bypassCaches()) { 52611051Sandreas.hansson@arm.com // @todo This should really enqueue the packet rather 52711051Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt); 52811051Sandreas.hansson@arm.com assert(success); 52911051Sandreas.hansson@arm.com return true; 53011051Sandreas.hansson@arm.com } 53111051Sandreas.hansson@arm.com 53211051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 53311051Sandreas.hansson@arm.com 53411051Sandreas.hansson@arm.com if (pkt->memInhibitAsserted()) { 53511051Sandreas.hansson@arm.com // a cache above us (but not where the packet came from) is 53611051Sandreas.hansson@arm.com // responding to the request 53711051Sandreas.hansson@arm.com DPRINTF(Cache, "mem inhibited on addr %#llx (%s): not responding\n", 53811051Sandreas.hansson@arm.com pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 53911051Sandreas.hansson@arm.com 54011051Sandreas.hansson@arm.com // if the packet needs exclusive, and the cache that has 54111051Sandreas.hansson@arm.com // promised to respond (setting the inhibit flag) is not 54211051Sandreas.hansson@arm.com // providing exclusive (it is in O vs M state), we know that 54311051Sandreas.hansson@arm.com // there may be other shared copies in the system; go out and 54411051Sandreas.hansson@arm.com // invalidate them all 54511051Sandreas.hansson@arm.com if (pkt->needsExclusive() && !pkt->isSupplyExclusive()) { 54611051Sandreas.hansson@arm.com // create a downstream express snoop with cleared packet 54711051Sandreas.hansson@arm.com // flags, there is no need to allocate any data as the 54811051Sandreas.hansson@arm.com // packet is merely used to co-ordinate state transitions 54911051Sandreas.hansson@arm.com Packet *snoop_pkt = new Packet(pkt, true, false); 55011051Sandreas.hansson@arm.com 55111051Sandreas.hansson@arm.com // also reset the bus time that the original packet has 55211051Sandreas.hansson@arm.com // not yet paid for 55311051Sandreas.hansson@arm.com snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0; 55411051Sandreas.hansson@arm.com 55511051Sandreas.hansson@arm.com // make this an instantaneous express snoop, and let the 55611051Sandreas.hansson@arm.com // other caches in the system know that the packet is 55711051Sandreas.hansson@arm.com // inhibited, because we have found the authorative copy 55811051Sandreas.hansson@arm.com // (O) that will supply the right data 55911051Sandreas.hansson@arm.com snoop_pkt->setExpressSnoop(); 56011051Sandreas.hansson@arm.com snoop_pkt->assertMemInhibit(); 56111051Sandreas.hansson@arm.com 56211051Sandreas.hansson@arm.com // this express snoop travels towards the memory, and at 56311051Sandreas.hansson@arm.com // every crossbar it is snooped upwards thus reaching 56411051Sandreas.hansson@arm.com // every cache in the system 56511051Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(snoop_pkt); 56611051Sandreas.hansson@arm.com // express snoops always succeed 56711051Sandreas.hansson@arm.com assert(success); 56811051Sandreas.hansson@arm.com 56911051Sandreas.hansson@arm.com // main memory will delete the packet 57011051Sandreas.hansson@arm.com } 57111051Sandreas.hansson@arm.com 57211051Sandreas.hansson@arm.com /// @todo nominally we should just delete the packet here, 57311051Sandreas.hansson@arm.com /// however, until 4-phase stuff we can't because sending 57411051Sandreas.hansson@arm.com /// cache is still relying on it. 57511051Sandreas.hansson@arm.com pendingDelete.push_back(pkt); 57611051Sandreas.hansson@arm.com 57711051Sandreas.hansson@arm.com // no need to take any action in this particular cache as the 57811051Sandreas.hansson@arm.com // caches along the path to memory are allowed to keep lines 57911051Sandreas.hansson@arm.com // in a shared state, and a cache above us already committed 58011051Sandreas.hansson@arm.com // to responding 58111051Sandreas.hansson@arm.com return true; 58211051Sandreas.hansson@arm.com } 58311051Sandreas.hansson@arm.com 58411051Sandreas.hansson@arm.com // anything that is merely forwarded pays for the forward latency and 58511051Sandreas.hansson@arm.com // the delay provided by the crossbar 58611051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 58711051Sandreas.hansson@arm.com 58811051Sandreas.hansson@arm.com // We use lookupLatency here because it is used to specify the latency 58911051Sandreas.hansson@arm.com // to access. 59011051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 59111051Sandreas.hansson@arm.com CacheBlk *blk = NULL; 59211051Sandreas.hansson@arm.com bool satisfied = false; 59311051Sandreas.hansson@arm.com { 59411051Sandreas.hansson@arm.com PacketList writebacks; 59511051Sandreas.hansson@arm.com // Note that lat is passed by reference here. The function 59611051Sandreas.hansson@arm.com // access() calls accessBlock() which can modify lat value. 59711051Sandreas.hansson@arm.com satisfied = access(pkt, blk, lat, writebacks); 59811051Sandreas.hansson@arm.com 59911051Sandreas.hansson@arm.com // copy writebacks to write buffer here to ensure they logically 60011051Sandreas.hansson@arm.com // proceed anything happening below 60111051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 60211051Sandreas.hansson@arm.com } 60311051Sandreas.hansson@arm.com 60411051Sandreas.hansson@arm.com // Here we charge the headerDelay that takes into account the latencies 60511051Sandreas.hansson@arm.com // of the bus, if the packet comes from it. 60611051Sandreas.hansson@arm.com // The latency charged it is just lat that is the value of lookupLatency 60711051Sandreas.hansson@arm.com // modified by access() function, or if not just lookupLatency. 60811051Sandreas.hansson@arm.com // In case of a hit we are neglecting response latency. 60911051Sandreas.hansson@arm.com // In case of a miss we are neglecting forward latency. 61011051Sandreas.hansson@arm.com Tick request_time = clockEdge(lat) + pkt->headerDelay; 61111051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 61211051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 61311051Sandreas.hansson@arm.com 61411051Sandreas.hansson@arm.com // track time of availability of next prefetch, if any 61511051Sandreas.hansson@arm.com Tick next_pf_time = MaxTick; 61611051Sandreas.hansson@arm.com 61711051Sandreas.hansson@arm.com bool needsResponse = pkt->needsResponse(); 61811051Sandreas.hansson@arm.com 61911051Sandreas.hansson@arm.com if (satisfied) { 62011051Sandreas.hansson@arm.com // should never be satisfying an uncacheable access as we 62111051Sandreas.hansson@arm.com // flush and invalidate any existing block as part of the 62211051Sandreas.hansson@arm.com // lookup 62311051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 62411051Sandreas.hansson@arm.com 62511051Sandreas.hansson@arm.com // hit (for all other request types) 62611051Sandreas.hansson@arm.com 62711051Sandreas.hansson@arm.com if (prefetcher && (prefetchOnAccess || (blk && blk->wasPrefetched()))) { 62811051Sandreas.hansson@arm.com if (blk) 62911051Sandreas.hansson@arm.com blk->status &= ~BlkHWPrefetched; 63011051Sandreas.hansson@arm.com 63111051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 63211051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 63311051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 63411051Sandreas.hansson@arm.com } 63511051Sandreas.hansson@arm.com 63611051Sandreas.hansson@arm.com if (needsResponse) { 63711051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 63811051Sandreas.hansson@arm.com // @todo: Make someone pay for this 63911051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 64011051Sandreas.hansson@arm.com 64111051Sandreas.hansson@arm.com // In this case we are considering request_time that takes 64211051Sandreas.hansson@arm.com // into account the delay of the xbar, if any, and just 64311051Sandreas.hansson@arm.com // lat, neglecting responseLatency, modelling hit latency 64411051Sandreas.hansson@arm.com // just as lookupLatency or or the value of lat overriden 64511051Sandreas.hansson@arm.com // by access(), that calls accessBlock() function. 64611051Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(pkt, request_time); 64711051Sandreas.hansson@arm.com } else { 64811051Sandreas.hansson@arm.com /// @todo nominally we should just delete the packet here, 64911051Sandreas.hansson@arm.com /// however, until 4-phase stuff we can't because sending cache is 65011051Sandreas.hansson@arm.com /// still relying on it. If the block is found in access(), 65111051Sandreas.hansson@arm.com /// CleanEvict and Writeback messages will be deleted here as 65211051Sandreas.hansson@arm.com /// well. 65311051Sandreas.hansson@arm.com pendingDelete.push_back(pkt); 65411051Sandreas.hansson@arm.com } 65511051Sandreas.hansson@arm.com } else { 65611051Sandreas.hansson@arm.com // miss 65711051Sandreas.hansson@arm.com 65811051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 65911051Sandreas.hansson@arm.com 66011051Sandreas.hansson@arm.com // ignore any existing MSHR if we are dealing with an 66111051Sandreas.hansson@arm.com // uncacheable request 66211051Sandreas.hansson@arm.com MSHR *mshr = pkt->req->isUncacheable() ? nullptr : 66311051Sandreas.hansson@arm.com mshrQueue.findMatch(blk_addr, pkt->isSecure()); 66411051Sandreas.hansson@arm.com 66511051Sandreas.hansson@arm.com // Software prefetch handling: 66611051Sandreas.hansson@arm.com // To keep the core from waiting on data it won't look at 66711051Sandreas.hansson@arm.com // anyway, send back a response with dummy data. Miss handling 66811051Sandreas.hansson@arm.com // will continue asynchronously. Unfortunately, the core will 66911051Sandreas.hansson@arm.com // insist upon freeing original Packet/Request, so we have to 67011051Sandreas.hansson@arm.com // create a new pair with a different lifecycle. Note that this 67111051Sandreas.hansson@arm.com // processing happens before any MSHR munging on the behalf of 67211051Sandreas.hansson@arm.com // this request because this new Request will be the one stored 67311051Sandreas.hansson@arm.com // into the MSHRs, not the original. 67411051Sandreas.hansson@arm.com if (pkt->cmd.isSWPrefetch()) { 67511051Sandreas.hansson@arm.com assert(needsResponse); 67611051Sandreas.hansson@arm.com assert(pkt->req->hasPaddr()); 67711051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 67811051Sandreas.hansson@arm.com 67911051Sandreas.hansson@arm.com // There's no reason to add a prefetch as an additional target 68011051Sandreas.hansson@arm.com // to an existing MSHR. If an outstanding request is already 68111051Sandreas.hansson@arm.com // in progress, there is nothing for the prefetch to do. 68211051Sandreas.hansson@arm.com // If this is the case, we don't even create a request at all. 68311051Sandreas.hansson@arm.com PacketPtr pf = nullptr; 68411051Sandreas.hansson@arm.com 68511051Sandreas.hansson@arm.com if (!mshr) { 68611051Sandreas.hansson@arm.com // copy the request and create a new SoftPFReq packet 68711051Sandreas.hansson@arm.com RequestPtr req = new Request(pkt->req->getPaddr(), 68811051Sandreas.hansson@arm.com pkt->req->getSize(), 68911051Sandreas.hansson@arm.com pkt->req->getFlags(), 69011051Sandreas.hansson@arm.com pkt->req->masterId()); 69111051Sandreas.hansson@arm.com pf = new Packet(req, pkt->cmd); 69211051Sandreas.hansson@arm.com pf->allocate(); 69311051Sandreas.hansson@arm.com assert(pf->getAddr() == pkt->getAddr()); 69411051Sandreas.hansson@arm.com assert(pf->getSize() == pkt->getSize()); 69511051Sandreas.hansson@arm.com } 69611051Sandreas.hansson@arm.com 69711051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 69811051Sandreas.hansson@arm.com // for debugging, set all the bits in the response data 69911051Sandreas.hansson@arm.com // (also keeps valgrind from complaining when debugging settings 70011051Sandreas.hansson@arm.com // print out instruction results) 70111051Sandreas.hansson@arm.com std::memset(pkt->getPtr<uint8_t>(), 0xFF, pkt->getSize()); 70211051Sandreas.hansson@arm.com // request_time is used here, taking into account lat and the delay 70311051Sandreas.hansson@arm.com // charged if the packet comes from the xbar. 70411051Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(pkt, request_time); 70511051Sandreas.hansson@arm.com 70611051Sandreas.hansson@arm.com // If an outstanding request is in progress (we found an 70711051Sandreas.hansson@arm.com // MSHR) this is set to null 70811051Sandreas.hansson@arm.com pkt = pf; 70911051Sandreas.hansson@arm.com } 71011051Sandreas.hansson@arm.com 71111051Sandreas.hansson@arm.com if (mshr) { 71211051Sandreas.hansson@arm.com /// MSHR hit 71311051Sandreas.hansson@arm.com /// @note writebacks will be checked in getNextMSHR() 71411051Sandreas.hansson@arm.com /// for any conflicting requests to the same block 71511051Sandreas.hansson@arm.com 71611051Sandreas.hansson@arm.com //@todo remove hw_pf here 71711051Sandreas.hansson@arm.com 71811051Sandreas.hansson@arm.com // Coalesce unless it was a software prefetch (see above). 71911051Sandreas.hansson@arm.com if (pkt) { 72011051Sandreas.hansson@arm.com assert(pkt->cmd != MemCmd::Writeback); 72111051Sandreas.hansson@arm.com // CleanEvicts corresponding to blocks which have outstanding 72211051Sandreas.hansson@arm.com // requests in MSHRs can be deleted here. 72311051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::CleanEvict) { 72411051Sandreas.hansson@arm.com pendingDelete.push_back(pkt); 72511051Sandreas.hansson@arm.com } else { 72611051Sandreas.hansson@arm.com DPRINTF(Cache, "%s coalescing MSHR for %s addr %#llx size %d\n", 72711051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), 72811051Sandreas.hansson@arm.com pkt->getSize()); 72911051Sandreas.hansson@arm.com 73011051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 73111051Sandreas.hansson@arm.com mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 73211051Sandreas.hansson@arm.com if (mshr->threadNum != 0/*pkt->req->threadId()*/) { 73311051Sandreas.hansson@arm.com mshr->threadNum = -1; 73411051Sandreas.hansson@arm.com } 73511051Sandreas.hansson@arm.com // We use forward_time here because it is the same 73611051Sandreas.hansson@arm.com // considering new targets. We have multiple 73711051Sandreas.hansson@arm.com // requests for the same address here. It 73811051Sandreas.hansson@arm.com // specifies the latency to allocate an internal 73911051Sandreas.hansson@arm.com // buffer and to schedule an event to the queued 74011051Sandreas.hansson@arm.com // port and also takes into account the additional 74111051Sandreas.hansson@arm.com // delay of the xbar. 74211051Sandreas.hansson@arm.com mshr->allocateTarget(pkt, forward_time, order++); 74311051Sandreas.hansson@arm.com if (mshr->getNumTargets() == numTarget) { 74411051Sandreas.hansson@arm.com noTargetMSHR = mshr; 74511051Sandreas.hansson@arm.com setBlocked(Blocked_NoTargets); 74611051Sandreas.hansson@arm.com // need to be careful with this... if this mshr isn't 74711051Sandreas.hansson@arm.com // ready yet (i.e. time > curTick()), we don't want to 74811051Sandreas.hansson@arm.com // move it ahead of mshrs that are ready 74911051Sandreas.hansson@arm.com // mshrQueue.moveToFront(mshr); 75011051Sandreas.hansson@arm.com } 75111051Sandreas.hansson@arm.com } 75211051Sandreas.hansson@arm.com // We should call the prefetcher reguardless if the request is 75311051Sandreas.hansson@arm.com // satisfied or not, reguardless if the request is in the MSHR or 75411051Sandreas.hansson@arm.com // not. The request could be a ReadReq hit, but still not 75511051Sandreas.hansson@arm.com // satisfied (potentially because of a prior write to the same 75611051Sandreas.hansson@arm.com // cache line. So, even when not satisfied, tehre is an MSHR 75711051Sandreas.hansson@arm.com // already allocated for this, we need to let the prefetcher know 75811051Sandreas.hansson@arm.com // about the request 75911051Sandreas.hansson@arm.com if (prefetcher) { 76011051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 76111051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 76211051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 76311051Sandreas.hansson@arm.com } 76411051Sandreas.hansson@arm.com } 76511051Sandreas.hansson@arm.com } else { 76611051Sandreas.hansson@arm.com // no MSHR 76711051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 76811051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 76911051Sandreas.hansson@arm.com mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++; 77011051Sandreas.hansson@arm.com } else { 77111051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 77211051Sandreas.hansson@arm.com } 77311051Sandreas.hansson@arm.com 77411051Sandreas.hansson@arm.com if (pkt->evictingBlock() || 77511051Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 77611051Sandreas.hansson@arm.com // We use forward_time here because there is an 77711051Sandreas.hansson@arm.com // uncached memory write, forwarded to WriteBuffer. 77811051Sandreas.hansson@arm.com allocateWriteBuffer(pkt, forward_time); 77911051Sandreas.hansson@arm.com } else { 78011051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 78111051Sandreas.hansson@arm.com // should have flushed and have no valid block 78211051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 78311051Sandreas.hansson@arm.com 78411051Sandreas.hansson@arm.com // If we have a write miss to a valid block, we 78511051Sandreas.hansson@arm.com // need to mark the block non-readable. Otherwise 78611051Sandreas.hansson@arm.com // if we allow reads while there's an outstanding 78711051Sandreas.hansson@arm.com // write miss, the read could return stale data 78811051Sandreas.hansson@arm.com // out of the cache block... a more aggressive 78911051Sandreas.hansson@arm.com // system could detect the overlap (if any) and 79011051Sandreas.hansson@arm.com // forward data out of the MSHRs, but we don't do 79111051Sandreas.hansson@arm.com // that yet. Note that we do need to leave the 79211051Sandreas.hansson@arm.com // block valid so that it stays in the cache, in 79311051Sandreas.hansson@arm.com // case we get an upgrade response (and hence no 79411051Sandreas.hansson@arm.com // new data) when the write miss completes. 79511051Sandreas.hansson@arm.com // As long as CPUs do proper store/load forwarding 79611051Sandreas.hansson@arm.com // internally, and have a sufficiently weak memory 79711051Sandreas.hansson@arm.com // model, this is probably unnecessary, but at some 79811051Sandreas.hansson@arm.com // point it must have seemed like we needed it... 79911051Sandreas.hansson@arm.com assert(pkt->needsExclusive()); 80011051Sandreas.hansson@arm.com assert(!blk->isWritable()); 80111051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 80211051Sandreas.hansson@arm.com } 80311051Sandreas.hansson@arm.com // Here we are using forward_time, modelling the latency of 80411051Sandreas.hansson@arm.com // a miss (outbound) just as forwardLatency, neglecting the 80511051Sandreas.hansson@arm.com // lookupLatency component. 80611051Sandreas.hansson@arm.com allocateMissBuffer(pkt, forward_time); 80711051Sandreas.hansson@arm.com } 80811051Sandreas.hansson@arm.com 80911051Sandreas.hansson@arm.com if (prefetcher) { 81011051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 81111051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 81211051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 81311051Sandreas.hansson@arm.com } 81411051Sandreas.hansson@arm.com } 81511051Sandreas.hansson@arm.com } 81611051Sandreas.hansson@arm.com 81711051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 81811051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 81911051Sandreas.hansson@arm.com 82011051Sandreas.hansson@arm.com return true; 82111051Sandreas.hansson@arm.com} 82211051Sandreas.hansson@arm.com 82311051Sandreas.hansson@arm.com 82411051Sandreas.hansson@arm.com// See comment in cache.hh. 82511051Sandreas.hansson@arm.comPacketPtr 82611051Sandreas.hansson@arm.comCache::getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk, 82711051Sandreas.hansson@arm.com bool needsExclusive) const 82811051Sandreas.hansson@arm.com{ 82911051Sandreas.hansson@arm.com bool blkValid = blk && blk->isValid(); 83011051Sandreas.hansson@arm.com 83111051Sandreas.hansson@arm.com if (cpu_pkt->req->isUncacheable()) { 83211051Sandreas.hansson@arm.com // note that at the point we see the uncacheable request we 83311051Sandreas.hansson@arm.com // flush any block, but there could be an outstanding MSHR, 83411051Sandreas.hansson@arm.com // and the cache could have filled again before we actually 83511051Sandreas.hansson@arm.com // send out the forwarded uncacheable request (blk could thus 83611051Sandreas.hansson@arm.com // be non-null) 83711051Sandreas.hansson@arm.com return NULL; 83811051Sandreas.hansson@arm.com } 83911051Sandreas.hansson@arm.com 84011051Sandreas.hansson@arm.com if (!blkValid && 84111051Sandreas.hansson@arm.com (cpu_pkt->isUpgrade() || 84211051Sandreas.hansson@arm.com cpu_pkt->evictingBlock())) { 84311051Sandreas.hansson@arm.com // Writebacks that weren't allocated in access() and upgrades 84411051Sandreas.hansson@arm.com // from upper-level caches that missed completely just go 84511051Sandreas.hansson@arm.com // through. 84611051Sandreas.hansson@arm.com return NULL; 84711051Sandreas.hansson@arm.com } 84811051Sandreas.hansson@arm.com 84911051Sandreas.hansson@arm.com assert(cpu_pkt->needsResponse()); 85011051Sandreas.hansson@arm.com 85111051Sandreas.hansson@arm.com MemCmd cmd; 85211051Sandreas.hansson@arm.com // @TODO make useUpgrades a parameter. 85311051Sandreas.hansson@arm.com // Note that ownership protocols require upgrade, otherwise a 85411051Sandreas.hansson@arm.com // write miss on a shared owned block will generate a ReadExcl, 85511051Sandreas.hansson@arm.com // which will clobber the owned copy. 85611051Sandreas.hansson@arm.com const bool useUpgrades = true; 85711051Sandreas.hansson@arm.com if (blkValid && useUpgrades) { 85811051Sandreas.hansson@arm.com // only reason to be here is that blk is shared 85911051Sandreas.hansson@arm.com // (read-only) and we need exclusive 86011051Sandreas.hansson@arm.com assert(needsExclusive); 86111051Sandreas.hansson@arm.com assert(!blk->isWritable()); 86211051Sandreas.hansson@arm.com cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq; 86311051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq || 86411051Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::StoreCondFailReq) { 86511051Sandreas.hansson@arm.com // Even though this SC will fail, we still need to send out the 86611051Sandreas.hansson@arm.com // request and get the data to supply it to other snoopers in the case 86711051Sandreas.hansson@arm.com // where the determination the StoreCond fails is delayed due to 86811051Sandreas.hansson@arm.com // all caches not being on the same local bus. 86911051Sandreas.hansson@arm.com cmd = MemCmd::SCUpgradeFailReq; 87011051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::WriteLineReq) { 87111051Sandreas.hansson@arm.com // forward as invalidate to all other caches, this gives us 87211051Sandreas.hansson@arm.com // the line in exclusive state, and invalidates all other 87311051Sandreas.hansson@arm.com // copies 87411051Sandreas.hansson@arm.com cmd = MemCmd::InvalidateReq; 87511051Sandreas.hansson@arm.com } else { 87611051Sandreas.hansson@arm.com // block is invalid 87711051Sandreas.hansson@arm.com cmd = needsExclusive ? MemCmd::ReadExReq : 87811051Sandreas.hansson@arm.com (isReadOnly ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq); 87911051Sandreas.hansson@arm.com } 88011051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize); 88111051Sandreas.hansson@arm.com 88211051Sandreas.hansson@arm.com // if there are sharers in the upper levels, pass that info downstream 88311051Sandreas.hansson@arm.com if (cpu_pkt->sharedAsserted()) { 88411051Sandreas.hansson@arm.com // note that cpu_pkt may have spent a considerable time in the 88511051Sandreas.hansson@arm.com // MSHR queue and that the information could possibly be out 88611051Sandreas.hansson@arm.com // of date, however, there is no harm in conservatively 88711051Sandreas.hansson@arm.com // assuming the block is shared 88811051Sandreas.hansson@arm.com pkt->assertShared(); 88911051Sandreas.hansson@arm.com DPRINTF(Cache, "%s passing shared from %s to %s addr %#llx size %d\n", 89011051Sandreas.hansson@arm.com __func__, cpu_pkt->cmdString(), pkt->cmdString(), 89111051Sandreas.hansson@arm.com pkt->getAddr(), pkt->getSize()); 89211051Sandreas.hansson@arm.com } 89311051Sandreas.hansson@arm.com 89411051Sandreas.hansson@arm.com // the packet should be block aligned 89511051Sandreas.hansson@arm.com assert(pkt->getAddr() == blockAlign(pkt->getAddr())); 89611051Sandreas.hansson@arm.com 89711051Sandreas.hansson@arm.com pkt->allocate(); 89811051Sandreas.hansson@arm.com DPRINTF(Cache, "%s created %s from %s for addr %#llx size %d\n", 89911051Sandreas.hansson@arm.com __func__, pkt->cmdString(), cpu_pkt->cmdString(), pkt->getAddr(), 90011051Sandreas.hansson@arm.com pkt->getSize()); 90111051Sandreas.hansson@arm.com return pkt; 90211051Sandreas.hansson@arm.com} 90311051Sandreas.hansson@arm.com 90411051Sandreas.hansson@arm.com 90511051Sandreas.hansson@arm.comTick 90611051Sandreas.hansson@arm.comCache::recvAtomic(PacketPtr pkt) 90711051Sandreas.hansson@arm.com{ 90811051Sandreas.hansson@arm.com // We are in atomic mode so we pay just for lookupLatency here. 90911051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 91011051Sandreas.hansson@arm.com // @TODO: make this a parameter 91111051Sandreas.hansson@arm.com bool last_level_cache = false; 91211051Sandreas.hansson@arm.com 91311051Sandreas.hansson@arm.com // Forward the request if the system is in cache bypass mode. 91411051Sandreas.hansson@arm.com if (system->bypassCaches()) 91511051Sandreas.hansson@arm.com return ticksToCycles(memSidePort->sendAtomic(pkt)); 91611051Sandreas.hansson@arm.com 91711051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 91811051Sandreas.hansson@arm.com 91911051Sandreas.hansson@arm.com if (pkt->memInhibitAsserted()) { 92011051Sandreas.hansson@arm.com // have to invalidate ourselves and any lower caches even if 92111051Sandreas.hansson@arm.com // upper cache will be responding 92211051Sandreas.hansson@arm.com if (pkt->isInvalidate()) { 92311051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 92411051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 92511051Sandreas.hansson@arm.com tags->invalidate(blk); 92611051Sandreas.hansson@arm.com blk->invalidate(); 92711051Sandreas.hansson@arm.com DPRINTF(Cache, "rcvd mem-inhibited %s on %#llx (%s):" 92811051Sandreas.hansson@arm.com " invalidating\n", 92911051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), 93011051Sandreas.hansson@arm.com pkt->isSecure() ? "s" : "ns"); 93111051Sandreas.hansson@arm.com } 93211051Sandreas.hansson@arm.com if (!last_level_cache) { 93311051Sandreas.hansson@arm.com DPRINTF(Cache, "forwarding mem-inhibited %s on %#llx (%s)\n", 93411051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), 93511051Sandreas.hansson@arm.com pkt->isSecure() ? "s" : "ns"); 93611051Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 93711051Sandreas.hansson@arm.com } 93811051Sandreas.hansson@arm.com } else { 93911051Sandreas.hansson@arm.com DPRINTF(Cache, "rcvd mem-inhibited %s on %#llx: not responding\n", 94011051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 94111051Sandreas.hansson@arm.com } 94211051Sandreas.hansson@arm.com 94311051Sandreas.hansson@arm.com return lat * clockPeriod(); 94411051Sandreas.hansson@arm.com } 94511051Sandreas.hansson@arm.com 94611051Sandreas.hansson@arm.com // should assert here that there are no outstanding MSHRs or 94711051Sandreas.hansson@arm.com // writebacks... that would mean that someone used an atomic 94811051Sandreas.hansson@arm.com // access in timing mode 94911051Sandreas.hansson@arm.com 95011051Sandreas.hansson@arm.com CacheBlk *blk = NULL; 95111051Sandreas.hansson@arm.com PacketList writebacks; 95211051Sandreas.hansson@arm.com bool satisfied = access(pkt, blk, lat, writebacks); 95311051Sandreas.hansson@arm.com 95411051Sandreas.hansson@arm.com // handle writebacks resulting from the access here to ensure they 95511051Sandreas.hansson@arm.com // logically proceed anything happening below 95611051Sandreas.hansson@arm.com while (!writebacks.empty()){ 95711051Sandreas.hansson@arm.com PacketPtr wbPkt = writebacks.front(); 95811051Sandreas.hansson@arm.com memSidePort->sendAtomic(wbPkt); 95911051Sandreas.hansson@arm.com writebacks.pop_front(); 96011051Sandreas.hansson@arm.com delete wbPkt; 96111051Sandreas.hansson@arm.com } 96211051Sandreas.hansson@arm.com 96311051Sandreas.hansson@arm.com if (!satisfied) { 96411051Sandreas.hansson@arm.com // MISS 96511051Sandreas.hansson@arm.com 96611051Sandreas.hansson@arm.com PacketPtr bus_pkt = getBusPacket(pkt, blk, pkt->needsExclusive()); 96711051Sandreas.hansson@arm.com 96811051Sandreas.hansson@arm.com bool is_forward = (bus_pkt == NULL); 96911051Sandreas.hansson@arm.com 97011051Sandreas.hansson@arm.com if (is_forward) { 97111051Sandreas.hansson@arm.com // just forwarding the same request to the next level 97211051Sandreas.hansson@arm.com // no local cache operation involved 97311051Sandreas.hansson@arm.com bus_pkt = pkt; 97411051Sandreas.hansson@arm.com } 97511051Sandreas.hansson@arm.com 97611051Sandreas.hansson@arm.com DPRINTF(Cache, "Sending an atomic %s for %#llx (%s)\n", 97711051Sandreas.hansson@arm.com bus_pkt->cmdString(), bus_pkt->getAddr(), 97811051Sandreas.hansson@arm.com bus_pkt->isSecure() ? "s" : "ns"); 97911051Sandreas.hansson@arm.com 98011051Sandreas.hansson@arm.com#if TRACING_ON 98111051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 98211051Sandreas.hansson@arm.com#endif 98311051Sandreas.hansson@arm.com 98411051Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt)); 98511051Sandreas.hansson@arm.com 98611051Sandreas.hansson@arm.com // We are now dealing with the response handling 98711051Sandreas.hansson@arm.com DPRINTF(Cache, "Receive response: %s for addr %#llx (%s) in state %i\n", 98811051Sandreas.hansson@arm.com bus_pkt->cmdString(), bus_pkt->getAddr(), 98911051Sandreas.hansson@arm.com bus_pkt->isSecure() ? "s" : "ns", 99011051Sandreas.hansson@arm.com old_state); 99111051Sandreas.hansson@arm.com 99211051Sandreas.hansson@arm.com // If packet was a forward, the response (if any) is already 99311051Sandreas.hansson@arm.com // in place in the bus_pkt == pkt structure, so we don't need 99411051Sandreas.hansson@arm.com // to do anything. Otherwise, use the separate bus_pkt to 99511051Sandreas.hansson@arm.com // generate response to pkt and then delete it. 99611051Sandreas.hansson@arm.com if (!is_forward) { 99711051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 99811051Sandreas.hansson@arm.com assert(bus_pkt->isResponse()); 99911051Sandreas.hansson@arm.com if (bus_pkt->isError()) { 100011051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 100111051Sandreas.hansson@arm.com pkt->copyError(bus_pkt); 100211051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::InvalidateReq) { 100311051Sandreas.hansson@arm.com if (blk) { 100411051Sandreas.hansson@arm.com // invalidate response to a cache that received 100511051Sandreas.hansson@arm.com // an invalidate request 100611051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 100711051Sandreas.hansson@arm.com } 100811051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::WriteLineReq) { 100911051Sandreas.hansson@arm.com // note the use of pkt, not bus_pkt here. 101011051Sandreas.hansson@arm.com 101111051Sandreas.hansson@arm.com // write-line request to the cache that promoted 101211051Sandreas.hansson@arm.com // the write to a whole line 101311051Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks); 101411051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 101511051Sandreas.hansson@arm.com } else if (bus_pkt->isRead() || 101611051Sandreas.hansson@arm.com bus_pkt->cmd == MemCmd::UpgradeResp) { 101711051Sandreas.hansson@arm.com // we're updating cache state to allow us to 101811051Sandreas.hansson@arm.com // satisfy the upstream request from the cache 101911051Sandreas.hansson@arm.com blk = handleFill(bus_pkt, blk, writebacks); 102011051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 102111051Sandreas.hansson@arm.com } else { 102211051Sandreas.hansson@arm.com // we're satisfying the upstream request without 102311051Sandreas.hansson@arm.com // modifying cache state, e.g., a write-through 102411051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 102511051Sandreas.hansson@arm.com } 102611051Sandreas.hansson@arm.com } 102711051Sandreas.hansson@arm.com delete bus_pkt; 102811051Sandreas.hansson@arm.com } 102911051Sandreas.hansson@arm.com } 103011051Sandreas.hansson@arm.com 103111051Sandreas.hansson@arm.com // Note that we don't invoke the prefetcher at all in atomic mode. 103211051Sandreas.hansson@arm.com // It's not clear how to do it properly, particularly for 103311051Sandreas.hansson@arm.com // prefetchers that aggressively generate prefetch candidates and 103411051Sandreas.hansson@arm.com // rely on bandwidth contention to throttle them; these will tend 103511051Sandreas.hansson@arm.com // to pollute the cache in atomic mode since there is no bandwidth 103611051Sandreas.hansson@arm.com // contention. If we ever do want to enable prefetching in atomic 103711051Sandreas.hansson@arm.com // mode, though, this is the place to do it... see timingAccess() 103811051Sandreas.hansson@arm.com // for an example (though we'd want to issue the prefetch(es) 103911051Sandreas.hansson@arm.com // immediately rather than calling requestMemSideBus() as we do 104011051Sandreas.hansson@arm.com // there). 104111051Sandreas.hansson@arm.com 104211051Sandreas.hansson@arm.com // Handle writebacks (from the response handling) if needed 104311051Sandreas.hansson@arm.com while (!writebacks.empty()){ 104411051Sandreas.hansson@arm.com PacketPtr wbPkt = writebacks.front(); 104511051Sandreas.hansson@arm.com memSidePort->sendAtomic(wbPkt); 104611051Sandreas.hansson@arm.com writebacks.pop_front(); 104711051Sandreas.hansson@arm.com delete wbPkt; 104811051Sandreas.hansson@arm.com } 104911051Sandreas.hansson@arm.com 105011051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 105111051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 105211051Sandreas.hansson@arm.com } 105311051Sandreas.hansson@arm.com 105411051Sandreas.hansson@arm.com return lat * clockPeriod(); 105511051Sandreas.hansson@arm.com} 105611051Sandreas.hansson@arm.com 105711051Sandreas.hansson@arm.com 105811051Sandreas.hansson@arm.comvoid 105911051Sandreas.hansson@arm.comCache::functionalAccess(PacketPtr pkt, bool fromCpuSide) 106011051Sandreas.hansson@arm.com{ 106111051Sandreas.hansson@arm.com if (system->bypassCaches()) { 106211051Sandreas.hansson@arm.com // Packets from the memory side are snoop request and 106311051Sandreas.hansson@arm.com // shouldn't happen in bypass mode. 106411051Sandreas.hansson@arm.com assert(fromCpuSide); 106511051Sandreas.hansson@arm.com 106611051Sandreas.hansson@arm.com // The cache should be flushed if we are in cache bypass mode, 106711051Sandreas.hansson@arm.com // so we don't need to check if we need to update anything. 106811051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 106911051Sandreas.hansson@arm.com return; 107011051Sandreas.hansson@arm.com } 107111051Sandreas.hansson@arm.com 107211051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 107311051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 107411051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 107511051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 107611051Sandreas.hansson@arm.com 107711051Sandreas.hansson@arm.com pkt->pushLabel(name()); 107811051Sandreas.hansson@arm.com 107911051Sandreas.hansson@arm.com CacheBlkPrintWrapper cbpw(blk); 108011051Sandreas.hansson@arm.com 108111051Sandreas.hansson@arm.com // Note that just because an L2/L3 has valid data doesn't mean an 108211051Sandreas.hansson@arm.com // L1 doesn't have a more up-to-date modified copy that still 108311051Sandreas.hansson@arm.com // needs to be found. As a result we always update the request if 108411051Sandreas.hansson@arm.com // we have it, but only declare it satisfied if we are the owner. 108511051Sandreas.hansson@arm.com 108611051Sandreas.hansson@arm.com // see if we have data at all (owned or otherwise) 108711051Sandreas.hansson@arm.com bool have_data = blk && blk->isValid() 108811051Sandreas.hansson@arm.com && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize, 108911051Sandreas.hansson@arm.com blk->data); 109011051Sandreas.hansson@arm.com 109111051Sandreas.hansson@arm.com // data we have is dirty if marked as such or if valid & ownership 109211051Sandreas.hansson@arm.com // pending due to outstanding UpgradeReq 109311051Sandreas.hansson@arm.com bool have_dirty = 109411051Sandreas.hansson@arm.com have_data && (blk->isDirty() || 109511051Sandreas.hansson@arm.com (mshr && mshr->inService && mshr->isPendingDirty())); 109611051Sandreas.hansson@arm.com 109711051Sandreas.hansson@arm.com bool done = have_dirty 109811051Sandreas.hansson@arm.com || cpuSidePort->checkFunctional(pkt) 109911051Sandreas.hansson@arm.com || mshrQueue.checkFunctional(pkt, blk_addr) 110011051Sandreas.hansson@arm.com || writeBuffer.checkFunctional(pkt, blk_addr) 110111051Sandreas.hansson@arm.com || memSidePort->checkFunctional(pkt); 110211051Sandreas.hansson@arm.com 110311051Sandreas.hansson@arm.com DPRINTF(Cache, "functional %s %#llx (%s) %s%s%s\n", 110411051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), is_secure ? "s" : "ns", 110511051Sandreas.hansson@arm.com (blk && blk->isValid()) ? "valid " : "", 110611051Sandreas.hansson@arm.com have_data ? "data " : "", done ? "done " : ""); 110711051Sandreas.hansson@arm.com 110811051Sandreas.hansson@arm.com // We're leaving the cache, so pop cache->name() label 110911051Sandreas.hansson@arm.com pkt->popLabel(); 111011051Sandreas.hansson@arm.com 111111051Sandreas.hansson@arm.com if (done) { 111211051Sandreas.hansson@arm.com pkt->makeResponse(); 111311051Sandreas.hansson@arm.com } else { 111411051Sandreas.hansson@arm.com // if it came as a request from the CPU side then make sure it 111511051Sandreas.hansson@arm.com // continues towards the memory side 111611051Sandreas.hansson@arm.com if (fromCpuSide) { 111711051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 111811051Sandreas.hansson@arm.com } else if (forwardSnoops && cpuSidePort->isSnooping()) { 111911051Sandreas.hansson@arm.com // if it came from the memory side, it must be a snoop request 112011051Sandreas.hansson@arm.com // and we should only forward it if we are forwarding snoops 112111051Sandreas.hansson@arm.com cpuSidePort->sendFunctionalSnoop(pkt); 112211051Sandreas.hansson@arm.com } 112311051Sandreas.hansson@arm.com } 112411051Sandreas.hansson@arm.com} 112511051Sandreas.hansson@arm.com 112611051Sandreas.hansson@arm.com 112711051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 112811051Sandreas.hansson@arm.com// 112911051Sandreas.hansson@arm.com// Response handling: responses from the memory side 113011051Sandreas.hansson@arm.com// 113111051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 113211051Sandreas.hansson@arm.com 113311051Sandreas.hansson@arm.com 113411051Sandreas.hansson@arm.comvoid 113511051Sandreas.hansson@arm.comCache::recvTimingResp(PacketPtr pkt) 113611051Sandreas.hansson@arm.com{ 113711051Sandreas.hansson@arm.com assert(pkt->isResponse()); 113811051Sandreas.hansson@arm.com 113911051Sandreas.hansson@arm.com // all header delay should be paid for by the crossbar, unless 114011051Sandreas.hansson@arm.com // this is a prefetch response from above 114111051Sandreas.hansson@arm.com panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 114211051Sandreas.hansson@arm.com "%s saw a non-zero packet delay\n", name()); 114311051Sandreas.hansson@arm.com 114411051Sandreas.hansson@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState); 114511051Sandreas.hansson@arm.com bool is_error = pkt->isError(); 114611051Sandreas.hansson@arm.com 114711051Sandreas.hansson@arm.com assert(mshr); 114811051Sandreas.hansson@arm.com 114911051Sandreas.hansson@arm.com if (is_error) { 115011051Sandreas.hansson@arm.com DPRINTF(Cache, "Cache received packet with error for addr %#llx (%s), " 115111051Sandreas.hansson@arm.com "cmd: %s\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns", 115211051Sandreas.hansson@arm.com pkt->cmdString()); 115311051Sandreas.hansson@arm.com } 115411051Sandreas.hansson@arm.com 115511051Sandreas.hansson@arm.com DPRINTF(Cache, "Handling response %s for addr %#llx size %d (%s)\n", 115611051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize(), 115711051Sandreas.hansson@arm.com pkt->isSecure() ? "s" : "ns"); 115811051Sandreas.hansson@arm.com 115911051Sandreas.hansson@arm.com MSHRQueue *mq = mshr->queue; 116011051Sandreas.hansson@arm.com bool wasFull = mq->isFull(); 116111051Sandreas.hansson@arm.com 116211051Sandreas.hansson@arm.com if (mshr == noTargetMSHR) { 116311051Sandreas.hansson@arm.com // we always clear at least one target 116411051Sandreas.hansson@arm.com clearBlocked(Blocked_NoTargets); 116511051Sandreas.hansson@arm.com noTargetMSHR = NULL; 116611051Sandreas.hansson@arm.com } 116711051Sandreas.hansson@arm.com 116811051Sandreas.hansson@arm.com // Initial target is used just for stats 116911051Sandreas.hansson@arm.com MSHR::Target *initial_tgt = mshr->getTarget(); 117011051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 117111051Sandreas.hansson@arm.com int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 117211051Sandreas.hansson@arm.com Tick miss_latency = curTick() - initial_tgt->recvTime; 117311051Sandreas.hansson@arm.com PacketList writebacks; 117411051Sandreas.hansson@arm.com // We need forward_time here because we have a call of 117511051Sandreas.hansson@arm.com // allocateWriteBuffer() that need this parameter to specify the 117611051Sandreas.hansson@arm.com // time to request the bus. In this case we use forward latency 117711051Sandreas.hansson@arm.com // because there is a writeback. We pay also here for headerDelay 117811051Sandreas.hansson@arm.com // that is charged of bus latencies if the packet comes from the 117911051Sandreas.hansson@arm.com // bus. 118011051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 118111051Sandreas.hansson@arm.com 118211051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 118311051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 118411051Sandreas.hansson@arm.com mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 118511051Sandreas.hansson@arm.com miss_latency; 118611051Sandreas.hansson@arm.com } else { 118711051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 118811051Sandreas.hansson@arm.com mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 118911051Sandreas.hansson@arm.com miss_latency; 119011051Sandreas.hansson@arm.com } 119111051Sandreas.hansson@arm.com 119211051Sandreas.hansson@arm.com bool is_fill = !mshr->isForward && 119311051Sandreas.hansson@arm.com (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp); 119411051Sandreas.hansson@arm.com 119511051Sandreas.hansson@arm.com if (is_fill && !is_error) { 119611051Sandreas.hansson@arm.com DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 119711051Sandreas.hansson@arm.com pkt->getAddr()); 119811051Sandreas.hansson@arm.com 119911051Sandreas.hansson@arm.com // give mshr a chance to do some dirty work 120011051Sandreas.hansson@arm.com mshr->handleFill(pkt, blk); 120111051Sandreas.hansson@arm.com 120211051Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks); 120311051Sandreas.hansson@arm.com assert(blk != NULL); 120411051Sandreas.hansson@arm.com } 120511051Sandreas.hansson@arm.com 120611051Sandreas.hansson@arm.com // allow invalidation responses originating from write-line 120711051Sandreas.hansson@arm.com // requests to be discarded 120811051Sandreas.hansson@arm.com bool discard_invalidate = false; 120911051Sandreas.hansson@arm.com 121011051Sandreas.hansson@arm.com // First offset for critical word first calculations 121111051Sandreas.hansson@arm.com int initial_offset = initial_tgt->pkt->getOffset(blkSize); 121211051Sandreas.hansson@arm.com 121311051Sandreas.hansson@arm.com while (mshr->hasTargets()) { 121411051Sandreas.hansson@arm.com MSHR::Target *target = mshr->getTarget(); 121511051Sandreas.hansson@arm.com Packet *tgt_pkt = target->pkt; 121611051Sandreas.hansson@arm.com 121711051Sandreas.hansson@arm.com switch (target->source) { 121811051Sandreas.hansson@arm.com case MSHR::Target::FromCPU: 121911051Sandreas.hansson@arm.com Tick completion_time; 122011051Sandreas.hansson@arm.com // Here we charge on completion_time the delay of the xbar if the 122111051Sandreas.hansson@arm.com // packet comes from it, charged on headerDelay. 122211051Sandreas.hansson@arm.com completion_time = pkt->headerDelay; 122311051Sandreas.hansson@arm.com 122411051Sandreas.hansson@arm.com // Software prefetch handling for cache closest to core 122511051Sandreas.hansson@arm.com if (tgt_pkt->cmd.isSWPrefetch()) { 122611051Sandreas.hansson@arm.com // a software prefetch would have already been ack'd immediately 122711051Sandreas.hansson@arm.com // with dummy data so the core would be able to retire it. 122811051Sandreas.hansson@arm.com // this request completes right here, so we deallocate it. 122911051Sandreas.hansson@arm.com delete tgt_pkt->req; 123011051Sandreas.hansson@arm.com delete tgt_pkt; 123111051Sandreas.hansson@arm.com break; // skip response 123211051Sandreas.hansson@arm.com } 123311051Sandreas.hansson@arm.com 123411051Sandreas.hansson@arm.com // unlike the other packet flows, where data is found in other 123511051Sandreas.hansson@arm.com // caches or memory and brought back, write-line requests always 123611051Sandreas.hansson@arm.com // have the data right away, so the above check for "is fill?" 123711051Sandreas.hansson@arm.com // cannot actually be determined until examining the stored MSHR 123811051Sandreas.hansson@arm.com // state. We "catch up" with that logic here, which is duplicated 123911051Sandreas.hansson@arm.com // from above. 124011051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::WriteLineReq) { 124111051Sandreas.hansson@arm.com assert(!is_error); 124211051Sandreas.hansson@arm.com 124311051Sandreas.hansson@arm.com // NB: we use the original packet here and not the response! 124411051Sandreas.hansson@arm.com mshr->handleFill(tgt_pkt, blk); 124511051Sandreas.hansson@arm.com blk = handleFill(tgt_pkt, blk, writebacks); 124611051Sandreas.hansson@arm.com assert(blk != NULL); 124711051Sandreas.hansson@arm.com 124811051Sandreas.hansson@arm.com // treat as a fill, and discard the invalidation 124911051Sandreas.hansson@arm.com // response 125011051Sandreas.hansson@arm.com is_fill = true; 125111051Sandreas.hansson@arm.com discard_invalidate = true; 125211051Sandreas.hansson@arm.com } 125311051Sandreas.hansson@arm.com 125411051Sandreas.hansson@arm.com if (is_fill) { 125511051Sandreas.hansson@arm.com satisfyCpuSideRequest(tgt_pkt, blk, 125611051Sandreas.hansson@arm.com true, mshr->hasPostDowngrade()); 125711051Sandreas.hansson@arm.com 125811051Sandreas.hansson@arm.com // How many bytes past the first request is this one 125911051Sandreas.hansson@arm.com int transfer_offset = 126011051Sandreas.hansson@arm.com tgt_pkt->getOffset(blkSize) - initial_offset; 126111051Sandreas.hansson@arm.com if (transfer_offset < 0) { 126211051Sandreas.hansson@arm.com transfer_offset += blkSize; 126311051Sandreas.hansson@arm.com } 126411051Sandreas.hansson@arm.com 126511051Sandreas.hansson@arm.com // If not critical word (offset) return payloadDelay. 126611051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 126711051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 126811051Sandreas.hansson@arm.com // the core. 126911051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 127011051Sandreas.hansson@arm.com (transfer_offset ? pkt->payloadDelay : 0); 127111051Sandreas.hansson@arm.com 127211051Sandreas.hansson@arm.com assert(!tgt_pkt->req->isUncacheable()); 127311051Sandreas.hansson@arm.com 127411051Sandreas.hansson@arm.com assert(tgt_pkt->req->masterId() < system->maxMasters()); 127511051Sandreas.hansson@arm.com missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] += 127611051Sandreas.hansson@arm.com completion_time - target->recvTime; 127711051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::UpgradeFailResp) { 127811051Sandreas.hansson@arm.com // failed StoreCond upgrade 127911051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::StoreCondReq || 128011051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::StoreCondFailReq || 128111051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::SCUpgradeFailReq); 128211051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 128311051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 128411051Sandreas.hansson@arm.com // the core. 128511051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 128611051Sandreas.hansson@arm.com pkt->payloadDelay; 128711051Sandreas.hansson@arm.com tgt_pkt->req->setExtraData(0); 128811051Sandreas.hansson@arm.com } else { 128911051Sandreas.hansson@arm.com // not a cache fill, just forwarding response 129011051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 129111051Sandreas.hansson@arm.com // from lower level cahces/memory to the core. 129211051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 129311051Sandreas.hansson@arm.com pkt->payloadDelay; 129411051Sandreas.hansson@arm.com if (pkt->isRead() && !is_error) { 129511051Sandreas.hansson@arm.com // sanity check 129611051Sandreas.hansson@arm.com assert(pkt->getAddr() == tgt_pkt->getAddr()); 129711051Sandreas.hansson@arm.com assert(pkt->getSize() >= tgt_pkt->getSize()); 129811051Sandreas.hansson@arm.com 129911051Sandreas.hansson@arm.com tgt_pkt->setData(pkt->getConstPtr<uint8_t>()); 130011051Sandreas.hansson@arm.com } 130111051Sandreas.hansson@arm.com } 130211051Sandreas.hansson@arm.com tgt_pkt->makeTimingResponse(); 130311051Sandreas.hansson@arm.com // if this packet is an error copy that to the new packet 130411051Sandreas.hansson@arm.com if (is_error) 130511051Sandreas.hansson@arm.com tgt_pkt->copyError(pkt); 130611051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::ReadResp && 130711051Sandreas.hansson@arm.com (pkt->isInvalidate() || mshr->hasPostInvalidate())) { 130811051Sandreas.hansson@arm.com // If intermediate cache got ReadRespWithInvalidate, 130911051Sandreas.hansson@arm.com // propagate that. Response should not have 131011051Sandreas.hansson@arm.com // isInvalidate() set otherwise. 131111051Sandreas.hansson@arm.com tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate; 131211051Sandreas.hansson@arm.com DPRINTF(Cache, "%s updated cmd to %s for addr %#llx\n", 131311051Sandreas.hansson@arm.com __func__, tgt_pkt->cmdString(), tgt_pkt->getAddr()); 131411051Sandreas.hansson@arm.com } 131511051Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 131611051Sandreas.hansson@arm.com tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; 131711051Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(tgt_pkt, completion_time); 131811051Sandreas.hansson@arm.com break; 131911051Sandreas.hansson@arm.com 132011051Sandreas.hansson@arm.com case MSHR::Target::FromPrefetcher: 132111051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::HardPFReq); 132211051Sandreas.hansson@arm.com if (blk) 132311051Sandreas.hansson@arm.com blk->status |= BlkHWPrefetched; 132411051Sandreas.hansson@arm.com delete tgt_pkt->req; 132511051Sandreas.hansson@arm.com delete tgt_pkt; 132611051Sandreas.hansson@arm.com break; 132711051Sandreas.hansson@arm.com 132811051Sandreas.hansson@arm.com case MSHR::Target::FromSnoop: 132911051Sandreas.hansson@arm.com // I don't believe that a snoop can be in an error state 133011051Sandreas.hansson@arm.com assert(!is_error); 133111051Sandreas.hansson@arm.com // response to snoop request 133211051Sandreas.hansson@arm.com DPRINTF(Cache, "processing deferred snoop...\n"); 133311051Sandreas.hansson@arm.com assert(!(pkt->isInvalidate() && !mshr->hasPostInvalidate())); 133411051Sandreas.hansson@arm.com handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate()); 133511051Sandreas.hansson@arm.com break; 133611051Sandreas.hansson@arm.com 133711051Sandreas.hansson@arm.com default: 133811051Sandreas.hansson@arm.com panic("Illegal target->source enum %d\n", target->source); 133911051Sandreas.hansson@arm.com } 134011051Sandreas.hansson@arm.com 134111051Sandreas.hansson@arm.com mshr->popTarget(); 134211051Sandreas.hansson@arm.com } 134311051Sandreas.hansson@arm.com 134411051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 134511051Sandreas.hansson@arm.com // an invalidate response stemming from a write line request 134611051Sandreas.hansson@arm.com // should not invalidate the block, so check if the 134711051Sandreas.hansson@arm.com // invalidation should be discarded 134811051Sandreas.hansson@arm.com if ((pkt->isInvalidate() || mshr->hasPostInvalidate()) && 134911051Sandreas.hansson@arm.com !discard_invalidate) { 135011051Sandreas.hansson@arm.com assert(blk != tempBlock); 135111051Sandreas.hansson@arm.com tags->invalidate(blk); 135211051Sandreas.hansson@arm.com blk->invalidate(); 135311051Sandreas.hansson@arm.com } else if (mshr->hasPostDowngrade()) { 135411051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 135511051Sandreas.hansson@arm.com } 135611051Sandreas.hansson@arm.com } 135711051Sandreas.hansson@arm.com 135811051Sandreas.hansson@arm.com if (mshr->promoteDeferredTargets()) { 135911051Sandreas.hansson@arm.com // avoid later read getting stale data while write miss is 136011051Sandreas.hansson@arm.com // outstanding.. see comment in timingAccess() 136111051Sandreas.hansson@arm.com if (blk) { 136211051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 136311051Sandreas.hansson@arm.com } 136411051Sandreas.hansson@arm.com mq = mshr->queue; 136511051Sandreas.hansson@arm.com mq->markPending(mshr); 136611051Sandreas.hansson@arm.com schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 136711051Sandreas.hansson@arm.com } else { 136811051Sandreas.hansson@arm.com mq->deallocate(mshr); 136911051Sandreas.hansson@arm.com if (wasFull && !mq->isFull()) { 137011051Sandreas.hansson@arm.com clearBlocked((BlockedCause)mq->index); 137111051Sandreas.hansson@arm.com } 137211051Sandreas.hansson@arm.com 137311051Sandreas.hansson@arm.com // Request the bus for a prefetch if this deallocation freed enough 137411051Sandreas.hansson@arm.com // MSHRs for a prefetch to take place 137511051Sandreas.hansson@arm.com if (prefetcher && mq == &mshrQueue && mshrQueue.canPrefetch()) { 137611051Sandreas.hansson@arm.com Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 137711051Sandreas.hansson@arm.com clockEdge()); 137811051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 137911051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 138011051Sandreas.hansson@arm.com } 138111051Sandreas.hansson@arm.com } 138211051Sandreas.hansson@arm.com // reset the xbar additional timinig as it is now accounted for 138311051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 138411051Sandreas.hansson@arm.com 138511051Sandreas.hansson@arm.com // copy writebacks to write buffer 138611051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 138711051Sandreas.hansson@arm.com 138811051Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and then clear it out 138911051Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 139011051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying 139111051Sandreas.hansson@arm.com // Writebacks/CleanEvicts to write buffer. It specifies the latency to 139211051Sandreas.hansson@arm.com // allocate an internal buffer and to schedule an event to the 139311051Sandreas.hansson@arm.com // queued port. 139411051Sandreas.hansson@arm.com if (blk->isDirty()) { 139511051Sandreas.hansson@arm.com PacketPtr wbPkt = writebackBlk(blk); 139611051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 139711051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag if cached above. 139811051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) 139911051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 140011051Sandreas.hansson@arm.com } else { 140111051Sandreas.hansson@arm.com PacketPtr wcPkt = cleanEvictBlk(blk); 140211051Sandreas.hansson@arm.com // Check to see if block is cached above. If not allocate 140311051Sandreas.hansson@arm.com // write buffer 140411051Sandreas.hansson@arm.com if (isCachedAbove(wcPkt)) 140511051Sandreas.hansson@arm.com delete wcPkt; 140611051Sandreas.hansson@arm.com else 140711051Sandreas.hansson@arm.com allocateWriteBuffer(wcPkt, forward_time); 140811051Sandreas.hansson@arm.com } 140911051Sandreas.hansson@arm.com blk->invalidate(); 141011051Sandreas.hansson@arm.com } 141111051Sandreas.hansson@arm.com 141211051Sandreas.hansson@arm.com DPRINTF(Cache, "Leaving %s with %s for addr %#llx\n", __func__, 141311051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 141411051Sandreas.hansson@arm.com delete pkt; 141511051Sandreas.hansson@arm.com} 141611051Sandreas.hansson@arm.com 141711051Sandreas.hansson@arm.comPacketPtr 141811051Sandreas.hansson@arm.comCache::writebackBlk(CacheBlk *blk) 141911051Sandreas.hansson@arm.com{ 142011051Sandreas.hansson@arm.com chatty_assert(!isReadOnly, "Writeback from read-only cache"); 142111051Sandreas.hansson@arm.com assert(blk && blk->isValid() && blk->isDirty()); 142211051Sandreas.hansson@arm.com 142311051Sandreas.hansson@arm.com writebacks[Request::wbMasterId]++; 142411051Sandreas.hansson@arm.com 142511051Sandreas.hansson@arm.com Request *writebackReq = 142611051Sandreas.hansson@arm.com new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0, 142711051Sandreas.hansson@arm.com Request::wbMasterId); 142811051Sandreas.hansson@arm.com if (blk->isSecure()) 142911051Sandreas.hansson@arm.com writebackReq->setFlags(Request::SECURE); 143011051Sandreas.hansson@arm.com 143111051Sandreas.hansson@arm.com writebackReq->taskId(blk->task_id); 143211051Sandreas.hansson@arm.com blk->task_id= ContextSwitchTaskId::Unknown; 143311051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 143411051Sandreas.hansson@arm.com 143511051Sandreas.hansson@arm.com PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback); 143611051Sandreas.hansson@arm.com if (blk->isWritable()) { 143711051Sandreas.hansson@arm.com // not asserting shared means we pass the block in modified 143811051Sandreas.hansson@arm.com // state, mark our own block non-writeable 143911051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 144011051Sandreas.hansson@arm.com } else { 144111051Sandreas.hansson@arm.com // we are in the owned state, tell the receiver 144211051Sandreas.hansson@arm.com writeback->assertShared(); 144311051Sandreas.hansson@arm.com } 144411051Sandreas.hansson@arm.com 144511051Sandreas.hansson@arm.com writeback->allocate(); 144611051Sandreas.hansson@arm.com std::memcpy(writeback->getPtr<uint8_t>(), blk->data, blkSize); 144711051Sandreas.hansson@arm.com 144811051Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 144911051Sandreas.hansson@arm.com return writeback; 145011051Sandreas.hansson@arm.com} 145111051Sandreas.hansson@arm.com 145211051Sandreas.hansson@arm.comPacketPtr 145311051Sandreas.hansson@arm.comCache::cleanEvictBlk(CacheBlk *blk) 145411051Sandreas.hansson@arm.com{ 145511051Sandreas.hansson@arm.com assert(blk && blk->isValid() && !blk->isDirty()); 145611051Sandreas.hansson@arm.com // Creating a zero sized write, a message to the snoop filter 145711051Sandreas.hansson@arm.com Request *req = 145811051Sandreas.hansson@arm.com new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0, 145911051Sandreas.hansson@arm.com Request::wbMasterId); 146011051Sandreas.hansson@arm.com if (blk->isSecure()) 146111051Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 146211051Sandreas.hansson@arm.com 146311051Sandreas.hansson@arm.com req->taskId(blk->task_id); 146411051Sandreas.hansson@arm.com blk->task_id = ContextSwitchTaskId::Unknown; 146511051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 146611051Sandreas.hansson@arm.com 146711051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::CleanEvict); 146811051Sandreas.hansson@arm.com pkt->allocate(); 146911051Sandreas.hansson@arm.com DPRINTF(Cache, "%s%s %x Create CleanEvict\n", pkt->cmdString(), 147011051Sandreas.hansson@arm.com pkt->req->isInstFetch() ? " (ifetch)" : "", 147111051Sandreas.hansson@arm.com pkt->getAddr()); 147211051Sandreas.hansson@arm.com 147311051Sandreas.hansson@arm.com return pkt; 147411051Sandreas.hansson@arm.com} 147511051Sandreas.hansson@arm.com 147611051Sandreas.hansson@arm.comvoid 147711051Sandreas.hansson@arm.comCache::memWriteback() 147811051Sandreas.hansson@arm.com{ 147911051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::writebackVisitor); 148011051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 148111051Sandreas.hansson@arm.com} 148211051Sandreas.hansson@arm.com 148311051Sandreas.hansson@arm.comvoid 148411051Sandreas.hansson@arm.comCache::memInvalidate() 148511051Sandreas.hansson@arm.com{ 148611051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::invalidateVisitor); 148711051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 148811051Sandreas.hansson@arm.com} 148911051Sandreas.hansson@arm.com 149011051Sandreas.hansson@arm.combool 149111051Sandreas.hansson@arm.comCache::isDirty() const 149211051Sandreas.hansson@arm.com{ 149311051Sandreas.hansson@arm.com CacheBlkIsDirtyVisitor visitor; 149411051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 149511051Sandreas.hansson@arm.com 149611051Sandreas.hansson@arm.com return visitor.isDirty(); 149711051Sandreas.hansson@arm.com} 149811051Sandreas.hansson@arm.com 149911051Sandreas.hansson@arm.combool 150011051Sandreas.hansson@arm.comCache::writebackVisitor(CacheBlk &blk) 150111051Sandreas.hansson@arm.com{ 150211051Sandreas.hansson@arm.com if (blk.isDirty()) { 150311051Sandreas.hansson@arm.com assert(blk.isValid()); 150411051Sandreas.hansson@arm.com 150511051Sandreas.hansson@arm.com Request request(tags->regenerateBlkAddr(blk.tag, blk.set), 150611051Sandreas.hansson@arm.com blkSize, 0, Request::funcMasterId); 150711051Sandreas.hansson@arm.com request.taskId(blk.task_id); 150811051Sandreas.hansson@arm.com 150911051Sandreas.hansson@arm.com Packet packet(&request, MemCmd::WriteReq); 151011051Sandreas.hansson@arm.com packet.dataStatic(blk.data); 151111051Sandreas.hansson@arm.com 151211051Sandreas.hansson@arm.com memSidePort->sendFunctional(&packet); 151311051Sandreas.hansson@arm.com 151411051Sandreas.hansson@arm.com blk.status &= ~BlkDirty; 151511051Sandreas.hansson@arm.com } 151611051Sandreas.hansson@arm.com 151711051Sandreas.hansson@arm.com return true; 151811051Sandreas.hansson@arm.com} 151911051Sandreas.hansson@arm.com 152011051Sandreas.hansson@arm.combool 152111051Sandreas.hansson@arm.comCache::invalidateVisitor(CacheBlk &blk) 152211051Sandreas.hansson@arm.com{ 152311051Sandreas.hansson@arm.com 152411051Sandreas.hansson@arm.com if (blk.isDirty()) 152511051Sandreas.hansson@arm.com warn_once("Invalidating dirty cache lines. Expect things to break.\n"); 152611051Sandreas.hansson@arm.com 152711051Sandreas.hansson@arm.com if (blk.isValid()) { 152811051Sandreas.hansson@arm.com assert(!blk.isDirty()); 152911051Sandreas.hansson@arm.com tags->invalidate(&blk); 153011051Sandreas.hansson@arm.com blk.invalidate(); 153111051Sandreas.hansson@arm.com } 153211051Sandreas.hansson@arm.com 153311051Sandreas.hansson@arm.com return true; 153411051Sandreas.hansson@arm.com} 153511051Sandreas.hansson@arm.com 153611051Sandreas.hansson@arm.comCacheBlk* 153711051Sandreas.hansson@arm.comCache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks) 153811051Sandreas.hansson@arm.com{ 153911051Sandreas.hansson@arm.com CacheBlk *blk = tags->findVictim(addr); 154011051Sandreas.hansson@arm.com 154111051Sandreas.hansson@arm.com // It is valid to return NULL if there is no victim 154211051Sandreas.hansson@arm.com if (!blk) 154311051Sandreas.hansson@arm.com return nullptr; 154411051Sandreas.hansson@arm.com 154511051Sandreas.hansson@arm.com if (blk->isValid()) { 154611051Sandreas.hansson@arm.com Addr repl_addr = tags->regenerateBlkAddr(blk->tag, blk->set); 154711051Sandreas.hansson@arm.com MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure()); 154811051Sandreas.hansson@arm.com if (repl_mshr) { 154911051Sandreas.hansson@arm.com // must be an outstanding upgrade request 155011051Sandreas.hansson@arm.com // on a block we're about to replace... 155111051Sandreas.hansson@arm.com assert(!blk->isWritable() || blk->isDirty()); 155211051Sandreas.hansson@arm.com assert(repl_mshr->needsExclusive()); 155311051Sandreas.hansson@arm.com // too hard to replace block with transient state 155411051Sandreas.hansson@arm.com // allocation failed, block not inserted 155511051Sandreas.hansson@arm.com return NULL; 155611051Sandreas.hansson@arm.com } else { 155711051Sandreas.hansson@arm.com DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx (%s): %s\n", 155811051Sandreas.hansson@arm.com repl_addr, blk->isSecure() ? "s" : "ns", 155911051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", 156011051Sandreas.hansson@arm.com blk->isDirty() ? "writeback" : "clean"); 156111051Sandreas.hansson@arm.com 156211051Sandreas.hansson@arm.com // Will send up Writeback/CleanEvict snoops via isCachedAbove 156311051Sandreas.hansson@arm.com // when pushing this writeback list into the write buffer. 156411051Sandreas.hansson@arm.com if (blk->isDirty()) { 156511051Sandreas.hansson@arm.com // Save writeback packet for handling by caller 156611051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(blk)); 156711051Sandreas.hansson@arm.com } else { 156811051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(blk)); 156911051Sandreas.hansson@arm.com } 157011051Sandreas.hansson@arm.com } 157111051Sandreas.hansson@arm.com } 157211051Sandreas.hansson@arm.com 157311051Sandreas.hansson@arm.com return blk; 157411051Sandreas.hansson@arm.com} 157511051Sandreas.hansson@arm.com 157611051Sandreas.hansson@arm.com 157711051Sandreas.hansson@arm.com// Note that the reason we return a list of writebacks rather than 157811051Sandreas.hansson@arm.com// inserting them directly in the write buffer is that this function 157911051Sandreas.hansson@arm.com// is called by both atomic and timing-mode accesses, and in atomic 158011051Sandreas.hansson@arm.com// mode we don't mess with the write buffer (we just perform the 158111051Sandreas.hansson@arm.com// writebacks atomically once the original request is complete). 158211051Sandreas.hansson@arm.comCacheBlk* 158311051Sandreas.hansson@arm.comCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks) 158411051Sandreas.hansson@arm.com{ 158511051Sandreas.hansson@arm.com assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq); 158611051Sandreas.hansson@arm.com Addr addr = pkt->getAddr(); 158711051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 158811051Sandreas.hansson@arm.com#if TRACING_ON 158911051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 159011051Sandreas.hansson@arm.com#endif 159111051Sandreas.hansson@arm.com 159211051Sandreas.hansson@arm.com // When handling a fill, discard any CleanEvicts for the 159311051Sandreas.hansson@arm.com // same address in write buffer. 159411051Sandreas.hansson@arm.com Addr M5_VAR_USED blk_addr = blockAlign(pkt->getAddr()); 159511051Sandreas.hansson@arm.com std::vector<MSHR *> M5_VAR_USED wbs; 159611051Sandreas.hansson@arm.com assert (!writeBuffer.findMatches(blk_addr, is_secure, wbs)); 159711051Sandreas.hansson@arm.com 159811051Sandreas.hansson@arm.com if (blk == NULL) { 159911051Sandreas.hansson@arm.com // better have read new data... 160011051Sandreas.hansson@arm.com assert(pkt->hasData()); 160111051Sandreas.hansson@arm.com 160211051Sandreas.hansson@arm.com // only read responses and write-line requests have data; 160311051Sandreas.hansson@arm.com // note that we don't write the data here for write-line - that 160411051Sandreas.hansson@arm.com // happens in the subsequent satisfyCpuSideRequest. 160511051Sandreas.hansson@arm.com assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq); 160611051Sandreas.hansson@arm.com 160711051Sandreas.hansson@arm.com // need to do a replacement 160811051Sandreas.hansson@arm.com blk = allocateBlock(addr, is_secure, writebacks); 160911051Sandreas.hansson@arm.com if (blk == NULL) { 161011051Sandreas.hansson@arm.com // No replaceable block... just use temporary storage to 161111051Sandreas.hansson@arm.com // complete the current request and then get rid of it 161211051Sandreas.hansson@arm.com assert(!tempBlock->isValid()); 161311051Sandreas.hansson@arm.com blk = tempBlock; 161411051Sandreas.hansson@arm.com tempBlock->set = tags->extractSet(addr); 161511051Sandreas.hansson@arm.com tempBlock->tag = tags->extractTag(addr); 161611051Sandreas.hansson@arm.com // @todo: set security state as well... 161711051Sandreas.hansson@arm.com DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr, 161811051Sandreas.hansson@arm.com is_secure ? "s" : "ns"); 161911051Sandreas.hansson@arm.com } else { 162011051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 162111051Sandreas.hansson@arm.com } 162211051Sandreas.hansson@arm.com 162311051Sandreas.hansson@arm.com // we should never be overwriting a valid block 162411051Sandreas.hansson@arm.com assert(!blk->isValid()); 162511051Sandreas.hansson@arm.com } else { 162611051Sandreas.hansson@arm.com // existing block... probably an upgrade 162711051Sandreas.hansson@arm.com assert(blk->tag == tags->extractTag(addr)); 162811051Sandreas.hansson@arm.com // either we're getting new data or the block should already be valid 162911051Sandreas.hansson@arm.com assert(pkt->hasData() || blk->isValid()); 163011051Sandreas.hansson@arm.com // don't clear block status... if block is already dirty we 163111051Sandreas.hansson@arm.com // don't want to lose that 163211051Sandreas.hansson@arm.com } 163311051Sandreas.hansson@arm.com 163411051Sandreas.hansson@arm.com if (is_secure) 163511051Sandreas.hansson@arm.com blk->status |= BlkSecure; 163611051Sandreas.hansson@arm.com blk->status |= BlkValid | BlkReadable; 163711051Sandreas.hansson@arm.com 163811051Sandreas.hansson@arm.com if (!pkt->sharedAsserted()) { 163911051Sandreas.hansson@arm.com // we could get non-shared responses from memory (rather than 164011051Sandreas.hansson@arm.com // a cache) even in a read-only cache, note that we set this 164111051Sandreas.hansson@arm.com // bit even for a read-only cache as we use it to represent 164211051Sandreas.hansson@arm.com // the exclusive state 164311051Sandreas.hansson@arm.com blk->status |= BlkWritable; 164411051Sandreas.hansson@arm.com 164511051Sandreas.hansson@arm.com // If we got this via cache-to-cache transfer (i.e., from a 164611051Sandreas.hansson@arm.com // cache that was an owner) and took away that owner's copy, 164711051Sandreas.hansson@arm.com // then we need to write it back. Normally this happens 164811051Sandreas.hansson@arm.com // anyway as a side effect of getting a copy to write it, but 164911051Sandreas.hansson@arm.com // there are cases (such as failed store conditionals or 165011051Sandreas.hansson@arm.com // compare-and-swaps) where we'll demand an exclusive copy but 165111051Sandreas.hansson@arm.com // end up not writing it. 165211051Sandreas.hansson@arm.com if (pkt->memInhibitAsserted()) { 165311051Sandreas.hansson@arm.com blk->status |= BlkDirty; 165411051Sandreas.hansson@arm.com 165511051Sandreas.hansson@arm.com chatty_assert(!isReadOnly, "Should never see dirty snoop response " 165611051Sandreas.hansson@arm.com "in read-only cache %s\n", name()); 165711051Sandreas.hansson@arm.com } 165811051Sandreas.hansson@arm.com } 165911051Sandreas.hansson@arm.com 166011051Sandreas.hansson@arm.com DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n", 166111051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", old_state, blk->print()); 166211051Sandreas.hansson@arm.com 166311051Sandreas.hansson@arm.com // if we got new data, copy it in (checking for a read response 166411051Sandreas.hansson@arm.com // and a response that has data is the same in the end) 166511051Sandreas.hansson@arm.com if (pkt->isRead()) { 166611051Sandreas.hansson@arm.com // sanity checks 166711051Sandreas.hansson@arm.com assert(pkt->hasData()); 166811051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 166911051Sandreas.hansson@arm.com 167011051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 167111051Sandreas.hansson@arm.com } 167211051Sandreas.hansson@arm.com // We pay for fillLatency here. 167311051Sandreas.hansson@arm.com blk->whenReady = clockEdge() + fillLatency * clockPeriod() + 167411051Sandreas.hansson@arm.com pkt->payloadDelay; 167511051Sandreas.hansson@arm.com 167611051Sandreas.hansson@arm.com return blk; 167711051Sandreas.hansson@arm.com} 167811051Sandreas.hansson@arm.com 167911051Sandreas.hansson@arm.com 168011051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 168111051Sandreas.hansson@arm.com// 168211051Sandreas.hansson@arm.com// Snoop path: requests coming in from the memory side 168311051Sandreas.hansson@arm.com// 168411051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 168511051Sandreas.hansson@arm.com 168611051Sandreas.hansson@arm.comvoid 168711051Sandreas.hansson@arm.comCache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 168811051Sandreas.hansson@arm.com bool already_copied, bool pending_inval) 168911051Sandreas.hansson@arm.com{ 169011051Sandreas.hansson@arm.com // sanity check 169111051Sandreas.hansson@arm.com assert(req_pkt->isRequest()); 169211051Sandreas.hansson@arm.com assert(req_pkt->needsResponse()); 169311051Sandreas.hansson@arm.com 169411051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 169511051Sandreas.hansson@arm.com req_pkt->cmdString(), req_pkt->getAddr(), req_pkt->getSize()); 169611051Sandreas.hansson@arm.com // timing-mode snoop responses require a new packet, unless we 169711051Sandreas.hansson@arm.com // already made a copy... 169811051Sandreas.hansson@arm.com PacketPtr pkt = req_pkt; 169911051Sandreas.hansson@arm.com if (!already_copied) 170011051Sandreas.hansson@arm.com // do not clear flags, and allocate space for data if the 170111051Sandreas.hansson@arm.com // packet needs it (the only packets that carry data are read 170211051Sandreas.hansson@arm.com // responses) 170311051Sandreas.hansson@arm.com pkt = new Packet(req_pkt, false, req_pkt->isRead()); 170411051Sandreas.hansson@arm.com 170511051Sandreas.hansson@arm.com assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() || 170611051Sandreas.hansson@arm.com pkt->sharedAsserted()); 170711051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 170811051Sandreas.hansson@arm.com if (pkt->isRead()) { 170911051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk_data, blkSize); 171011051Sandreas.hansson@arm.com } 171111051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadResp && pending_inval) { 171211051Sandreas.hansson@arm.com // Assume we defer a response to a read from a far-away cache 171311051Sandreas.hansson@arm.com // A, then later defer a ReadExcl from a cache B on the same 171411051Sandreas.hansson@arm.com // bus as us. We'll assert MemInhibit in both cases, but in 171511051Sandreas.hansson@arm.com // the latter case MemInhibit will keep the invalidation from 171611051Sandreas.hansson@arm.com // reaching cache A. This special response tells cache A that 171711051Sandreas.hansson@arm.com // it gets the block to satisfy its read, but must immediately 171811051Sandreas.hansson@arm.com // invalidate it. 171911051Sandreas.hansson@arm.com pkt->cmd = MemCmd::ReadRespWithInvalidate; 172011051Sandreas.hansson@arm.com } 172111051Sandreas.hansson@arm.com // Here we consider forward_time, paying for just forward latency and 172211051Sandreas.hansson@arm.com // also charging the delay provided by the xbar. 172311051Sandreas.hansson@arm.com // forward_time is used as send_time in next allocateWriteBuffer(). 172411051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 172511051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 172611051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 172711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s created response: %s addr %#llx size %d tick: %lu\n", 172811051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize(), 172911051Sandreas.hansson@arm.com forward_time); 173011051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, forward_time, true); 173111051Sandreas.hansson@arm.com} 173211051Sandreas.hansson@arm.com 173311051Sandreas.hansson@arm.comvoid 173411051Sandreas.hansson@arm.comCache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, 173511051Sandreas.hansson@arm.com bool is_deferred, bool pending_inval) 173611051Sandreas.hansson@arm.com{ 173711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 173811051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 173911051Sandreas.hansson@arm.com // deferred snoops can only happen in timing mode 174011051Sandreas.hansson@arm.com assert(!(is_deferred && !is_timing)); 174111051Sandreas.hansson@arm.com // pending_inval only makes sense on deferred snoops 174211051Sandreas.hansson@arm.com assert(!(pending_inval && !is_deferred)); 174311051Sandreas.hansson@arm.com assert(pkt->isRequest()); 174411051Sandreas.hansson@arm.com 174511051Sandreas.hansson@arm.com // the packet may get modified if we or a forwarded snooper 174611051Sandreas.hansson@arm.com // responds in atomic mode, so remember a few things about the 174711051Sandreas.hansson@arm.com // original packet up front 174811051Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 174911051Sandreas.hansson@arm.com bool M5_VAR_USED needs_exclusive = pkt->needsExclusive(); 175011051Sandreas.hansson@arm.com 175111051Sandreas.hansson@arm.com if (forwardSnoops) { 175211051Sandreas.hansson@arm.com // first propagate snoop upward to see if anyone above us wants to 175311051Sandreas.hansson@arm.com // handle it. save & restore packet src since it will get 175411051Sandreas.hansson@arm.com // rewritten to be relative to cpu-side bus (if any) 175511051Sandreas.hansson@arm.com bool alreadyResponded = pkt->memInhibitAsserted(); 175611051Sandreas.hansson@arm.com if (is_timing) { 175711051Sandreas.hansson@arm.com // copy the packet so that we can clear any flags before 175811051Sandreas.hansson@arm.com // forwarding it upwards, we also allocate data (passing 175911051Sandreas.hansson@arm.com // the pointer along in case of static data), in case 176011051Sandreas.hansson@arm.com // there is a snoop hit in upper levels 176111051Sandreas.hansson@arm.com Packet snoopPkt(pkt, true, true); 176211051Sandreas.hansson@arm.com snoopPkt.setExpressSnoop(); 176311051Sandreas.hansson@arm.com snoopPkt.pushSenderState(new ForwardResponseRecord()); 176411051Sandreas.hansson@arm.com // the snoop packet does not need to wait any additional 176511051Sandreas.hansson@arm.com // time 176611051Sandreas.hansson@arm.com snoopPkt.headerDelay = snoopPkt.payloadDelay = 0; 176711051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoopPkt); 176811051Sandreas.hansson@arm.com if (snoopPkt.memInhibitAsserted()) { 176911051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache 177011051Sandreas.hansson@arm.com assert(!alreadyResponded); 177111051Sandreas.hansson@arm.com pkt->assertMemInhibit(); 177211051Sandreas.hansson@arm.com } else { 177311051Sandreas.hansson@arm.com // no cache (or anyone else for that matter) will 177411051Sandreas.hansson@arm.com // respond, so delete the ForwardResponseRecord here 177511051Sandreas.hansson@arm.com delete snoopPkt.popSenderState(); 177611051Sandreas.hansson@arm.com } 177711051Sandreas.hansson@arm.com if (snoopPkt.sharedAsserted()) { 177811051Sandreas.hansson@arm.com pkt->assertShared(); 177911051Sandreas.hansson@arm.com } 178011051Sandreas.hansson@arm.com // If this request is a prefetch or clean evict and an upper level 178111051Sandreas.hansson@arm.com // signals block present, make sure to propagate the block 178211051Sandreas.hansson@arm.com // presence to the requester. 178311051Sandreas.hansson@arm.com if (snoopPkt.isBlockCached()) { 178411051Sandreas.hansson@arm.com pkt->setBlockCached(); 178511051Sandreas.hansson@arm.com } 178611051Sandreas.hansson@arm.com } else { 178711051Sandreas.hansson@arm.com cpuSidePort->sendAtomicSnoop(pkt); 178811051Sandreas.hansson@arm.com if (!alreadyResponded && pkt->memInhibitAsserted()) { 178911051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache: 179011051Sandreas.hansson@arm.com // forward response to original requester 179111051Sandreas.hansson@arm.com assert(pkt->isResponse()); 179211051Sandreas.hansson@arm.com } 179311051Sandreas.hansson@arm.com } 179411051Sandreas.hansson@arm.com } 179511051Sandreas.hansson@arm.com 179611051Sandreas.hansson@arm.com if (!blk || !blk->isValid()) { 179711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s snoop miss for %s addr %#llx size %d\n", 179811051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 179911051Sandreas.hansson@arm.com return; 180011051Sandreas.hansson@arm.com } else { 180111051Sandreas.hansson@arm.com DPRINTF(Cache, "%s snoop hit for %s for addr %#llx size %d, " 180211051Sandreas.hansson@arm.com "old state is %s\n", __func__, pkt->cmdString(), 180311051Sandreas.hansson@arm.com pkt->getAddr(), pkt->getSize(), blk->print()); 180411051Sandreas.hansson@arm.com } 180511051Sandreas.hansson@arm.com 180611051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && blk->isDirty()), 180711051Sandreas.hansson@arm.com "Should never have a dirty block in a read-only cache %s\n", 180811051Sandreas.hansson@arm.com name()); 180911051Sandreas.hansson@arm.com 181011051Sandreas.hansson@arm.com // We may end up modifying both the block state and the packet (if 181111051Sandreas.hansson@arm.com // we respond in atomic mode), so just figure out what to do now 181211051Sandreas.hansson@arm.com // and then do it later. If we find dirty data while snooping for 181311051Sandreas.hansson@arm.com // an invalidate, we don't need to send a response. The 181411051Sandreas.hansson@arm.com // invalidation itself is taken care of below. 181511051Sandreas.hansson@arm.com bool respond = blk->isDirty() && pkt->needsResponse() && 181611051Sandreas.hansson@arm.com pkt->cmd != MemCmd::InvalidateReq; 181711051Sandreas.hansson@arm.com bool have_exclusive = blk->isWritable(); 181811051Sandreas.hansson@arm.com 181911051Sandreas.hansson@arm.com // Invalidate any prefetch's from below that would strip write permissions 182011051Sandreas.hansson@arm.com // MemCmd::HardPFReq is only observed by upstream caches. After missing 182111051Sandreas.hansson@arm.com // above and in it's own cache, a new MemCmd::ReadReq is created that 182211051Sandreas.hansson@arm.com // downstream caches observe. 182311051Sandreas.hansson@arm.com if (pkt->mustCheckAbove()) { 182411051Sandreas.hansson@arm.com DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s from" 182511051Sandreas.hansson@arm.com " lower cache\n", pkt->getAddr(), pkt->cmdString()); 182611051Sandreas.hansson@arm.com pkt->setBlockCached(); 182711051Sandreas.hansson@arm.com return; 182811051Sandreas.hansson@arm.com } 182911051Sandreas.hansson@arm.com 183011051Sandreas.hansson@arm.com if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) { 183111081Sandreas.hansson@arm.com // reading non-exclusive shared data, note that we retain 183211081Sandreas.hansson@arm.com // the block in owned state if it is dirty, with the response 183311081Sandreas.hansson@arm.com // taken care of below, and otherwhise simply downgrade to 183411081Sandreas.hansson@arm.com // shared 183511051Sandreas.hansson@arm.com assert(!needs_exclusive); 183611051Sandreas.hansson@arm.com pkt->assertShared(); 183711081Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 183811051Sandreas.hansson@arm.com } 183911051Sandreas.hansson@arm.com 184011051Sandreas.hansson@arm.com if (respond) { 184111051Sandreas.hansson@arm.com // prevent anyone else from responding, cache as well as 184211051Sandreas.hansson@arm.com // memory, and also prevent any memory from even seeing the 184311051Sandreas.hansson@arm.com // request (with current inhibited semantics), note that this 184411051Sandreas.hansson@arm.com // applies both to reads and writes and that for writes it 184511051Sandreas.hansson@arm.com // works thanks to the fact that we still have dirty data and 184611051Sandreas.hansson@arm.com // will write it back at a later point 184711051Sandreas.hansson@arm.com pkt->assertMemInhibit(); 184811051Sandreas.hansson@arm.com if (have_exclusive) { 184911081Sandreas.hansson@arm.com // in the case of an uncacheable request there is no point 185011081Sandreas.hansson@arm.com // in setting the exclusive flag, but since the recipient 185111081Sandreas.hansson@arm.com // does not care there is no harm in doing so, in any case 185211081Sandreas.hansson@arm.com // it is just a hint 185311051Sandreas.hansson@arm.com pkt->setSupplyExclusive(); 185411051Sandreas.hansson@arm.com } 185511051Sandreas.hansson@arm.com if (is_timing) { 185611051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval); 185711051Sandreas.hansson@arm.com } else { 185811051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 185911051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 186011051Sandreas.hansson@arm.com } 186111051Sandreas.hansson@arm.com } 186211051Sandreas.hansson@arm.com 186311051Sandreas.hansson@arm.com if (!respond && is_timing && is_deferred) { 186411051Sandreas.hansson@arm.com // if it's a deferred timing snoop then we've made a copy of 186511051Sandreas.hansson@arm.com // both the request and the packet, and so if we're not using 186611051Sandreas.hansson@arm.com // those copies to respond and delete them here 186711051Sandreas.hansson@arm.com DPRINTF(Cache, "Deleting pkt %p and request %p for cmd %s addr: %p\n", 186811051Sandreas.hansson@arm.com pkt, pkt->req, pkt->cmdString(), pkt->getAddr()); 186911051Sandreas.hansson@arm.com 187011051Sandreas.hansson@arm.com // the packets needs a response (just not from us), so we also 187111051Sandreas.hansson@arm.com // need to delete the request and not rely on the packet 187211051Sandreas.hansson@arm.com // destructor 187311051Sandreas.hansson@arm.com assert(pkt->needsResponse()); 187411051Sandreas.hansson@arm.com delete pkt->req; 187511051Sandreas.hansson@arm.com delete pkt; 187611051Sandreas.hansson@arm.com } 187711051Sandreas.hansson@arm.com 187811051Sandreas.hansson@arm.com // Do this last in case it deallocates block data or something 187911051Sandreas.hansson@arm.com // like that 188011051Sandreas.hansson@arm.com if (invalidate) { 188111051Sandreas.hansson@arm.com if (blk != tempBlock) 188211051Sandreas.hansson@arm.com tags->invalidate(blk); 188311051Sandreas.hansson@arm.com blk->invalidate(); 188411051Sandreas.hansson@arm.com } 188511051Sandreas.hansson@arm.com 188611051Sandreas.hansson@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 188711051Sandreas.hansson@arm.com} 188811051Sandreas.hansson@arm.com 188911051Sandreas.hansson@arm.com 189011051Sandreas.hansson@arm.comvoid 189111051Sandreas.hansson@arm.comCache::recvTimingSnoopReq(PacketPtr pkt) 189211051Sandreas.hansson@arm.com{ 189311051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 189411051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 189511051Sandreas.hansson@arm.com 189611051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 189711051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 189811051Sandreas.hansson@arm.com 189911051Sandreas.hansson@arm.com // no need to snoop writebacks or requests that are not in range 190011051Sandreas.hansson@arm.com if (!inRange(pkt->getAddr())) { 190111051Sandreas.hansson@arm.com return; 190211051Sandreas.hansson@arm.com } 190311051Sandreas.hansson@arm.com 190411051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 190511051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 190611051Sandreas.hansson@arm.com 190711051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 190811051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 190911051Sandreas.hansson@arm.com 191011051Sandreas.hansson@arm.com // Inform request(Prefetch, CleanEvict or Writeback) from below of 191111051Sandreas.hansson@arm.com // MSHR hit, set setBlockCached. 191211051Sandreas.hansson@arm.com if (mshr && pkt->mustCheckAbove()) { 191311051Sandreas.hansson@arm.com DPRINTF(Cache, "Setting block cached for %s from" 191411051Sandreas.hansson@arm.com "lower cache on mshr hit %#x\n", 191511051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 191611051Sandreas.hansson@arm.com pkt->setBlockCached(); 191711051Sandreas.hansson@arm.com return; 191811051Sandreas.hansson@arm.com } 191911051Sandreas.hansson@arm.com 192011051Sandreas.hansson@arm.com // Let the MSHR itself track the snoop and decide whether we want 192111051Sandreas.hansson@arm.com // to go ahead and do the regular cache snoop 192211051Sandreas.hansson@arm.com if (mshr && mshr->handleSnoop(pkt, order++)) { 192311051Sandreas.hansson@arm.com DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)." 192411051Sandreas.hansson@arm.com "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns", 192511051Sandreas.hansson@arm.com mshr->print()); 192611051Sandreas.hansson@arm.com 192711051Sandreas.hansson@arm.com if (mshr->getNumTargets() > numTarget) 192811051Sandreas.hansson@arm.com warn("allocating bonus target for snoop"); //handle later 192911051Sandreas.hansson@arm.com return; 193011051Sandreas.hansson@arm.com } 193111051Sandreas.hansson@arm.com 193211051Sandreas.hansson@arm.com //We also need to check the writeback buffers and handle those 193311051Sandreas.hansson@arm.com std::vector<MSHR *> writebacks; 193411051Sandreas.hansson@arm.com if (writeBuffer.findMatches(blk_addr, is_secure, writebacks)) { 193511051Sandreas.hansson@arm.com DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n", 193611051Sandreas.hansson@arm.com pkt->getAddr(), is_secure ? "s" : "ns"); 193711051Sandreas.hansson@arm.com 193811051Sandreas.hansson@arm.com // Look through writebacks for any cachable writes. 193911051Sandreas.hansson@arm.com // We should only ever find a single match 194011051Sandreas.hansson@arm.com assert(writebacks.size() == 1); 194111051Sandreas.hansson@arm.com MSHR *wb_entry = writebacks[0]; 194211051Sandreas.hansson@arm.com // Expect to see only Writebacks and/or CleanEvicts here, both of 194311051Sandreas.hansson@arm.com // which should not be generated for uncacheable data. 194411051Sandreas.hansson@arm.com assert(!wb_entry->isUncacheable()); 194511051Sandreas.hansson@arm.com // There should only be a single request responsible for generating 194611051Sandreas.hansson@arm.com // Writebacks/CleanEvicts. 194711051Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 194811051Sandreas.hansson@arm.com PacketPtr wb_pkt = wb_entry->getTarget()->pkt; 194911051Sandreas.hansson@arm.com assert(wb_pkt->evictingBlock()); 195011051Sandreas.hansson@arm.com 195111051Sandreas.hansson@arm.com if (pkt->evictingBlock()) { 195211051Sandreas.hansson@arm.com // if the block is found in the write queue, set the BLOCK_CACHED 195311051Sandreas.hansson@arm.com // flag for Writeback/CleanEvict snoop. On return the snoop will 195411051Sandreas.hansson@arm.com // propagate the BLOCK_CACHED flag in Writeback packets and prevent 195511051Sandreas.hansson@arm.com // any CleanEvicts from travelling down the memory hierarchy. 195611051Sandreas.hansson@arm.com pkt->setBlockCached(); 195711051Sandreas.hansson@arm.com DPRINTF(Cache, "Squashing %s from lower cache on writequeue hit" 195811051Sandreas.hansson@arm.com " %#x\n", pkt->cmdString(), pkt->getAddr()); 195911051Sandreas.hansson@arm.com return; 196011051Sandreas.hansson@arm.com } 196111051Sandreas.hansson@arm.com 196211051Sandreas.hansson@arm.com if (wb_pkt->cmd == MemCmd::Writeback) { 196311051Sandreas.hansson@arm.com assert(!pkt->memInhibitAsserted()); 196411051Sandreas.hansson@arm.com pkt->assertMemInhibit(); 196511051Sandreas.hansson@arm.com if (!pkt->needsExclusive()) { 196611051Sandreas.hansson@arm.com pkt->assertShared(); 196711051Sandreas.hansson@arm.com // the writeback is no longer passing exclusivity (the 196811051Sandreas.hansson@arm.com // receiving cache should consider the block owned 196911051Sandreas.hansson@arm.com // rather than modified) 197011051Sandreas.hansson@arm.com wb_pkt->assertShared(); 197111051Sandreas.hansson@arm.com } else { 197211051Sandreas.hansson@arm.com // if we're not asserting the shared line, we need to 197311051Sandreas.hansson@arm.com // invalidate our copy. we'll do that below as long as 197411051Sandreas.hansson@arm.com // the packet's invalidate flag is set... 197511051Sandreas.hansson@arm.com assert(pkt->isInvalidate()); 197611051Sandreas.hansson@arm.com } 197711051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(), 197811051Sandreas.hansson@arm.com false, false); 197911051Sandreas.hansson@arm.com } else { 198011051Sandreas.hansson@arm.com assert(wb_pkt->cmd == MemCmd::CleanEvict); 198111051Sandreas.hansson@arm.com // The cache technically holds the block until the 198211051Sandreas.hansson@arm.com // corresponding CleanEvict message reaches the crossbar 198311051Sandreas.hansson@arm.com // below. Therefore when a snoop encounters a CleanEvict 198411051Sandreas.hansson@arm.com // message we must set assertShared (just like when it 198511051Sandreas.hansson@arm.com // encounters a Writeback) to avoid the snoop filter 198611051Sandreas.hansson@arm.com // prematurely clearing the holder bit in the crossbar 198711051Sandreas.hansson@arm.com // below 198811051Sandreas.hansson@arm.com if (!pkt->needsExclusive()) 198911051Sandreas.hansson@arm.com pkt->assertShared(); 199011051Sandreas.hansson@arm.com else 199111051Sandreas.hansson@arm.com assert(pkt->isInvalidate()); 199211051Sandreas.hansson@arm.com } 199311051Sandreas.hansson@arm.com 199411051Sandreas.hansson@arm.com if (pkt->isInvalidate()) { 199511051Sandreas.hansson@arm.com // Invalidation trumps our writeback... discard here 199611051Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 199711051Sandreas.hansson@arm.com markInService(wb_entry, false); 199811051Sandreas.hansson@arm.com delete wb_pkt; 199911051Sandreas.hansson@arm.com } 200011051Sandreas.hansson@arm.com } 200111051Sandreas.hansson@arm.com 200211051Sandreas.hansson@arm.com // If this was a shared writeback, there may still be 200311051Sandreas.hansson@arm.com // other shared copies above that require invalidation. 200411051Sandreas.hansson@arm.com // We could be more selective and return here if the 200511051Sandreas.hansson@arm.com // request is non-exclusive or if the writeback is 200611051Sandreas.hansson@arm.com // exclusive. 200711051Sandreas.hansson@arm.com handleSnoop(pkt, blk, true, false, false); 200811051Sandreas.hansson@arm.com} 200911051Sandreas.hansson@arm.com 201011051Sandreas.hansson@arm.combool 201111051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 201211051Sandreas.hansson@arm.com{ 201311051Sandreas.hansson@arm.com // Express snoop responses from master to slave, e.g., from L1 to L2 201411051Sandreas.hansson@arm.com cache->recvTimingSnoopResp(pkt); 201511051Sandreas.hansson@arm.com return true; 201611051Sandreas.hansson@arm.com} 201711051Sandreas.hansson@arm.com 201811051Sandreas.hansson@arm.comTick 201911051Sandreas.hansson@arm.comCache::recvAtomicSnoop(PacketPtr pkt) 202011051Sandreas.hansson@arm.com{ 202111051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 202211051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 202311051Sandreas.hansson@arm.com 202411051Sandreas.hansson@arm.com // no need to snoop writebacks or requests that are not in range. In 202511051Sandreas.hansson@arm.com // atomic we have no Writebacks/CleanEvicts queued and no prefetches, 202611051Sandreas.hansson@arm.com // hence there is no need to snoop upwards and determine if they are 202711051Sandreas.hansson@arm.com // present above. 202811051Sandreas.hansson@arm.com if (pkt->evictingBlock() || !inRange(pkt->getAddr())) { 202911051Sandreas.hansson@arm.com return 0; 203011051Sandreas.hansson@arm.com } 203111051Sandreas.hansson@arm.com 203211051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 203311051Sandreas.hansson@arm.com handleSnoop(pkt, blk, false, false, false); 203411051Sandreas.hansson@arm.com // We consider forwardLatency here because a snoop occurs in atomic mode 203511051Sandreas.hansson@arm.com return forwardLatency * clockPeriod(); 203611051Sandreas.hansson@arm.com} 203711051Sandreas.hansson@arm.com 203811051Sandreas.hansson@arm.com 203911051Sandreas.hansson@arm.comMSHR * 204011051Sandreas.hansson@arm.comCache::getNextMSHR() 204111051Sandreas.hansson@arm.com{ 204211051Sandreas.hansson@arm.com // Check both MSHR queue and write buffer for potential requests, 204311051Sandreas.hansson@arm.com // note that null does not mean there is no request, it could 204411051Sandreas.hansson@arm.com // simply be that it is not ready 204511051Sandreas.hansson@arm.com MSHR *miss_mshr = mshrQueue.getNextMSHR(); 204611051Sandreas.hansson@arm.com MSHR *write_mshr = writeBuffer.getNextMSHR(); 204711051Sandreas.hansson@arm.com 204811051Sandreas.hansson@arm.com // If we got a write buffer request ready, first priority is a 204911051Sandreas.hansson@arm.com // full write buffer, otherwhise we favour the miss requests 205011051Sandreas.hansson@arm.com if (write_mshr && 205111051Sandreas.hansson@arm.com ((writeBuffer.isFull() && writeBuffer.inServiceEntries == 0) || 205211051Sandreas.hansson@arm.com !miss_mshr)) { 205311051Sandreas.hansson@arm.com // need to search MSHR queue for conflicting earlier miss. 205411051Sandreas.hansson@arm.com MSHR *conflict_mshr = 205511051Sandreas.hansson@arm.com mshrQueue.findPending(write_mshr->blkAddr, 205611051Sandreas.hansson@arm.com write_mshr->isSecure); 205711051Sandreas.hansson@arm.com 205811051Sandreas.hansson@arm.com if (conflict_mshr && conflict_mshr->order < write_mshr->order) { 205911051Sandreas.hansson@arm.com // Service misses in order until conflict is cleared. 206011051Sandreas.hansson@arm.com return conflict_mshr; 206111051Sandreas.hansson@arm.com 206211051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 206311051Sandreas.hansson@arm.com } 206411051Sandreas.hansson@arm.com 206511051Sandreas.hansson@arm.com // No conflicts; issue write 206611051Sandreas.hansson@arm.com return write_mshr; 206711051Sandreas.hansson@arm.com } else if (miss_mshr) { 206811051Sandreas.hansson@arm.com // need to check for conflicting earlier writeback 206911051Sandreas.hansson@arm.com MSHR *conflict_mshr = 207011051Sandreas.hansson@arm.com writeBuffer.findPending(miss_mshr->blkAddr, 207111051Sandreas.hansson@arm.com miss_mshr->isSecure); 207211051Sandreas.hansson@arm.com if (conflict_mshr) { 207311051Sandreas.hansson@arm.com // not sure why we don't check order here... it was in the 207411051Sandreas.hansson@arm.com // original code but commented out. 207511051Sandreas.hansson@arm.com 207611051Sandreas.hansson@arm.com // The only way this happens is if we are 207711051Sandreas.hansson@arm.com // doing a write and we didn't have permissions 207811051Sandreas.hansson@arm.com // then subsequently saw a writeback (owned got evicted) 207911051Sandreas.hansson@arm.com // We need to make sure to perform the writeback first 208011051Sandreas.hansson@arm.com // To preserve the dirty data, then we can issue the write 208111051Sandreas.hansson@arm.com 208211051Sandreas.hansson@arm.com // should we return write_mshr here instead? I.e. do we 208311051Sandreas.hansson@arm.com // have to flush writes in order? I don't think so... not 208411051Sandreas.hansson@arm.com // for Alpha anyway. Maybe for x86? 208511051Sandreas.hansson@arm.com return conflict_mshr; 208611051Sandreas.hansson@arm.com 208711051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 208811051Sandreas.hansson@arm.com } 208911051Sandreas.hansson@arm.com 209011051Sandreas.hansson@arm.com // No conflicts; issue read 209111051Sandreas.hansson@arm.com return miss_mshr; 209211051Sandreas.hansson@arm.com } 209311051Sandreas.hansson@arm.com 209411051Sandreas.hansson@arm.com // fall through... no pending requests. Try a prefetch. 209511051Sandreas.hansson@arm.com assert(!miss_mshr && !write_mshr); 209611051Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 209711051Sandreas.hansson@arm.com // If we have a miss queue slot, we can try a prefetch 209811051Sandreas.hansson@arm.com PacketPtr pkt = prefetcher->getPacket(); 209911051Sandreas.hansson@arm.com if (pkt) { 210011051Sandreas.hansson@arm.com Addr pf_addr = blockAlign(pkt->getAddr()); 210111051Sandreas.hansson@arm.com if (!tags->findBlock(pf_addr, pkt->isSecure()) && 210211051Sandreas.hansson@arm.com !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 210311051Sandreas.hansson@arm.com !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 210411051Sandreas.hansson@arm.com // Update statistic on number of prefetches issued 210511051Sandreas.hansson@arm.com // (hwpf_mshr_misses) 210611051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 210711051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 210811051Sandreas.hansson@arm.com 210911051Sandreas.hansson@arm.com // allocate an MSHR and return it, note 211011051Sandreas.hansson@arm.com // that we send the packet straight away, so do not 211111051Sandreas.hansson@arm.com // schedule the send 211211051Sandreas.hansson@arm.com return allocateMissBuffer(pkt, curTick(), false); 211311051Sandreas.hansson@arm.com } else { 211411051Sandreas.hansson@arm.com // free the request and packet 211511051Sandreas.hansson@arm.com delete pkt->req; 211611051Sandreas.hansson@arm.com delete pkt; 211711051Sandreas.hansson@arm.com } 211811051Sandreas.hansson@arm.com } 211911051Sandreas.hansson@arm.com } 212011051Sandreas.hansson@arm.com 212111051Sandreas.hansson@arm.com return NULL; 212211051Sandreas.hansson@arm.com} 212311051Sandreas.hansson@arm.com 212411051Sandreas.hansson@arm.combool 212511051Sandreas.hansson@arm.comCache::isCachedAbove(const PacketPtr pkt) const 212611051Sandreas.hansson@arm.com{ 212711051Sandreas.hansson@arm.com if (!forwardSnoops) 212811051Sandreas.hansson@arm.com return false; 212911051Sandreas.hansson@arm.com // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and 213011051Sandreas.hansson@arm.com // Writeback snoops into upper level caches to check for copies of the 213111051Sandreas.hansson@arm.com // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict 213211051Sandreas.hansson@arm.com // packet, the cache can inform the crossbar below of presence or absence 213311051Sandreas.hansson@arm.com // of the block. 213411051Sandreas.hansson@arm.com 213511051Sandreas.hansson@arm.com Packet snoop_pkt(pkt, true, false); 213611051Sandreas.hansson@arm.com snoop_pkt.setExpressSnoop(); 213711051Sandreas.hansson@arm.com // Assert that packet is either Writeback or CleanEvict and not a prefetch 213811051Sandreas.hansson@arm.com // request because prefetch requests need an MSHR and may generate a snoop 213911051Sandreas.hansson@arm.com // response. 214011051Sandreas.hansson@arm.com assert(pkt->evictingBlock()); 214111051Sandreas.hansson@arm.com snoop_pkt.senderState = NULL; 214211051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 214311051Sandreas.hansson@arm.com // Writeback/CleanEvict snoops do not generate a separate snoop response. 214411051Sandreas.hansson@arm.com assert(!(snoop_pkt.memInhibitAsserted())); 214511051Sandreas.hansson@arm.com return snoop_pkt.isBlockCached(); 214611051Sandreas.hansson@arm.com} 214711051Sandreas.hansson@arm.com 214811051Sandreas.hansson@arm.comPacketPtr 214911051Sandreas.hansson@arm.comCache::getTimingPacket() 215011051Sandreas.hansson@arm.com{ 215111051Sandreas.hansson@arm.com MSHR *mshr = getNextMSHR(); 215211051Sandreas.hansson@arm.com 215311051Sandreas.hansson@arm.com if (mshr == NULL) { 215411051Sandreas.hansson@arm.com return NULL; 215511051Sandreas.hansson@arm.com } 215611051Sandreas.hansson@arm.com 215711051Sandreas.hansson@arm.com // use request from 1st target 215811051Sandreas.hansson@arm.com PacketPtr tgt_pkt = mshr->getTarget()->pkt; 215911051Sandreas.hansson@arm.com PacketPtr pkt = NULL; 216011051Sandreas.hansson@arm.com 216111051Sandreas.hansson@arm.com DPRINTF(CachePort, "%s %s for addr %#llx size %d\n", __func__, 216211051Sandreas.hansson@arm.com tgt_pkt->cmdString(), tgt_pkt->getAddr(), tgt_pkt->getSize()); 216311051Sandreas.hansson@arm.com 216411051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 216511051Sandreas.hansson@arm.com 216611051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) { 216711051Sandreas.hansson@arm.com // We need to check the caches above us to verify that 216811051Sandreas.hansson@arm.com // they don't have a copy of this block in the dirty state 216911051Sandreas.hansson@arm.com // at the moment. Without this check we could get a stale 217011051Sandreas.hansson@arm.com // copy from memory that might get used in place of the 217111051Sandreas.hansson@arm.com // dirty one. 217211051Sandreas.hansson@arm.com Packet snoop_pkt(tgt_pkt, true, false); 217311051Sandreas.hansson@arm.com snoop_pkt.setExpressSnoop(); 217411051Sandreas.hansson@arm.com snoop_pkt.senderState = mshr; 217511051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 217611051Sandreas.hansson@arm.com 217711051Sandreas.hansson@arm.com // Check to see if the prefetch was squashed by an upper cache (to 217811051Sandreas.hansson@arm.com // prevent us from grabbing the line) or if a Check to see if a 217911051Sandreas.hansson@arm.com // writeback arrived between the time the prefetch was placed in 218011051Sandreas.hansson@arm.com // the MSHRs and when it was selected to be sent or if the 218111051Sandreas.hansson@arm.com // prefetch was squashed by an upper cache. 218211051Sandreas.hansson@arm.com 218311051Sandreas.hansson@arm.com // It is important to check memInhibitAsserted before 218411051Sandreas.hansson@arm.com // prefetchSquashed. If another cache has asserted MEM_INGIBIT, it 218511051Sandreas.hansson@arm.com // will be sending a response which will arrive at the MSHR 218611051Sandreas.hansson@arm.com // allocated ofr this request. Checking the prefetchSquash first 218711051Sandreas.hansson@arm.com // may result in the MSHR being prematurely deallocated. 218811051Sandreas.hansson@arm.com 218911051Sandreas.hansson@arm.com if (snoop_pkt.memInhibitAsserted()) { 219011051Sandreas.hansson@arm.com // If we are getting a non-shared response it is dirty 219111051Sandreas.hansson@arm.com bool pending_dirty_resp = !snoop_pkt.sharedAsserted(); 219211051Sandreas.hansson@arm.com markInService(mshr, pending_dirty_resp); 219311051Sandreas.hansson@arm.com DPRINTF(Cache, "Upward snoop of prefetch for addr" 219411051Sandreas.hansson@arm.com " %#x (%s) hit\n", 219511051Sandreas.hansson@arm.com tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns"); 219611051Sandreas.hansson@arm.com return NULL; 219711051Sandreas.hansson@arm.com } 219811051Sandreas.hansson@arm.com 219911051Sandreas.hansson@arm.com if (snoop_pkt.isBlockCached() || blk != NULL) { 220011051Sandreas.hansson@arm.com DPRINTF(Cache, "Block present, prefetch squashed by cache. " 220111051Sandreas.hansson@arm.com "Deallocating mshr target %#x.\n", 220211051Sandreas.hansson@arm.com mshr->blkAddr); 220311051Sandreas.hansson@arm.com 220411051Sandreas.hansson@arm.com // Deallocate the mshr target 220511051Sandreas.hansson@arm.com if (tgt_pkt->cmd != MemCmd::Writeback) { 220611051Sandreas.hansson@arm.com if (mshr->queue->forceDeallocateTarget(mshr)) { 220711051Sandreas.hansson@arm.com // Clear block if this deallocation resulted freed an 220811051Sandreas.hansson@arm.com // mshr when all had previously been utilized 220911051Sandreas.hansson@arm.com clearBlocked((BlockedCause)(mshr->queue->index)); 221011051Sandreas.hansson@arm.com } 221111051Sandreas.hansson@arm.com return NULL; 221211051Sandreas.hansson@arm.com } else { 221311051Sandreas.hansson@arm.com // If this is a Writeback, and the snoops indicate that the blk 221411051Sandreas.hansson@arm.com // is cached above, set the BLOCK_CACHED flag in the Writeback 221511051Sandreas.hansson@arm.com // packet, so that it does not reset the bits corresponding to 221611051Sandreas.hansson@arm.com // this block in the snoop filter below. 221711051Sandreas.hansson@arm.com tgt_pkt->setBlockCached(); 221811051Sandreas.hansson@arm.com } 221911051Sandreas.hansson@arm.com } 222011051Sandreas.hansson@arm.com } 222111051Sandreas.hansson@arm.com 222211051Sandreas.hansson@arm.com if (mshr->isForwardNoResponse()) { 222311051Sandreas.hansson@arm.com // no response expected, just forward packet as it is 222411051Sandreas.hansson@arm.com assert(tags->findBlock(mshr->blkAddr, mshr->isSecure) == NULL); 222511051Sandreas.hansson@arm.com pkt = tgt_pkt; 222611051Sandreas.hansson@arm.com } else { 222711051Sandreas.hansson@arm.com pkt = getBusPacket(tgt_pkt, blk, mshr->needsExclusive()); 222811051Sandreas.hansson@arm.com 222911051Sandreas.hansson@arm.com mshr->isForward = (pkt == NULL); 223011051Sandreas.hansson@arm.com 223111051Sandreas.hansson@arm.com if (mshr->isForward) { 223211051Sandreas.hansson@arm.com // not a cache block request, but a response is expected 223311051Sandreas.hansson@arm.com // make copy of current packet to forward, keep current 223411051Sandreas.hansson@arm.com // copy for response handling 223511051Sandreas.hansson@arm.com pkt = new Packet(tgt_pkt, false, true); 223611051Sandreas.hansson@arm.com if (pkt->isWrite()) { 223711051Sandreas.hansson@arm.com pkt->setData(tgt_pkt->getConstPtr<uint8_t>()); 223811051Sandreas.hansson@arm.com } 223911051Sandreas.hansson@arm.com } 224011051Sandreas.hansson@arm.com } 224111051Sandreas.hansson@arm.com 224211051Sandreas.hansson@arm.com assert(pkt != NULL); 224311051Sandreas.hansson@arm.com pkt->senderState = mshr; 224411051Sandreas.hansson@arm.com return pkt; 224511051Sandreas.hansson@arm.com} 224611051Sandreas.hansson@arm.com 224711051Sandreas.hansson@arm.com 224811051Sandreas.hansson@arm.comTick 224911051Sandreas.hansson@arm.comCache::nextMSHRReadyTime() const 225011051Sandreas.hansson@arm.com{ 225111051Sandreas.hansson@arm.com Tick nextReady = std::min(mshrQueue.nextMSHRReadyTime(), 225211051Sandreas.hansson@arm.com writeBuffer.nextMSHRReadyTime()); 225311051Sandreas.hansson@arm.com 225411051Sandreas.hansson@arm.com // Don't signal prefetch ready time if no MSHRs available 225511051Sandreas.hansson@arm.com // Will signal once enoguh MSHRs are deallocated 225611051Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 225711051Sandreas.hansson@arm.com nextReady = std::min(nextReady, 225811051Sandreas.hansson@arm.com prefetcher->nextPrefetchReadyTime()); 225911051Sandreas.hansson@arm.com } 226011051Sandreas.hansson@arm.com 226111051Sandreas.hansson@arm.com return nextReady; 226211051Sandreas.hansson@arm.com} 226311051Sandreas.hansson@arm.com 226411051Sandreas.hansson@arm.comvoid 226511051Sandreas.hansson@arm.comCache::serialize(CheckpointOut &cp) const 226611051Sandreas.hansson@arm.com{ 226711051Sandreas.hansson@arm.com bool dirty(isDirty()); 226811051Sandreas.hansson@arm.com 226911051Sandreas.hansson@arm.com if (dirty) { 227011051Sandreas.hansson@arm.com warn("*** The cache still contains dirty data. ***\n"); 227111051Sandreas.hansson@arm.com warn(" Make sure to drain the system using the correct flags.\n"); 227211051Sandreas.hansson@arm.com warn(" This checkpoint will not restore correctly and dirty data in " 227311051Sandreas.hansson@arm.com "the cache will be lost!\n"); 227411051Sandreas.hansson@arm.com } 227511051Sandreas.hansson@arm.com 227611051Sandreas.hansson@arm.com // Since we don't checkpoint the data in the cache, any dirty data 227711051Sandreas.hansson@arm.com // will be lost when restoring from a checkpoint of a system that 227811051Sandreas.hansson@arm.com // wasn't drained properly. Flag the checkpoint as invalid if the 227911051Sandreas.hansson@arm.com // cache contains dirty data. 228011051Sandreas.hansson@arm.com bool bad_checkpoint(dirty); 228111051Sandreas.hansson@arm.com SERIALIZE_SCALAR(bad_checkpoint); 228211051Sandreas.hansson@arm.com} 228311051Sandreas.hansson@arm.com 228411051Sandreas.hansson@arm.comvoid 228511051Sandreas.hansson@arm.comCache::unserialize(CheckpointIn &cp) 228611051Sandreas.hansson@arm.com{ 228711051Sandreas.hansson@arm.com bool bad_checkpoint; 228811051Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(bad_checkpoint); 228911051Sandreas.hansson@arm.com if (bad_checkpoint) { 229011051Sandreas.hansson@arm.com fatal("Restoring from checkpoints with dirty caches is not supported " 229111051Sandreas.hansson@arm.com "in the classic memory system. Please remove any caches or " 229211051Sandreas.hansson@arm.com " drain them properly before taking checkpoints.\n"); 229311051Sandreas.hansson@arm.com } 229411051Sandreas.hansson@arm.com} 229511051Sandreas.hansson@arm.com 229611051Sandreas.hansson@arm.com/////////////// 229711051Sandreas.hansson@arm.com// 229811051Sandreas.hansson@arm.com// CpuSidePort 229911051Sandreas.hansson@arm.com// 230011051Sandreas.hansson@arm.com/////////////// 230111051Sandreas.hansson@arm.com 230211051Sandreas.hansson@arm.comAddrRangeList 230311051Sandreas.hansson@arm.comCache::CpuSidePort::getAddrRanges() const 230411051Sandreas.hansson@arm.com{ 230511051Sandreas.hansson@arm.com return cache->getAddrRanges(); 230611051Sandreas.hansson@arm.com} 230711051Sandreas.hansson@arm.com 230811051Sandreas.hansson@arm.combool 230911051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingReq(PacketPtr pkt) 231011051Sandreas.hansson@arm.com{ 231111051Sandreas.hansson@arm.com assert(!cache->system->bypassCaches()); 231211051Sandreas.hansson@arm.com 231311051Sandreas.hansson@arm.com bool success = false; 231411051Sandreas.hansson@arm.com 231511051Sandreas.hansson@arm.com // always let inhibited requests through, even if blocked, 231611051Sandreas.hansson@arm.com // ultimately we should check if this is an express snoop, but at 231711051Sandreas.hansson@arm.com // the moment that flag is only set in the cache itself 231811051Sandreas.hansson@arm.com if (pkt->memInhibitAsserted()) { 231911051Sandreas.hansson@arm.com // do not change the current retry state 232011051Sandreas.hansson@arm.com bool M5_VAR_USED bypass_success = cache->recvTimingReq(pkt); 232111051Sandreas.hansson@arm.com assert(bypass_success); 232211051Sandreas.hansson@arm.com return true; 232311051Sandreas.hansson@arm.com } else if (blocked || mustSendRetry) { 232411051Sandreas.hansson@arm.com // either already committed to send a retry, or blocked 232511051Sandreas.hansson@arm.com success = false; 232611051Sandreas.hansson@arm.com } else { 232711051Sandreas.hansson@arm.com // pass it on to the cache, and let the cache decide if we 232811051Sandreas.hansson@arm.com // have to retry or not 232911051Sandreas.hansson@arm.com success = cache->recvTimingReq(pkt); 233011051Sandreas.hansson@arm.com } 233111051Sandreas.hansson@arm.com 233211051Sandreas.hansson@arm.com // remember if we have to retry 233311051Sandreas.hansson@arm.com mustSendRetry = !success; 233411051Sandreas.hansson@arm.com return success; 233511051Sandreas.hansson@arm.com} 233611051Sandreas.hansson@arm.com 233711051Sandreas.hansson@arm.comTick 233811051Sandreas.hansson@arm.comCache::CpuSidePort::recvAtomic(PacketPtr pkt) 233911051Sandreas.hansson@arm.com{ 234011051Sandreas.hansson@arm.com return cache->recvAtomic(pkt); 234111051Sandreas.hansson@arm.com} 234211051Sandreas.hansson@arm.com 234311051Sandreas.hansson@arm.comvoid 234411051Sandreas.hansson@arm.comCache::CpuSidePort::recvFunctional(PacketPtr pkt) 234511051Sandreas.hansson@arm.com{ 234611051Sandreas.hansson@arm.com // functional request 234711051Sandreas.hansson@arm.com cache->functionalAccess(pkt, true); 234811051Sandreas.hansson@arm.com} 234911051Sandreas.hansson@arm.com 235011051Sandreas.hansson@arm.comCache:: 235111051Sandreas.hansson@arm.comCpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache, 235211051Sandreas.hansson@arm.com const std::string &_label) 235311051Sandreas.hansson@arm.com : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache) 235411051Sandreas.hansson@arm.com{ 235511051Sandreas.hansson@arm.com} 235611051Sandreas.hansson@arm.com 235711053Sandreas.hansson@arm.comCache* 235811053Sandreas.hansson@arm.comCacheParams::create() 235911053Sandreas.hansson@arm.com{ 236011053Sandreas.hansson@arm.com assert(tags); 236111053Sandreas.hansson@arm.com 236211053Sandreas.hansson@arm.com return new Cache(this); 236311053Sandreas.hansson@arm.com} 236411051Sandreas.hansson@arm.com/////////////// 236511051Sandreas.hansson@arm.com// 236611051Sandreas.hansson@arm.com// MemSidePort 236711051Sandreas.hansson@arm.com// 236811051Sandreas.hansson@arm.com/////////////// 236911051Sandreas.hansson@arm.com 237011051Sandreas.hansson@arm.combool 237111051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingResp(PacketPtr pkt) 237211051Sandreas.hansson@arm.com{ 237311051Sandreas.hansson@arm.com cache->recvTimingResp(pkt); 237411051Sandreas.hansson@arm.com return true; 237511051Sandreas.hansson@arm.com} 237611051Sandreas.hansson@arm.com 237711051Sandreas.hansson@arm.com// Express snooping requests to memside port 237811051Sandreas.hansson@arm.comvoid 237911051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 238011051Sandreas.hansson@arm.com{ 238111051Sandreas.hansson@arm.com // handle snooping requests 238211051Sandreas.hansson@arm.com cache->recvTimingSnoopReq(pkt); 238311051Sandreas.hansson@arm.com} 238411051Sandreas.hansson@arm.com 238511051Sandreas.hansson@arm.comTick 238611051Sandreas.hansson@arm.comCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 238711051Sandreas.hansson@arm.com{ 238811051Sandreas.hansson@arm.com return cache->recvAtomicSnoop(pkt); 238911051Sandreas.hansson@arm.com} 239011051Sandreas.hansson@arm.com 239111051Sandreas.hansson@arm.comvoid 239211051Sandreas.hansson@arm.comCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 239311051Sandreas.hansson@arm.com{ 239411051Sandreas.hansson@arm.com // functional snoop (note that in contrast to atomic we don't have 239511051Sandreas.hansson@arm.com // a specific functionalSnoop method, as they have the same 239611051Sandreas.hansson@arm.com // behaviour regardless) 239711051Sandreas.hansson@arm.com cache->functionalAccess(pkt, false); 239811051Sandreas.hansson@arm.com} 239911051Sandreas.hansson@arm.com 240011051Sandreas.hansson@arm.comvoid 240111051Sandreas.hansson@arm.comCache::CacheReqPacketQueue::sendDeferredPacket() 240211051Sandreas.hansson@arm.com{ 240311051Sandreas.hansson@arm.com // sanity check 240411051Sandreas.hansson@arm.com assert(!waitingOnRetry); 240511051Sandreas.hansson@arm.com 240611051Sandreas.hansson@arm.com // there should never be any deferred request packets in the 240711051Sandreas.hansson@arm.com // queue, instead we resly on the cache to provide the packets 240811051Sandreas.hansson@arm.com // from the MSHR queue or write queue 240911051Sandreas.hansson@arm.com assert(deferredPacketReadyTime() == MaxTick); 241011051Sandreas.hansson@arm.com 241111051Sandreas.hansson@arm.com // check for request packets (requests & writebacks) 241211051Sandreas.hansson@arm.com PacketPtr pkt = cache.getTimingPacket(); 241311051Sandreas.hansson@arm.com if (pkt == NULL) { 241411051Sandreas.hansson@arm.com // can happen if e.g. we attempt a writeback and fail, but 241511051Sandreas.hansson@arm.com // before the retry, the writeback is eliminated because 241611051Sandreas.hansson@arm.com // we snoop another cache's ReadEx. 241711051Sandreas.hansson@arm.com } else { 241811051Sandreas.hansson@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState); 241911051Sandreas.hansson@arm.com // in most cases getTimingPacket allocates a new packet, and 242011051Sandreas.hansson@arm.com // we must delete it unless it is successfully sent 242111051Sandreas.hansson@arm.com bool delete_pkt = !mshr->isForwardNoResponse(); 242211051Sandreas.hansson@arm.com 242311051Sandreas.hansson@arm.com // let our snoop responses go first if there are responses to 242411051Sandreas.hansson@arm.com // the same addresses we are about to writeback, note that 242511051Sandreas.hansson@arm.com // this creates a dependency between requests and snoop 242611051Sandreas.hansson@arm.com // responses, but that should not be a problem since there is 242711051Sandreas.hansson@arm.com // a chain already and the key is that the snoop responses can 242811051Sandreas.hansson@arm.com // sink unconditionally 242911051Sandreas.hansson@arm.com if (snoopRespQueue.hasAddr(pkt->getAddr())) { 243011051Sandreas.hansson@arm.com DPRINTF(CachePort, "Waiting for snoop response to be sent\n"); 243111051Sandreas.hansson@arm.com Tick when = snoopRespQueue.deferredPacketReadyTime(); 243211051Sandreas.hansson@arm.com schedSendEvent(when); 243311051Sandreas.hansson@arm.com 243411051Sandreas.hansson@arm.com if (delete_pkt) 243511051Sandreas.hansson@arm.com delete pkt; 243611051Sandreas.hansson@arm.com 243711051Sandreas.hansson@arm.com return; 243811051Sandreas.hansson@arm.com } 243911051Sandreas.hansson@arm.com 244011051Sandreas.hansson@arm.com 244111051Sandreas.hansson@arm.com waitingOnRetry = !masterPort.sendTimingReq(pkt); 244211051Sandreas.hansson@arm.com 244311051Sandreas.hansson@arm.com if (waitingOnRetry) { 244411051Sandreas.hansson@arm.com DPRINTF(CachePort, "now waiting on a retry\n"); 244511051Sandreas.hansson@arm.com if (delete_pkt) { 244611051Sandreas.hansson@arm.com // we are awaiting a retry, but we 244711051Sandreas.hansson@arm.com // delete the packet and will be creating a new packet 244811051Sandreas.hansson@arm.com // when we get the opportunity 244911051Sandreas.hansson@arm.com delete pkt; 245011051Sandreas.hansson@arm.com } 245111051Sandreas.hansson@arm.com // note that we have now masked any requestBus and 245211051Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 245311051Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 245411051Sandreas.hansson@arm.com // care about this packet and might override it before 245511051Sandreas.hansson@arm.com // it gets retried 245611051Sandreas.hansson@arm.com } else { 245711051Sandreas.hansson@arm.com // As part of the call to sendTimingReq the packet is 245811051Sandreas.hansson@arm.com // forwarded to all neighbouring caches (and any 245911051Sandreas.hansson@arm.com // caches above them) as a snoop. The packet is also 246011051Sandreas.hansson@arm.com // sent to any potential cache below as the 246111051Sandreas.hansson@arm.com // interconnect is not allowed to buffer the 246211051Sandreas.hansson@arm.com // packet. Thus at this point we know if any of the 246311051Sandreas.hansson@arm.com // neighbouring, or the downstream cache is 246411051Sandreas.hansson@arm.com // responding, and if so, if it is with a dirty line 246511051Sandreas.hansson@arm.com // or not. 246611051Sandreas.hansson@arm.com bool pending_dirty_resp = !pkt->sharedAsserted() && 246711051Sandreas.hansson@arm.com pkt->memInhibitAsserted(); 246811051Sandreas.hansson@arm.com 246911051Sandreas.hansson@arm.com cache.markInService(mshr, pending_dirty_resp); 247011051Sandreas.hansson@arm.com } 247111051Sandreas.hansson@arm.com } 247211051Sandreas.hansson@arm.com 247311051Sandreas.hansson@arm.com // if we succeeded and are not waiting for a retry, schedule the 247411051Sandreas.hansson@arm.com // next send considering when the next MSHR is ready, note that 247511051Sandreas.hansson@arm.com // snoop responses have their own packet queue and thus schedule 247611051Sandreas.hansson@arm.com // their own events 247711051Sandreas.hansson@arm.com if (!waitingOnRetry) { 247811051Sandreas.hansson@arm.com schedSendEvent(cache.nextMSHRReadyTime()); 247911051Sandreas.hansson@arm.com } 248011051Sandreas.hansson@arm.com} 248111051Sandreas.hansson@arm.com 248211051Sandreas.hansson@arm.comCache:: 248311051Sandreas.hansson@arm.comMemSidePort::MemSidePort(const std::string &_name, Cache *_cache, 248411051Sandreas.hansson@arm.com const std::string &_label) 248511051Sandreas.hansson@arm.com : BaseCache::CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 248611051Sandreas.hansson@arm.com _reqQueue(*_cache, *this, _snoopRespQueue, _label), 248711051Sandreas.hansson@arm.com _snoopRespQueue(*_cache, *this, _label), cache(_cache) 248811051Sandreas.hansson@arm.com{ 248911051Sandreas.hansson@arm.com} 2490