base.hh revision 8736:2d8a57343fe3
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 * Steve Reinhardt 30 * Ron Dreslinski 31 */ 32 33/** 34 * @file 35 * Declares a basic cache interface BaseCache. 36 */ 37 38#ifndef __BASE_CACHE_HH__ 39#define __BASE_CACHE_HH__ 40 41#include <algorithm> 42#include <list> 43#include <string> 44#include <vector> 45 46#include "base/misc.hh" 47#include "base/statistics.hh" 48#include "base/trace.hh" 49#include "base/types.hh" 50#include "config/full_system.hh" 51#include "debug/Cache.hh" 52#include "debug/CachePort.hh" 53#include "mem/cache/mshr_queue.hh" 54#include "mem/mem_object.hh" 55#include "mem/packet.hh" 56#include "mem/request.hh" 57#include "mem/tport.hh" 58#include "params/BaseCache.hh" 59#include "sim/eventq.hh" 60#include "sim/sim_exit.hh" 61 62class MSHR; 63/** 64 * A basic cache interface. Implements some common functions for speed. 65 */ 66class BaseCache : public MemObject 67{ 68 /** 69 * Indexes to enumerate the MSHR queues. 70 */ 71 enum MSHRQueueIndex { 72 MSHRQueue_MSHRs, 73 MSHRQueue_WriteBuffer 74 }; 75 76 /** 77 * Reasons for caches to be blocked. 78 */ 79 enum BlockedCause { 80 Blocked_NoMSHRs = MSHRQueue_MSHRs, 81 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 82 Blocked_NoTargets, 83 NUM_BLOCKED_CAUSES 84 }; 85 86 public: 87 /** 88 * Reasons for cache to request a bus. 89 */ 90 enum RequestCause { 91 Request_MSHR = MSHRQueue_MSHRs, 92 Request_WB = MSHRQueue_WriteBuffer, 93 Request_PF, 94 NUM_REQUEST_CAUSES 95 }; 96 97 private: 98 99 class CachePort : public SimpleTimingPort 100 { 101 public: 102 BaseCache *cache; 103 104 protected: 105 CachePort(const std::string &_name, BaseCache *_cache, 106 const std::string &_label); 107 108 virtual unsigned deviceBlockSize() const; 109 110 bool recvRetryCommon(); 111 112 typedef EventWrapper<Port, &Port::sendRetry> 113 SendRetryEvent; 114 115 const std::string label; 116 117 public: 118 void setBlocked(); 119 120 void clearBlocked(); 121 122 bool checkFunctional(PacketPtr pkt); 123 124 bool blocked; 125 126 bool mustSendRetry; 127 128 void requestBus(RequestCause cause, Tick time) 129 { 130 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); 131 if (!waitingOnRetry) { 132 schedSendEvent(time); 133 } 134 } 135 136 void respond(PacketPtr pkt, Tick time) { 137 schedSendTiming(pkt, time); 138 } 139 }; 140 141 public: //Made public so coherence can get at it. 142 CachePort *cpuSidePort; 143 CachePort *memSidePort; 144 145 protected: 146 147 /** Miss status registers */ 148 MSHRQueue mshrQueue; 149 150 /** Write/writeback buffer */ 151 MSHRQueue writeBuffer; 152 153 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 154 PacketPtr pkt, Tick time, bool requestBus) 155 { 156 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++); 157 158 if (mq->isFull()) { 159 setBlocked((BlockedCause)mq->index); 160 } 161 162 if (requestBus) { 163 requestMemSideBus((RequestCause)mq->index, time); 164 } 165 166 return mshr; 167 } 168 169 void markInServiceInternal(MSHR *mshr, PacketPtr pkt) 170 { 171 MSHRQueue *mq = mshr->queue; 172 bool wasFull = mq->isFull(); 173 mq->markInService(mshr, pkt); 174 if (wasFull && !mq->isFull()) { 175 clearBlocked((BlockedCause)mq->index); 176 } 177 } 178 179 /** Block size of this cache */ 180 const unsigned blkSize; 181 182 /** 183 * The latency of a hit in this device. 184 */ 185 int hitLatency; 186 187 /** The number of targets for each MSHR. */ 188 const int numTarget; 189 190 /** Do we forward snoops from mem side port through to cpu side port? */ 191 bool forwardSnoops; 192 193 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should 194 * never try to forward ownership and similar optimizations to the cpu 195 * side */ 196 bool isTopLevel; 197 198 /** 199 * Bit vector of the blocking reasons for the access path. 200 * @sa #BlockedCause 201 */ 202 uint8_t blocked; 203 204 /** Increasing order number assigned to each incoming request. */ 205 uint64_t order; 206 207 /** Stores time the cache blocked for statistics. */ 208 Tick blockedCycle; 209 210 /** Pointer to the MSHR that has no targets. */ 211 MSHR *noTargetMSHR; 212 213 /** The number of misses to trigger an exit event. */ 214 Counter missCount; 215 216 /** The drain event. */ 217 Event *drainEvent; 218 219 /** 220 * The address range to which the cache responds on the CPU side. 221 * Normally this is all possible memory addresses. */ 222 Range<Addr> addrRange; 223 224 /** number of cpus sharing this cache - from config file */ 225 int _numCpus; 226 227 public: 228 int numCpus() { return _numCpus; } 229 // Statistics 230 /** 231 * @addtogroup CacheStatistics 232 * @{ 233 */ 234 235 /** Number of hits per thread for each type of command. @sa Packet::Command */ 236 Stats::Vector hits[MemCmd::NUM_MEM_CMDS]; 237 /** Number of hits for demand accesses. */ 238 Stats::Formula demandHits; 239 /** Number of hit for all accesses. */ 240 Stats::Formula overallHits; 241 242 /** Number of misses per thread for each type of command. @sa Packet::Command */ 243 Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; 244 /** Number of misses for demand accesses. */ 245 Stats::Formula demandMisses; 246 /** Number of misses for all accesses. */ 247 Stats::Formula overallMisses; 248 249 /** 250 * Total number of cycles per thread/command spent waiting for a miss. 251 * Used to calculate the average miss latency. 252 */ 253 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS]; 254 /** Total number of cycles spent waiting for demand misses. */ 255 Stats::Formula demandMissLatency; 256 /** Total number of cycles spent waiting for all misses. */ 257 Stats::Formula overallMissLatency; 258 259 /** The number of accesses per command and thread. */ 260 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 261 /** The number of demand accesses. */ 262 Stats::Formula demandAccesses; 263 /** The number of overall accesses. */ 264 Stats::Formula overallAccesses; 265 266 /** The miss rate per command and thread. */ 267 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 268 /** The miss rate of all demand accesses. */ 269 Stats::Formula demandMissRate; 270 /** The miss rate for all accesses. */ 271 Stats::Formula overallMissRate; 272 273 /** The average miss latency per command and thread. */ 274 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 275 /** The average miss latency for demand misses. */ 276 Stats::Formula demandAvgMissLatency; 277 /** The average miss latency for all misses. */ 278 Stats::Formula overallAvgMissLatency; 279 280 /** The total number of cycles blocked for each blocked cause. */ 281 Stats::Vector blocked_cycles; 282 /** The number of times this cache blocked for each blocked cause. */ 283 Stats::Vector blocked_causes; 284 285 /** The average number of cycles blocked for each blocked cause. */ 286 Stats::Formula avg_blocked; 287 288 /** The number of fast writes (WH64) performed. */ 289 Stats::Scalar fastWrites; 290 291 /** The number of cache copies performed. */ 292 Stats::Scalar cacheCopies; 293 294 /** Number of blocks written back per thread. */ 295 Stats::Vector writebacks; 296 297 /** Number of misses that hit in the MSHRs per command and thread. */ 298 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS]; 299 /** Demand misses that hit in the MSHRs. */ 300 Stats::Formula demandMshrHits; 301 /** Total number of misses that hit in the MSHRs. */ 302 Stats::Formula overallMshrHits; 303 304 /** Number of misses that miss in the MSHRs, per command and thread. */ 305 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS]; 306 /** Demand misses that miss in the MSHRs. */ 307 Stats::Formula demandMshrMisses; 308 /** Total number of misses that miss in the MSHRs. */ 309 Stats::Formula overallMshrMisses; 310 311 /** Number of misses that miss in the MSHRs, per command and thread. */ 312 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 313 /** Total number of misses that miss in the MSHRs. */ 314 Stats::Formula overallMshrUncacheable; 315 316 /** Total cycle latency of each MSHR miss, per command and thread. */ 317 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 318 /** Total cycle latency of demand MSHR misses. */ 319 Stats::Formula demandMshrMissLatency; 320 /** Total cycle latency of overall MSHR misses. */ 321 Stats::Formula overallMshrMissLatency; 322 323 /** Total cycle latency of each MSHR miss, per command and thread. */ 324 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 325 /** Total cycle latency of overall MSHR misses. */ 326 Stats::Formula overallMshrUncacheableLatency; 327 328#if 0 329 /** The total number of MSHR accesses per command and thread. */ 330 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 331 /** The total number of demand MSHR accesses. */ 332 Stats::Formula demandMshrAccesses; 333 /** The total number of MSHR accesses. */ 334 Stats::Formula overallMshrAccesses; 335#endif 336 337 /** The miss rate in the MSHRs pre command and thread. */ 338 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 339 /** The demand miss rate in the MSHRs. */ 340 Stats::Formula demandMshrMissRate; 341 /** The overall miss rate in the MSHRs. */ 342 Stats::Formula overallMshrMissRate; 343 344 /** The average latency of an MSHR miss, per command and thread. */ 345 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 346 /** The average latency of a demand MSHR miss. */ 347 Stats::Formula demandAvgMshrMissLatency; 348 /** The average overall latency of an MSHR miss. */ 349 Stats::Formula overallAvgMshrMissLatency; 350 351 /** The average latency of an MSHR miss, per command and thread. */ 352 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 353 /** The average overall latency of an MSHR miss. */ 354 Stats::Formula overallAvgMshrUncacheableLatency; 355 356 /** The number of times a thread hit its MSHR cap. */ 357 Stats::Vector mshr_cap_events; 358 /** The number of times software prefetches caused the MSHR to block. */ 359 Stats::Vector soft_prefetch_mshr_full; 360 361 Stats::Scalar mshr_no_allocate_misses; 362 363 /** 364 * @} 365 */ 366 367 /** 368 * Register stats for this object. 369 */ 370 virtual void regStats(); 371 372 public: 373 typedef BaseCacheParams Params; 374 BaseCache(const Params *p); 375 ~BaseCache() {} 376 377 virtual void init(); 378 379 /** 380 * Query block size of a cache. 381 * @return The block size 382 */ 383 unsigned 384 getBlockSize() const 385 { 386 return blkSize; 387 } 388 389 390 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); } 391 392 393 const Range<Addr> &getAddrRange() const { return addrRange; } 394 395 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 396 { 397 assert(!pkt->req->isUncacheable()); 398 return allocateBufferInternal(&mshrQueue, 399 blockAlign(pkt->getAddr()), blkSize, 400 pkt, time, requestBus); 401 } 402 403 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus) 404 { 405 assert(pkt->isWrite() && !pkt->isRead()); 406 return allocateBufferInternal(&writeBuffer, 407 pkt->getAddr(), pkt->getSize(), 408 pkt, time, requestBus); 409 } 410 411 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus) 412 { 413 assert(pkt->req->isUncacheable()); 414 assert(pkt->isRead()); 415 return allocateBufferInternal(&mshrQueue, 416 pkt->getAddr(), pkt->getSize(), 417 pkt, time, requestBus); 418 } 419 420 /** 421 * Returns true if the cache is blocked for accesses. 422 */ 423 bool isBlocked() 424 { 425 return blocked != 0; 426 } 427 428 /** 429 * Marks the access path of the cache as blocked for the given cause. This 430 * also sets the blocked flag in the slave interface. 431 * @param cause The reason for the cache blocking. 432 */ 433 void setBlocked(BlockedCause cause) 434 { 435 uint8_t flag = 1 << cause; 436 if (blocked == 0) { 437 blocked_causes[cause]++; 438 blockedCycle = curTick(); 439 cpuSidePort->setBlocked(); 440 } 441 blocked |= flag; 442 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 443 } 444 445 /** 446 * Marks the cache as unblocked for the given cause. This also clears the 447 * blocked flags in the appropriate interfaces. 448 * @param cause The newly unblocked cause. 449 * @warning Calling this function can cause a blocked request on the bus to 450 * access the cache. The cache must be in a state to handle that request. 451 */ 452 void clearBlocked(BlockedCause cause) 453 { 454 uint8_t flag = 1 << cause; 455 blocked &= ~flag; 456 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 457 if (blocked == 0) { 458 blocked_cycles[cause] += curTick() - blockedCycle; 459 cpuSidePort->clearBlocked(); 460 } 461 } 462 463 /** 464 * Request the master bus for the given cause and time. 465 * @param cause The reason for the request. 466 * @param time The time to make the request. 467 */ 468 void requestMemSideBus(RequestCause cause, Tick time) 469 { 470 memSidePort->requestBus(cause, time); 471 } 472 473 /** 474 * Clear the master bus request for the given cause. 475 * @param cause The request reason to clear. 476 */ 477 void deassertMemSideBusRequest(RequestCause cause) 478 { 479 // Obsolete... we no longer signal bus requests explicitly so 480 // we can't deassert them. Leaving this in as a no-op since 481 // the prefetcher calls it to indicate that it no longer wants 482 // to request a prefetch, and someday that might be 483 // interesting again. 484 } 485 486 virtual unsigned int drain(Event *de); 487 488 virtual bool inCache(Addr addr) = 0; 489 490 virtual bool inMissQueue(Addr addr) = 0; 491 492 void incMissCount(PacketPtr pkt, int id) 493 { 494 495 if (pkt->cmd == MemCmd::Writeback) { 496 assert(id == -1); 497 misses[pkt->cmdToIndex()][0]++; 498 /* same thing for writeback hits as misses - no context id 499 * available, meanwhile writeback hit/miss stats are not used 500 * in any aggregate hit/miss calculations, so just lump them all 501 * in bucket 0 */ 502#if FULL_SYSTEM 503 } else if (id == -1) { 504 // Device accesses have id -1 505 // lump device accesses into their own bucket 506 misses[pkt->cmdToIndex()][_numCpus]++; 507#endif 508 } else { 509 misses[pkt->cmdToIndex()][id % _numCpus]++; 510 } 511 512 if (missCount) { 513 --missCount; 514 if (missCount == 0) 515 exitSimLoop("A cache reached the maximum miss count"); 516 } 517 } 518 void incHitCount(PacketPtr pkt, int id) 519 { 520 521 /* Writeback requests don't have a context id associated with 522 * them, so attributing a hit to a -1 context id is obviously a 523 * problem. I've noticed in the stats that hits are split into 524 * demand and non-demand hits - neither of which include writeback 525 * hits, so here, I'll just put the writeback hits into bucket 0 526 * since it won't mess with any other stats -hsul */ 527 if (pkt->cmd == MemCmd::Writeback) { 528 assert(id == -1); 529 hits[pkt->cmdToIndex()][0]++; 530#if FULL_SYSTEM 531 } else if (id == -1) { 532 // Device accesses have id -1 533 // lump device accesses into their own bucket 534 hits[pkt->cmdToIndex()][_numCpus]++; 535#endif 536 } else { 537 /* the % is necessary in case there are switch cpus */ 538 hits[pkt->cmdToIndex()][id % _numCpus]++; 539 } 540 } 541 542}; 543 544#endif //__BASE_CACHE_HH__ 545