base.hh revision 8229:78bf55f23338
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 * Steve Reinhardt 30 * Ron Dreslinski 31 */ 32 33/** 34 * @file 35 * Declares a basic cache interface BaseCache. 36 */ 37 38#ifndef __BASE_CACHE_HH__ 39#define __BASE_CACHE_HH__ 40 41#include <algorithm> 42#include <list> 43#include <string> 44#include <vector> 45 46#include "base/misc.hh" 47#include "base/statistics.hh" 48#include "base/trace.hh" 49#include "base/types.hh" 50#include "config/full_system.hh" 51#include "mem/cache/mshr_queue.hh" 52#include "mem/mem_object.hh" 53#include "mem/packet.hh" 54#include "mem/request.hh" 55#include "mem/tport.hh" 56#include "params/BaseCache.hh" 57#include "sim/eventq.hh" 58#include "sim/sim_exit.hh" 59 60class MSHR; 61/** 62 * A basic cache interface. Implements some common functions for speed. 63 */ 64class BaseCache : public MemObject 65{ 66 /** 67 * Indexes to enumerate the MSHR queues. 68 */ 69 enum MSHRQueueIndex { 70 MSHRQueue_MSHRs, 71 MSHRQueue_WriteBuffer 72 }; 73 74 /** 75 * Reasons for caches to be blocked. 76 */ 77 enum BlockedCause { 78 Blocked_NoMSHRs = MSHRQueue_MSHRs, 79 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 80 Blocked_NoTargets, 81 NUM_BLOCKED_CAUSES 82 }; 83 84 public: 85 /** 86 * Reasons for cache to request a bus. 87 */ 88 enum RequestCause { 89 Request_MSHR = MSHRQueue_MSHRs, 90 Request_WB = MSHRQueue_WriteBuffer, 91 Request_PF, 92 NUM_REQUEST_CAUSES 93 }; 94 95 private: 96 97 class CachePort : public SimpleTimingPort 98 { 99 public: 100 BaseCache *cache; 101 102 protected: 103 CachePort(const std::string &_name, BaseCache *_cache, 104 const std::string &_label); 105 106 virtual void recvStatusChange(Status status); 107 108 virtual unsigned deviceBlockSize() const; 109 110 bool recvRetryCommon(); 111 112 typedef EventWrapper<Port, &Port::sendRetry> 113 SendRetryEvent; 114 115 const std::string label; 116 117 public: 118 void setOtherPort(CachePort *_otherPort) { otherPort = _otherPort; } 119 120 void setBlocked(); 121 122 void clearBlocked(); 123 124 bool checkFunctional(PacketPtr pkt); 125 126 CachePort *otherPort; 127 128 bool blocked; 129 130 bool mustSendRetry; 131 132 void requestBus(RequestCause cause, Tick time) 133 { 134 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); 135 if (!waitingOnRetry) { 136 schedSendEvent(time); 137 } 138 } 139 140 void respond(PacketPtr pkt, Tick time) { 141 schedSendTiming(pkt, time); 142 } 143 }; 144 145 public: //Made public so coherence can get at it. 146 CachePort *cpuSidePort; 147 CachePort *memSidePort; 148 149 protected: 150 151 /** Miss status registers */ 152 MSHRQueue mshrQueue; 153 154 /** Write/writeback buffer */ 155 MSHRQueue writeBuffer; 156 157 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 158 PacketPtr pkt, Tick time, bool requestBus) 159 { 160 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++); 161 162 if (mq->isFull()) { 163 setBlocked((BlockedCause)mq->index); 164 } 165 166 if (requestBus) { 167 requestMemSideBus((RequestCause)mq->index, time); 168 } 169 170 return mshr; 171 } 172 173 void markInServiceInternal(MSHR *mshr, PacketPtr pkt) 174 { 175 MSHRQueue *mq = mshr->queue; 176 bool wasFull = mq->isFull(); 177 mq->markInService(mshr, pkt); 178 if (wasFull && !mq->isFull()) { 179 clearBlocked((BlockedCause)mq->index); 180 } 181 } 182 183 /** Block size of this cache */ 184 const unsigned blkSize; 185 186 /** 187 * The latency of a hit in this device. 188 */ 189 int hitLatency; 190 191 /** The number of targets for each MSHR. */ 192 const int numTarget; 193 194 /** Do we forward snoops from mem side port through to cpu side port? */ 195 bool forwardSnoops; 196 197 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should 198 * never try to forward ownership and similar optimizations to the cpu 199 * side */ 200 bool isTopLevel; 201 202 /** 203 * Bit vector of the blocking reasons for the access path. 204 * @sa #BlockedCause 205 */ 206 uint8_t blocked; 207 208 /** Increasing order number assigned to each incoming request. */ 209 uint64_t order; 210 211 /** Stores time the cache blocked for statistics. */ 212 Tick blockedCycle; 213 214 /** Pointer to the MSHR that has no targets. */ 215 MSHR *noTargetMSHR; 216 217 /** The number of misses to trigger an exit event. */ 218 Counter missCount; 219 220 /** The drain event. */ 221 Event *drainEvent; 222 223 /** 224 * The address range to which the cache responds on the CPU side. 225 * Normally this is all possible memory addresses. */ 226 Range<Addr> addrRange; 227 228 /** number of cpus sharing this cache - from config file */ 229 int _numCpus; 230 231 public: 232 int numCpus() { return _numCpus; } 233 // Statistics 234 /** 235 * @addtogroup CacheStatistics 236 * @{ 237 */ 238 239 /** Number of hits per thread for each type of command. @sa Packet::Command */ 240 Stats::Vector hits[MemCmd::NUM_MEM_CMDS]; 241 /** Number of hits for demand accesses. */ 242 Stats::Formula demandHits; 243 /** Number of hit for all accesses. */ 244 Stats::Formula overallHits; 245 246 /** Number of misses per thread for each type of command. @sa Packet::Command */ 247 Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; 248 /** Number of misses for demand accesses. */ 249 Stats::Formula demandMisses; 250 /** Number of misses for all accesses. */ 251 Stats::Formula overallMisses; 252 253 /** 254 * Total number of cycles per thread/command spent waiting for a miss. 255 * Used to calculate the average miss latency. 256 */ 257 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS]; 258 /** Total number of cycles spent waiting for demand misses. */ 259 Stats::Formula demandMissLatency; 260 /** Total number of cycles spent waiting for all misses. */ 261 Stats::Formula overallMissLatency; 262 263 /** The number of accesses per command and thread. */ 264 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 265 /** The number of demand accesses. */ 266 Stats::Formula demandAccesses; 267 /** The number of overall accesses. */ 268 Stats::Formula overallAccesses; 269 270 /** The miss rate per command and thread. */ 271 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 272 /** The miss rate of all demand accesses. */ 273 Stats::Formula demandMissRate; 274 /** The miss rate for all accesses. */ 275 Stats::Formula overallMissRate; 276 277 /** The average miss latency per command and thread. */ 278 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 279 /** The average miss latency for demand misses. */ 280 Stats::Formula demandAvgMissLatency; 281 /** The average miss latency for all misses. */ 282 Stats::Formula overallAvgMissLatency; 283 284 /** The total number of cycles blocked for each blocked cause. */ 285 Stats::Vector blocked_cycles; 286 /** The number of times this cache blocked for each blocked cause. */ 287 Stats::Vector blocked_causes; 288 289 /** The average number of cycles blocked for each blocked cause. */ 290 Stats::Formula avg_blocked; 291 292 /** The number of fast writes (WH64) performed. */ 293 Stats::Scalar fastWrites; 294 295 /** The number of cache copies performed. */ 296 Stats::Scalar cacheCopies; 297 298 /** Number of blocks written back per thread. */ 299 Stats::Vector writebacks; 300 301 /** Number of misses that hit in the MSHRs per command and thread. */ 302 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS]; 303 /** Demand misses that hit in the MSHRs. */ 304 Stats::Formula demandMshrHits; 305 /** Total number of misses that hit in the MSHRs. */ 306 Stats::Formula overallMshrHits; 307 308 /** Number of misses that miss in the MSHRs, per command and thread. */ 309 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS]; 310 /** Demand misses that miss in the MSHRs. */ 311 Stats::Formula demandMshrMisses; 312 /** Total number of misses that miss in the MSHRs. */ 313 Stats::Formula overallMshrMisses; 314 315 /** Number of misses that miss in the MSHRs, per command and thread. */ 316 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 317 /** Total number of misses that miss in the MSHRs. */ 318 Stats::Formula overallMshrUncacheable; 319 320 /** Total cycle latency of each MSHR miss, per command and thread. */ 321 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 322 /** Total cycle latency of demand MSHR misses. */ 323 Stats::Formula demandMshrMissLatency; 324 /** Total cycle latency of overall MSHR misses. */ 325 Stats::Formula overallMshrMissLatency; 326 327 /** Total cycle latency of each MSHR miss, per command and thread. */ 328 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 329 /** Total cycle latency of overall MSHR misses. */ 330 Stats::Formula overallMshrUncacheableLatency; 331 332#if 0 333 /** The total number of MSHR accesses per command and thread. */ 334 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 335 /** The total number of demand MSHR accesses. */ 336 Stats::Formula demandMshrAccesses; 337 /** The total number of MSHR accesses. */ 338 Stats::Formula overallMshrAccesses; 339#endif 340 341 /** The miss rate in the MSHRs pre command and thread. */ 342 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 343 /** The demand miss rate in the MSHRs. */ 344 Stats::Formula demandMshrMissRate; 345 /** The overall miss rate in the MSHRs. */ 346 Stats::Formula overallMshrMissRate; 347 348 /** The average latency of an MSHR miss, per command and thread. */ 349 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 350 /** The average latency of a demand MSHR miss. */ 351 Stats::Formula demandAvgMshrMissLatency; 352 /** The average overall latency of an MSHR miss. */ 353 Stats::Formula overallAvgMshrMissLatency; 354 355 /** The average latency of an MSHR miss, per command and thread. */ 356 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 357 /** The average overall latency of an MSHR miss. */ 358 Stats::Formula overallAvgMshrUncacheableLatency; 359 360 /** The number of times a thread hit its MSHR cap. */ 361 Stats::Vector mshr_cap_events; 362 /** The number of times software prefetches caused the MSHR to block. */ 363 Stats::Vector soft_prefetch_mshr_full; 364 365 Stats::Scalar mshr_no_allocate_misses; 366 367 /** 368 * @} 369 */ 370 371 /** 372 * Register stats for this object. 373 */ 374 virtual void regStats(); 375 376 public: 377 typedef BaseCacheParams Params; 378 BaseCache(const Params *p); 379 ~BaseCache() {} 380 381 virtual void init(); 382 383 /** 384 * Query block size of a cache. 385 * @return The block size 386 */ 387 unsigned 388 getBlockSize() const 389 { 390 return blkSize; 391 } 392 393 394 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); } 395 396 397 const Range<Addr> &getAddrRange() const { return addrRange; } 398 399 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 400 { 401 assert(!pkt->req->isUncacheable()); 402 return allocateBufferInternal(&mshrQueue, 403 blockAlign(pkt->getAddr()), blkSize, 404 pkt, time, requestBus); 405 } 406 407 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus) 408 { 409 assert(pkt->isWrite() && !pkt->isRead()); 410 return allocateBufferInternal(&writeBuffer, 411 pkt->getAddr(), pkt->getSize(), 412 pkt, time, requestBus); 413 } 414 415 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus) 416 { 417 assert(pkt->req->isUncacheable()); 418 assert(pkt->isRead()); 419 return allocateBufferInternal(&mshrQueue, 420 pkt->getAddr(), pkt->getSize(), 421 pkt, time, requestBus); 422 } 423 424 /** 425 * Returns true if the cache is blocked for accesses. 426 */ 427 bool isBlocked() 428 { 429 return blocked != 0; 430 } 431 432 /** 433 * Marks the access path of the cache as blocked for the given cause. This 434 * also sets the blocked flag in the slave interface. 435 * @param cause The reason for the cache blocking. 436 */ 437 void setBlocked(BlockedCause cause) 438 { 439 uint8_t flag = 1 << cause; 440 if (blocked == 0) { 441 blocked_causes[cause]++; 442 blockedCycle = curTick(); 443 cpuSidePort->setBlocked(); 444 } 445 blocked |= flag; 446 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 447 } 448 449 /** 450 * Marks the cache as unblocked for the given cause. This also clears the 451 * blocked flags in the appropriate interfaces. 452 * @param cause The newly unblocked cause. 453 * @warning Calling this function can cause a blocked request on the bus to 454 * access the cache. The cache must be in a state to handle that request. 455 */ 456 void clearBlocked(BlockedCause cause) 457 { 458 uint8_t flag = 1 << cause; 459 blocked &= ~flag; 460 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 461 if (blocked == 0) { 462 blocked_cycles[cause] += curTick() - blockedCycle; 463 cpuSidePort->clearBlocked(); 464 } 465 } 466 467 /** 468 * Request the master bus for the given cause and time. 469 * @param cause The reason for the request. 470 * @param time The time to make the request. 471 */ 472 void requestMemSideBus(RequestCause cause, Tick time) 473 { 474 memSidePort->requestBus(cause, time); 475 } 476 477 /** 478 * Clear the master bus request for the given cause. 479 * @param cause The request reason to clear. 480 */ 481 void deassertMemSideBusRequest(RequestCause cause) 482 { 483 // Obsolete... we no longer signal bus requests explicitly so 484 // we can't deassert them. Leaving this in as a no-op since 485 // the prefetcher calls it to indicate that it no longer wants 486 // to request a prefetch, and someday that might be 487 // interesting again. 488 } 489 490 virtual unsigned int drain(Event *de); 491 492 virtual bool inCache(Addr addr) = 0; 493 494 virtual bool inMissQueue(Addr addr) = 0; 495 496 void incMissCount(PacketPtr pkt, int id) 497 { 498 499 if (pkt->cmd == MemCmd::Writeback) { 500 assert(id == -1); 501 misses[pkt->cmdToIndex()][0]++; 502 /* same thing for writeback hits as misses - no context id 503 * available, meanwhile writeback hit/miss stats are not used 504 * in any aggregate hit/miss calculations, so just lump them all 505 * in bucket 0 */ 506#if FULL_SYSTEM 507 } else if (id == -1) { 508 // Device accesses have id -1 509 // lump device accesses into their own bucket 510 misses[pkt->cmdToIndex()][_numCpus]++; 511#endif 512 } else { 513 misses[pkt->cmdToIndex()][id % _numCpus]++; 514 } 515 516 if (missCount) { 517 --missCount; 518 if (missCount == 0) 519 exitSimLoop("A cache reached the maximum miss count"); 520 } 521 } 522 void incHitCount(PacketPtr pkt, int id) 523 { 524 525 /* Writeback requests don't have a context id associated with 526 * them, so attributing a hit to a -1 context id is obviously a 527 * problem. I've noticed in the stats that hits are split into 528 * demand and non-demand hits - neither of which include writeback 529 * hits, so here, I'll just put the writeback hits into bucket 0 530 * since it won't mess with any other stats -hsul */ 531 if (pkt->cmd == MemCmd::Writeback) { 532 assert(id == -1); 533 hits[pkt->cmdToIndex()][0]++; 534#if FULL_SYSTEM 535 } else if (id == -1) { 536 // Device accesses have id -1 537 // lump device accesses into their own bucket 538 hits[pkt->cmdToIndex()][_numCpus]++; 539#endif 540 } else { 541 /* the % is necessary in case there are switch cpus */ 542 hits[pkt->cmdToIndex()][id % _numCpus]++; 543 } 544 } 545 546}; 547 548#endif //__BASE_CACHE_HH__ 549