base.hh revision 7676:92274350b953
12068SN/A/* 22068SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32068SN/A * All rights reserved. 42068SN/A * 52068SN/A * Redistribution and use in source and binary forms, with or without 62068SN/A * modification, are permitted provided that the following conditions are 72068SN/A * met: redistributions of source code must retain the above copyright 82068SN/A * notice, this list of conditions and the following disclaimer; 92068SN/A * redistributions in binary form must reproduce the above copyright 102068SN/A * notice, this list of conditions and the following disclaimer in the 112068SN/A * documentation and/or other materials provided with the distribution; 122068SN/A * neither the name of the copyright holders nor the names of its 132068SN/A * contributors may be used to endorse or promote products derived from 142068SN/A * this software without specific prior written permission. 152068SN/A * 162068SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172068SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182068SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192068SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202068SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212068SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222068SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232068SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242068SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252068SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262068SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272068SN/A * 282665Ssaidi@eecs.umich.edu * Authors: Erik Hallnor 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302068SN/A * Ron Dreslinski 312649Ssaidi@eecs.umich.edu */ 322649Ssaidi@eecs.umich.edu 332649Ssaidi@eecs.umich.edu/** 342649Ssaidi@eecs.umich.edu * @file 352649Ssaidi@eecs.umich.edu * Declares a basic cache interface BaseCache. 362068SN/A */ 372068SN/A 382068SN/A#ifndef __BASE_CACHE_HH__ 392068SN/A#define __BASE_CACHE_HH__ 402068SN/A 412068SN/A#include <algorithm> 422068SN/A#include <list> 432068SN/A#include <string> 442068SN/A#include <vector> 452068SN/A 462068SN/A#include "base/misc.hh" 472068SN/A#include "base/statistics.hh" 482068SN/A#include "base/trace.hh" 492068SN/A#include "base/types.hh" 502068SN/A#include "config/full_system.hh" 512068SN/A#include "mem/cache/mshr_queue.hh" 522068SN/A#include "mem/mem_object.hh" 532068SN/A#include "mem/packet.hh" 542068SN/A#include "mem/tport.hh" 552068SN/A#include "mem/request.hh" 562227SN/A#include "params/BaseCache.hh" 572068SN/A#include "sim/eventq.hh" 582068SN/A#include "sim/sim_exit.hh" 592068SN/A 602068SN/Aclass MSHR; 612068SN/A/** 622068SN/A * A basic cache interface. Implements some common functions for speed. 632068SN/A */ 642068SN/Aclass BaseCache : public MemObject 652068SN/A{ 662068SN/A /** 672068SN/A * Indexes to enumerate the MSHR queues. 682068SN/A */ 692068SN/A enum MSHRQueueIndex { 702068SN/A MSHRQueue_MSHRs, 712068SN/A MSHRQueue_WriteBuffer 722068SN/A }; 732068SN/A 742068SN/A /** 752068SN/A * Reasons for caches to be blocked. 762068SN/A */ 772068SN/A enum BlockedCause { 782227SN/A Blocked_NoMSHRs = MSHRQueue_MSHRs, 792068SN/A Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 802068SN/A Blocked_NoTargets, 812068SN/A NUM_BLOCKED_CAUSES 822068SN/A }; 832068SN/A 842068SN/A public: 852068SN/A /** 862068SN/A * Reasons for cache to request a bus. 872068SN/A */ 882068SN/A enum RequestCause { 892068SN/A Request_MSHR = MSHRQueue_MSHRs, 902068SN/A Request_WB = MSHRQueue_WriteBuffer, 912068SN/A Request_PF, 922068SN/A NUM_REQUEST_CAUSES 932068SN/A }; 942068SN/A 952068SN/A private: 962068SN/A 972068SN/A class CachePort : public SimpleTimingPort 982068SN/A { 992068SN/A public: 1002068SN/A BaseCache *cache; 1012068SN/A 1022068SN/A protected: 1032227SN/A CachePort(const std::string &_name, BaseCache *_cache, 1042068SN/A const std::string &_label); 1052068SN/A 1062068SN/A virtual void recvStatusChange(Status status); 1072068SN/A 1082068SN/A virtual unsigned deviceBlockSize() const; 1092680Sktlim@umich.edu 1102068SN/A bool recvRetryCommon(); 1112068SN/A 1122068SN/A typedef EventWrapper<Port, &Port::sendRetry> 1132068SN/A SendRetryEvent; 1142068SN/A 1152068SN/A const std::string label; 1162068SN/A 1172068SN/A public: 1182068SN/A void setOtherPort(CachePort *_otherPort) { otherPort = _otherPort; } 1192068SN/A 1202068SN/A void setBlocked(); 1212068SN/A 1222068SN/A void clearBlocked(); 1232068SN/A 1242680Sktlim@umich.edu bool checkFunctional(PacketPtr pkt); 1252068SN/A 1262680Sktlim@umich.edu CachePort *otherPort; 1272680Sktlim@umich.edu 1282068SN/A bool blocked; 1292068SN/A 1302068SN/A bool mustSendRetry; 1312068SN/A 1322068SN/A void requestBus(RequestCause cause, Tick time) 1332068SN/A { 1342068SN/A DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); 1352068SN/A if (!waitingOnRetry) { 1362068SN/A schedSendEvent(time); 1372068SN/A } 1382068SN/A } 1392068SN/A 1402068SN/A void respond(PacketPtr pkt, Tick time) { 1412068SN/A schedSendTiming(pkt, time); 1422068SN/A } 1432068SN/A }; 1442068SN/A 1452068SN/A public: //Made public so coherence can get at it. 1462068SN/A CachePort *cpuSidePort; 1472068SN/A CachePort *memSidePort; 1482068SN/A 1492068SN/A protected: 1502068SN/A 1512068SN/A /** Miss status registers */ 1522068SN/A MSHRQueue mshrQueue; 1532068SN/A 1542068SN/A /** Write/writeback buffer */ 1552068SN/A MSHRQueue writeBuffer; 1562068SN/A 1572068SN/A MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 1582068SN/A PacketPtr pkt, Tick time, bool requestBus) 1592068SN/A { 1602068SN/A MSHR *mshr = mq->allocate(addr, size, pkt, time, order++); 1612068SN/A 1622068SN/A if (mq->isFull()) { 1632068SN/A setBlocked((BlockedCause)mq->index); 1642068SN/A } 1652068SN/A 1662068SN/A if (requestBus) { 1672068SN/A requestMemSideBus((RequestCause)mq->index, time); 1682068SN/A } 1692068SN/A 1702068SN/A return mshr; 1712068SN/A } 1722068SN/A 1732068SN/A void markInServiceInternal(MSHR *mshr, PacketPtr pkt) 1742068SN/A { 1752068SN/A MSHRQueue *mq = mshr->queue; 1762068SN/A bool wasFull = mq->isFull(); 1772068SN/A mq->markInService(mshr, pkt); 1782068SN/A if (wasFull && !mq->isFull()) { 1792068SN/A clearBlocked((BlockedCause)mq->index); 1802068SN/A } 1812068SN/A } 1822068SN/A 1832068SN/A /** Block size of this cache */ 1842068SN/A const unsigned blkSize; 1852068SN/A 1862068SN/A /** 1872068SN/A * The latency of a hit in this device. 1882068SN/A */ 1892068SN/A int hitLatency; 1902068SN/A 1912068SN/A /** The number of targets for each MSHR. */ 1922068SN/A const int numTarget; 1932068SN/A 1942068SN/A /** Do we forward snoops from mem side port through to cpu side port? */ 1952068SN/A bool forwardSnoops; 1962068SN/A 1972068SN/A /** 1982068SN/A * Bit vector of the blocking reasons for the access path. 1992068SN/A * @sa #BlockedCause 2002068SN/A */ 2012068SN/A uint8_t blocked; 2022068SN/A 2032068SN/A /** Increasing order number assigned to each incoming request. */ 2042068SN/A uint64_t order; 2052068SN/A 2062068SN/A /** Stores time the cache blocked for statistics. */ 2072068SN/A Tick blockedCycle; 2082068SN/A 2092068SN/A /** Pointer to the MSHR that has no targets. */ 2102068SN/A MSHR *noTargetMSHR; 2112068SN/A 2122068SN/A /** The number of misses to trigger an exit event. */ 2132068SN/A Counter missCount; 2142068SN/A 2152107SN/A /** The drain event. */ 2162107SN/A Event *drainEvent; 2172068SN/A 2182068SN/A /** 2192068SN/A * The address range to which the cache responds on the CPU side. 2202068SN/A * Normally this is all possible memory addresses. */ 2213953Sstever@eecs.umich.edu Range<Addr> addrRange; 2222068SN/A 2232068SN/A /** number of cpus sharing this cache - from config file */ 2242068SN/A int _numCpus; 2252068SN/A 2262068SN/A public: 2272068SN/A int numCpus() { return _numCpus; } 2282068SN/A // Statistics 2292068SN/A /** 2302068SN/A * @addtogroup CacheStatistics 2312068SN/A * @{ 2322068SN/A */ 2333953Sstever@eecs.umich.edu 2342068SN/A /** Number of hits per thread for each type of command. @sa Packet::Command */ 2352068SN/A Stats::Vector hits[MemCmd::NUM_MEM_CMDS]; 2362068SN/A /** Number of hits for demand accesses. */ 2372068SN/A Stats::Formula demandHits; 2382068SN/A /** Number of hit for all accesses. */ 2392068SN/A Stats::Formula overallHits; 2402068SN/A 2413953Sstever@eecs.umich.edu /** Number of misses per thread for each type of command. @sa Packet::Command */ 2422068SN/A Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; 2432068SN/A /** Number of misses for demand accesses. */ 2442068SN/A Stats::Formula demandMisses; 2452068SN/A /** Number of misses for all accesses. */ 2462068SN/A Stats::Formula overallMisses; 2472068SN/A 2482068SN/A /** 2492068SN/A * Total number of cycles per thread/command spent waiting for a miss. 2502068SN/A * Used to calculate the average miss latency. 2512068SN/A */ 2522068SN/A Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS]; 2532068SN/A /** Total number of cycles spent waiting for demand misses. */ 2542068SN/A Stats::Formula demandMissLatency; 2552068SN/A /** Total number of cycles spent waiting for all misses. */ 2562068SN/A Stats::Formula overallMissLatency; 2572068SN/A 2582068SN/A /** The number of accesses per command and thread. */ 2592068SN/A Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 2602068SN/A /** The number of demand accesses. */ 2612068SN/A Stats::Formula demandAccesses; 2622068SN/A /** The number of overall accesses. */ 2632068SN/A Stats::Formula overallAccesses; 2642068SN/A 2652068SN/A /** The miss rate per command and thread. */ 266 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 267 /** The miss rate of all demand accesses. */ 268 Stats::Formula demandMissRate; 269 /** The miss rate for all accesses. */ 270 Stats::Formula overallMissRate; 271 272 /** The average miss latency per command and thread. */ 273 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 274 /** The average miss latency for demand misses. */ 275 Stats::Formula demandAvgMissLatency; 276 /** The average miss latency for all misses. */ 277 Stats::Formula overallAvgMissLatency; 278 279 /** The total number of cycles blocked for each blocked cause. */ 280 Stats::Vector blocked_cycles; 281 /** The number of times this cache blocked for each blocked cause. */ 282 Stats::Vector blocked_causes; 283 284 /** The average number of cycles blocked for each blocked cause. */ 285 Stats::Formula avg_blocked; 286 287 /** The number of fast writes (WH64) performed. */ 288 Stats::Scalar fastWrites; 289 290 /** The number of cache copies performed. */ 291 Stats::Scalar cacheCopies; 292 293 /** Number of blocks written back per thread. */ 294 Stats::Vector writebacks; 295 296 /** Number of misses that hit in the MSHRs per command and thread. */ 297 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS]; 298 /** Demand misses that hit in the MSHRs. */ 299 Stats::Formula demandMshrHits; 300 /** Total number of misses that hit in the MSHRs. */ 301 Stats::Formula overallMshrHits; 302 303 /** Number of misses that miss in the MSHRs, per command and thread. */ 304 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS]; 305 /** Demand misses that miss in the MSHRs. */ 306 Stats::Formula demandMshrMisses; 307 /** Total number of misses that miss in the MSHRs. */ 308 Stats::Formula overallMshrMisses; 309 310 /** Number of misses that miss in the MSHRs, per command and thread. */ 311 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 312 /** Total number of misses that miss in the MSHRs. */ 313 Stats::Formula overallMshrUncacheable; 314 315 /** Total cycle latency of each MSHR miss, per command and thread. */ 316 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 317 /** Total cycle latency of demand MSHR misses. */ 318 Stats::Formula demandMshrMissLatency; 319 /** Total cycle latency of overall MSHR misses. */ 320 Stats::Formula overallMshrMissLatency; 321 322 /** Total cycle latency of each MSHR miss, per command and thread. */ 323 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 324 /** Total cycle latency of overall MSHR misses. */ 325 Stats::Formula overallMshrUncacheableLatency; 326 327#if 0 328 /** The total number of MSHR accesses per command and thread. */ 329 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 330 /** The total number of demand MSHR accesses. */ 331 Stats::Formula demandMshrAccesses; 332 /** The total number of MSHR accesses. */ 333 Stats::Formula overallMshrAccesses; 334#endif 335 336 /** The miss rate in the MSHRs pre command and thread. */ 337 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 338 /** The demand miss rate in the MSHRs. */ 339 Stats::Formula demandMshrMissRate; 340 /** The overall miss rate in the MSHRs. */ 341 Stats::Formula overallMshrMissRate; 342 343 /** The average latency of an MSHR miss, per command and thread. */ 344 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 345 /** The average latency of a demand MSHR miss. */ 346 Stats::Formula demandAvgMshrMissLatency; 347 /** The average overall latency of an MSHR miss. */ 348 Stats::Formula overallAvgMshrMissLatency; 349 350 /** The average latency of an MSHR miss, per command and thread. */ 351 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 352 /** The average overall latency of an MSHR miss. */ 353 Stats::Formula overallAvgMshrUncacheableLatency; 354 355 /** The number of times a thread hit its MSHR cap. */ 356 Stats::Vector mshr_cap_events; 357 /** The number of times software prefetches caused the MSHR to block. */ 358 Stats::Vector soft_prefetch_mshr_full; 359 360 Stats::Scalar mshr_no_allocate_misses; 361 362 /** 363 * @} 364 */ 365 366 /** 367 * Register stats for this object. 368 */ 369 virtual void regStats(); 370 371 public: 372 typedef BaseCacheParams Params; 373 BaseCache(const Params *p); 374 ~BaseCache() {} 375 376 virtual void init(); 377 378 /** 379 * Query block size of a cache. 380 * @return The block size 381 */ 382 unsigned 383 getBlockSize() const 384 { 385 return blkSize; 386 } 387 388 389 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); } 390 391 392 const Range<Addr> &getAddrRange() const { return addrRange; } 393 394 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 395 { 396 assert(!pkt->req->isUncacheable()); 397 return allocateBufferInternal(&mshrQueue, 398 blockAlign(pkt->getAddr()), blkSize, 399 pkt, time, requestBus); 400 } 401 402 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus) 403 { 404 assert(pkt->isWrite() && !pkt->isRead()); 405 return allocateBufferInternal(&writeBuffer, 406 pkt->getAddr(), pkt->getSize(), 407 pkt, time, requestBus); 408 } 409 410 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus) 411 { 412 assert(pkt->req->isUncacheable()); 413 assert(pkt->isRead()); 414 return allocateBufferInternal(&mshrQueue, 415 pkt->getAddr(), pkt->getSize(), 416 pkt, time, requestBus); 417 } 418 419 /** 420 * Returns true if the cache is blocked for accesses. 421 */ 422 bool isBlocked() 423 { 424 return blocked != 0; 425 } 426 427 /** 428 * Marks the access path of the cache as blocked for the given cause. This 429 * also sets the blocked flag in the slave interface. 430 * @param cause The reason for the cache blocking. 431 */ 432 void setBlocked(BlockedCause cause) 433 { 434 uint8_t flag = 1 << cause; 435 if (blocked == 0) { 436 blocked_causes[cause]++; 437 blockedCycle = curTick; 438 cpuSidePort->setBlocked(); 439 } 440 blocked |= flag; 441 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 442 } 443 444 /** 445 * Marks the cache as unblocked for the given cause. This also clears the 446 * blocked flags in the appropriate interfaces. 447 * @param cause The newly unblocked cause. 448 * @warning Calling this function can cause a blocked request on the bus to 449 * access the cache. The cache must be in a state to handle that request. 450 */ 451 void clearBlocked(BlockedCause cause) 452 { 453 uint8_t flag = 1 << cause; 454 blocked &= ~flag; 455 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 456 if (blocked == 0) { 457 blocked_cycles[cause] += curTick - blockedCycle; 458 cpuSidePort->clearBlocked(); 459 } 460 } 461 462 /** 463 * Request the master bus for the given cause and time. 464 * @param cause The reason for the request. 465 * @param time The time to make the request. 466 */ 467 void requestMemSideBus(RequestCause cause, Tick time) 468 { 469 memSidePort->requestBus(cause, time); 470 } 471 472 /** 473 * Clear the master bus request for the given cause. 474 * @param cause The request reason to clear. 475 */ 476 void deassertMemSideBusRequest(RequestCause cause) 477 { 478 // Obsolete... we no longer signal bus requests explicitly so 479 // we can't deassert them. Leaving this in as a no-op since 480 // the prefetcher calls it to indicate that it no longer wants 481 // to request a prefetch, and someday that might be 482 // interesting again. 483 } 484 485 virtual unsigned int drain(Event *de); 486 487 virtual bool inCache(Addr addr) = 0; 488 489 virtual bool inMissQueue(Addr addr) = 0; 490 491 void incMissCount(PacketPtr pkt, int id) 492 { 493 494 if (pkt->cmd == MemCmd::Writeback) { 495 assert(id == -1); 496 misses[pkt->cmdToIndex()][0]++; 497 /* same thing for writeback hits as misses - no context id 498 * available, meanwhile writeback hit/miss stats are not used 499 * in any aggregate hit/miss calculations, so just lump them all 500 * in bucket 0 */ 501#if FULL_SYSTEM 502 } else if (id == -1) { 503 // Device accesses have id -1 504 // lump device accesses into their own bucket 505 misses[pkt->cmdToIndex()][_numCpus]++; 506#endif 507 } else { 508 misses[pkt->cmdToIndex()][id % _numCpus]++; 509 } 510 511 if (missCount) { 512 --missCount; 513 if (missCount == 0) 514 exitSimLoop("A cache reached the maximum miss count"); 515 } 516 } 517 void incHitCount(PacketPtr pkt, int id) 518 { 519 520 /* Writeback requests don't have a context id associated with 521 * them, so attributing a hit to a -1 context id is obviously a 522 * problem. I've noticed in the stats that hits are split into 523 * demand and non-demand hits - neither of which include writeback 524 * hits, so here, I'll just put the writeback hits into bucket 0 525 * since it won't mess with any other stats -hsul */ 526 if (pkt->cmd == MemCmd::Writeback) { 527 assert(id == -1); 528 hits[pkt->cmdToIndex()][0]++; 529#if FULL_SYSTEM 530 } else if (id == -1) { 531 // Device accesses have id -1 532 // lump device accesses into their own bucket 533 hits[pkt->cmdToIndex()][_numCpus]++; 534#endif 535 } else { 536 /* the % is necessary in case there are switch cpus */ 537 hits[pkt->cmdToIndex()][id % _numCpus]++; 538 } 539 } 540 541}; 542 543#endif //__BASE_CACHE_HH__ 544