base.hh revision 4630
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 * Steve Reinhardt 30 * Ron Dreslinski 31 */ 32 33/** 34 * @file 35 * Declares a basic cache interface BaseCache. 36 */ 37 38#ifndef __BASE_CACHE_HH__ 39#define __BASE_CACHE_HH__ 40 41#include <vector> 42#include <string> 43#include <list> 44#include <inttypes.h> 45 46#include "base/misc.hh" 47#include "base/statistics.hh" 48#include "base/trace.hh" 49#include "mem/cache/miss/mshr_queue.hh" 50#include "mem/mem_object.hh" 51#include "mem/packet.hh" 52#include "mem/tport.hh" 53#include "mem/request.hh" 54#include "sim/eventq.hh" 55#include "sim/sim_exit.hh" 56 57class MSHR; 58/** 59 * A basic cache interface. Implements some common functions for speed. 60 */ 61class BaseCache : public MemObject 62{ 63 /** 64 * Indexes to enumerate the MSHR queues. 65 */ 66 enum MSHRQueueIndex { 67 MSHRQueue_MSHRs, 68 MSHRQueue_WriteBuffer 69 }; 70 71 /** 72 * Reasons for caches to be blocked. 73 */ 74 enum BlockedCause { 75 Blocked_NoMSHRs = MSHRQueue_MSHRs, 76 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 77 Blocked_NoTargets, 78 NUM_BLOCKED_CAUSES 79 }; 80 81 public: 82 /** 83 * Reasons for cache to request a bus. 84 */ 85 enum RequestCause { 86 Request_MSHR = MSHRQueue_MSHRs, 87 Request_WB = MSHRQueue_WriteBuffer, 88 Request_PF, 89 NUM_REQUEST_CAUSES 90 }; 91 92 private: 93 94 class CachePort : public SimpleTimingPort 95 { 96 public: 97 BaseCache *cache; 98 99 protected: 100 CachePort(const std::string &_name, BaseCache *_cache); 101 102 virtual void recvStatusChange(Status status); 103 104 virtual int deviceBlockSize(); 105 106 bool recvRetryCommon(); 107 108 public: 109 void setOtherPort(CachePort *_otherPort) { otherPort = _otherPort; } 110 111 void setBlocked(); 112 113 void clearBlocked(); 114 115 void checkAndSendFunctional(PacketPtr pkt); 116 117 CachePort *otherPort; 118 119 bool blocked; 120 121 bool waitingOnRetry; 122 123 bool mustSendRetry; 124 125 /** 126 * Bit vector for the outstanding requests for the master interface. 127 */ 128 uint8_t requestCauses; 129 130 bool isBusRequested() { return requestCauses != 0; } 131 132 void requestBus(RequestCause cause, Tick time) 133 { 134 DPRINTF(Cache, "Asserting bus request for cause %d\n", cause); 135 if (!isBusRequested() && !waitingOnRetry) { 136 assert(!sendEvent->scheduled()); 137 sendEvent->schedule(time); 138 } 139 requestCauses |= (1 << cause); 140 } 141 142 void deassertBusRequest(RequestCause cause) 143 { 144 DPRINTF(Cache, "Deasserting bus request for cause %d\n", cause); 145 requestCauses &= ~(1 << cause); 146 } 147 148 void respond(PacketPtr pkt, Tick time) { 149 schedSendTiming(pkt, time); 150 } 151 }; 152 153 public: //Made public so coherence can get at it. 154 CachePort *cpuSidePort; 155 CachePort *memSidePort; 156 157 protected: 158 159 /** Miss status registers */ 160 MSHRQueue mshrQueue; 161 162 /** Write/writeback buffer */ 163 MSHRQueue writeBuffer; 164 165 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 166 PacketPtr pkt, Tick time, bool requestBus) 167 { 168 MSHR *mshr = mq->allocate(addr, size, pkt); 169 mshr->order = order++; 170 171 if (mq->isFull()) { 172 setBlocked((BlockedCause)mq->index); 173 } 174 175 if (requestBus) { 176 requestMemSideBus((RequestCause)mq->index, time); 177 } 178 179 return mshr; 180 } 181 182 void markInServiceInternal(MSHR *mshr) 183 { 184 MSHRQueue *mq = mshr->queue; 185 bool wasFull = mq->isFull(); 186 mq->markInService(mshr); 187 if (!mq->havePending()) { 188 deassertMemSideBusRequest((RequestCause)mq->index); 189 } 190 if (wasFull && !mq->isFull()) { 191 clearBlocked((BlockedCause)mq->index); 192 } 193 } 194 195 /** Block size of this cache */ 196 const int blkSize; 197 198 /** 199 * The latency of a hit in this device. 200 */ 201 int hitLatency; 202 203 /** The number of targets for each MSHR. */ 204 const int numTarget; 205 206 /** Increasing order number assigned to each incoming request. */ 207 uint64_t order; 208 209 /** 210 * Bit vector of the blocking reasons for the access path. 211 * @sa #BlockedCause 212 */ 213 uint8_t blocked; 214 215 /** Stores time the cache blocked for statistics. */ 216 Tick blockedCycle; 217 218 /** Pointer to the MSHR that has no targets. */ 219 MSHR *noTargetMSHR; 220 221 /** The number of misses to trigger an exit event. */ 222 Counter missCount; 223 224 /** The drain event. */ 225 Event *drainEvent; 226 227 public: 228 // Statistics 229 /** 230 * @addtogroup CacheStatistics 231 * @{ 232 */ 233 234 /** Number of hits per thread for each type of command. @sa Packet::Command */ 235 Stats::Vector<> hits[MemCmd::NUM_MEM_CMDS]; 236 /** Number of hits for demand accesses. */ 237 Stats::Formula demandHits; 238 /** Number of hit for all accesses. */ 239 Stats::Formula overallHits; 240 241 /** Number of misses per thread for each type of command. @sa Packet::Command */ 242 Stats::Vector<> misses[MemCmd::NUM_MEM_CMDS]; 243 /** Number of misses for demand accesses. */ 244 Stats::Formula demandMisses; 245 /** Number of misses for all accesses. */ 246 Stats::Formula overallMisses; 247 248 /** 249 * Total number of cycles per thread/command spent waiting for a miss. 250 * Used to calculate the average miss latency. 251 */ 252 Stats::Vector<> missLatency[MemCmd::NUM_MEM_CMDS]; 253 /** Total number of cycles spent waiting for demand misses. */ 254 Stats::Formula demandMissLatency; 255 /** Total number of cycles spent waiting for all misses. */ 256 Stats::Formula overallMissLatency; 257 258 /** The number of accesses per command and thread. */ 259 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 260 /** The number of demand accesses. */ 261 Stats::Formula demandAccesses; 262 /** The number of overall accesses. */ 263 Stats::Formula overallAccesses; 264 265 /** The miss rate per command and thread. */ 266 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 267 /** The miss rate of all demand accesses. */ 268 Stats::Formula demandMissRate; 269 /** The miss rate for all accesses. */ 270 Stats::Formula overallMissRate; 271 272 /** The average miss latency per command and thread. */ 273 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 274 /** The average miss latency for demand misses. */ 275 Stats::Formula demandAvgMissLatency; 276 /** The average miss latency for all misses. */ 277 Stats::Formula overallAvgMissLatency; 278 279 /** The total number of cycles blocked for each blocked cause. */ 280 Stats::Vector<> blocked_cycles; 281 /** The number of times this cache blocked for each blocked cause. */ 282 Stats::Vector<> blocked_causes; 283 284 /** The average number of cycles blocked for each blocked cause. */ 285 Stats::Formula avg_blocked; 286 287 /** The number of fast writes (WH64) performed. */ 288 Stats::Scalar<> fastWrites; 289 290 /** The number of cache copies performed. */ 291 Stats::Scalar<> cacheCopies; 292 293 /** Number of blocks written back per thread. */ 294 Stats::Vector<> writebacks; 295 296 /** Number of misses that hit in the MSHRs per command and thread. */ 297 Stats::Vector<> mshr_hits[MemCmd::NUM_MEM_CMDS]; 298 /** Demand misses that hit in the MSHRs. */ 299 Stats::Formula demandMshrHits; 300 /** Total number of misses that hit in the MSHRs. */ 301 Stats::Formula overallMshrHits; 302 303 /** Number of misses that miss in the MSHRs, per command and thread. */ 304 Stats::Vector<> mshr_misses[MemCmd::NUM_MEM_CMDS]; 305 /** Demand misses that miss in the MSHRs. */ 306 Stats::Formula demandMshrMisses; 307 /** Total number of misses that miss in the MSHRs. */ 308 Stats::Formula overallMshrMisses; 309 310 /** Number of misses that miss in the MSHRs, per command and thread. */ 311 Stats::Vector<> mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 312 /** Total number of misses that miss in the MSHRs. */ 313 Stats::Formula overallMshrUncacheable; 314 315 /** Total cycle latency of each MSHR miss, per command and thread. */ 316 Stats::Vector<> mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 317 /** Total cycle latency of demand MSHR misses. */ 318 Stats::Formula demandMshrMissLatency; 319 /** Total cycle latency of overall MSHR misses. */ 320 Stats::Formula overallMshrMissLatency; 321 322 /** Total cycle latency of each MSHR miss, per command and thread. */ 323 Stats::Vector<> mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 324 /** Total cycle latency of overall MSHR misses. */ 325 Stats::Formula overallMshrUncacheableLatency; 326 327 /** The total number of MSHR accesses per command and thread. */ 328 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 329 /** The total number of demand MSHR accesses. */ 330 Stats::Formula demandMshrAccesses; 331 /** The total number of MSHR accesses. */ 332 Stats::Formula overallMshrAccesses; 333 334 /** The miss rate in the MSHRs pre command and thread. */ 335 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 336 /** The demand miss rate in the MSHRs. */ 337 Stats::Formula demandMshrMissRate; 338 /** The overall miss rate in the MSHRs. */ 339 Stats::Formula overallMshrMissRate; 340 341 /** The average latency of an MSHR miss, per command and thread. */ 342 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 343 /** The average latency of a demand MSHR miss. */ 344 Stats::Formula demandAvgMshrMissLatency; 345 /** The average overall latency of an MSHR miss. */ 346 Stats::Formula overallAvgMshrMissLatency; 347 348 /** The average latency of an MSHR miss, per command and thread. */ 349 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 350 /** The average overall latency of an MSHR miss. */ 351 Stats::Formula overallAvgMshrUncacheableLatency; 352 353 /** The number of times a thread hit its MSHR cap. */ 354 Stats::Vector<> mshr_cap_events; 355 /** The number of times software prefetches caused the MSHR to block. */ 356 Stats::Vector<> soft_prefetch_mshr_full; 357 358 Stats::Scalar<> mshr_no_allocate_misses; 359 360 /** 361 * @} 362 */ 363 364 /** 365 * Register stats for this object. 366 */ 367 virtual void regStats(); 368 369 public: 370 371 class Params 372 { 373 public: 374 /** The hit latency for this cache. */ 375 int hitLatency; 376 /** The block size of this cache. */ 377 int blkSize; 378 int numMSHRs; 379 int numTargets; 380 int numWriteBuffers; 381 /** 382 * The maximum number of misses this cache should handle before 383 * ending the simulation. 384 */ 385 Counter maxMisses; 386 387 /** 388 * Construct an instance of this parameter class. 389 */ 390 Params(int _hitLatency, int _blkSize, 391 int _numMSHRs, int _numTargets, int _numWriteBuffers, 392 Counter _maxMisses) 393 : hitLatency(_hitLatency), blkSize(_blkSize), 394 numMSHRs(_numMSHRs), numTargets(_numTargets), 395 numWriteBuffers(_numWriteBuffers), maxMisses(_maxMisses) 396 { 397 } 398 }; 399 400 /** 401 * Create and initialize a basic cache object. 402 * @param name The name of this cache. 403 * @param hier_params Pointer to the HierParams object for this hierarchy 404 * of this cache. 405 * @param params The parameter object for this BaseCache. 406 */ 407 BaseCache(const std::string &name, Params ¶ms); 408 409 ~BaseCache() 410 { 411 } 412 413 virtual void init(); 414 415 /** 416 * Query block size of a cache. 417 * @return The block size 418 */ 419 int getBlockSize() const 420 { 421 return blkSize; 422 } 423 424 425 Addr blockAlign(Addr addr) const { return (addr & ~(blkSize - 1)); } 426 427 428 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 429 { 430 return allocateBufferInternal(&mshrQueue, 431 blockAlign(pkt->getAddr()), blkSize, 432 pkt, time, requestBus); 433 } 434 435 MSHR *allocateBuffer(PacketPtr pkt, Tick time, bool requestBus) 436 { 437 MSHRQueue *mq = NULL; 438 439 if (pkt->isWrite() && !pkt->isRead()) { 440 /** 441 * @todo Add write merging here. 442 */ 443 mq = &writeBuffer; 444 } else { 445 mq = &mshrQueue; 446 } 447 448 return allocateBufferInternal(mq, pkt->getAddr(), pkt->getSize(), 449 pkt, time, requestBus); 450 } 451 452 453 /** 454 * Returns true if the cache is blocked for accesses. 455 */ 456 bool isBlocked() 457 { 458 return blocked != 0; 459 } 460 461 /** 462 * Marks the access path of the cache as blocked for the given cause. This 463 * also sets the blocked flag in the slave interface. 464 * @param cause The reason for the cache blocking. 465 */ 466 void setBlocked(BlockedCause cause) 467 { 468 uint8_t flag = 1 << cause; 469 if (blocked == 0) { 470 blocked_causes[cause]++; 471 blockedCycle = curTick; 472 cpuSidePort->setBlocked(); 473 } 474 blocked |= flag; 475 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 476 } 477 478 /** 479 * Marks the cache as unblocked for the given cause. This also clears the 480 * blocked flags in the appropriate interfaces. 481 * @param cause The newly unblocked cause. 482 * @warning Calling this function can cause a blocked request on the bus to 483 * access the cache. The cache must be in a state to handle that request. 484 */ 485 void clearBlocked(BlockedCause cause) 486 { 487 uint8_t flag = 1 << cause; 488 blocked &= ~flag; 489 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 490 if (blocked == 0) { 491 blocked_cycles[cause] += curTick - blockedCycle; 492 cpuSidePort->clearBlocked(); 493 } 494 } 495 496 /** 497 * True if the memory-side bus should be requested. 498 * @return True if there are outstanding requests for the master bus. 499 */ 500 bool isMemSideBusRequested() 501 { 502 return memSidePort->isBusRequested(); 503 } 504 505 /** 506 * Request the master bus for the given cause and time. 507 * @param cause The reason for the request. 508 * @param time The time to make the request. 509 */ 510 void requestMemSideBus(RequestCause cause, Tick time) 511 { 512 memSidePort->requestBus(cause, time); 513 } 514 515 /** 516 * Clear the master bus request for the given cause. 517 * @param cause The request reason to clear. 518 */ 519 void deassertMemSideBusRequest(RequestCause cause) 520 { 521 memSidePort->deassertBusRequest(cause); 522 // checkDrain(); 523 } 524 525 virtual unsigned int drain(Event *de); 526 527 virtual bool inCache(Addr addr) = 0; 528 529 virtual bool inMissQueue(Addr addr) = 0; 530 531 void incMissCount(PacketPtr pkt) 532 { 533 misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; 534 535 if (missCount) { 536 --missCount; 537 if (missCount == 0) 538 exitSimLoop("A cache reached the maximum miss count"); 539 } 540 } 541 542}; 543 544#endif //__BASE_CACHE_HH__ 545