base.hh revision 4628
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 * Steve Reinhardt 30 * Ron Dreslinski 31 */ 32 33/** 34 * @file 35 * Declares a basic cache interface BaseCache. 36 */ 37 38#ifndef __BASE_CACHE_HH__ 39#define __BASE_CACHE_HH__ 40 41#include <vector> 42#include <string> 43#include <list> 44#include <inttypes.h> 45 46#include "base/misc.hh" 47#include "base/statistics.hh" 48#include "base/trace.hh" 49#include "mem/cache/miss/mshr_queue.hh" 50#include "mem/mem_object.hh" 51#include "mem/packet.hh" 52#include "mem/tport.hh" 53#include "mem/request.hh" 54#include "sim/eventq.hh" 55#include "sim/sim_exit.hh" 56 57class MSHR; 58/** 59 * A basic cache interface. Implements some common functions for speed. 60 */ 61class BaseCache : public MemObject 62{ 63 /** 64 * Indexes to enumerate the MSHR queues. 65 */ 66 enum MSHRQueueIndex { 67 MSHRQueue_MSHRs, 68 MSHRQueue_WriteBuffer 69 }; 70 71 /** 72 * Reasons for caches to be blocked. 73 */ 74 enum BlockedCause { 75 Blocked_NoMSHRs = MSHRQueue_MSHRs, 76 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 77 Blocked_NoTargets, 78 NUM_BLOCKED_CAUSES 79 }; 80 81 public: 82 /** 83 * Reasons for cache to request a bus. 84 */ 85 enum RequestCause { 86 Request_MSHR = MSHRQueue_MSHRs, 87 Request_WB = MSHRQueue_WriteBuffer, 88 Request_PF, 89 NUM_REQUEST_CAUSES 90 }; 91 92 private: 93 94 class CachePort : public SimpleTimingPort 95 { 96 public: 97 BaseCache *cache; 98 99 protected: 100 CachePort(const std::string &_name, BaseCache *_cache); 101 102 virtual void recvStatusChange(Status status); 103 104 virtual int deviceBlockSize(); 105 106 bool recvRetryCommon(); 107 108 public: 109 void setOtherPort(CachePort *_otherPort) { otherPort = _otherPort; } 110 111 void setBlocked(); 112 113 void clearBlocked(); 114 115 void checkAndSendFunctional(PacketPtr pkt); 116 117 CachePort *otherPort; 118 119 bool blocked; 120 121 bool waitingOnRetry; 122 123 bool mustSendRetry; 124 125 /** 126 * Bit vector for the outstanding requests for the master interface. 127 */ 128 uint8_t requestCauses; 129 130 bool isBusRequested() { return requestCauses != 0; } 131 132 void requestBus(RequestCause cause, Tick time) 133 { 134 DPRINTF(Cache, "Asserting bus request for cause %d\n", cause); 135 if (!isBusRequested() && !waitingOnRetry) { 136 assert(!sendEvent->scheduled()); 137 sendEvent->schedule(time); 138 } 139 requestCauses |= (1 << cause); 140 } 141 142 void deassertBusRequest(RequestCause cause) 143 { 144 DPRINTF(Cache, "Deasserting bus request for cause %d\n", cause); 145 requestCauses &= ~(1 << cause); 146 } 147 148 void respond(PacketPtr pkt, Tick time) { 149 schedSendTiming(pkt, time); 150 } 151 }; 152 153 public: //Made public so coherence can get at it. 154 CachePort *cpuSidePort; 155 CachePort *memSidePort; 156 157 protected: 158 159 /** Miss status registers */ 160 MSHRQueue mshrQueue; 161 162 /** Write/writeback buffer */ 163 MSHRQueue writeBuffer; 164 165 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 166 PacketPtr pkt, Tick time, bool requestBus) 167 { 168 MSHR *mshr = mq->allocate(addr, size, pkt); 169 mshr->order = order++; 170 171 if (mq->isFull()) { 172 setBlocked((BlockedCause)mq->index); 173 } 174 175 if (requestBus) { 176 requestMemSideBus((RequestCause)mq->index, time); 177 } 178 179 return mshr; 180 } 181 182 void markInServiceInternal(MSHR *mshr) 183 { 184 MSHRQueue *mq = mshr->queue; 185 bool wasFull = mq->isFull(); 186 mq->markInService(mshr); 187 if (!mq->havePending()) { 188 deassertMemSideBusRequest((RequestCause)mq->index); 189 } 190 if (wasFull && !mq->isFull()) { 191 clearBlocked((BlockedCause)mq->index); 192 } 193 } 194 195 /** Block size of this cache */ 196 const int blkSize; 197 198 /** The number of targets for each MSHR. */ 199 const int numTarget; 200 201 /** Increasing order number assigned to each incoming request. */ 202 uint64_t order; 203 204 /** 205 * Bit vector of the blocking reasons for the access path. 206 * @sa #BlockedCause 207 */ 208 uint8_t blocked; 209 210 /** Stores time the cache blocked for statistics. */ 211 Tick blockedCycle; 212 213 /** Pointer to the MSHR that has no targets. */ 214 MSHR *noTargetMSHR; 215 216 /** The number of misses to trigger an exit event. */ 217 Counter missCount; 218 219 /** The drain event. */ 220 Event *drainEvent; 221 222 public: 223 // Statistics 224 /** 225 * @addtogroup CacheStatistics 226 * @{ 227 */ 228 229 /** Number of hits per thread for each type of command. @sa Packet::Command */ 230 Stats::Vector<> hits[MemCmd::NUM_MEM_CMDS]; 231 /** Number of hits for demand accesses. */ 232 Stats::Formula demandHits; 233 /** Number of hit for all accesses. */ 234 Stats::Formula overallHits; 235 236 /** Number of misses per thread for each type of command. @sa Packet::Command */ 237 Stats::Vector<> misses[MemCmd::NUM_MEM_CMDS]; 238 /** Number of misses for demand accesses. */ 239 Stats::Formula demandMisses; 240 /** Number of misses for all accesses. */ 241 Stats::Formula overallMisses; 242 243 /** 244 * Total number of cycles per thread/command spent waiting for a miss. 245 * Used to calculate the average miss latency. 246 */ 247 Stats::Vector<> missLatency[MemCmd::NUM_MEM_CMDS]; 248 /** Total number of cycles spent waiting for demand misses. */ 249 Stats::Formula demandMissLatency; 250 /** Total number of cycles spent waiting for all misses. */ 251 Stats::Formula overallMissLatency; 252 253 /** The number of accesses per command and thread. */ 254 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 255 /** The number of demand accesses. */ 256 Stats::Formula demandAccesses; 257 /** The number of overall accesses. */ 258 Stats::Formula overallAccesses; 259 260 /** The miss rate per command and thread. */ 261 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 262 /** The miss rate of all demand accesses. */ 263 Stats::Formula demandMissRate; 264 /** The miss rate for all accesses. */ 265 Stats::Formula overallMissRate; 266 267 /** The average miss latency per command and thread. */ 268 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 269 /** The average miss latency for demand misses. */ 270 Stats::Formula demandAvgMissLatency; 271 /** The average miss latency for all misses. */ 272 Stats::Formula overallAvgMissLatency; 273 274 /** The total number of cycles blocked for each blocked cause. */ 275 Stats::Vector<> blocked_cycles; 276 /** The number of times this cache blocked for each blocked cause. */ 277 Stats::Vector<> blocked_causes; 278 279 /** The average number of cycles blocked for each blocked cause. */ 280 Stats::Formula avg_blocked; 281 282 /** The number of fast writes (WH64) performed. */ 283 Stats::Scalar<> fastWrites; 284 285 /** The number of cache copies performed. */ 286 Stats::Scalar<> cacheCopies; 287 288 /** Number of blocks written back per thread. */ 289 Stats::Vector<> writebacks; 290 291 /** Number of misses that hit in the MSHRs per command and thread. */ 292 Stats::Vector<> mshr_hits[MemCmd::NUM_MEM_CMDS]; 293 /** Demand misses that hit in the MSHRs. */ 294 Stats::Formula demandMshrHits; 295 /** Total number of misses that hit in the MSHRs. */ 296 Stats::Formula overallMshrHits; 297 298 /** Number of misses that miss in the MSHRs, per command and thread. */ 299 Stats::Vector<> mshr_misses[MemCmd::NUM_MEM_CMDS]; 300 /** Demand misses that miss in the MSHRs. */ 301 Stats::Formula demandMshrMisses; 302 /** Total number of misses that miss in the MSHRs. */ 303 Stats::Formula overallMshrMisses; 304 305 /** Number of misses that miss in the MSHRs, per command and thread. */ 306 Stats::Vector<> mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 307 /** Total number of misses that miss in the MSHRs. */ 308 Stats::Formula overallMshrUncacheable; 309 310 /** Total cycle latency of each MSHR miss, per command and thread. */ 311 Stats::Vector<> mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 312 /** Total cycle latency of demand MSHR misses. */ 313 Stats::Formula demandMshrMissLatency; 314 /** Total cycle latency of overall MSHR misses. */ 315 Stats::Formula overallMshrMissLatency; 316 317 /** Total cycle latency of each MSHR miss, per command and thread. */ 318 Stats::Vector<> mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 319 /** Total cycle latency of overall MSHR misses. */ 320 Stats::Formula overallMshrUncacheableLatency; 321 322 /** The total number of MSHR accesses per command and thread. */ 323 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 324 /** The total number of demand MSHR accesses. */ 325 Stats::Formula demandMshrAccesses; 326 /** The total number of MSHR accesses. */ 327 Stats::Formula overallMshrAccesses; 328 329 /** The miss rate in the MSHRs pre command and thread. */ 330 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 331 /** The demand miss rate in the MSHRs. */ 332 Stats::Formula demandMshrMissRate; 333 /** The overall miss rate in the MSHRs. */ 334 Stats::Formula overallMshrMissRate; 335 336 /** The average latency of an MSHR miss, per command and thread. */ 337 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 338 /** The average latency of a demand MSHR miss. */ 339 Stats::Formula demandAvgMshrMissLatency; 340 /** The average overall latency of an MSHR miss. */ 341 Stats::Formula overallAvgMshrMissLatency; 342 343 /** The average latency of an MSHR miss, per command and thread. */ 344 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 345 /** The average overall latency of an MSHR miss. */ 346 Stats::Formula overallAvgMshrUncacheableLatency; 347 348 /** The number of times a thread hit its MSHR cap. */ 349 Stats::Vector<> mshr_cap_events; 350 /** The number of times software prefetches caused the MSHR to block. */ 351 Stats::Vector<> soft_prefetch_mshr_full; 352 353 Stats::Scalar<> mshr_no_allocate_misses; 354 355 /** 356 * @} 357 */ 358 359 /** 360 * Register stats for this object. 361 */ 362 virtual void regStats(); 363 364 public: 365 366 class Params 367 { 368 public: 369 /** The hit latency for this cache. */ 370 int hitLatency; 371 /** The block size of this cache. */ 372 int blkSize; 373 int numMSHRs; 374 int numTargets; 375 int numWriteBuffers; 376 /** 377 * The maximum number of misses this cache should handle before 378 * ending the simulation. 379 */ 380 Counter maxMisses; 381 382 /** 383 * Construct an instance of this parameter class. 384 */ 385 Params(int _hitLatency, int _blkSize, 386 int _numMSHRs, int _numTargets, int _numWriteBuffers, 387 Counter _maxMisses) 388 : hitLatency(_hitLatency), blkSize(_blkSize), 389 numMSHRs(_numMSHRs), numTargets(_numTargets), 390 numWriteBuffers(_numWriteBuffers), maxMisses(_maxMisses) 391 { 392 } 393 }; 394 395 /** 396 * Create and initialize a basic cache object. 397 * @param name The name of this cache. 398 * @param hier_params Pointer to the HierParams object for this hierarchy 399 * of this cache. 400 * @param params The parameter object for this BaseCache. 401 */ 402 BaseCache(const std::string &name, Params ¶ms); 403 404 ~BaseCache() 405 { 406 } 407 408 virtual void init(); 409 410 /** 411 * Query block size of a cache. 412 * @return The block size 413 */ 414 int getBlockSize() const 415 { 416 return blkSize; 417 } 418 419 420 Addr blockAlign(Addr addr) const { return (addr & ~(blkSize - 1)); } 421 422 423 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 424 { 425 return allocateBufferInternal(&mshrQueue, 426 blockAlign(pkt->getAddr()), blkSize, 427 pkt, time, requestBus); 428 } 429 430 MSHR *allocateBuffer(PacketPtr pkt, Tick time, bool requestBus) 431 { 432 MSHRQueue *mq = NULL; 433 434 if (pkt->isWrite() && !pkt->isRead()) { 435 /** 436 * @todo Add write merging here. 437 */ 438 mq = &writeBuffer; 439 } else { 440 mq = &mshrQueue; 441 } 442 443 return allocateBufferInternal(mq, pkt->getAddr(), pkt->getSize(), 444 pkt, time, requestBus); 445 } 446 447 448 /** 449 * Returns true if the cache is blocked for accesses. 450 */ 451 bool isBlocked() 452 { 453 return blocked != 0; 454 } 455 456 /** 457 * Marks the access path of the cache as blocked for the given cause. This 458 * also sets the blocked flag in the slave interface. 459 * @param cause The reason for the cache blocking. 460 */ 461 void setBlocked(BlockedCause cause) 462 { 463 uint8_t flag = 1 << cause; 464 if (blocked == 0) { 465 blocked_causes[cause]++; 466 blockedCycle = curTick; 467 } 468 int old_state = blocked; 469 if (!(blocked & flag)) { 470 //Wasn't already blocked for this cause 471 blocked |= flag; 472 DPRINTF(Cache,"Blocking for cause %s\n", cause); 473 if (!old_state) 474 cpuSidePort->setBlocked(); 475 } 476 } 477 478 /** 479 * Marks the cache as unblocked for the given cause. This also clears the 480 * blocked flags in the appropriate interfaces. 481 * @param cause The newly unblocked cause. 482 * @warning Calling this function can cause a blocked request on the bus to 483 * access the cache. The cache must be in a state to handle that request. 484 */ 485 void clearBlocked(BlockedCause cause) 486 { 487 uint8_t flag = 1 << cause; 488 DPRINTF(Cache,"Unblocking for cause %s, causes left=%i\n", 489 cause, blocked); 490 if (blocked & flag) 491 { 492 blocked &= ~flag; 493 if (!isBlocked()) { 494 blocked_cycles[cause] += curTick - blockedCycle; 495 DPRINTF(Cache,"Unblocking from all causes\n"); 496 cpuSidePort->clearBlocked(); 497 } 498 } 499 } 500 501 /** 502 * True if the memory-side bus should be requested. 503 * @return True if there are outstanding requests for the master bus. 504 */ 505 bool isMemSideBusRequested() 506 { 507 return memSidePort->isBusRequested(); 508 } 509 510 /** 511 * Request the master bus for the given cause and time. 512 * @param cause The reason for the request. 513 * @param time The time to make the request. 514 */ 515 void requestMemSideBus(RequestCause cause, Tick time) 516 { 517 memSidePort->requestBus(cause, time); 518 } 519 520 /** 521 * Clear the master bus request for the given cause. 522 * @param cause The request reason to clear. 523 */ 524 void deassertMemSideBusRequest(RequestCause cause) 525 { 526 memSidePort->deassertBusRequest(cause); 527 // checkDrain(); 528 } 529 530 virtual unsigned int drain(Event *de); 531 532 virtual bool inCache(Addr addr) = 0; 533 534 virtual bool inMissQueue(Addr addr) = 0; 535 536 void incMissCount(PacketPtr pkt) 537 { 538 misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; 539 540 if (missCount) { 541 --missCount; 542 if (missCount == 0) 543 exitSimLoop("A cache reached the maximum miss count"); 544 } 545 } 546 547}; 548 549#endif //__BASE_CACHE_HH__ 550