base.hh revision 8833
112952Sgabeblack@google.com/* 212952Sgabeblack@google.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 312952Sgabeblack@google.com * All rights reserved. 412952Sgabeblack@google.com * 512952Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 612952Sgabeblack@google.com * modification, are permitted provided that the following conditions are 712952Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 812952Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 912952Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 1012952Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 1112952Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 1212952Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 1312952Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 1412952Sgabeblack@google.com * this software without specific prior written permission. 1512952Sgabeblack@google.com * 1612952Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712952Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812952Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912952Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012952Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112952Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212952Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312952Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412952Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512952Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612952Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712952Sgabeblack@google.com * 2812952Sgabeblack@google.com * Authors: Erik Hallnor 2912952Sgabeblack@google.com * Steve Reinhardt 3012952Sgabeblack@google.com * Ron Dreslinski 3112957Sgabeblack@google.com */ 3212957Sgabeblack@google.com 3312957Sgabeblack@google.com/** 3412953Sgabeblack@google.com * @file 3512952Sgabeblack@google.com * Declares a basic cache interface BaseCache. 3612952Sgabeblack@google.com */ 3712952Sgabeblack@google.com 3812952Sgabeblack@google.com#ifndef __BASE_CACHE_HH__ 3912957Sgabeblack@google.com#define __BASE_CACHE_HH__ 4012962Sgabeblack@google.com 4112957Sgabeblack@google.com#include <algorithm> 4212962Sgabeblack@google.com#include <list> 4312962Sgabeblack@google.com#include <string> 4412957Sgabeblack@google.com#include <vector> 4512957Sgabeblack@google.com 4612957Sgabeblack@google.com#include "base/misc.hh" 4712957Sgabeblack@google.com#include "base/statistics.hh" 4812957Sgabeblack@google.com#include "base/trace.hh" 4912962Sgabeblack@google.com#include "base/types.hh" 5012962Sgabeblack@google.com#include "debug/Cache.hh" 5112962Sgabeblack@google.com#include "debug/CachePort.hh" 5212962Sgabeblack@google.com#include "mem/cache/mshr_queue.hh" 5312962Sgabeblack@google.com#include "mem/mem_object.hh" 5412962Sgabeblack@google.com#include "mem/packet.hh" 5512962Sgabeblack@google.com#include "mem/request.hh" 5612962Sgabeblack@google.com#include "mem/tport.hh" 5712957Sgabeblack@google.com#include "params/BaseCache.hh" 5812957Sgabeblack@google.com#include "sim/eventq.hh" 5912957Sgabeblack@google.com#include "sim/full_system.hh" 6012957Sgabeblack@google.com#include "sim/sim_exit.hh" 6112957Sgabeblack@google.com#include "sim/system.hh" 6212957Sgabeblack@google.com 6312957Sgabeblack@google.comclass MSHR; 6412957Sgabeblack@google.com/** 6512957Sgabeblack@google.com * A basic cache interface. Implements some common functions for speed. 6612957Sgabeblack@google.com */ 6712957Sgabeblack@google.comclass BaseCache : public MemObject 6812957Sgabeblack@google.com{ 6912957Sgabeblack@google.com /** 7012957Sgabeblack@google.com * Indexes to enumerate the MSHR queues. 7112957Sgabeblack@google.com */ 7212957Sgabeblack@google.com enum MSHRQueueIndex { 7312957Sgabeblack@google.com MSHRQueue_MSHRs, 7412957Sgabeblack@google.com MSHRQueue_WriteBuffer 7512957Sgabeblack@google.com }; 7612957Sgabeblack@google.com 7712957Sgabeblack@google.com public: 7812957Sgabeblack@google.com /** 7912957Sgabeblack@google.com * Reasons for caches to be blocked. 8012957Sgabeblack@google.com */ 8112957Sgabeblack@google.com enum BlockedCause { 8212957Sgabeblack@google.com Blocked_NoMSHRs = MSHRQueue_MSHRs, 8312957Sgabeblack@google.com Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 8412957Sgabeblack@google.com Blocked_NoTargets, 8512957Sgabeblack@google.com NUM_BLOCKED_CAUSES 8612957Sgabeblack@google.com }; 8712957Sgabeblack@google.com 8812957Sgabeblack@google.com /** 8912957Sgabeblack@google.com * Reasons for cache to request a bus. 9012959Sgabeblack@google.com */ 9112957Sgabeblack@google.com enum RequestCause { 9212957Sgabeblack@google.com Request_MSHR = MSHRQueue_MSHRs, 9312957Sgabeblack@google.com Request_WB = MSHRQueue_WriteBuffer, 9412957Sgabeblack@google.com Request_PF, 9512957Sgabeblack@google.com NUM_REQUEST_CAUSES 9612957Sgabeblack@google.com }; 9712957Sgabeblack@google.com 9812957Sgabeblack@google.com protected: 9912957Sgabeblack@google.com 10012957Sgabeblack@google.com class CachePort : public SimpleTimingPort 10112957Sgabeblack@google.com { 10212957Sgabeblack@google.com public: 10312957Sgabeblack@google.com BaseCache *cache; 10412957Sgabeblack@google.com 10512957Sgabeblack@google.com protected: 10612957Sgabeblack@google.com CachePort(const std::string &_name, BaseCache *_cache, 10712957Sgabeblack@google.com const std::string &_label); 10812952Sgabeblack@google.com 10912952Sgabeblack@google.com virtual unsigned deviceBlockSize() const; 11012952Sgabeblack@google.com 11112995Sgabeblack@google.com bool recvRetryCommon(); 11212952Sgabeblack@google.com 11312952Sgabeblack@google.com typedef EventWrapper<Port, &Port::sendRetry> 11412952Sgabeblack@google.com SendRetryEvent; 11512952Sgabeblack@google.com 11612952Sgabeblack@google.com const std::string label; 11712995Sgabeblack@google.com 11812952Sgabeblack@google.com public: 11912952Sgabeblack@google.com void setBlocked(); 12012952Sgabeblack@google.com 12112952Sgabeblack@google.com void clearBlocked(); 12212952Sgabeblack@google.com 12312952Sgabeblack@google.com bool checkFunctional(PacketPtr pkt); 12412952Sgabeblack@google.com 12512952Sgabeblack@google.com bool blocked; 12612952Sgabeblack@google.com 12712952Sgabeblack@google.com bool mustSendRetry; 12812952Sgabeblack@google.com 12912952Sgabeblack@google.com void requestBus(RequestCause cause, Tick time) 13012952Sgabeblack@google.com { 13112952Sgabeblack@google.com DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); 13212952Sgabeblack@google.com if (!waitingOnRetry) { 13312952Sgabeblack@google.com schedSendEvent(time); 13412952Sgabeblack@google.com } 13512952Sgabeblack@google.com } 13612952Sgabeblack@google.com 13712952Sgabeblack@google.com void respond(PacketPtr pkt, Tick time) { 13812952Sgabeblack@google.com schedSendTiming(pkt, time); 13912952Sgabeblack@google.com } 14012952Sgabeblack@google.com }; 14112952Sgabeblack@google.com 14212952Sgabeblack@google.com CachePort *cpuSidePort; 14312952Sgabeblack@google.com CachePort *memSidePort; 14412952Sgabeblack@google.com 14512952Sgabeblack@google.com protected: 14612952Sgabeblack@google.com 14712952Sgabeblack@google.com /** Miss status registers */ 14812952Sgabeblack@google.com MSHRQueue mshrQueue; 14912952Sgabeblack@google.com 15012959Sgabeblack@google.com /** Write/writeback buffer */ 15112952Sgabeblack@google.com MSHRQueue writeBuffer; 15212952Sgabeblack@google.com 15312953Sgabeblack@google.com MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 15412953Sgabeblack@google.com PacketPtr pkt, Tick time, bool requestBus) 15512953Sgabeblack@google.com { 15612952Sgabeblack@google.com MSHR *mshr = mq->allocate(addr, size, pkt, time, order++); 15712952Sgabeblack@google.com 15812952Sgabeblack@google.com if (mq->isFull()) { 15912952Sgabeblack@google.com setBlocked((BlockedCause)mq->index); 16012952Sgabeblack@google.com } 16112952Sgabeblack@google.com 16212952Sgabeblack@google.com if (requestBus) { 16312952Sgabeblack@google.com requestMemSideBus((RequestCause)mq->index, time); 16412952Sgabeblack@google.com } 16512952Sgabeblack@google.com 16612952Sgabeblack@google.com return mshr; 16712959Sgabeblack@google.com } 16812959Sgabeblack@google.com 16912959Sgabeblack@google.com void markInServiceInternal(MSHR *mshr, PacketPtr pkt) 17012952Sgabeblack@google.com { 17112952Sgabeblack@google.com MSHRQueue *mq = mshr->queue; 17212952Sgabeblack@google.com bool wasFull = mq->isFull(); 17312952Sgabeblack@google.com mq->markInService(mshr, pkt); 17412952Sgabeblack@google.com if (wasFull && !mq->isFull()) { 17512952Sgabeblack@google.com clearBlocked((BlockedCause)mq->index); 17612952Sgabeblack@google.com } 17712952Sgabeblack@google.com } 17812952Sgabeblack@google.com 17912952Sgabeblack@google.com /** Block size of this cache */ 18012952Sgabeblack@google.com const unsigned blkSize; 18112952Sgabeblack@google.com 18212952Sgabeblack@google.com /** 18312952Sgabeblack@google.com * The latency of a hit in this device. 18412952Sgabeblack@google.com */ 18512952Sgabeblack@google.com int hitLatency; 18612952Sgabeblack@google.com 18712952Sgabeblack@google.com /** The number of targets for each MSHR. */ 18812952Sgabeblack@google.com const int numTarget; 18912952Sgabeblack@google.com 19012952Sgabeblack@google.com /** Do we forward snoops from mem side port through to cpu side port? */ 19112952Sgabeblack@google.com bool forwardSnoops; 19212952Sgabeblack@google.com 19312952Sgabeblack@google.com /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should 19412952Sgabeblack@google.com * never try to forward ownership and similar optimizations to the cpu 19512952Sgabeblack@google.com * side */ 19612952Sgabeblack@google.com bool isTopLevel; 19712952Sgabeblack@google.com 19812952Sgabeblack@google.com /** 19912952Sgabeblack@google.com * Bit vector of the blocking reasons for the access path. 20012952Sgabeblack@google.com * @sa #BlockedCause 20112952Sgabeblack@google.com */ 20212952Sgabeblack@google.com uint8_t blocked; 20312995Sgabeblack@google.com 20412995Sgabeblack@google.com /** Increasing order number assigned to each incoming request. */ 20512995Sgabeblack@google.com uint64_t order; 20612995Sgabeblack@google.com 20712995Sgabeblack@google.com /** Stores time the cache blocked for statistics. */ 20812995Sgabeblack@google.com Tick blockedCycle; 20912995Sgabeblack@google.com 21012952Sgabeblack@google.com /** Pointer to the MSHR that has no targets. */ 21112952Sgabeblack@google.com MSHR *noTargetMSHR; 21212952Sgabeblack@google.com 21312952Sgabeblack@google.com /** The number of misses to trigger an exit event. */ 21412952Sgabeblack@google.com Counter missCount; 21512952Sgabeblack@google.com 21612952Sgabeblack@google.com /** The drain event. */ 21712952Sgabeblack@google.com Event *drainEvent; 21812952Sgabeblack@google.com 21912952Sgabeblack@google.com /** 22012952Sgabeblack@google.com * The address range to which the cache responds on the CPU side. 22112952Sgabeblack@google.com * Normally this is all possible memory addresses. */ 22212952Sgabeblack@google.com Range<Addr> addrRange; 22312952Sgabeblack@google.com 22412952Sgabeblack@google.com public: 22512952Sgabeblack@google.com /** System we are currently operating in. */ 22612952Sgabeblack@google.com System *system; 22712995Sgabeblack@google.com 22812995Sgabeblack@google.com // Statistics 22912995Sgabeblack@google.com /** 23012952Sgabeblack@google.com * @addtogroup CacheStatistics 23112952Sgabeblack@google.com * @{ 23212952Sgabeblack@google.com */ 23312952Sgabeblack@google.com 23412952Sgabeblack@google.com /** Number of hits per thread for each type of command. @sa Packet::Command */ 23512952Sgabeblack@google.com Stats::Vector hits[MemCmd::NUM_MEM_CMDS]; 23612952Sgabeblack@google.com /** Number of hits for demand accesses. */ 23712952Sgabeblack@google.com Stats::Formula demandHits; 23812952Sgabeblack@google.com /** Number of hit for all accesses. */ 23912952Sgabeblack@google.com Stats::Formula overallHits; 24012952Sgabeblack@google.com 24112952Sgabeblack@google.com /** Number of misses per thread for each type of command. @sa Packet::Command */ 24212952Sgabeblack@google.com Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; 24312952Sgabeblack@google.com /** Number of misses for demand accesses. */ 24412952Sgabeblack@google.com Stats::Formula demandMisses; 24512952Sgabeblack@google.com /** Number of misses for all accesses. */ 24612952Sgabeblack@google.com Stats::Formula overallMisses; 24712995Sgabeblack@google.com 24812952Sgabeblack@google.com /** 24912952Sgabeblack@google.com * Total number of cycles per thread/command spent waiting for a miss. 25012952Sgabeblack@google.com * Used to calculate the average miss latency. 25112952Sgabeblack@google.com */ 25212952Sgabeblack@google.com Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS]; 25312952Sgabeblack@google.com /** Total number of cycles spent waiting for demand misses. */ 25412952Sgabeblack@google.com Stats::Formula demandMissLatency; 25512952Sgabeblack@google.com /** Total number of cycles spent waiting for all misses. */ 25612952Sgabeblack@google.com Stats::Formula overallMissLatency; 25712952Sgabeblack@google.com 25812952Sgabeblack@google.com /** The number of accesses per command and thread. */ 25912952Sgabeblack@google.com Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 26012952Sgabeblack@google.com /** The number of demand accesses. */ 26112952Sgabeblack@google.com Stats::Formula demandAccesses; 26212952Sgabeblack@google.com /** The number of overall accesses. */ 26312952Sgabeblack@google.com Stats::Formula overallAccesses; 26412952Sgabeblack@google.com 26512952Sgabeblack@google.com /** The miss rate per command and thread. */ 26612952Sgabeblack@google.com Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 26712952Sgabeblack@google.com /** The miss rate of all demand accesses. */ 26812952Sgabeblack@google.com Stats::Formula demandMissRate; 26912957Sgabeblack@google.com /** The miss rate for all accesses. */ 27012957Sgabeblack@google.com Stats::Formula overallMissRate; 27112957Sgabeblack@google.com 27212957Sgabeblack@google.com /** The average miss latency per command and thread. */ 27312957Sgabeblack@google.com Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 27412957Sgabeblack@google.com /** The average miss latency for demand misses. */ 27512957Sgabeblack@google.com Stats::Formula demandAvgMissLatency; 27612957Sgabeblack@google.com /** The average miss latency for all misses. */ 27712957Sgabeblack@google.com Stats::Formula overallAvgMissLatency; 27812957Sgabeblack@google.com 27912957Sgabeblack@google.com /** The total number of cycles blocked for each blocked cause. */ 28012957Sgabeblack@google.com Stats::Vector blocked_cycles; 28112957Sgabeblack@google.com /** The number of times this cache blocked for each blocked cause. */ 28212957Sgabeblack@google.com Stats::Vector blocked_causes; 28312957Sgabeblack@google.com 28412957Sgabeblack@google.com /** The average number of cycles blocked for each blocked cause. */ 28512957Sgabeblack@google.com Stats::Formula avg_blocked; 28612953Sgabeblack@google.com 28712952Sgabeblack@google.com /** The number of fast writes (WH64) performed. */ 28812953Sgabeblack@google.com Stats::Scalar fastWrites; 28912953Sgabeblack@google.com 29012953Sgabeblack@google.com /** The number of cache copies performed. */ 29112953Sgabeblack@google.com Stats::Scalar cacheCopies; 29212953Sgabeblack@google.com 29312995Sgabeblack@google.com /** Number of blocks written back per thread. */ 29412953Sgabeblack@google.com Stats::Vector writebacks; 29512995Sgabeblack@google.com 29612953Sgabeblack@google.com /** Number of misses that hit in the MSHRs per command and thread. */ 29712953Sgabeblack@google.com Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS]; 29812961Sgabeblack@google.com /** Demand misses that hit in the MSHRs. */ 29912953Sgabeblack@google.com Stats::Formula demandMshrHits; 30012952Sgabeblack@google.com /** Total number of misses that hit in the MSHRs. */ 30112957Sgabeblack@google.com Stats::Formula overallMshrHits; 30212957Sgabeblack@google.com 30312957Sgabeblack@google.com /** Number of misses that miss in the MSHRs, per command and thread. */ 30412957Sgabeblack@google.com Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS]; 30512957Sgabeblack@google.com /** Demand misses that miss in the MSHRs. */ 30612957Sgabeblack@google.com Stats::Formula demandMshrMisses; 30712957Sgabeblack@google.com /** Total number of misses that miss in the MSHRs. */ 30812957Sgabeblack@google.com Stats::Formula overallMshrMisses; 30912957Sgabeblack@google.com 31012957Sgabeblack@google.com /** Number of misses that miss in the MSHRs, per command and thread. */ 31112957Sgabeblack@google.com Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 31212957Sgabeblack@google.com /** Total number of misses that miss in the MSHRs. */ 31312957Sgabeblack@google.com Stats::Formula overallMshrUncacheable; 31412959Sgabeblack@google.com 31512959Sgabeblack@google.com /** Total cycle latency of each MSHR miss, per command and thread. */ 31612959Sgabeblack@google.com Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 31712959Sgabeblack@google.com /** Total cycle latency of demand MSHR misses. */ 31812959Sgabeblack@google.com Stats::Formula demandMshrMissLatency; 31912959Sgabeblack@google.com /** Total cycle latency of overall MSHR misses. */ 32012959Sgabeblack@google.com Stats::Formula overallMshrMissLatency; 32112959Sgabeblack@google.com 32212959Sgabeblack@google.com /** Total cycle latency of each MSHR miss, per command and thread. */ 32312959Sgabeblack@google.com Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 32412959Sgabeblack@google.com /** Total cycle latency of overall MSHR misses. */ 32512959Sgabeblack@google.com Stats::Formula overallMshrUncacheableLatency; 32612959Sgabeblack@google.com 32712959Sgabeblack@google.com#if 0 32812996Sgabeblack@google.com /** The total number of MSHR accesses per command and thread. */ 32912996Sgabeblack@google.com Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 33012959Sgabeblack@google.com /** The total number of demand MSHR accesses. */ 33112959Sgabeblack@google.com Stats::Formula demandMshrAccesses; 33212959Sgabeblack@google.com /** The total number of MSHR accesses. */ 33312959Sgabeblack@google.com Stats::Formula overallMshrAccesses; 33412959Sgabeblack@google.com#endif 33512959Sgabeblack@google.com 33612961Sgabeblack@google.com /** The miss rate in the MSHRs pre command and thread. */ 33712961Sgabeblack@google.com Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 33812953Sgabeblack@google.com /** The demand miss rate in the MSHRs. */ 33912961Sgabeblack@google.com Stats::Formula demandMshrMissRate; 34012953Sgabeblack@google.com /** The overall miss rate in the MSHRs. */ 34112957Sgabeblack@google.com Stats::Formula overallMshrMissRate; 34212957Sgabeblack@google.com 34312953Sgabeblack@google.com /** The average latency of an MSHR miss, per command and thread. */ 34412953Sgabeblack@google.com Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 34512953Sgabeblack@google.com /** The average latency of a demand MSHR miss. */ 34612952Sgabeblack@google.com Stats::Formula demandAvgMshrMissLatency; 34712953Sgabeblack@google.com /** The average overall latency of an MSHR miss. */ 34812952Sgabeblack@google.com Stats::Formula overallAvgMshrMissLatency; 34912952Sgabeblack@google.com 35012952Sgabeblack@google.com /** The average latency of an MSHR miss, per command and thread. */ 35112952Sgabeblack@google.com Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 35212952Sgabeblack@google.com /** The average overall latency of an MSHR miss. */ 35312952Sgabeblack@google.com Stats::Formula overallAvgMshrUncacheableLatency; 35412952Sgabeblack@google.com 35512952Sgabeblack@google.com /** The number of times a thread hit its MSHR cap. */ 356 Stats::Vector mshr_cap_events; 357 /** The number of times software prefetches caused the MSHR to block. */ 358 Stats::Vector soft_prefetch_mshr_full; 359 360 Stats::Scalar mshr_no_allocate_misses; 361 362 /** 363 * @} 364 */ 365 366 /** 367 * Register stats for this object. 368 */ 369 virtual void regStats(); 370 371 public: 372 typedef BaseCacheParams Params; 373 BaseCache(const Params *p); 374 ~BaseCache() {} 375 376 virtual void init(); 377 378 /** 379 * Query block size of a cache. 380 * @return The block size 381 */ 382 unsigned 383 getBlockSize() const 384 { 385 return blkSize; 386 } 387 388 389 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); } 390 391 392 const Range<Addr> &getAddrRange() const { return addrRange; } 393 394 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 395 { 396 assert(!pkt->req->isUncacheable()); 397 return allocateBufferInternal(&mshrQueue, 398 blockAlign(pkt->getAddr()), blkSize, 399 pkt, time, requestBus); 400 } 401 402 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus) 403 { 404 assert(pkt->isWrite() && !pkt->isRead()); 405 return allocateBufferInternal(&writeBuffer, 406 pkt->getAddr(), pkt->getSize(), 407 pkt, time, requestBus); 408 } 409 410 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus) 411 { 412 assert(pkt->req->isUncacheable()); 413 assert(pkt->isRead()); 414 return allocateBufferInternal(&mshrQueue, 415 pkt->getAddr(), pkt->getSize(), 416 pkt, time, requestBus); 417 } 418 419 /** 420 * Returns true if the cache is blocked for accesses. 421 */ 422 bool isBlocked() 423 { 424 return blocked != 0; 425 } 426 427 /** 428 * Marks the access path of the cache as blocked for the given cause. This 429 * also sets the blocked flag in the slave interface. 430 * @param cause The reason for the cache blocking. 431 */ 432 void setBlocked(BlockedCause cause) 433 { 434 uint8_t flag = 1 << cause; 435 if (blocked == 0) { 436 blocked_causes[cause]++; 437 blockedCycle = curTick(); 438 cpuSidePort->setBlocked(); 439 } 440 blocked |= flag; 441 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 442 } 443 444 /** 445 * Marks the cache as unblocked for the given cause. This also clears the 446 * blocked flags in the appropriate interfaces. 447 * @param cause The newly unblocked cause. 448 * @warning Calling this function can cause a blocked request on the bus to 449 * access the cache. The cache must be in a state to handle that request. 450 */ 451 void clearBlocked(BlockedCause cause) 452 { 453 uint8_t flag = 1 << cause; 454 blocked &= ~flag; 455 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 456 if (blocked == 0) { 457 blocked_cycles[cause] += curTick() - blockedCycle; 458 cpuSidePort->clearBlocked(); 459 } 460 } 461 462 /** 463 * Request the master bus for the given cause and time. 464 * @param cause The reason for the request. 465 * @param time The time to make the request. 466 */ 467 void requestMemSideBus(RequestCause cause, Tick time) 468 { 469 memSidePort->requestBus(cause, time); 470 } 471 472 /** 473 * Clear the master bus request for the given cause. 474 * @param cause The request reason to clear. 475 */ 476 void deassertMemSideBusRequest(RequestCause cause) 477 { 478 // Obsolete... we no longer signal bus requests explicitly so 479 // we can't deassert them. Leaving this in as a no-op since 480 // the prefetcher calls it to indicate that it no longer wants 481 // to request a prefetch, and someday that might be 482 // interesting again. 483 } 484 485 virtual unsigned int drain(Event *de); 486 487 virtual bool inCache(Addr addr) = 0; 488 489 virtual bool inMissQueue(Addr addr) = 0; 490 491 void incMissCount(PacketPtr pkt) 492 { 493 assert(pkt->req->masterId() < system->maxMasters()); 494 misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 495 496 if (missCount) { 497 --missCount; 498 if (missCount == 0) 499 exitSimLoop("A cache reached the maximum miss count"); 500 } 501 } 502 void incHitCount(PacketPtr pkt) 503 { 504 assert(pkt->req->masterId() < system->maxMasters()); 505 hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 506 507 } 508 509}; 510 511#endif //__BASE_CACHE_HH__ 512