base.hh revision 6122
12810SN/A/* 22810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32810SN/A * All rights reserved. 42810SN/A * 52810SN/A * Redistribution and use in source and binary forms, with or without 62810SN/A * modification, are permitted provided that the following conditions are 72810SN/A * met: redistributions of source code must retain the above copyright 82810SN/A * notice, this list of conditions and the following disclaimer; 92810SN/A * redistributions in binary form must reproduce the above copyright 102810SN/A * notice, this list of conditions and the following disclaimer in the 112810SN/A * documentation and/or other materials provided with the distribution; 122810SN/A * neither the name of the copyright holders nor the names of its 132810SN/A * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A * 282810SN/A * Authors: Erik Hallnor 294458SN/A * Steve Reinhardt 304458SN/A * Ron Dreslinski 312810SN/A */ 322810SN/A 332810SN/A/** 342810SN/A * @file 352810SN/A * Declares a basic cache interface BaseCache. 362810SN/A */ 372810SN/A 382810SN/A#ifndef __BASE_CACHE_HH__ 392810SN/A#define __BASE_CACHE_HH__ 402810SN/A 412810SN/A#include <vector> 422810SN/A#include <string> 432810SN/A#include <list> 444666SN/A#include <algorithm> 452810SN/A#include <inttypes.h> 462810SN/A 472825SN/A#include "base/misc.hh" 482810SN/A#include "base/statistics.hh" 492810SN/A#include "base/trace.hh" 505338Sstever@gmail.com#include "mem/cache/mshr_queue.hh" 512810SN/A#include "mem/mem_object.hh" 522810SN/A#include "mem/packet.hh" 534626SN/A#include "mem/tport.hh" 542810SN/A#include "mem/request.hh" 555034SN/A#include "params/BaseCache.hh" 562811SN/A#include "sim/eventq.hh" 574626SN/A#include "sim/sim_exit.hh" 582810SN/A 593194SN/Aclass MSHR; 602810SN/A/** 612810SN/A * A basic cache interface. Implements some common functions for speed. 622810SN/A */ 632810SN/Aclass BaseCache : public MemObject 642810SN/A{ 654628SN/A /** 664628SN/A * Indexes to enumerate the MSHR queues. 674628SN/A */ 684628SN/A enum MSHRQueueIndex { 694628SN/A MSHRQueue_MSHRs, 704628SN/A MSHRQueue_WriteBuffer 714628SN/A }; 724628SN/A 734628SN/A /** 744628SN/A * Reasons for caches to be blocked. 754628SN/A */ 764628SN/A enum BlockedCause { 774628SN/A Blocked_NoMSHRs = MSHRQueue_MSHRs, 784628SN/A Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 794628SN/A Blocked_NoTargets, 804628SN/A NUM_BLOCKED_CAUSES 814628SN/A }; 824628SN/A 834628SN/A public: 844628SN/A /** 854628SN/A * Reasons for cache to request a bus. 864628SN/A */ 874628SN/A enum RequestCause { 884628SN/A Request_MSHR = MSHRQueue_MSHRs, 894628SN/A Request_WB = MSHRQueue_WriteBuffer, 904628SN/A Request_PF, 914628SN/A NUM_REQUEST_CAUSES 924628SN/A }; 934628SN/A 944628SN/A private: 954628SN/A 964626SN/A class CachePort : public SimpleTimingPort 972810SN/A { 982844SN/A public: 992810SN/A BaseCache *cache; 1002810SN/A 1013738SN/A protected: 1024965SN/A CachePort(const std::string &_name, BaseCache *_cache, 1036122SSteve.Reinhardt@amd.com const std::string &_label); 1044458SN/A 1052810SN/A virtual void recvStatusChange(Status status); 1062810SN/A 1072810SN/A virtual int deviceBlockSize(); 1082810SN/A 1094458SN/A bool recvRetryCommon(); 1103013SN/A 1114666SN/A typedef EventWrapper<Port, &Port::sendRetry> 1124666SN/A SendRetryEvent; 1134666SN/A 1145314SN/A const std::string label; 1155314SN/A 1162811SN/A public: 1174458SN/A void setOtherPort(CachePort *_otherPort) { otherPort = _otherPort; } 1184458SN/A 1192810SN/A void setBlocked(); 1202810SN/A 1212810SN/A void clearBlocked(); 1222810SN/A 1235314SN/A bool checkFunctional(PacketPtr pkt); 1243606SN/A 1254458SN/A CachePort *otherPort; 1264458SN/A 1272810SN/A bool blocked; 1282810SN/A 1292897SN/A bool mustSendRetry; 1302897SN/A 1314458SN/A void requestBus(RequestCause cause, Tick time) 1324458SN/A { 1334888SN/A DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); 1344666SN/A if (!waitingOnRetry) { 1354666SN/A schedSendEvent(time); 1364458SN/A } 1374458SN/A } 1384458SN/A 1394626SN/A void respond(PacketPtr pkt, Tick time) { 1404626SN/A schedSendTiming(pkt, time); 1414626SN/A } 1422811SN/A }; 1432810SN/A 1443338SN/A public: //Made public so coherence can get at it. 1453338SN/A CachePort *cpuSidePort; 1463738SN/A CachePort *memSidePort; 1473338SN/A 1484626SN/A protected: 1494626SN/A 1504626SN/A /** Miss status registers */ 1514626SN/A MSHRQueue mshrQueue; 1524626SN/A 1534626SN/A /** Write/writeback buffer */ 1544626SN/A MSHRQueue writeBuffer; 1554626SN/A 1564628SN/A MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 1574628SN/A PacketPtr pkt, Tick time, bool requestBus) 1584628SN/A { 1594666SN/A MSHR *mshr = mq->allocate(addr, size, pkt, time, order++); 1604628SN/A 1614628SN/A if (mq->isFull()) { 1624628SN/A setBlocked((BlockedCause)mq->index); 1634628SN/A } 1644628SN/A 1654628SN/A if (requestBus) { 1664628SN/A requestMemSideBus((RequestCause)mq->index, time); 1674628SN/A } 1684628SN/A 1694628SN/A return mshr; 1704628SN/A } 1714628SN/A 1724628SN/A void markInServiceInternal(MSHR *mshr) 1734628SN/A { 1744628SN/A MSHRQueue *mq = mshr->queue; 1754628SN/A bool wasFull = mq->isFull(); 1764628SN/A mq->markInService(mshr); 1774628SN/A if (wasFull && !mq->isFull()) { 1784628SN/A clearBlocked((BlockedCause)mq->index); 1794628SN/A } 1804628SN/A } 1814628SN/A 1824626SN/A /** Block size of this cache */ 1834626SN/A const int blkSize; 1844626SN/A 1854630SN/A /** 1864630SN/A * The latency of a hit in this device. 1874630SN/A */ 1884630SN/A int hitLatency; 1894630SN/A 1904626SN/A /** The number of targets for each MSHR. */ 1914626SN/A const int numTarget; 1924626SN/A 1936122SSteve.Reinhardt@amd.com /** Do we forward snoops from mem side port through to cpu side port? */ 1946122SSteve.Reinhardt@amd.com bool forwardSnoops; 1954626SN/A 1962810SN/A /** 1972810SN/A * Bit vector of the blocking reasons for the access path. 1982810SN/A * @sa #BlockedCause 1992810SN/A */ 2002810SN/A uint8_t blocked; 2012810SN/A 2026122SSteve.Reinhardt@amd.com /** Increasing order number assigned to each incoming request. */ 2036122SSteve.Reinhardt@amd.com uint64_t order; 2046122SSteve.Reinhardt@amd.com 2052810SN/A /** Stores time the cache blocked for statistics. */ 2062810SN/A Tick blockedCycle; 2072810SN/A 2084626SN/A /** Pointer to the MSHR that has no targets. */ 2094626SN/A MSHR *noTargetMSHR; 2102810SN/A 2112810SN/A /** The number of misses to trigger an exit event. */ 2122810SN/A Counter missCount; 2132810SN/A 2143503SN/A /** The drain event. */ 2153503SN/A Event *drainEvent; 2163503SN/A 2176122SSteve.Reinhardt@amd.com /** 2186122SSteve.Reinhardt@amd.com * The address range to which the cache responds on the CPU side. 2196122SSteve.Reinhardt@amd.com * Normally this is all possible memory addresses. */ 2206122SSteve.Reinhardt@amd.com Range<Addr> addrRange; 2216122SSteve.Reinhardt@amd.com 2222810SN/A public: 2232810SN/A // Statistics 2242810SN/A /** 2252810SN/A * @addtogroup CacheStatistics 2262810SN/A * @{ 2272810SN/A */ 2282810SN/A 2292810SN/A /** Number of hits per thread for each type of command. @sa Packet::Command */ 2305999Snate@binkert.org Stats::Vector hits[MemCmd::NUM_MEM_CMDS]; 2312810SN/A /** Number of hits for demand accesses. */ 2322810SN/A Stats::Formula demandHits; 2332810SN/A /** Number of hit for all accesses. */ 2342810SN/A Stats::Formula overallHits; 2352810SN/A 2362810SN/A /** Number of misses per thread for each type of command. @sa Packet::Command */ 2375999Snate@binkert.org Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; 2382810SN/A /** Number of misses for demand accesses. */ 2392810SN/A Stats::Formula demandMisses; 2402810SN/A /** Number of misses for all accesses. */ 2412810SN/A Stats::Formula overallMisses; 2422810SN/A 2432810SN/A /** 2442810SN/A * Total number of cycles per thread/command spent waiting for a miss. 2452810SN/A * Used to calculate the average miss latency. 2462810SN/A */ 2475999Snate@binkert.org Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS]; 2482810SN/A /** Total number of cycles spent waiting for demand misses. */ 2492810SN/A Stats::Formula demandMissLatency; 2502810SN/A /** Total number of cycles spent waiting for all misses. */ 2512810SN/A Stats::Formula overallMissLatency; 2522810SN/A 2532810SN/A /** The number of accesses per command and thread. */ 2544022SN/A Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 2552810SN/A /** The number of demand accesses. */ 2562810SN/A Stats::Formula demandAccesses; 2572810SN/A /** The number of overall accesses. */ 2582810SN/A Stats::Formula overallAccesses; 2592810SN/A 2602810SN/A /** The miss rate per command and thread. */ 2614022SN/A Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 2622810SN/A /** The miss rate of all demand accesses. */ 2632810SN/A Stats::Formula demandMissRate; 2642810SN/A /** The miss rate for all accesses. */ 2652810SN/A Stats::Formula overallMissRate; 2662810SN/A 2672810SN/A /** The average miss latency per command and thread. */ 2684022SN/A Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 2692810SN/A /** The average miss latency for demand misses. */ 2702810SN/A Stats::Formula demandAvgMissLatency; 2712810SN/A /** The average miss latency for all misses. */ 2722810SN/A Stats::Formula overallAvgMissLatency; 2732810SN/A 2742810SN/A /** The total number of cycles blocked for each blocked cause. */ 2755999Snate@binkert.org Stats::Vector blocked_cycles; 2762810SN/A /** The number of times this cache blocked for each blocked cause. */ 2775999Snate@binkert.org Stats::Vector blocked_causes; 2782810SN/A 2792810SN/A /** The average number of cycles blocked for each blocked cause. */ 2802810SN/A Stats::Formula avg_blocked; 2812810SN/A 2822810SN/A /** The number of fast writes (WH64) performed. */ 2835999Snate@binkert.org Stats::Scalar fastWrites; 2842810SN/A 2852810SN/A /** The number of cache copies performed. */ 2865999Snate@binkert.org Stats::Scalar cacheCopies; 2872810SN/A 2884626SN/A /** Number of blocks written back per thread. */ 2895999Snate@binkert.org Stats::Vector writebacks; 2904626SN/A 2914626SN/A /** Number of misses that hit in the MSHRs per command and thread. */ 2925999Snate@binkert.org Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS]; 2934626SN/A /** Demand misses that hit in the MSHRs. */ 2944626SN/A Stats::Formula demandMshrHits; 2954626SN/A /** Total number of misses that hit in the MSHRs. */ 2964626SN/A Stats::Formula overallMshrHits; 2974626SN/A 2984626SN/A /** Number of misses that miss in the MSHRs, per command and thread. */ 2995999Snate@binkert.org Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS]; 3004626SN/A /** Demand misses that miss in the MSHRs. */ 3014626SN/A Stats::Formula demandMshrMisses; 3024626SN/A /** Total number of misses that miss in the MSHRs. */ 3034626SN/A Stats::Formula overallMshrMisses; 3044626SN/A 3054626SN/A /** Number of misses that miss in the MSHRs, per command and thread. */ 3065999Snate@binkert.org Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 3074626SN/A /** Total number of misses that miss in the MSHRs. */ 3084626SN/A Stats::Formula overallMshrUncacheable; 3094626SN/A 3104626SN/A /** Total cycle latency of each MSHR miss, per command and thread. */ 3115999Snate@binkert.org Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 3124626SN/A /** Total cycle latency of demand MSHR misses. */ 3134626SN/A Stats::Formula demandMshrMissLatency; 3144626SN/A /** Total cycle latency of overall MSHR misses. */ 3154626SN/A Stats::Formula overallMshrMissLatency; 3164626SN/A 3174626SN/A /** Total cycle latency of each MSHR miss, per command and thread. */ 3185999Snate@binkert.org Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 3194626SN/A /** Total cycle latency of overall MSHR misses. */ 3204626SN/A Stats::Formula overallMshrUncacheableLatency; 3214626SN/A 3224626SN/A /** The total number of MSHR accesses per command and thread. */ 3234626SN/A Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 3244626SN/A /** The total number of demand MSHR accesses. */ 3254626SN/A Stats::Formula demandMshrAccesses; 3264626SN/A /** The total number of MSHR accesses. */ 3274626SN/A Stats::Formula overallMshrAccesses; 3284626SN/A 3294626SN/A /** The miss rate in the MSHRs pre command and thread. */ 3304626SN/A Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 3314626SN/A /** The demand miss rate in the MSHRs. */ 3324626SN/A Stats::Formula demandMshrMissRate; 3334626SN/A /** The overall miss rate in the MSHRs. */ 3344626SN/A Stats::Formula overallMshrMissRate; 3354626SN/A 3364626SN/A /** The average latency of an MSHR miss, per command and thread. */ 3374626SN/A Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 3384626SN/A /** The average latency of a demand MSHR miss. */ 3394626SN/A Stats::Formula demandAvgMshrMissLatency; 3404626SN/A /** The average overall latency of an MSHR miss. */ 3414626SN/A Stats::Formula overallAvgMshrMissLatency; 3424626SN/A 3434626SN/A /** The average latency of an MSHR miss, per command and thread. */ 3444626SN/A Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 3454626SN/A /** The average overall latency of an MSHR miss. */ 3464626SN/A Stats::Formula overallAvgMshrUncacheableLatency; 3474626SN/A 3484626SN/A /** The number of times a thread hit its MSHR cap. */ 3495999Snate@binkert.org Stats::Vector mshr_cap_events; 3504626SN/A /** The number of times software prefetches caused the MSHR to block. */ 3515999Snate@binkert.org Stats::Vector soft_prefetch_mshr_full; 3524626SN/A 3535999Snate@binkert.org Stats::Scalar mshr_no_allocate_misses; 3544626SN/A 3552810SN/A /** 3562810SN/A * @} 3572810SN/A */ 3582810SN/A 3592810SN/A /** 3602810SN/A * Register stats for this object. 3612810SN/A */ 3622810SN/A virtual void regStats(); 3632810SN/A 3642810SN/A public: 3655034SN/A typedef BaseCacheParams Params; 3665034SN/A BaseCache(const Params *p); 3675034SN/A ~BaseCache() {} 3683606SN/A 3692858SN/A virtual void init(); 3702858SN/A 3712810SN/A /** 3722810SN/A * Query block size of a cache. 3732810SN/A * @return The block size 3742810SN/A */ 3752810SN/A int getBlockSize() const 3762810SN/A { 3772810SN/A return blkSize; 3782810SN/A } 3792810SN/A 3804626SN/A 3814626SN/A Addr blockAlign(Addr addr) const { return (addr & ~(blkSize - 1)); } 3824626SN/A 3834626SN/A 3846122SSteve.Reinhardt@amd.com const Range<Addr> &getAddrRange() const { return addrRange; } 3856122SSteve.Reinhardt@amd.com 3864628SN/A MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 3874628SN/A { 3884902SN/A assert(!pkt->req->isUncacheable()); 3894628SN/A return allocateBufferInternal(&mshrQueue, 3904628SN/A blockAlign(pkt->getAddr()), blkSize, 3914628SN/A pkt, time, requestBus); 3924628SN/A } 3934628SN/A 3944902SN/A MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus) 3954628SN/A { 3964902SN/A assert(pkt->isWrite() && !pkt->isRead()); 3974902SN/A return allocateBufferInternal(&writeBuffer, 3984902SN/A pkt->getAddr(), pkt->getSize(), 3994628SN/A pkt, time, requestBus); 4004628SN/A } 4014628SN/A 4024902SN/A MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus) 4034902SN/A { 4044902SN/A assert(pkt->req->isUncacheable()); 4054902SN/A assert(pkt->isRead()); 4064902SN/A return allocateBufferInternal(&mshrQueue, 4074902SN/A pkt->getAddr(), pkt->getSize(), 4084902SN/A pkt, time, requestBus); 4094902SN/A } 4104628SN/A 4112810SN/A /** 4122810SN/A * Returns true if the cache is blocked for accesses. 4132810SN/A */ 4142810SN/A bool isBlocked() 4152810SN/A { 4162810SN/A return blocked != 0; 4172810SN/A } 4182810SN/A 4192810SN/A /** 4202810SN/A * Marks the access path of the cache as blocked for the given cause. This 4212810SN/A * also sets the blocked flag in the slave interface. 4222810SN/A * @param cause The reason for the cache blocking. 4232810SN/A */ 4242810SN/A void setBlocked(BlockedCause cause) 4252810SN/A { 4262810SN/A uint8_t flag = 1 << cause; 4272810SN/A if (blocked == 0) { 4282810SN/A blocked_causes[cause]++; 4292810SN/A blockedCycle = curTick; 4304630SN/A cpuSidePort->setBlocked(); 4312810SN/A } 4324630SN/A blocked |= flag; 4334630SN/A DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 4342810SN/A } 4352810SN/A 4362810SN/A /** 4372810SN/A * Marks the cache as unblocked for the given cause. This also clears the 4382810SN/A * blocked flags in the appropriate interfaces. 4392810SN/A * @param cause The newly unblocked cause. 4402810SN/A * @warning Calling this function can cause a blocked request on the bus to 4412810SN/A * access the cache. The cache must be in a state to handle that request. 4422810SN/A */ 4432810SN/A void clearBlocked(BlockedCause cause) 4442810SN/A { 4452810SN/A uint8_t flag = 1 << cause; 4464630SN/A blocked &= ~flag; 4474630SN/A DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 4484630SN/A if (blocked == 0) { 4494630SN/A blocked_cycles[cause] += curTick - blockedCycle; 4504630SN/A cpuSidePort->clearBlocked(); 4512810SN/A } 4522810SN/A } 4532810SN/A 4542810SN/A /** 4552810SN/A * Request the master bus for the given cause and time. 4562810SN/A * @param cause The reason for the request. 4572810SN/A * @param time The time to make the request. 4582810SN/A */ 4594458SN/A void requestMemSideBus(RequestCause cause, Tick time) 4602810SN/A { 4614458SN/A memSidePort->requestBus(cause, time); 4622810SN/A } 4632810SN/A 4642810SN/A /** 4652810SN/A * Clear the master bus request for the given cause. 4662810SN/A * @param cause The request reason to clear. 4672810SN/A */ 4684458SN/A void deassertMemSideBusRequest(RequestCause cause) 4692810SN/A { 4705875Ssteve.reinhardt@amd.com // Obsolete... we no longer signal bus requests explicitly so 4715875Ssteve.reinhardt@amd.com // we can't deassert them. Leaving this in as a no-op since 4725875Ssteve.reinhardt@amd.com // the prefetcher calls it to indicate that it no longer wants 4735875Ssteve.reinhardt@amd.com // to request a prefetch, and someday that might be 4745875Ssteve.reinhardt@amd.com // interesting again. 4752811SN/A } 4763503SN/A 4773503SN/A virtual unsigned int drain(Event *de); 4783503SN/A 4794626SN/A virtual bool inCache(Addr addr) = 0; 4804626SN/A 4814626SN/A virtual bool inMissQueue(Addr addr) = 0; 4824626SN/A 4834626SN/A void incMissCount(PacketPtr pkt) 4843503SN/A { 4855715Shsul@eecs.umich.edu misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++; 4864626SN/A 4874626SN/A if (missCount) { 4884626SN/A --missCount; 4894626SN/A if (missCount == 0) 4904626SN/A exitSimLoop("A cache reached the maximum miss count"); 4913503SN/A } 4923503SN/A } 4933503SN/A 4942810SN/A}; 4952810SN/A 4962810SN/A#endif //__BASE_CACHE_HH__ 497