base.hh revision 13624
12810SN/A/* 212724Snikos.nikoleris@arm.com * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98856Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138856Sandreas.hansson@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 414458SN/A * Steve Reinhardt 424458SN/A * Ron Dreslinski 4312724Snikos.nikoleris@arm.com * Andreas Hansson 4412724Snikos.nikoleris@arm.com * Nikos Nikoleris 452810SN/A */ 462810SN/A 472810SN/A/** 482810SN/A * @file 492810SN/A * Declares a basic cache interface BaseCache. 502810SN/A */ 512810SN/A 5211051Sandreas.hansson@arm.com#ifndef __MEM_CACHE_BASE_HH__ 5311051Sandreas.hansson@arm.com#define __MEM_CACHE_BASE_HH__ 542810SN/A 5512724Snikos.nikoleris@arm.com#include <cassert> 5612724Snikos.nikoleris@arm.com#include <cstdint> 577676Snate@binkert.org#include <string> 582810SN/A 5912724Snikos.nikoleris@arm.com#include "base/addr_range.hh" 602810SN/A#include "base/statistics.hh" 612810SN/A#include "base/trace.hh" 626215Snate@binkert.org#include "base/types.hh" 638232Snate@binkert.org#include "debug/Cache.hh" 648232Snate@binkert.org#include "debug/CachePort.hh" 6512724Snikos.nikoleris@arm.com#include "enums/Clusivity.hh" 6613223Sodanrc@yahoo.com.br#include "mem/cache/cache_blk.hh" 675338Sstever@gmail.com#include "mem/cache/mshr_queue.hh" 6812724Snikos.nikoleris@arm.com#include "mem/cache/tags/base.hh" 6911375Sandreas.hansson@arm.com#include "mem/cache/write_queue.hh" 7012724Snikos.nikoleris@arm.com#include "mem/cache/write_queue_entry.hh" 712810SN/A#include "mem/mem_object.hh" 722810SN/A#include "mem/packet.hh" 7312724Snikos.nikoleris@arm.com#include "mem/packet_queue.hh" 748914Sandreas.hansson@arm.com#include "mem/qport.hh" 758229Snate@binkert.org#include "mem/request.hh" 7613352Snikos.nikoleris@arm.com#include "params/WriteAllocator.hh" 772811SN/A#include "sim/eventq.hh" 7813416Sjavier.bueno@metempsy.com#include "sim/probe/probe.hh" 7912724Snikos.nikoleris@arm.com#include "sim/serialize.hh" 804626SN/A#include "sim/sim_exit.hh" 818833Sdam.sunwoo@arm.com#include "sim/system.hh" 822810SN/A 8312724Snikos.nikoleris@arm.comclass BaseMasterPort; 8412724Snikos.nikoleris@arm.comclass BasePrefetcher; 8512724Snikos.nikoleris@arm.comclass BaseSlavePort; 8612724Snikos.nikoleris@arm.comclass MSHR; 8712724Snikos.nikoleris@arm.comclass MasterPort; 8812724Snikos.nikoleris@arm.comclass QueueEntry; 8912724Snikos.nikoleris@arm.comstruct BaseCacheParams; 9012724Snikos.nikoleris@arm.com 912810SN/A/** 922810SN/A * A basic cache interface. Implements some common functions for speed. 932810SN/A */ 942810SN/Aclass BaseCache : public MemObject 952810SN/A{ 9611375Sandreas.hansson@arm.com protected: 974628SN/A /** 984628SN/A * Indexes to enumerate the MSHR queues. 994628SN/A */ 1004628SN/A enum MSHRQueueIndex { 1014628SN/A MSHRQueue_MSHRs, 1024628SN/A MSHRQueue_WriteBuffer 1034628SN/A }; 1044628SN/A 1058737Skoansin.tan@gmail.com public: 1064628SN/A /** 1074628SN/A * Reasons for caches to be blocked. 1084628SN/A */ 1094628SN/A enum BlockedCause { 1104628SN/A Blocked_NoMSHRs = MSHRQueue_MSHRs, 1114628SN/A Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 1124628SN/A Blocked_NoTargets, 1134628SN/A NUM_BLOCKED_CAUSES 1144628SN/A }; 1154628SN/A 1168737Skoansin.tan@gmail.com protected: 1174628SN/A 1188856Sandreas.hansson@arm.com /** 1198856Sandreas.hansson@arm.com * A cache master port is used for the memory-side port of the 1208856Sandreas.hansson@arm.com * cache, and in addition to the basic timing port that only sends 1218856Sandreas.hansson@arm.com * response packets through a transmit list, it also offers the 1228856Sandreas.hansson@arm.com * ability to schedule and send request packets (requests & 12310942Sandreas.hansson@arm.com * writebacks). The send event is scheduled through schedSendEvent, 1248856Sandreas.hansson@arm.com * and the sendDeferredPacket of the timing port is modified to 1258856Sandreas.hansson@arm.com * consider both the transmit list and the requests from the MSHR. 1268856Sandreas.hansson@arm.com */ 1278922Swilliam.wang@arm.com class CacheMasterPort : public QueuedMasterPort 1282810SN/A { 1298856Sandreas.hansson@arm.com 1302844SN/A public: 1318856Sandreas.hansson@arm.com 1328856Sandreas.hansson@arm.com /** 1338856Sandreas.hansson@arm.com * Schedule a send of a request packet (from the MSHR). Note 13410713Sandreas.hansson@arm.com * that we could already have a retry outstanding. 1358856Sandreas.hansson@arm.com */ 13610942Sandreas.hansson@arm.com void schedSendEvent(Tick time) 1378856Sandreas.hansson@arm.com { 13810942Sandreas.hansson@arm.com DPRINTF(CachePort, "Scheduling send event at %llu\n", time); 13910713Sandreas.hansson@arm.com reqQueue.schedSendEvent(time); 1408856Sandreas.hansson@arm.com } 1418856Sandreas.hansson@arm.com 1423738SN/A protected: 1434458SN/A 1448856Sandreas.hansson@arm.com CacheMasterPort(const std::string &_name, BaseCache *_cache, 14510713Sandreas.hansson@arm.com ReqPacketQueue &_reqQueue, 14610713Sandreas.hansson@arm.com SnoopRespPacketQueue &_snoopRespQueue) : 14710713Sandreas.hansson@arm.com QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue) 1488914Sandreas.hansson@arm.com { } 1492810SN/A 1508856Sandreas.hansson@arm.com /** 1518856Sandreas.hansson@arm.com * Memory-side port always snoops. 1528856Sandreas.hansson@arm.com * 1538914Sandreas.hansson@arm.com * @return always true 1548856Sandreas.hansson@arm.com */ 1558922Swilliam.wang@arm.com virtual bool isSnooping() const { return true; } 1568856Sandreas.hansson@arm.com }; 1573013SN/A 1588856Sandreas.hansson@arm.com /** 15912724Snikos.nikoleris@arm.com * Override the default behaviour of sendDeferredPacket to enable 16012724Snikos.nikoleris@arm.com * the memory-side cache port to also send requests based on the 16112724Snikos.nikoleris@arm.com * current MSHR status. This queue has a pointer to our specific 16212724Snikos.nikoleris@arm.com * cache implementation and is used by the MemSidePort. 16312724Snikos.nikoleris@arm.com */ 16412724Snikos.nikoleris@arm.com class CacheReqPacketQueue : public ReqPacketQueue 16512724Snikos.nikoleris@arm.com { 16612724Snikos.nikoleris@arm.com 16712724Snikos.nikoleris@arm.com protected: 16812724Snikos.nikoleris@arm.com 16912724Snikos.nikoleris@arm.com BaseCache &cache; 17012724Snikos.nikoleris@arm.com SnoopRespPacketQueue &snoopRespQueue; 17112724Snikos.nikoleris@arm.com 17212724Snikos.nikoleris@arm.com public: 17312724Snikos.nikoleris@arm.com 17412724Snikos.nikoleris@arm.com CacheReqPacketQueue(BaseCache &cache, MasterPort &port, 17512724Snikos.nikoleris@arm.com SnoopRespPacketQueue &snoop_resp_queue, 17612724Snikos.nikoleris@arm.com const std::string &label) : 17712724Snikos.nikoleris@arm.com ReqPacketQueue(cache, port, label), cache(cache), 17812724Snikos.nikoleris@arm.com snoopRespQueue(snoop_resp_queue) { } 17912724Snikos.nikoleris@arm.com 18012724Snikos.nikoleris@arm.com /** 18112724Snikos.nikoleris@arm.com * Override the normal sendDeferredPacket and do not only 18212724Snikos.nikoleris@arm.com * consider the transmit list (used for responses), but also 18312724Snikos.nikoleris@arm.com * requests. 18412724Snikos.nikoleris@arm.com */ 18512724Snikos.nikoleris@arm.com virtual void sendDeferredPacket(); 18612724Snikos.nikoleris@arm.com 18712724Snikos.nikoleris@arm.com /** 18812724Snikos.nikoleris@arm.com * Check if there is a conflicting snoop response about to be 18912724Snikos.nikoleris@arm.com * send out, and if so simply stall any requests, and schedule 19012724Snikos.nikoleris@arm.com * a send event at the same time as the next snoop response is 19112724Snikos.nikoleris@arm.com * being sent out. 19212724Snikos.nikoleris@arm.com */ 19312724Snikos.nikoleris@arm.com bool checkConflictingSnoop(Addr addr) 19412724Snikos.nikoleris@arm.com { 19512724Snikos.nikoleris@arm.com if (snoopRespQueue.hasAddr(addr)) { 19612724Snikos.nikoleris@arm.com DPRINTF(CachePort, "Waiting for snoop response to be " 19712724Snikos.nikoleris@arm.com "sent\n"); 19812724Snikos.nikoleris@arm.com Tick when = snoopRespQueue.deferredPacketReadyTime(); 19912724Snikos.nikoleris@arm.com schedSendEvent(when); 20012724Snikos.nikoleris@arm.com return true; 20112724Snikos.nikoleris@arm.com } 20212724Snikos.nikoleris@arm.com return false; 20312724Snikos.nikoleris@arm.com } 20412724Snikos.nikoleris@arm.com }; 20512724Snikos.nikoleris@arm.com 20612724Snikos.nikoleris@arm.com 20712724Snikos.nikoleris@arm.com /** 20812724Snikos.nikoleris@arm.com * The memory-side port extends the base cache master port with 20912724Snikos.nikoleris@arm.com * access functions for functional, atomic and timing snoops. 21012724Snikos.nikoleris@arm.com */ 21112724Snikos.nikoleris@arm.com class MemSidePort : public CacheMasterPort 21212724Snikos.nikoleris@arm.com { 21312724Snikos.nikoleris@arm.com private: 21412724Snikos.nikoleris@arm.com 21512724Snikos.nikoleris@arm.com /** The cache-specific queue. */ 21612724Snikos.nikoleris@arm.com CacheReqPacketQueue _reqQueue; 21712724Snikos.nikoleris@arm.com 21812724Snikos.nikoleris@arm.com SnoopRespPacketQueue _snoopRespQueue; 21912724Snikos.nikoleris@arm.com 22012724Snikos.nikoleris@arm.com // a pointer to our specific cache implementation 22112724Snikos.nikoleris@arm.com BaseCache *cache; 22212724Snikos.nikoleris@arm.com 22312724Snikos.nikoleris@arm.com protected: 22412724Snikos.nikoleris@arm.com 22512724Snikos.nikoleris@arm.com virtual void recvTimingSnoopReq(PacketPtr pkt); 22612724Snikos.nikoleris@arm.com 22712724Snikos.nikoleris@arm.com virtual bool recvTimingResp(PacketPtr pkt); 22812724Snikos.nikoleris@arm.com 22912724Snikos.nikoleris@arm.com virtual Tick recvAtomicSnoop(PacketPtr pkt); 23012724Snikos.nikoleris@arm.com 23112724Snikos.nikoleris@arm.com virtual void recvFunctionalSnoop(PacketPtr pkt); 23212724Snikos.nikoleris@arm.com 23312724Snikos.nikoleris@arm.com public: 23412724Snikos.nikoleris@arm.com 23512724Snikos.nikoleris@arm.com MemSidePort(const std::string &_name, BaseCache *_cache, 23612724Snikos.nikoleris@arm.com const std::string &_label); 23712724Snikos.nikoleris@arm.com }; 23812724Snikos.nikoleris@arm.com 23912724Snikos.nikoleris@arm.com /** 2408856Sandreas.hansson@arm.com * A cache slave port is used for the CPU-side port of the cache, 2418856Sandreas.hansson@arm.com * and it is basically a simple timing port that uses a transmit 2428856Sandreas.hansson@arm.com * list for responses to the CPU (or connected master). In 2438856Sandreas.hansson@arm.com * addition, it has the functionality to block the port for 2448856Sandreas.hansson@arm.com * incoming requests. If blocked, the port will issue a retry once 2458856Sandreas.hansson@arm.com * unblocked. 2468856Sandreas.hansson@arm.com */ 2478922Swilliam.wang@arm.com class CacheSlavePort : public QueuedSlavePort 2488856Sandreas.hansson@arm.com { 2495314SN/A 2502811SN/A public: 2518856Sandreas.hansson@arm.com 2528856Sandreas.hansson@arm.com /** Do not accept any new requests. */ 2532810SN/A void setBlocked(); 2542810SN/A 2558856Sandreas.hansson@arm.com /** Return to normal operation and accept new requests. */ 2562810SN/A void clearBlocked(); 2572810SN/A 25810345SCurtis.Dunham@arm.com bool isBlocked() const { return blocked; } 25910345SCurtis.Dunham@arm.com 2608856Sandreas.hansson@arm.com protected: 2618856Sandreas.hansson@arm.com 2628856Sandreas.hansson@arm.com CacheSlavePort(const std::string &_name, BaseCache *_cache, 2638856Sandreas.hansson@arm.com const std::string &_label); 2643606SN/A 2658914Sandreas.hansson@arm.com /** A normal packet queue used to store responses. */ 26610713Sandreas.hansson@arm.com RespPacketQueue queue; 2678914Sandreas.hansson@arm.com 2682810SN/A bool blocked; 2692810SN/A 2702897SN/A bool mustSendRetry; 2712897SN/A 2728856Sandreas.hansson@arm.com private: 2734458SN/A 27410344Sandreas.hansson@arm.com void processSendRetry(); 27510344Sandreas.hansson@arm.com 27612084Sspwilson2@wisc.edu EventFunctionWrapper sendRetryEvent; 2778856Sandreas.hansson@arm.com 2782811SN/A }; 2792810SN/A 28012724Snikos.nikoleris@arm.com /** 28112724Snikos.nikoleris@arm.com * The CPU-side port extends the base cache slave port with access 28212724Snikos.nikoleris@arm.com * functions for functional, atomic and timing requests. 28312724Snikos.nikoleris@arm.com */ 28412724Snikos.nikoleris@arm.com class CpuSidePort : public CacheSlavePort 28512724Snikos.nikoleris@arm.com { 28612724Snikos.nikoleris@arm.com private: 28712724Snikos.nikoleris@arm.com 28812724Snikos.nikoleris@arm.com // a pointer to our specific cache implementation 28912724Snikos.nikoleris@arm.com BaseCache *cache; 29012724Snikos.nikoleris@arm.com 29112724Snikos.nikoleris@arm.com protected: 29212724Snikos.nikoleris@arm.com virtual bool recvTimingSnoopResp(PacketPtr pkt) override; 29312724Snikos.nikoleris@arm.com 29412724Snikos.nikoleris@arm.com virtual bool tryTiming(PacketPtr pkt) override; 29512724Snikos.nikoleris@arm.com 29612724Snikos.nikoleris@arm.com virtual bool recvTimingReq(PacketPtr pkt) override; 29712724Snikos.nikoleris@arm.com 29812724Snikos.nikoleris@arm.com virtual Tick recvAtomic(PacketPtr pkt) override; 29912724Snikos.nikoleris@arm.com 30012724Snikos.nikoleris@arm.com virtual void recvFunctional(PacketPtr pkt) override; 30112724Snikos.nikoleris@arm.com 30212724Snikos.nikoleris@arm.com virtual AddrRangeList getAddrRanges() const override; 30312724Snikos.nikoleris@arm.com 30412724Snikos.nikoleris@arm.com public: 30512724Snikos.nikoleris@arm.com 30612724Snikos.nikoleris@arm.com CpuSidePort(const std::string &_name, BaseCache *_cache, 30712724Snikos.nikoleris@arm.com const std::string &_label); 30812724Snikos.nikoleris@arm.com 30912724Snikos.nikoleris@arm.com }; 31012724Snikos.nikoleris@arm.com 31112724Snikos.nikoleris@arm.com CpuSidePort cpuSidePort; 31212724Snikos.nikoleris@arm.com MemSidePort memSidePort; 3133338SN/A 3144626SN/A protected: 3154626SN/A 3164626SN/A /** Miss status registers */ 3174626SN/A MSHRQueue mshrQueue; 3184626SN/A 3194626SN/A /** Write/writeback buffer */ 32011375Sandreas.hansson@arm.com WriteQueue writeBuffer; 3214626SN/A 32212724Snikos.nikoleris@arm.com /** Tag and data Storage */ 32312724Snikos.nikoleris@arm.com BaseTags *tags; 32412724Snikos.nikoleris@arm.com 32512724Snikos.nikoleris@arm.com /** Prefetcher */ 32612724Snikos.nikoleris@arm.com BasePrefetcher *prefetcher; 32712724Snikos.nikoleris@arm.com 32813416Sjavier.bueno@metempsy.com /** To probe when a cache hit occurs */ 32913416Sjavier.bueno@metempsy.com ProbePointArg<PacketPtr> *ppHit; 33013416Sjavier.bueno@metempsy.com 33113416Sjavier.bueno@metempsy.com /** To probe when a cache miss occurs */ 33213416Sjavier.bueno@metempsy.com ProbePointArg<PacketPtr> *ppMiss; 33312724Snikos.nikoleris@arm.com 33412724Snikos.nikoleris@arm.com /** 33513352Snikos.nikoleris@arm.com * The writeAllocator drive optimizations for streaming writes. 33613352Snikos.nikoleris@arm.com * It first determines whether a WriteReq MSHR should be delayed, 33713352Snikos.nikoleris@arm.com * thus ensuring that we wait longer in cases when we are write 33813352Snikos.nikoleris@arm.com * coalescing and allowing all the bytes of the line to be written 33913352Snikos.nikoleris@arm.com * before the MSHR packet is sent downstream. This works in unison 34013352Snikos.nikoleris@arm.com * with the tracking in the MSHR to check if the entire line is 34113352Snikos.nikoleris@arm.com * written. The write mode also affects the behaviour on filling 34213352Snikos.nikoleris@arm.com * any whole-line writes. Normally the cache allocates the line 34313352Snikos.nikoleris@arm.com * when receiving the InvalidateResp, but after seeing enough 34413352Snikos.nikoleris@arm.com * consecutive lines we switch to using the tempBlock, and thus 34513352Snikos.nikoleris@arm.com * end up not allocating the line, and instead turning the 34613352Snikos.nikoleris@arm.com * whole-line write into a writeback straight away. 34713352Snikos.nikoleris@arm.com */ 34813352Snikos.nikoleris@arm.com WriteAllocator * const writeAllocator; 34913352Snikos.nikoleris@arm.com 35013352Snikos.nikoleris@arm.com /** 35112724Snikos.nikoleris@arm.com * Temporary cache block for occasional transitory use. We use 35212724Snikos.nikoleris@arm.com * the tempBlock to fill when allocation fails (e.g., when there 35312724Snikos.nikoleris@arm.com * is an outstanding request that accesses the victim block) or 35412724Snikos.nikoleris@arm.com * when we want to avoid allocation (e.g., exclusive caches) 35512724Snikos.nikoleris@arm.com */ 35612730Sodanrc@yahoo.com.br TempCacheBlk *tempBlock; 35712724Snikos.nikoleris@arm.com 35812724Snikos.nikoleris@arm.com /** 35912724Snikos.nikoleris@arm.com * Upstream caches need this packet until true is returned, so 36012724Snikos.nikoleris@arm.com * hold it for deletion until a subsequent call 36112724Snikos.nikoleris@arm.com */ 36212724Snikos.nikoleris@arm.com std::unique_ptr<Packet> pendingDelete; 36312724Snikos.nikoleris@arm.com 36410693SMarco.Balboni@ARM.com /** 36511375Sandreas.hansson@arm.com * Mark a request as in service (sent downstream in the memory 36611375Sandreas.hansson@arm.com * system), effectively making this MSHR the ordering point. 36710693SMarco.Balboni@ARM.com */ 36811375Sandreas.hansson@arm.com void markInService(MSHR *mshr, bool pending_modified_resp) 3694628SN/A { 37011375Sandreas.hansson@arm.com bool wasFull = mshrQueue.isFull(); 37111375Sandreas.hansson@arm.com mshrQueue.markInService(mshr, pending_modified_resp); 37210764Sandreas.hansson@arm.com 37311375Sandreas.hansson@arm.com if (wasFull && !mshrQueue.isFull()) { 37411375Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 3754628SN/A } 3764628SN/A } 3774628SN/A 37811375Sandreas.hansson@arm.com void markInService(WriteQueueEntry *entry) 3794628SN/A { 38011375Sandreas.hansson@arm.com bool wasFull = writeBuffer.isFull(); 38111375Sandreas.hansson@arm.com writeBuffer.markInService(entry); 38211375Sandreas.hansson@arm.com 38311375Sandreas.hansson@arm.com if (wasFull && !writeBuffer.isFull()) { 38411375Sandreas.hansson@arm.com clearBlocked(Blocked_NoWBBuffers); 3854628SN/A } 3864628SN/A } 3874628SN/A 3889347SAndreas.Sandberg@arm.com /** 38912724Snikos.nikoleris@arm.com * Determine whether we should allocate on a fill or not. If this 39012724Snikos.nikoleris@arm.com * cache is mostly inclusive with regards to the upstream cache(s) 39112724Snikos.nikoleris@arm.com * we always allocate (for any non-forwarded and cacheable 39212724Snikos.nikoleris@arm.com * requests). In the case of a mostly exclusive cache, we allocate 39312724Snikos.nikoleris@arm.com * on fill if the packet did not come from a cache, thus if we: 39412724Snikos.nikoleris@arm.com * are dealing with a whole-line write (the latter behaves much 39512724Snikos.nikoleris@arm.com * like a writeback), the original target packet came from a 39612724Snikos.nikoleris@arm.com * non-caching source, or if we are performing a prefetch or LLSC. 39711197Sandreas.hansson@arm.com * 39812724Snikos.nikoleris@arm.com * @param cmd Command of the incoming requesting packet 39912724Snikos.nikoleris@arm.com * @return Whether we should allocate on the fill 40012724Snikos.nikoleris@arm.com */ 40112724Snikos.nikoleris@arm.com inline bool allocOnFill(MemCmd cmd) const 40212724Snikos.nikoleris@arm.com { 40312724Snikos.nikoleris@arm.com return clusivity == Enums::mostly_incl || 40412724Snikos.nikoleris@arm.com cmd == MemCmd::WriteLineReq || 40512724Snikos.nikoleris@arm.com cmd == MemCmd::ReadReq || 40612724Snikos.nikoleris@arm.com cmd == MemCmd::WriteReq || 40712724Snikos.nikoleris@arm.com cmd.isPrefetch() || 40812724Snikos.nikoleris@arm.com cmd.isLLSC(); 40912724Snikos.nikoleris@arm.com } 41012724Snikos.nikoleris@arm.com 41112724Snikos.nikoleris@arm.com /** 41212730Sodanrc@yahoo.com.br * Regenerate block address using tags. 41312730Sodanrc@yahoo.com.br * Block address regeneration depends on whether we're using a temporary 41412730Sodanrc@yahoo.com.br * block or not. 41512730Sodanrc@yahoo.com.br * 41612730Sodanrc@yahoo.com.br * @param blk The block to regenerate address. 41712730Sodanrc@yahoo.com.br * @return The block's address. 41812730Sodanrc@yahoo.com.br */ 41912730Sodanrc@yahoo.com.br Addr regenerateBlkAddr(CacheBlk* blk); 42012730Sodanrc@yahoo.com.br 42112730Sodanrc@yahoo.com.br /** 42213418Sodanrc@yahoo.com.br * Calculate access latency in ticks given a tag lookup latency, and 42313418Sodanrc@yahoo.com.br * whether access was a hit or miss. 42413418Sodanrc@yahoo.com.br * 42513418Sodanrc@yahoo.com.br * @param blk The cache block that was accessed. 42613418Sodanrc@yahoo.com.br * @param lookup_lat Latency of the respective tag lookup. 42713418Sodanrc@yahoo.com.br * @return The number of ticks that pass due to a block access. 42813418Sodanrc@yahoo.com.br */ 42913418Sodanrc@yahoo.com.br Cycles calculateAccessLatency(const CacheBlk* blk, 43013418Sodanrc@yahoo.com.br const Cycles lookup_lat) const; 43113418Sodanrc@yahoo.com.br 43213418Sodanrc@yahoo.com.br /** 43312724Snikos.nikoleris@arm.com * Does all the processing necessary to perform the provided request. 43412724Snikos.nikoleris@arm.com * @param pkt The memory request to perform. 43512724Snikos.nikoleris@arm.com * @param blk The cache block to be updated. 43612724Snikos.nikoleris@arm.com * @param lat The latency of the access. 43712724Snikos.nikoleris@arm.com * @param writebacks List for any writebacks that need to be performed. 43812724Snikos.nikoleris@arm.com * @return Boolean indicating whether the request was satisfied. 43912724Snikos.nikoleris@arm.com */ 44012724Snikos.nikoleris@arm.com virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 44112724Snikos.nikoleris@arm.com PacketList &writebacks); 44212724Snikos.nikoleris@arm.com 44312724Snikos.nikoleris@arm.com /* 44412724Snikos.nikoleris@arm.com * Handle a timing request that hit in the cache 44511197Sandreas.hansson@arm.com * 44612724Snikos.nikoleris@arm.com * @param ptk The request packet 44712724Snikos.nikoleris@arm.com * @param blk The referenced block 44812724Snikos.nikoleris@arm.com * @param request_time The tick at which the block lookup is compete 44911197Sandreas.hansson@arm.com */ 45012724Snikos.nikoleris@arm.com virtual void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, 45112724Snikos.nikoleris@arm.com Tick request_time); 45212724Snikos.nikoleris@arm.com 45312724Snikos.nikoleris@arm.com /* 45412724Snikos.nikoleris@arm.com * Handle a timing request that missed in the cache 45512724Snikos.nikoleris@arm.com * 45612724Snikos.nikoleris@arm.com * Implementation specific handling for different cache 45712724Snikos.nikoleris@arm.com * implementations 45812724Snikos.nikoleris@arm.com * 45912724Snikos.nikoleris@arm.com * @param ptk The request packet 46012724Snikos.nikoleris@arm.com * @param blk The referenced block 46112724Snikos.nikoleris@arm.com * @param forward_time The tick at which we can process dependent requests 46212724Snikos.nikoleris@arm.com * @param request_time The tick at which the block lookup is compete 46312724Snikos.nikoleris@arm.com */ 46412724Snikos.nikoleris@arm.com virtual void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, 46512724Snikos.nikoleris@arm.com Tick forward_time, 46612724Snikos.nikoleris@arm.com Tick request_time) = 0; 46712724Snikos.nikoleris@arm.com 46812724Snikos.nikoleris@arm.com /* 46912724Snikos.nikoleris@arm.com * Handle a timing request that missed in the cache 47012724Snikos.nikoleris@arm.com * 47112724Snikos.nikoleris@arm.com * Common functionality across different cache implementations 47212724Snikos.nikoleris@arm.com * 47312724Snikos.nikoleris@arm.com * @param ptk The request packet 47412724Snikos.nikoleris@arm.com * @param blk The referenced block 47512724Snikos.nikoleris@arm.com * @param mshr Any existing mshr for the referenced cache block 47612724Snikos.nikoleris@arm.com * @param forward_time The tick at which we can process dependent requests 47712724Snikos.nikoleris@arm.com * @param request_time The tick at which the block lookup is compete 47812724Snikos.nikoleris@arm.com */ 47912724Snikos.nikoleris@arm.com void handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk, 48012724Snikos.nikoleris@arm.com Tick forward_time, Tick request_time); 48112724Snikos.nikoleris@arm.com 48212724Snikos.nikoleris@arm.com /** 48312724Snikos.nikoleris@arm.com * Performs the access specified by the request. 48412724Snikos.nikoleris@arm.com * @param pkt The request to perform. 48512724Snikos.nikoleris@arm.com */ 48612724Snikos.nikoleris@arm.com virtual void recvTimingReq(PacketPtr pkt); 48712724Snikos.nikoleris@arm.com 48812724Snikos.nikoleris@arm.com /** 48912724Snikos.nikoleris@arm.com * Handling the special case of uncacheable write responses to 49012724Snikos.nikoleris@arm.com * make recvTimingResp less cluttered. 49112724Snikos.nikoleris@arm.com */ 49212724Snikos.nikoleris@arm.com void handleUncacheableWriteResp(PacketPtr pkt); 49312724Snikos.nikoleris@arm.com 49412724Snikos.nikoleris@arm.com /** 49512724Snikos.nikoleris@arm.com * Service non-deferred MSHR targets using the received response 49612724Snikos.nikoleris@arm.com * 49712724Snikos.nikoleris@arm.com * Iterates through the list of targets that can be serviced with 49813478Sodanrc@yahoo.com.br * the current response. 49912724Snikos.nikoleris@arm.com * 50012724Snikos.nikoleris@arm.com * @param mshr The MSHR that corresponds to the reponse 50112724Snikos.nikoleris@arm.com * @param pkt The response packet 50212724Snikos.nikoleris@arm.com * @param blk The reference block 50312724Snikos.nikoleris@arm.com */ 50412724Snikos.nikoleris@arm.com virtual void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, 50513478Sodanrc@yahoo.com.br CacheBlk *blk) = 0; 50612724Snikos.nikoleris@arm.com 50712724Snikos.nikoleris@arm.com /** 50812724Snikos.nikoleris@arm.com * Handles a response (cache line fill/write ack) from the bus. 50912724Snikos.nikoleris@arm.com * @param pkt The response packet 51012724Snikos.nikoleris@arm.com */ 51112724Snikos.nikoleris@arm.com virtual void recvTimingResp(PacketPtr pkt); 51212724Snikos.nikoleris@arm.com 51312724Snikos.nikoleris@arm.com /** 51412724Snikos.nikoleris@arm.com * Snoops bus transactions to maintain coherence. 51512724Snikos.nikoleris@arm.com * @param pkt The current bus transaction. 51612724Snikos.nikoleris@arm.com */ 51712724Snikos.nikoleris@arm.com virtual void recvTimingSnoopReq(PacketPtr pkt) = 0; 51812724Snikos.nikoleris@arm.com 51912724Snikos.nikoleris@arm.com /** 52012724Snikos.nikoleris@arm.com * Handle a snoop response. 52112724Snikos.nikoleris@arm.com * @param pkt Snoop response packet 52212724Snikos.nikoleris@arm.com */ 52312724Snikos.nikoleris@arm.com virtual void recvTimingSnoopResp(PacketPtr pkt) = 0; 52412724Snikos.nikoleris@arm.com 52512724Snikos.nikoleris@arm.com /** 52612724Snikos.nikoleris@arm.com * Handle a request in atomic mode that missed in this cache 52712724Snikos.nikoleris@arm.com * 52812724Snikos.nikoleris@arm.com * Creates a downstream request, sends it to the memory below and 52912724Snikos.nikoleris@arm.com * handles the response. As we are in atomic mode all operations 53012724Snikos.nikoleris@arm.com * are performed immediately. 53112724Snikos.nikoleris@arm.com * 53212724Snikos.nikoleris@arm.com * @param pkt The packet with the requests 53312724Snikos.nikoleris@arm.com * @param blk The referenced block 53412724Snikos.nikoleris@arm.com * @param writebacks A list with packets for any performed writebacks 53512724Snikos.nikoleris@arm.com * @return Cycles for handling the request 53612724Snikos.nikoleris@arm.com */ 53713017Snikos.nikoleris@arm.com virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, 53812724Snikos.nikoleris@arm.com PacketList &writebacks) = 0; 53912724Snikos.nikoleris@arm.com 54012724Snikos.nikoleris@arm.com /** 54112724Snikos.nikoleris@arm.com * Performs the access specified by the request. 54212724Snikos.nikoleris@arm.com * @param pkt The request to perform. 54312724Snikos.nikoleris@arm.com * @return The number of ticks required for the access. 54412724Snikos.nikoleris@arm.com */ 54512724Snikos.nikoleris@arm.com virtual Tick recvAtomic(PacketPtr pkt); 54612724Snikos.nikoleris@arm.com 54712724Snikos.nikoleris@arm.com /** 54812724Snikos.nikoleris@arm.com * Snoop for the provided request in the cache and return the estimated 54912724Snikos.nikoleris@arm.com * time taken. 55012724Snikos.nikoleris@arm.com * @param pkt The memory request to snoop 55112724Snikos.nikoleris@arm.com * @return The number of ticks required for the snoop. 55212724Snikos.nikoleris@arm.com */ 55312724Snikos.nikoleris@arm.com virtual Tick recvAtomicSnoop(PacketPtr pkt) = 0; 55412724Snikos.nikoleris@arm.com 55512724Snikos.nikoleris@arm.com /** 55612724Snikos.nikoleris@arm.com * Performs the access specified by the request. 55712724Snikos.nikoleris@arm.com * 55812724Snikos.nikoleris@arm.com * @param pkt The request to perform. 55912724Snikos.nikoleris@arm.com * @param fromCpuSide from the CPU side port or the memory side port 56012724Snikos.nikoleris@arm.com */ 56112724Snikos.nikoleris@arm.com virtual void functionalAccess(PacketPtr pkt, bool from_cpu_side); 56212724Snikos.nikoleris@arm.com 56312724Snikos.nikoleris@arm.com /** 56412724Snikos.nikoleris@arm.com * Handle doing the Compare and Swap function for SPARC. 56512724Snikos.nikoleris@arm.com */ 56612724Snikos.nikoleris@arm.com void cmpAndSwap(CacheBlk *blk, PacketPtr pkt); 56712724Snikos.nikoleris@arm.com 56812724Snikos.nikoleris@arm.com /** 56912724Snikos.nikoleris@arm.com * Return the next queue entry to service, either a pending miss 57012724Snikos.nikoleris@arm.com * from the MSHR queue, a buffered write from the write buffer, or 57112724Snikos.nikoleris@arm.com * something from the prefetcher. This function is responsible 57212724Snikos.nikoleris@arm.com * for prioritizing among those sources on the fly. 57312724Snikos.nikoleris@arm.com */ 57412724Snikos.nikoleris@arm.com QueueEntry* getNextQueueEntry(); 57512724Snikos.nikoleris@arm.com 57612724Snikos.nikoleris@arm.com /** 57712724Snikos.nikoleris@arm.com * Insert writebacks into the write buffer 57812724Snikos.nikoleris@arm.com */ 57912724Snikos.nikoleris@arm.com virtual void doWritebacks(PacketList& writebacks, Tick forward_time) = 0; 58012724Snikos.nikoleris@arm.com 58112724Snikos.nikoleris@arm.com /** 58212724Snikos.nikoleris@arm.com * Send writebacks down the memory hierarchy in atomic mode 58312724Snikos.nikoleris@arm.com */ 58412724Snikos.nikoleris@arm.com virtual void doWritebacksAtomic(PacketList& writebacks) = 0; 58512724Snikos.nikoleris@arm.com 58612724Snikos.nikoleris@arm.com /** 58712724Snikos.nikoleris@arm.com * Create an appropriate downstream bus request packet. 58812724Snikos.nikoleris@arm.com * 58912724Snikos.nikoleris@arm.com * Creates a new packet with the request to be send to the memory 59012724Snikos.nikoleris@arm.com * below, or nullptr if the current request in cpu_pkt should just 59112724Snikos.nikoleris@arm.com * be forwarded on. 59212724Snikos.nikoleris@arm.com * 59312724Snikos.nikoleris@arm.com * @param cpu_pkt The miss packet that needs to be satisfied. 59412724Snikos.nikoleris@arm.com * @param blk The referenced block, can be nullptr. 59512724Snikos.nikoleris@arm.com * @param needs_writable Indicates that the block must be writable 59612724Snikos.nikoleris@arm.com * even if the request in cpu_pkt doesn't indicate that. 59713350Snikos.nikoleris@arm.com * @param is_whole_line_write True if there are writes for the 59813350Snikos.nikoleris@arm.com * whole line 59912724Snikos.nikoleris@arm.com * @return A packet send to the memory below 60012724Snikos.nikoleris@arm.com */ 60112724Snikos.nikoleris@arm.com virtual PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 60213350Snikos.nikoleris@arm.com bool needs_writable, 60313350Snikos.nikoleris@arm.com bool is_whole_line_write) const = 0; 60412724Snikos.nikoleris@arm.com 60512724Snikos.nikoleris@arm.com /** 60612724Snikos.nikoleris@arm.com * Determine if clean lines should be written back or not. In 60712724Snikos.nikoleris@arm.com * cases where a downstream cache is mostly inclusive we likely 60812724Snikos.nikoleris@arm.com * want it to act as a victim cache also for lines that have not 60912724Snikos.nikoleris@arm.com * been modified. Hence, we cannot simply drop the line (or send a 61012724Snikos.nikoleris@arm.com * clean evict), but rather need to send the actual data. 61112724Snikos.nikoleris@arm.com */ 61212724Snikos.nikoleris@arm.com const bool writebackClean; 61312724Snikos.nikoleris@arm.com 61412724Snikos.nikoleris@arm.com /** 61512724Snikos.nikoleris@arm.com * Writebacks from the tempBlock, resulting on the response path 61612724Snikos.nikoleris@arm.com * in atomic mode, must happen after the call to recvAtomic has 61712724Snikos.nikoleris@arm.com * finished (for the right ordering of the packets). We therefore 61812724Snikos.nikoleris@arm.com * need to hold on to the packets, and have a method and an event 61912724Snikos.nikoleris@arm.com * to send them. 62012724Snikos.nikoleris@arm.com */ 62112724Snikos.nikoleris@arm.com PacketPtr tempBlockWriteback; 62212724Snikos.nikoleris@arm.com 62312724Snikos.nikoleris@arm.com /** 62412724Snikos.nikoleris@arm.com * Send the outstanding tempBlock writeback. To be called after 62512724Snikos.nikoleris@arm.com * recvAtomic finishes in cases where the block we filled is in 62612724Snikos.nikoleris@arm.com * fact the tempBlock, and now needs to be written back. 62712724Snikos.nikoleris@arm.com */ 62812724Snikos.nikoleris@arm.com void writebackTempBlockAtomic() { 62912724Snikos.nikoleris@arm.com assert(tempBlockWriteback != nullptr); 63012724Snikos.nikoleris@arm.com PacketList writebacks{tempBlockWriteback}; 63112724Snikos.nikoleris@arm.com doWritebacksAtomic(writebacks); 63212724Snikos.nikoleris@arm.com tempBlockWriteback = nullptr; 63312724Snikos.nikoleris@arm.com } 63412724Snikos.nikoleris@arm.com 63512724Snikos.nikoleris@arm.com /** 63612724Snikos.nikoleris@arm.com * An event to writeback the tempBlock after recvAtomic 63712724Snikos.nikoleris@arm.com * finishes. To avoid other calls to recvAtomic getting in 63812724Snikos.nikoleris@arm.com * between, we create this event with a higher priority. 63912724Snikos.nikoleris@arm.com */ 64012724Snikos.nikoleris@arm.com EventFunctionWrapper writebackTempBlockAtomicEvent; 64112724Snikos.nikoleris@arm.com 64212724Snikos.nikoleris@arm.com /** 64312724Snikos.nikoleris@arm.com * Perform any necessary updates to the block and perform any data 64412724Snikos.nikoleris@arm.com * exchange between the packet and the block. The flags of the 64512724Snikos.nikoleris@arm.com * packet are also set accordingly. 64612724Snikos.nikoleris@arm.com * 64712724Snikos.nikoleris@arm.com * @param pkt Request packet from upstream that hit a block 64812724Snikos.nikoleris@arm.com * @param blk Cache block that the packet hit 64912724Snikos.nikoleris@arm.com * @param deferred_response Whether this request originally missed 65012724Snikos.nikoleris@arm.com * @param pending_downgrade Whether the writable flag is to be removed 65112724Snikos.nikoleris@arm.com */ 65212724Snikos.nikoleris@arm.com virtual void satisfyRequest(PacketPtr pkt, CacheBlk *blk, 65312724Snikos.nikoleris@arm.com bool deferred_response = false, 65412724Snikos.nikoleris@arm.com bool pending_downgrade = false); 65512724Snikos.nikoleris@arm.com 65612724Snikos.nikoleris@arm.com /** 65712724Snikos.nikoleris@arm.com * Maintain the clusivity of this cache by potentially 65812724Snikos.nikoleris@arm.com * invalidating a block. This method works in conjunction with 65912724Snikos.nikoleris@arm.com * satisfyRequest, but is separate to allow us to handle all MSHR 66012724Snikos.nikoleris@arm.com * targets before potentially dropping a block. 66112724Snikos.nikoleris@arm.com * 66212724Snikos.nikoleris@arm.com * @param from_cache Whether we have dealt with a packet from a cache 66312724Snikos.nikoleris@arm.com * @param blk The block that should potentially be dropped 66412724Snikos.nikoleris@arm.com */ 66512724Snikos.nikoleris@arm.com void maintainClusivity(bool from_cache, CacheBlk *blk); 66612724Snikos.nikoleris@arm.com 66712724Snikos.nikoleris@arm.com /** 66812724Snikos.nikoleris@arm.com * Handle a fill operation caused by a received packet. 66912724Snikos.nikoleris@arm.com * 67012724Snikos.nikoleris@arm.com * Populates a cache block and handles all outstanding requests for the 67112724Snikos.nikoleris@arm.com * satisfied fill request. This version takes two memory requests. One 67212724Snikos.nikoleris@arm.com * contains the fill data, the other is an optional target to satisfy. 67312724Snikos.nikoleris@arm.com * Note that the reason we return a list of writebacks rather than 67412724Snikos.nikoleris@arm.com * inserting them directly in the write buffer is that this function 67512724Snikos.nikoleris@arm.com * is called by both atomic and timing-mode accesses, and in atomic 67612724Snikos.nikoleris@arm.com * mode we don't mess with the write buffer (we just perform the 67712724Snikos.nikoleris@arm.com * writebacks atomically once the original request is complete). 67812724Snikos.nikoleris@arm.com * 67912724Snikos.nikoleris@arm.com * @param pkt The memory request with the fill data. 68012724Snikos.nikoleris@arm.com * @param blk The cache block if it already exists. 68112724Snikos.nikoleris@arm.com * @param writebacks List for any writebacks that need to be performed. 68212724Snikos.nikoleris@arm.com * @param allocate Whether to allocate a block or use the temp block 68312724Snikos.nikoleris@arm.com * @return Pointer to the new cache block. 68412724Snikos.nikoleris@arm.com */ 68512724Snikos.nikoleris@arm.com CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk, 68612724Snikos.nikoleris@arm.com PacketList &writebacks, bool allocate); 68712724Snikos.nikoleris@arm.com 68812724Snikos.nikoleris@arm.com /** 68912724Snikos.nikoleris@arm.com * Allocate a new block and perform any necessary writebacks 69012724Snikos.nikoleris@arm.com * 69112724Snikos.nikoleris@arm.com * Find a victim block and if necessary prepare writebacks for any 69212724Snikos.nikoleris@arm.com * existing data. May return nullptr if there are no replaceable 69312754Sodanrc@yahoo.com.br * blocks. If a replaceable block is found, it inserts the new block in 69412754Sodanrc@yahoo.com.br * its place. The new block, however, is not set as valid yet. 69512724Snikos.nikoleris@arm.com * 69612754Sodanrc@yahoo.com.br * @param pkt Packet holding the address to update 69712724Snikos.nikoleris@arm.com * @param writebacks A list of writeback packets for the evicted blocks 69812724Snikos.nikoleris@arm.com * @return the allocated block 69912724Snikos.nikoleris@arm.com */ 70012754Sodanrc@yahoo.com.br CacheBlk *allocateBlock(const PacketPtr pkt, PacketList &writebacks); 70112724Snikos.nikoleris@arm.com /** 70212724Snikos.nikoleris@arm.com * Evict a cache block. 70312724Snikos.nikoleris@arm.com * 70412724Snikos.nikoleris@arm.com * Performs a writeback if necesssary and invalidates the block 70512724Snikos.nikoleris@arm.com * 70612724Snikos.nikoleris@arm.com * @param blk Block to invalidate 70712724Snikos.nikoleris@arm.com * @return A packet with the writeback, can be nullptr 70812724Snikos.nikoleris@arm.com */ 70912724Snikos.nikoleris@arm.com M5_NODISCARD virtual PacketPtr evictBlock(CacheBlk *blk) = 0; 71012724Snikos.nikoleris@arm.com 71112724Snikos.nikoleris@arm.com /** 71212724Snikos.nikoleris@arm.com * Evict a cache block. 71312724Snikos.nikoleris@arm.com * 71412724Snikos.nikoleris@arm.com * Performs a writeback if necesssary and invalidates the block 71512724Snikos.nikoleris@arm.com * 71612724Snikos.nikoleris@arm.com * @param blk Block to invalidate 71712724Snikos.nikoleris@arm.com * @param writebacks Return a list of packets with writebacks 71812724Snikos.nikoleris@arm.com */ 71913358Sodanrc@yahoo.com.br void evictBlock(CacheBlk *blk, PacketList &writebacks); 72012724Snikos.nikoleris@arm.com 72112724Snikos.nikoleris@arm.com /** 72212724Snikos.nikoleris@arm.com * Invalidate a cache block. 72312724Snikos.nikoleris@arm.com * 72412724Snikos.nikoleris@arm.com * @param blk Block to invalidate 72512724Snikos.nikoleris@arm.com */ 72612724Snikos.nikoleris@arm.com void invalidateBlock(CacheBlk *blk); 72712724Snikos.nikoleris@arm.com 72812724Snikos.nikoleris@arm.com /** 72912724Snikos.nikoleris@arm.com * Create a writeback request for the given block. 73012724Snikos.nikoleris@arm.com * 73112724Snikos.nikoleris@arm.com * @param blk The block to writeback. 73212724Snikos.nikoleris@arm.com * @return The writeback request for the block. 73312724Snikos.nikoleris@arm.com */ 73412724Snikos.nikoleris@arm.com PacketPtr writebackBlk(CacheBlk *blk); 73512724Snikos.nikoleris@arm.com 73612724Snikos.nikoleris@arm.com /** 73712724Snikos.nikoleris@arm.com * Create a writeclean request for the given block. 73812724Snikos.nikoleris@arm.com * 73912724Snikos.nikoleris@arm.com * Creates a request that writes the block to the cache below 74012724Snikos.nikoleris@arm.com * without evicting the block from the current cache. 74112724Snikos.nikoleris@arm.com * 74212724Snikos.nikoleris@arm.com * @param blk The block to write clean. 74312724Snikos.nikoleris@arm.com * @param dest The destination of the write clean operation. 74412724Snikos.nikoleris@arm.com * @param id Use the given packet id for the write clean operation. 74512724Snikos.nikoleris@arm.com * @return The generated write clean packet. 74612724Snikos.nikoleris@arm.com */ 74712724Snikos.nikoleris@arm.com PacketPtr writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id); 74811197Sandreas.hansson@arm.com 74911197Sandreas.hansson@arm.com /** 7509347SAndreas.Sandberg@arm.com * Write back dirty blocks in the cache using functional accesses. 7519347SAndreas.Sandberg@arm.com */ 75212724Snikos.nikoleris@arm.com virtual void memWriteback() override; 75312724Snikos.nikoleris@arm.com 7549347SAndreas.Sandberg@arm.com /** 7559347SAndreas.Sandberg@arm.com * Invalidates all blocks in the cache. 7569347SAndreas.Sandberg@arm.com * 7579347SAndreas.Sandberg@arm.com * @warn Dirty cache lines will not be written back to 7589347SAndreas.Sandberg@arm.com * memory. Make sure to call functionalWriteback() first if you 7599347SAndreas.Sandberg@arm.com * want the to write them to memory. 7609347SAndreas.Sandberg@arm.com */ 76112724Snikos.nikoleris@arm.com virtual void memInvalidate() override; 76212724Snikos.nikoleris@arm.com 7639347SAndreas.Sandberg@arm.com /** 7649347SAndreas.Sandberg@arm.com * Determine if there are any dirty blocks in the cache. 7659347SAndreas.Sandberg@arm.com * 76612724Snikos.nikoleris@arm.com * @return true if at least one block is dirty, false otherwise. 7679347SAndreas.Sandberg@arm.com */ 76812724Snikos.nikoleris@arm.com bool isDirty() const; 7699347SAndreas.Sandberg@arm.com 77010821Sandreas.hansson@arm.com /** 77110821Sandreas.hansson@arm.com * Determine if an address is in the ranges covered by this 77210821Sandreas.hansson@arm.com * cache. This is useful to filter snoops. 77310821Sandreas.hansson@arm.com * 77410821Sandreas.hansson@arm.com * @param addr Address to check against 77510821Sandreas.hansson@arm.com * 77610821Sandreas.hansson@arm.com * @return If the address in question is in range 77710821Sandreas.hansson@arm.com */ 77810821Sandreas.hansson@arm.com bool inRange(Addr addr) const; 77910821Sandreas.hansson@arm.com 78012724Snikos.nikoleris@arm.com /** 78112724Snikos.nikoleris@arm.com * Find next request ready time from among possible sources. 78212724Snikos.nikoleris@arm.com */ 78312724Snikos.nikoleris@arm.com Tick nextQueueReadyTime() const; 78412724Snikos.nikoleris@arm.com 7854626SN/A /** Block size of this cache */ 7866227Snate@binkert.org const unsigned blkSize; 7874626SN/A 7884630SN/A /** 78910693SMarco.Balboni@ARM.com * The latency of tag lookup of a cache. It occurs when there is 79010693SMarco.Balboni@ARM.com * an access to the cache. 7914630SN/A */ 79210693SMarco.Balboni@ARM.com const Cycles lookupLatency; 7939263Smrinmoy.ghosh@arm.com 7949263Smrinmoy.ghosh@arm.com /** 79511722Ssophiane.senni@gmail.com * The latency of data access of a cache. It occurs when there is 79611722Ssophiane.senni@gmail.com * an access to the cache. 79711722Ssophiane.senni@gmail.com */ 79811722Ssophiane.senni@gmail.com const Cycles dataLatency; 79911722Ssophiane.senni@gmail.com 80011722Ssophiane.senni@gmail.com /** 80110693SMarco.Balboni@ARM.com * This is the forward latency of the cache. It occurs when there 80210693SMarco.Balboni@ARM.com * is a cache miss and a request is forwarded downstream, in 80310693SMarco.Balboni@ARM.com * particular an outbound miss. 80410693SMarco.Balboni@ARM.com */ 80510693SMarco.Balboni@ARM.com const Cycles forwardLatency; 80610693SMarco.Balboni@ARM.com 80710693SMarco.Balboni@ARM.com /** The latency to fill a cache block */ 80810693SMarco.Balboni@ARM.com const Cycles fillLatency; 80910693SMarco.Balboni@ARM.com 81010693SMarco.Balboni@ARM.com /** 81110693SMarco.Balboni@ARM.com * The latency of sending reponse to its upper level cache/core on 81210693SMarco.Balboni@ARM.com * a linefill. The responseLatency parameter captures this 81310693SMarco.Balboni@ARM.com * latency. 8149263Smrinmoy.ghosh@arm.com */ 8159288Sandreas.hansson@arm.com const Cycles responseLatency; 8164630SN/A 81713418Sodanrc@yahoo.com.br /** 81813418Sodanrc@yahoo.com.br * Whether tags and data are accessed sequentially. 81913418Sodanrc@yahoo.com.br */ 82013418Sodanrc@yahoo.com.br const bool sequentialAccess; 82113418Sodanrc@yahoo.com.br 8224626SN/A /** The number of targets for each MSHR. */ 8234626SN/A const int numTarget; 8244626SN/A 8256122SSteve.Reinhardt@amd.com /** Do we forward snoops from mem side port through to cpu side port? */ 82611331Sandreas.hansson@arm.com bool forwardSnoops; 8274626SN/A 8282810SN/A /** 82912724Snikos.nikoleris@arm.com * Clusivity with respect to the upstream cache, determining if we 83012724Snikos.nikoleris@arm.com * fill into both this cache and the cache above on a miss. Note 83112724Snikos.nikoleris@arm.com * that we currently do not support strict clusivity policies. 83212724Snikos.nikoleris@arm.com */ 83312724Snikos.nikoleris@arm.com const Enums::Clusivity clusivity; 83412724Snikos.nikoleris@arm.com 83512724Snikos.nikoleris@arm.com /** 83610884Sandreas.hansson@arm.com * Is this cache read only, for example the instruction cache, or 83710884Sandreas.hansson@arm.com * table-walker cache. A cache that is read only should never see 83810884Sandreas.hansson@arm.com * any writes, and should never get any dirty data (and hence 83910884Sandreas.hansson@arm.com * never have to do any writebacks). 84010884Sandreas.hansson@arm.com */ 84110884Sandreas.hansson@arm.com const bool isReadOnly; 84210884Sandreas.hansson@arm.com 84310884Sandreas.hansson@arm.com /** 8442810SN/A * Bit vector of the blocking reasons for the access path. 8452810SN/A * @sa #BlockedCause 8462810SN/A */ 8472810SN/A uint8_t blocked; 8482810SN/A 8496122SSteve.Reinhardt@amd.com /** Increasing order number assigned to each incoming request. */ 8506122SSteve.Reinhardt@amd.com uint64_t order; 8516122SSteve.Reinhardt@amd.com 8522810SN/A /** Stores time the cache blocked for statistics. */ 8539288Sandreas.hansson@arm.com Cycles blockedCycle; 8542810SN/A 8554626SN/A /** Pointer to the MSHR that has no targets. */ 8564626SN/A MSHR *noTargetMSHR; 8572810SN/A 8582810SN/A /** The number of misses to trigger an exit event. */ 8592810SN/A Counter missCount; 8602810SN/A 8616122SSteve.Reinhardt@amd.com /** 8626122SSteve.Reinhardt@amd.com * The address range to which the cache responds on the CPU side. 8636122SSteve.Reinhardt@amd.com * Normally this is all possible memory addresses. */ 8649529Sandreas.hansson@arm.com const AddrRangeList addrRanges; 8656122SSteve.Reinhardt@amd.com 8668833Sdam.sunwoo@arm.com public: 8678833Sdam.sunwoo@arm.com /** System we are currently operating in. */ 8688833Sdam.sunwoo@arm.com System *system; 8696978SLisa.Hsu@amd.com 8702810SN/A // Statistics 8712810SN/A /** 8722810SN/A * @addtogroup CacheStatistics 8732810SN/A * @{ 8742810SN/A */ 8752810SN/A 87611483Snikos.nikoleris@arm.com /** Number of hits per thread for each type of command. 87711483Snikos.nikoleris@arm.com @sa Packet::Command */ 8785999Snate@binkert.org Stats::Vector hits[MemCmd::NUM_MEM_CMDS]; 8792810SN/A /** Number of hits for demand accesses. */ 8802810SN/A Stats::Formula demandHits; 8812810SN/A /** Number of hit for all accesses. */ 8822810SN/A Stats::Formula overallHits; 8832810SN/A 88411483Snikos.nikoleris@arm.com /** Number of misses per thread for each type of command. 88511483Snikos.nikoleris@arm.com @sa Packet::Command */ 8865999Snate@binkert.org Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; 8872810SN/A /** Number of misses for demand accesses. */ 8882810SN/A Stats::Formula demandMisses; 8892810SN/A /** Number of misses for all accesses. */ 8902810SN/A Stats::Formula overallMisses; 8912810SN/A 8922810SN/A /** 8932810SN/A * Total number of cycles per thread/command spent waiting for a miss. 8942810SN/A * Used to calculate the average miss latency. 8952810SN/A */ 8965999Snate@binkert.org Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS]; 8972810SN/A /** Total number of cycles spent waiting for demand misses. */ 8982810SN/A Stats::Formula demandMissLatency; 8992810SN/A /** Total number of cycles spent waiting for all misses. */ 9002810SN/A Stats::Formula overallMissLatency; 9012810SN/A 9022810SN/A /** The number of accesses per command and thread. */ 9034022SN/A Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 9042810SN/A /** The number of demand accesses. */ 9052810SN/A Stats::Formula demandAccesses; 9062810SN/A /** The number of overall accesses. */ 9072810SN/A Stats::Formula overallAccesses; 9082810SN/A 9092810SN/A /** The miss rate per command and thread. */ 9104022SN/A Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 9112810SN/A /** The miss rate of all demand accesses. */ 9122810SN/A Stats::Formula demandMissRate; 9132810SN/A /** The miss rate for all accesses. */ 9142810SN/A Stats::Formula overallMissRate; 9152810SN/A 9162810SN/A /** The average miss latency per command and thread. */ 9174022SN/A Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 9182810SN/A /** The average miss latency for demand misses. */ 9192810SN/A Stats::Formula demandAvgMissLatency; 9202810SN/A /** The average miss latency for all misses. */ 9212810SN/A Stats::Formula overallAvgMissLatency; 9222810SN/A 9232810SN/A /** The total number of cycles blocked for each blocked cause. */ 9245999Snate@binkert.org Stats::Vector blocked_cycles; 9252810SN/A /** The number of times this cache blocked for each blocked cause. */ 9265999Snate@binkert.org Stats::Vector blocked_causes; 9272810SN/A 9282810SN/A /** The average number of cycles blocked for each blocked cause. */ 9292810SN/A Stats::Formula avg_blocked; 9302810SN/A 93111436SRekai.GonzalezAlberquilla@arm.com /** The number of times a HW-prefetched block is evicted w/o reference. */ 93211436SRekai.GonzalezAlberquilla@arm.com Stats::Scalar unusedPrefetches; 93311436SRekai.GonzalezAlberquilla@arm.com 9344626SN/A /** Number of blocks written back per thread. */ 9355999Snate@binkert.org Stats::Vector writebacks; 9364626SN/A 9374626SN/A /** Number of misses that hit in the MSHRs per command and thread. */ 9385999Snate@binkert.org Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS]; 9394626SN/A /** Demand misses that hit in the MSHRs. */ 9404626SN/A Stats::Formula demandMshrHits; 9414626SN/A /** Total number of misses that hit in the MSHRs. */ 9424626SN/A Stats::Formula overallMshrHits; 9434626SN/A 9444626SN/A /** Number of misses that miss in the MSHRs, per command and thread. */ 9455999Snate@binkert.org Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS]; 9464626SN/A /** Demand misses that miss in the MSHRs. */ 9474626SN/A Stats::Formula demandMshrMisses; 9484626SN/A /** Total number of misses that miss in the MSHRs. */ 9494626SN/A Stats::Formula overallMshrMisses; 9504626SN/A 9514626SN/A /** Number of misses that miss in the MSHRs, per command and thread. */ 9525999Snate@binkert.org Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 9534626SN/A /** Total number of misses that miss in the MSHRs. */ 9544626SN/A Stats::Formula overallMshrUncacheable; 9554626SN/A 9564626SN/A /** Total cycle latency of each MSHR miss, per command and thread. */ 9575999Snate@binkert.org Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 9584626SN/A /** Total cycle latency of demand MSHR misses. */ 9594626SN/A Stats::Formula demandMshrMissLatency; 9604626SN/A /** Total cycle latency of overall MSHR misses. */ 9614626SN/A Stats::Formula overallMshrMissLatency; 9624626SN/A 9634626SN/A /** Total cycle latency of each MSHR miss, per command and thread. */ 9645999Snate@binkert.org Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 9654626SN/A /** Total cycle latency of overall MSHR misses. */ 9664626SN/A Stats::Formula overallMshrUncacheableLatency; 9674626SN/A 9687461Snate@binkert.org#if 0 9694626SN/A /** The total number of MSHR accesses per command and thread. */ 9704626SN/A Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 9714626SN/A /** The total number of demand MSHR accesses. */ 9724626SN/A Stats::Formula demandMshrAccesses; 9734626SN/A /** The total number of MSHR accesses. */ 9744626SN/A Stats::Formula overallMshrAccesses; 9757461Snate@binkert.org#endif 9764626SN/A 9774626SN/A /** The miss rate in the MSHRs pre command and thread. */ 9784626SN/A Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 9794626SN/A /** The demand miss rate in the MSHRs. */ 9804626SN/A Stats::Formula demandMshrMissRate; 9814626SN/A /** The overall miss rate in the MSHRs. */ 9824626SN/A Stats::Formula overallMshrMissRate; 9834626SN/A 9844626SN/A /** The average latency of an MSHR miss, per command and thread. */ 9854626SN/A Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 9864626SN/A /** The average latency of a demand MSHR miss. */ 9874626SN/A Stats::Formula demandAvgMshrMissLatency; 9884626SN/A /** The average overall latency of an MSHR miss. */ 9894626SN/A Stats::Formula overallAvgMshrMissLatency; 9904626SN/A 9914626SN/A /** The average latency of an MSHR miss, per command and thread. */ 9924626SN/A Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 9934626SN/A /** The average overall latency of an MSHR miss. */ 9944626SN/A Stats::Formula overallAvgMshrUncacheableLatency; 9954626SN/A 99612702Snikos.nikoleris@arm.com /** Number of replacements of valid blocks. */ 99712702Snikos.nikoleris@arm.com Stats::Scalar replacements; 99812702Snikos.nikoleris@arm.com 9992810SN/A /** 10002810SN/A * @} 10012810SN/A */ 10022810SN/A 10032810SN/A /** 10042810SN/A * Register stats for this object. 10052810SN/A */ 100612724Snikos.nikoleris@arm.com void regStats() override; 10072810SN/A 100813416Sjavier.bueno@metempsy.com /** Registers probes. */ 100913416Sjavier.bueno@metempsy.com void regProbePoints() override; 101013416Sjavier.bueno@metempsy.com 10112810SN/A public: 101211053Sandreas.hansson@arm.com BaseCache(const BaseCacheParams *p, unsigned blk_size); 101312724Snikos.nikoleris@arm.com ~BaseCache(); 10143606SN/A 101512724Snikos.nikoleris@arm.com void init() override; 10162858SN/A 101712724Snikos.nikoleris@arm.com BaseMasterPort &getMasterPort(const std::string &if_name, 101812724Snikos.nikoleris@arm.com PortID idx = InvalidPortID) override; 101912724Snikos.nikoleris@arm.com BaseSlavePort &getSlavePort(const std::string &if_name, 102012724Snikos.nikoleris@arm.com PortID idx = InvalidPortID) override; 10218922Swilliam.wang@arm.com 10222810SN/A /** 10232810SN/A * Query block size of a cache. 10242810SN/A * @return The block size 10252810SN/A */ 10266227Snate@binkert.org unsigned 10276227Snate@binkert.org getBlockSize() const 10282810SN/A { 10292810SN/A return blkSize; 10302810SN/A } 10312810SN/A 10328883SAli.Saidi@ARM.com const AddrRangeList &getAddrRanges() const { return addrRanges; } 10336122SSteve.Reinhardt@amd.com 103410942Sandreas.hansson@arm.com MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true) 10354628SN/A { 103611892Snikos.nikoleris@arm.com MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize, 103711375Sandreas.hansson@arm.com pkt, time, order++, 103811375Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 103911375Sandreas.hansson@arm.com 104011375Sandreas.hansson@arm.com if (mshrQueue.isFull()) { 104111375Sandreas.hansson@arm.com setBlocked((BlockedCause)MSHRQueue_MSHRs); 104211375Sandreas.hansson@arm.com } 104311375Sandreas.hansson@arm.com 104411375Sandreas.hansson@arm.com if (sched_send) { 104511375Sandreas.hansson@arm.com // schedule the send 104611375Sandreas.hansson@arm.com schedMemSideSendEvent(time); 104711375Sandreas.hansson@arm.com } 104811375Sandreas.hansson@arm.com 104911375Sandreas.hansson@arm.com return mshr; 10504628SN/A } 10514628SN/A 105211375Sandreas.hansson@arm.com void allocateWriteBuffer(PacketPtr pkt, Tick time) 10534628SN/A { 105411191Sandreas.hansson@arm.com // should only see writes or clean evicts here 105511191Sandreas.hansson@arm.com assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict); 105611191Sandreas.hansson@arm.com 105711892Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 105811375Sandreas.hansson@arm.com 105911375Sandreas.hansson@arm.com WriteQueueEntry *wq_entry = 106011375Sandreas.hansson@arm.com writeBuffer.findMatch(blk_addr, pkt->isSecure()); 106111375Sandreas.hansson@arm.com if (wq_entry && !wq_entry->inService) { 106211744Snikos.nikoleris@arm.com DPRINTF(Cache, "Potential to merge writeback %s", pkt->print()); 106311375Sandreas.hansson@arm.com } 106411375Sandreas.hansson@arm.com 106511375Sandreas.hansson@arm.com writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++); 106611375Sandreas.hansson@arm.com 106711375Sandreas.hansson@arm.com if (writeBuffer.isFull()) { 106811375Sandreas.hansson@arm.com setBlocked((BlockedCause)MSHRQueue_WriteBuffer); 106911375Sandreas.hansson@arm.com } 107011375Sandreas.hansson@arm.com 107111375Sandreas.hansson@arm.com // schedule the send 107211375Sandreas.hansson@arm.com schedMemSideSendEvent(time); 10734628SN/A } 10744628SN/A 10752810SN/A /** 10762810SN/A * Returns true if the cache is blocked for accesses. 10772810SN/A */ 10789529Sandreas.hansson@arm.com bool isBlocked() const 10792810SN/A { 10802810SN/A return blocked != 0; 10812810SN/A } 10822810SN/A 10832810SN/A /** 10842810SN/A * Marks the access path of the cache as blocked for the given cause. This 10852810SN/A * also sets the blocked flag in the slave interface. 10862810SN/A * @param cause The reason for the cache blocking. 10872810SN/A */ 10882810SN/A void setBlocked(BlockedCause cause) 10892810SN/A { 10902810SN/A uint8_t flag = 1 << cause; 10912810SN/A if (blocked == 0) { 10922810SN/A blocked_causes[cause]++; 10939288Sandreas.hansson@arm.com blockedCycle = curCycle(); 109412724Snikos.nikoleris@arm.com cpuSidePort.setBlocked(); 10952810SN/A } 10964630SN/A blocked |= flag; 10974630SN/A DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 10982810SN/A } 10992810SN/A 11002810SN/A /** 11012810SN/A * Marks the cache as unblocked for the given cause. This also clears the 11022810SN/A * blocked flags in the appropriate interfaces. 11032810SN/A * @param cause The newly unblocked cause. 11042810SN/A * @warning Calling this function can cause a blocked request on the bus to 11052810SN/A * access the cache. The cache must be in a state to handle that request. 11062810SN/A */ 11072810SN/A void clearBlocked(BlockedCause cause) 11082810SN/A { 11092810SN/A uint8_t flag = 1 << cause; 11104630SN/A blocked &= ~flag; 11114630SN/A DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 11124630SN/A if (blocked == 0) { 11139288Sandreas.hansson@arm.com blocked_cycles[cause] += curCycle() - blockedCycle; 111412724Snikos.nikoleris@arm.com cpuSidePort.clearBlocked(); 11152810SN/A } 11162810SN/A } 11172810SN/A 11182810SN/A /** 111910942Sandreas.hansson@arm.com * Schedule a send event for the memory-side port. If already 112010942Sandreas.hansson@arm.com * scheduled, this may reschedule the event at an earlier 112110942Sandreas.hansson@arm.com * time. When the specified time is reached, the port is free to 112210942Sandreas.hansson@arm.com * send either a response, a request, or a prefetch request. 112310942Sandreas.hansson@arm.com * 112410942Sandreas.hansson@arm.com * @param time The time when to attempt sending a packet. 11252810SN/A */ 112610942Sandreas.hansson@arm.com void schedMemSideSendEvent(Tick time) 11272810SN/A { 112812724Snikos.nikoleris@arm.com memSidePort.schedSendEvent(time); 11292811SN/A } 11303503SN/A 113112724Snikos.nikoleris@arm.com bool inCache(Addr addr, bool is_secure) const { 113212724Snikos.nikoleris@arm.com return tags->findBlock(addr, is_secure); 113312724Snikos.nikoleris@arm.com } 11344626SN/A 113513624Sjavier.bueno@metempsy.com bool hasBeenPrefetched(Addr addr, bool is_secure) const { 113613624Sjavier.bueno@metempsy.com CacheBlk *block = tags->findBlock(addr, is_secure); 113713624Sjavier.bueno@metempsy.com if (block) { 113813624Sjavier.bueno@metempsy.com return block->wasPrefetched(); 113913624Sjavier.bueno@metempsy.com } else { 114013624Sjavier.bueno@metempsy.com return false; 114113624Sjavier.bueno@metempsy.com } 114213624Sjavier.bueno@metempsy.com } 114313624Sjavier.bueno@metempsy.com 114412724Snikos.nikoleris@arm.com bool inMissQueue(Addr addr, bool is_secure) const { 114512724Snikos.nikoleris@arm.com return mshrQueue.findMatch(addr, is_secure); 114612724Snikos.nikoleris@arm.com } 11474626SN/A 11488833Sdam.sunwoo@arm.com void incMissCount(PacketPtr pkt) 11493503SN/A { 11508833Sdam.sunwoo@arm.com assert(pkt->req->masterId() < system->maxMasters()); 11518833Sdam.sunwoo@arm.com misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 115210020Smatt.horsnell@ARM.com pkt->req->incAccessDepth(); 11534626SN/A if (missCount) { 11544626SN/A --missCount; 11554626SN/A if (missCount == 0) 11564626SN/A exitSimLoop("A cache reached the maximum miss count"); 11573503SN/A } 11583503SN/A } 11598833Sdam.sunwoo@arm.com void incHitCount(PacketPtr pkt) 11606978SLisa.Hsu@amd.com { 11618833Sdam.sunwoo@arm.com assert(pkt->req->masterId() < system->maxMasters()); 11628833Sdam.sunwoo@arm.com hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 11636978SLisa.Hsu@amd.com 11646978SLisa.Hsu@amd.com } 11653503SN/A 116612724Snikos.nikoleris@arm.com /** 116713416Sjavier.bueno@metempsy.com * Checks if the cache is coalescing writes 116813416Sjavier.bueno@metempsy.com * 116913416Sjavier.bueno@metempsy.com * @return True if the cache is coalescing writes 117013416Sjavier.bueno@metempsy.com */ 117113416Sjavier.bueno@metempsy.com bool coalesce() const; 117213416Sjavier.bueno@metempsy.com 117313416Sjavier.bueno@metempsy.com 117413416Sjavier.bueno@metempsy.com /** 117512724Snikos.nikoleris@arm.com * Cache block visitor that writes back dirty cache blocks using 117612724Snikos.nikoleris@arm.com * functional writes. 117712724Snikos.nikoleris@arm.com */ 117812728Snikos.nikoleris@arm.com void writebackVisitor(CacheBlk &blk); 117912724Snikos.nikoleris@arm.com 118012724Snikos.nikoleris@arm.com /** 118112724Snikos.nikoleris@arm.com * Cache block visitor that invalidates all blocks in the cache. 118212724Snikos.nikoleris@arm.com * 118312724Snikos.nikoleris@arm.com * @warn Dirty cache lines will not be written back to memory. 118412724Snikos.nikoleris@arm.com */ 118512728Snikos.nikoleris@arm.com void invalidateVisitor(CacheBlk &blk); 118612724Snikos.nikoleris@arm.com 118712724Snikos.nikoleris@arm.com /** 118812724Snikos.nikoleris@arm.com * Take an MSHR, turn it into a suitable downstream packet, and 118912724Snikos.nikoleris@arm.com * send it out. This construct allows a queue entry to choose a suitable 119012724Snikos.nikoleris@arm.com * approach based on its type. 119112724Snikos.nikoleris@arm.com * 119212724Snikos.nikoleris@arm.com * @param mshr The MSHR to turn into a packet and send 119312724Snikos.nikoleris@arm.com * @return True if the port is waiting for a retry 119412724Snikos.nikoleris@arm.com */ 119512724Snikos.nikoleris@arm.com virtual bool sendMSHRQueuePacket(MSHR* mshr); 119612724Snikos.nikoleris@arm.com 119712724Snikos.nikoleris@arm.com /** 119812724Snikos.nikoleris@arm.com * Similar to sendMSHR, but for a write-queue entry 119912724Snikos.nikoleris@arm.com * instead. Create the packet, and send it, and if successful also 120012724Snikos.nikoleris@arm.com * mark the entry in service. 120112724Snikos.nikoleris@arm.com * 120212724Snikos.nikoleris@arm.com * @param wq_entry The write-queue entry to turn into a packet and send 120312724Snikos.nikoleris@arm.com * @return True if the port is waiting for a retry 120412724Snikos.nikoleris@arm.com */ 120512724Snikos.nikoleris@arm.com bool sendWriteQueuePacket(WriteQueueEntry* wq_entry); 120612724Snikos.nikoleris@arm.com 120712724Snikos.nikoleris@arm.com /** 120812724Snikos.nikoleris@arm.com * Serialize the state of the caches 120912724Snikos.nikoleris@arm.com * 121012724Snikos.nikoleris@arm.com * We currently don't support checkpointing cache state, so this panics. 121112724Snikos.nikoleris@arm.com */ 121212724Snikos.nikoleris@arm.com void serialize(CheckpointOut &cp) const override; 121312724Snikos.nikoleris@arm.com void unserialize(CheckpointIn &cp) override; 121412724Snikos.nikoleris@arm.com}; 121512724Snikos.nikoleris@arm.com 121613352Snikos.nikoleris@arm.com/** 121713352Snikos.nikoleris@arm.com * The write allocator inspects write packets and detects streaming 121813352Snikos.nikoleris@arm.com * patterns. The write allocator supports a single stream where writes 121913352Snikos.nikoleris@arm.com * are expected to access consecutive locations and keeps track of 122013352Snikos.nikoleris@arm.com * size of the area covered by the concecutive writes in byteCount. 122113352Snikos.nikoleris@arm.com * 122213352Snikos.nikoleris@arm.com * 1) When byteCount has surpassed the coallesceLimit the mode 122313352Snikos.nikoleris@arm.com * switches from ALLOCATE to COALESCE where writes should be delayed 122413352Snikos.nikoleris@arm.com * until the whole block is written at which point a single packet 122513352Snikos.nikoleris@arm.com * (whole line write) can service them. 122613352Snikos.nikoleris@arm.com * 122713352Snikos.nikoleris@arm.com * 2) When byteCount has also exceeded the noAllocateLimit (whole 122813352Snikos.nikoleris@arm.com * line) we switch to NO_ALLOCATE when writes should not allocate in 122913352Snikos.nikoleris@arm.com * the cache but rather send a whole line write to the memory below. 123013352Snikos.nikoleris@arm.com */ 123113352Snikos.nikoleris@arm.comclass WriteAllocator : public SimObject { 123213352Snikos.nikoleris@arm.com public: 123313352Snikos.nikoleris@arm.com WriteAllocator(const WriteAllocatorParams *p) : 123413352Snikos.nikoleris@arm.com SimObject(p), 123513352Snikos.nikoleris@arm.com coalesceLimit(p->coalesce_limit * p->block_size), 123613352Snikos.nikoleris@arm.com noAllocateLimit(p->no_allocate_limit * p->block_size), 123713352Snikos.nikoleris@arm.com delayThreshold(p->delay_threshold) 123813352Snikos.nikoleris@arm.com { 123913352Snikos.nikoleris@arm.com reset(); 124013352Snikos.nikoleris@arm.com } 124113352Snikos.nikoleris@arm.com 124213352Snikos.nikoleris@arm.com /** 124313352Snikos.nikoleris@arm.com * Should writes be coalesced? This is true if the mode is set to 124413352Snikos.nikoleris@arm.com * NO_ALLOCATE. 124513352Snikos.nikoleris@arm.com * 124613352Snikos.nikoleris@arm.com * @return return true if the cache should coalesce writes. 124713352Snikos.nikoleris@arm.com */ 124813352Snikos.nikoleris@arm.com bool coalesce() const { 124913352Snikos.nikoleris@arm.com return mode != WriteMode::ALLOCATE; 125013352Snikos.nikoleris@arm.com } 125113352Snikos.nikoleris@arm.com 125213352Snikos.nikoleris@arm.com /** 125313352Snikos.nikoleris@arm.com * Should writes allocate? 125413352Snikos.nikoleris@arm.com * 125513352Snikos.nikoleris@arm.com * @return return true if the cache should not allocate for writes. 125613352Snikos.nikoleris@arm.com */ 125713352Snikos.nikoleris@arm.com bool allocate() const { 125813352Snikos.nikoleris@arm.com return mode != WriteMode::NO_ALLOCATE; 125913352Snikos.nikoleris@arm.com } 126013352Snikos.nikoleris@arm.com 126113352Snikos.nikoleris@arm.com /** 126213352Snikos.nikoleris@arm.com * Reset the write allocator state, meaning that it allocates for 126313352Snikos.nikoleris@arm.com * writes and has not recorded any information about qualifying 126413352Snikos.nikoleris@arm.com * writes that might trigger a switch to coalescing and later no 126513352Snikos.nikoleris@arm.com * allocation. 126613352Snikos.nikoleris@arm.com */ 126713352Snikos.nikoleris@arm.com void reset() { 126813352Snikos.nikoleris@arm.com mode = WriteMode::ALLOCATE; 126913352Snikos.nikoleris@arm.com byteCount = 0; 127013352Snikos.nikoleris@arm.com nextAddr = 0; 127113352Snikos.nikoleris@arm.com } 127213352Snikos.nikoleris@arm.com 127313352Snikos.nikoleris@arm.com /** 127413352Snikos.nikoleris@arm.com * Access whether we need to delay the current write. 127513352Snikos.nikoleris@arm.com * 127613352Snikos.nikoleris@arm.com * @param blk_addr The block address the packet writes to 127713352Snikos.nikoleris@arm.com * @return true if the current packet should be delayed 127813352Snikos.nikoleris@arm.com */ 127913352Snikos.nikoleris@arm.com bool delay(Addr blk_addr) { 128013352Snikos.nikoleris@arm.com if (delayCtr[blk_addr] > 0) { 128113352Snikos.nikoleris@arm.com --delayCtr[blk_addr]; 128213352Snikos.nikoleris@arm.com return true; 128313352Snikos.nikoleris@arm.com } else { 128413352Snikos.nikoleris@arm.com return false; 128513352Snikos.nikoleris@arm.com } 128613352Snikos.nikoleris@arm.com } 128713352Snikos.nikoleris@arm.com 128813352Snikos.nikoleris@arm.com /** 128913352Snikos.nikoleris@arm.com * Clear delay counter for the input block 129013352Snikos.nikoleris@arm.com * 129113352Snikos.nikoleris@arm.com * @param blk_addr The accessed cache block 129213352Snikos.nikoleris@arm.com */ 129313352Snikos.nikoleris@arm.com void resetDelay(Addr blk_addr) { 129413352Snikos.nikoleris@arm.com delayCtr.erase(blk_addr); 129513352Snikos.nikoleris@arm.com } 129613352Snikos.nikoleris@arm.com 129713352Snikos.nikoleris@arm.com /** 129813352Snikos.nikoleris@arm.com * Update the write mode based on the current write 129913352Snikos.nikoleris@arm.com * packet. This method compares the packet's address with any 130013352Snikos.nikoleris@arm.com * current stream, and updates the tracking and the mode 130113352Snikos.nikoleris@arm.com * accordingly. 130213352Snikos.nikoleris@arm.com * 130313352Snikos.nikoleris@arm.com * @param write_addr Start address of the write request 130413352Snikos.nikoleris@arm.com * @param write_size Size of the write request 130513352Snikos.nikoleris@arm.com * @param blk_addr The block address that this packet writes to 130613352Snikos.nikoleris@arm.com */ 130713352Snikos.nikoleris@arm.com void updateMode(Addr write_addr, unsigned write_size, Addr blk_addr); 130813352Snikos.nikoleris@arm.com 130913352Snikos.nikoleris@arm.com private: 131013352Snikos.nikoleris@arm.com /** 131113352Snikos.nikoleris@arm.com * The current mode for write coalescing and allocation, either 131213352Snikos.nikoleris@arm.com * normal operation (ALLOCATE), write coalescing (COALESCE), or 131313352Snikos.nikoleris@arm.com * write coalescing without allocation (NO_ALLOCATE). 131413352Snikos.nikoleris@arm.com */ 131513352Snikos.nikoleris@arm.com enum class WriteMode : char { 131613352Snikos.nikoleris@arm.com ALLOCATE, 131713352Snikos.nikoleris@arm.com COALESCE, 131813352Snikos.nikoleris@arm.com NO_ALLOCATE, 131913352Snikos.nikoleris@arm.com }; 132013352Snikos.nikoleris@arm.com WriteMode mode; 132113352Snikos.nikoleris@arm.com 132213352Snikos.nikoleris@arm.com /** Address to match writes against to detect streams. */ 132313352Snikos.nikoleris@arm.com Addr nextAddr; 132413352Snikos.nikoleris@arm.com 132513352Snikos.nikoleris@arm.com /** 132613352Snikos.nikoleris@arm.com * Bytes written contiguously. Saturating once we no longer 132713352Snikos.nikoleris@arm.com * allocate. 132813352Snikos.nikoleris@arm.com */ 132913352Snikos.nikoleris@arm.com uint32_t byteCount; 133013352Snikos.nikoleris@arm.com 133113352Snikos.nikoleris@arm.com /** 133213352Snikos.nikoleris@arm.com * Limits for when to switch between the different write modes. 133313352Snikos.nikoleris@arm.com */ 133413352Snikos.nikoleris@arm.com const uint32_t coalesceLimit; 133513352Snikos.nikoleris@arm.com const uint32_t noAllocateLimit; 133613352Snikos.nikoleris@arm.com /** 133713352Snikos.nikoleris@arm.com * The number of times the allocator will delay an WriteReq MSHR. 133813352Snikos.nikoleris@arm.com */ 133913352Snikos.nikoleris@arm.com const uint32_t delayThreshold; 134013352Snikos.nikoleris@arm.com 134113352Snikos.nikoleris@arm.com /** 134213352Snikos.nikoleris@arm.com * Keep track of the number of times the allocator has delayed an 134313352Snikos.nikoleris@arm.com * WriteReq MSHR. 134413352Snikos.nikoleris@arm.com */ 134513352Snikos.nikoleris@arm.com std::unordered_map<Addr, Counter> delayCtr; 134613352Snikos.nikoleris@arm.com}; 134713352Snikos.nikoleris@arm.com 134811051Sandreas.hansson@arm.com#endif //__MEM_CACHE_BASE_HH__ 1349