base.hh revision 10693
19793Sakash.bagdia@arm.com/* 210249Sstephan.diestelhorst@arm.com * Copyright (c) 2012-2013, 2015 ARM Limited 310000Sclt67@cornell.edu * All rights reserved. 49793Sakash.bagdia@arm.com * 59793Sakash.bagdia@arm.com * The license below extends only to copyright in the software and shall 69793Sakash.bagdia@arm.com * not be construed as granting a license to any other intellectual 79793Sakash.bagdia@arm.com * property including but not limited to intellectual property relating 89793Sakash.bagdia@arm.com * to a hardware implementation of the functionality of the software 99793Sakash.bagdia@arm.com * licensed hereunder. You may use the software subject to the license 109793Sakash.bagdia@arm.com * terms below provided that you ensure that this notice is replicated 119793Sakash.bagdia@arm.com * unmodified and in its entirety in all distributions of the software, 129793Sakash.bagdia@arm.com * modified or unmodified, in source code or in binary form. 139793Sakash.bagdia@arm.com * 149793Sakash.bagdia@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 159793Sakash.bagdia@arm.com * All rights reserved. 169793Sakash.bagdia@arm.com * 179793Sakash.bagdia@arm.com * Redistribution and use in source and binary forms, with or without 189793Sakash.bagdia@arm.com * modification, are permitted provided that the following conditions are 199793Sakash.bagdia@arm.com * met: redistributions of source code must retain the above copyright 209793Sakash.bagdia@arm.com * notice, this list of conditions and the following disclaimer; 219793Sakash.bagdia@arm.com * redistributions in binary form must reproduce the above copyright 229793Sakash.bagdia@arm.com * notice, this list of conditions and the following disclaimer in the 239793Sakash.bagdia@arm.com * documentation and/or other materials provided with the distribution; 249793Sakash.bagdia@arm.com * neither the name of the copyright holders nor the names of its 259793Sakash.bagdia@arm.com * contributors may be used to endorse or promote products derived from 269793Sakash.bagdia@arm.com * this software without specific prior written permission. 279793Sakash.bagdia@arm.com * 289793Sakash.bagdia@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299793Sakash.bagdia@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309793Sakash.bagdia@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319793Sakash.bagdia@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329793Sakash.bagdia@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339793Sakash.bagdia@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349793Sakash.bagdia@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359793Sakash.bagdia@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369793Sakash.bagdia@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379793Sakash.bagdia@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389793Sakash.bagdia@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399793Sakash.bagdia@arm.com * 4010000Sclt67@cornell.edu * Authors: Erik Hallnor 4110249Sstephan.diestelhorst@arm.com * Steve Reinhardt 429793Sakash.bagdia@arm.com * Ron Dreslinski 439793Sakash.bagdia@arm.com */ 449793Sakash.bagdia@arm.com 459793Sakash.bagdia@arm.com/** 469793Sakash.bagdia@arm.com * @file 479793Sakash.bagdia@arm.com * Declares a basic cache interface BaseCache. 489793Sakash.bagdia@arm.com */ 499793Sakash.bagdia@arm.com 509793Sakash.bagdia@arm.com#ifndef __BASE_CACHE_HH__ 519793Sakash.bagdia@arm.com#define __BASE_CACHE_HH__ 5210000Sclt67@cornell.edu 5310000Sclt67@cornell.edu#include <algorithm> 549793Sakash.bagdia@arm.com#include <list> 559793Sakash.bagdia@arm.com#include <string> 569793Sakash.bagdia@arm.com#include <vector> 579793Sakash.bagdia@arm.com 589793Sakash.bagdia@arm.com#include "base/misc.hh" 599793Sakash.bagdia@arm.com#include "base/statistics.hh" 609793Sakash.bagdia@arm.com#include "base/trace.hh" 619793Sakash.bagdia@arm.com#include "base/types.hh" 629793Sakash.bagdia@arm.com#include "debug/Cache.hh" 639793Sakash.bagdia@arm.com#include "debug/CachePort.hh" 649827Sakash.bagdia@arm.com#include "mem/cache/mshr_queue.hh" 6510000Sclt67@cornell.edu#include "mem/mem_object.hh" 669793Sakash.bagdia@arm.com#include "mem/packet.hh" 679793Sakash.bagdia@arm.com#include "mem/qport.hh" 689793Sakash.bagdia@arm.com#include "mem/request.hh" 699827Sakash.bagdia@arm.com#include "params/BaseCache.hh" 709827Sakash.bagdia@arm.com#include "sim/eventq.hh" 719793Sakash.bagdia@arm.com#include "sim/full_system.hh" 729793Sakash.bagdia@arm.com#include "sim/sim_exit.hh" 739793Sakash.bagdia@arm.com#include "sim/system.hh" 749793Sakash.bagdia@arm.com 759793Sakash.bagdia@arm.comclass MSHR; 7610021Sandreas.hansson@arm.com/** 7710021Sandreas.hansson@arm.com * A basic cache interface. Implements some common functions for speed. 7810021Sandreas.hansson@arm.com */ 7910021Sandreas.hansson@arm.comclass BaseCache : public MemObject 8010021Sandreas.hansson@arm.com{ 8110021Sandreas.hansson@arm.com /** 8210021Sandreas.hansson@arm.com * Indexes to enumerate the MSHR queues. 839793Sakash.bagdia@arm.com */ 849793Sakash.bagdia@arm.com enum MSHRQueueIndex { 859793Sakash.bagdia@arm.com MSHRQueue_MSHRs, 869793Sakash.bagdia@arm.com MSHRQueue_WriteBuffer 879793Sakash.bagdia@arm.com }; 889793Sakash.bagdia@arm.com 899793Sakash.bagdia@arm.com public: 909793Sakash.bagdia@arm.com /** 919793Sakash.bagdia@arm.com * Reasons for caches to be blocked. 929827Sakash.bagdia@arm.com */ 939827Sakash.bagdia@arm.com enum BlockedCause { 949827Sakash.bagdia@arm.com Blocked_NoMSHRs = MSHRQueue_MSHRs, 959827Sakash.bagdia@arm.com Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 969827Sakash.bagdia@arm.com Blocked_NoTargets, 979793Sakash.bagdia@arm.com NUM_BLOCKED_CAUSES 989793Sakash.bagdia@arm.com }; 999793Sakash.bagdia@arm.com 1009793Sakash.bagdia@arm.com /** 1019793Sakash.bagdia@arm.com * Reasons for cache to request a bus. 10210000Sclt67@cornell.edu */ 10310000Sclt67@cornell.edu enum RequestCause { 10410000Sclt67@cornell.edu Request_MSHR = MSHRQueue_MSHRs, 10510000Sclt67@cornell.edu Request_WB = MSHRQueue_WriteBuffer, 10610000Sclt67@cornell.edu Request_PF, 10710000Sclt67@cornell.edu NUM_REQUEST_CAUSES 1089793Sakash.bagdia@arm.com }; 1099793Sakash.bagdia@arm.com 1109793Sakash.bagdia@arm.com protected: 1119827Sakash.bagdia@arm.com 1129827Sakash.bagdia@arm.com /** 1139827Sakash.bagdia@arm.com * A cache master port is used for the memory-side port of the 1149827Sakash.bagdia@arm.com * cache, and in addition to the basic timing port that only sends 1159793Sakash.bagdia@arm.com * response packets through a transmit list, it also offers the 11610021Sandreas.hansson@arm.com * ability to schedule and send request packets (requests & 11710021Sandreas.hansson@arm.com * writebacks). The send event is scheduled through requestBus, 1189793Sakash.bagdia@arm.com * and the sendDeferredPacket of the timing port is modified to 1199793Sakash.bagdia@arm.com * consider both the transmit list and the requests from the MSHR. 1209793Sakash.bagdia@arm.com */ 1219793Sakash.bagdia@arm.com class CacheMasterPort : public QueuedMasterPort 1229793Sakash.bagdia@arm.com { 12310249Sstephan.diestelhorst@arm.com 1249793Sakash.bagdia@arm.com public: 1259793Sakash.bagdia@arm.com 12610000Sclt67@cornell.edu /** 12710000Sclt67@cornell.edu * Schedule a send of a request packet (from the MSHR). Note 12810000Sclt67@cornell.edu * that we could already have a retry or a transmit list of 12910000Sclt67@cornell.edu * responses outstanding. 13010000Sclt67@cornell.edu */ 13110000Sclt67@cornell.edu void requestBus(RequestCause cause, Tick time) 13210000Sclt67@cornell.edu { 13310000Sclt67@cornell.edu DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); 13410000Sclt67@cornell.edu queue.schedSendEvent(time); 13510000Sclt67@cornell.edu } 13610000Sclt67@cornell.edu 13710000Sclt67@cornell.edu protected: 1389827Sakash.bagdia@arm.com 1399827Sakash.bagdia@arm.com CacheMasterPort(const std::string &_name, BaseCache *_cache, 1409827Sakash.bagdia@arm.com MasterPacketQueue &_queue) : 1419827Sakash.bagdia@arm.com QueuedMasterPort(_name, _cache, _queue) 1429827Sakash.bagdia@arm.com { } 1439827Sakash.bagdia@arm.com 1449827Sakash.bagdia@arm.com /** 1459827Sakash.bagdia@arm.com * Memory-side port always snoops. 1469827Sakash.bagdia@arm.com * 1479827Sakash.bagdia@arm.com * @return always true 1489827Sakash.bagdia@arm.com */ 1499827Sakash.bagdia@arm.com virtual bool isSnooping() const { return true; } 15010249Sstephan.diestelhorst@arm.com }; 1519827Sakash.bagdia@arm.com 1529827Sakash.bagdia@arm.com /** 1539793Sakash.bagdia@arm.com * A cache slave port is used for the CPU-side port of the cache, 1549793Sakash.bagdia@arm.com * and it is basically a simple timing port that uses a transmit 1559793Sakash.bagdia@arm.com * list for responses to the CPU (or connected master). In 1569793Sakash.bagdia@arm.com * addition, it has the functionality to block the port for 1579793Sakash.bagdia@arm.com * incoming requests. If blocked, the port will issue a retry once 1589793Sakash.bagdia@arm.com * unblocked. 1599793Sakash.bagdia@arm.com */ 1609793Sakash.bagdia@arm.com class CacheSlavePort : public QueuedSlavePort 1619793Sakash.bagdia@arm.com { 1629793Sakash.bagdia@arm.com 1639793Sakash.bagdia@arm.com public: 1649793Sakash.bagdia@arm.com 16510249Sstephan.diestelhorst@arm.com /** Do not accept any new requests. */ 16610249Sstephan.diestelhorst@arm.com void setBlocked(); 16710249Sstephan.diestelhorst@arm.com 16810249Sstephan.diestelhorst@arm.com /** Return to normal operation and accept new requests. */ 16910249Sstephan.diestelhorst@arm.com void clearBlocked(); 1709793Sakash.bagdia@arm.com 1719793Sakash.bagdia@arm.com bool isBlocked() const { return blocked; } 1729793Sakash.bagdia@arm.com 1739793Sakash.bagdia@arm.com protected: 1749793Sakash.bagdia@arm.com 1759793Sakash.bagdia@arm.com CacheSlavePort(const std::string &_name, BaseCache *_cache, 1769793Sakash.bagdia@arm.com const std::string &_label); 1779793Sakash.bagdia@arm.com 1789793Sakash.bagdia@arm.com /** A normal packet queue used to store responses. */ 1799793Sakash.bagdia@arm.com SlavePacketQueue queue; 1809793Sakash.bagdia@arm.com 1819793Sakash.bagdia@arm.com bool blocked; 1829793Sakash.bagdia@arm.com 1839793Sakash.bagdia@arm.com bool mustSendRetry; 1849793Sakash.bagdia@arm.com 18510000Sclt67@cornell.edu private: 18610000Sclt67@cornell.edu 18710249Sstephan.diestelhorst@arm.com void processSendRetry(); 18810249Sstephan.diestelhorst@arm.com 18910249Sstephan.diestelhorst@arm.com EventWrapper<CacheSlavePort, 19010249Sstephan.diestelhorst@arm.com &CacheSlavePort::processSendRetry> sendRetryEvent; 19110249Sstephan.diestelhorst@arm.com 19210249Sstephan.diestelhorst@arm.com }; 19310249Sstephan.diestelhorst@arm.com 19410249Sstephan.diestelhorst@arm.com CacheSlavePort *cpuSidePort; 19510249Sstephan.diestelhorst@arm.com CacheMasterPort *memSidePort; 19610249Sstephan.diestelhorst@arm.com 19710249Sstephan.diestelhorst@arm.com protected: 19810249Sstephan.diestelhorst@arm.com 19910249Sstephan.diestelhorst@arm.com /** Miss status registers */ 20010249Sstephan.diestelhorst@arm.com MSHRQueue mshrQueue; 20110249Sstephan.diestelhorst@arm.com 20210249Sstephan.diestelhorst@arm.com /** Write/writeback buffer */ 20310249Sstephan.diestelhorst@arm.com MSHRQueue writeBuffer; 20410249Sstephan.diestelhorst@arm.com 20510249Sstephan.diestelhorst@arm.com /** 20610249Sstephan.diestelhorst@arm.com * Allocate a buffer, passing the time indicating when schedule an 20710249Sstephan.diestelhorst@arm.com * event to the queued port to go and ask the MSHR and write queue 20810249Sstephan.diestelhorst@arm.com * if they have packets to send. 20910249Sstephan.diestelhorst@arm.com * 21010249Sstephan.diestelhorst@arm.com * allocateBufferInternal() function is called in: 21110249Sstephan.diestelhorst@arm.com * - MSHR allocateWriteBuffer (unchached write forwarded to WriteBuffer); 21210249Sstephan.diestelhorst@arm.com * - MSHR allocateMissBuffer (cacheable miss in MSHR queue); 21310249Sstephan.diestelhorst@arm.com * - MSHR allocateUncachedReadBuffer (unchached read allocated in MSHR 21410249Sstephan.diestelhorst@arm.com * queue) 21510249Sstephan.diestelhorst@arm.com */ 21610249Sstephan.diestelhorst@arm.com MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 21710249Sstephan.diestelhorst@arm.com PacketPtr pkt, Tick time, bool requestBus) 21810249Sstephan.diestelhorst@arm.com { 21910249Sstephan.diestelhorst@arm.com MSHR *mshr = mq->allocate(addr, size, pkt, time, order++); 22010249Sstephan.diestelhorst@arm.com 22110249Sstephan.diestelhorst@arm.com if (mq->isFull()) { 22210249Sstephan.diestelhorst@arm.com setBlocked((BlockedCause)mq->index); 22310249Sstephan.diestelhorst@arm.com } 22410249Sstephan.diestelhorst@arm.com 22510249Sstephan.diestelhorst@arm.com if (requestBus) { 22610249Sstephan.diestelhorst@arm.com requestMemSideBus((RequestCause)mq->index, time); 22710249Sstephan.diestelhorst@arm.com } 22810249Sstephan.diestelhorst@arm.com 22910249Sstephan.diestelhorst@arm.com return mshr; 23010249Sstephan.diestelhorst@arm.com } 23110249Sstephan.diestelhorst@arm.com 23210249Sstephan.diestelhorst@arm.com void markInServiceInternal(MSHR *mshr, bool pending_dirty_resp) 23310249Sstephan.diestelhorst@arm.com { 23410249Sstephan.diestelhorst@arm.com MSHRQueue *mq = mshr->queue; 23510249Sstephan.diestelhorst@arm.com bool wasFull = mq->isFull(); 23610249Sstephan.diestelhorst@arm.com mq->markInService(mshr, pending_dirty_resp); 23710249Sstephan.diestelhorst@arm.com if (wasFull && !mq->isFull()) { 23810249Sstephan.diestelhorst@arm.com clearBlocked((BlockedCause)mq->index); 23910249Sstephan.diestelhorst@arm.com } 24010395Sstephan.diestelhorst@arm.com } 24110905Sandreas.sandberg@arm.com 24210905Sandreas.sandberg@arm.com /** 24310905Sandreas.sandberg@arm.com * Write back dirty blocks in the cache using functional accesses. 24410249Sstephan.diestelhorst@arm.com */ 24510249Sstephan.diestelhorst@arm.com virtual void memWriteback() = 0; 24610249Sstephan.diestelhorst@arm.com /** 24710249Sstephan.diestelhorst@arm.com * Invalidates all blocks in the cache. 24810249Sstephan.diestelhorst@arm.com * 24910249Sstephan.diestelhorst@arm.com * @warn Dirty cache lines will not be written back to 25010249Sstephan.diestelhorst@arm.com * memory. Make sure to call functionalWriteback() first if you 25110249Sstephan.diestelhorst@arm.com * want the to write them to memory. 25210249Sstephan.diestelhorst@arm.com */ 25310249Sstephan.diestelhorst@arm.com virtual void memInvalidate() = 0; 25410249Sstephan.diestelhorst@arm.com /** 25510249Sstephan.diestelhorst@arm.com * Determine if there are any dirty blocks in the cache. 25610249Sstephan.diestelhorst@arm.com * 25710249Sstephan.diestelhorst@arm.com * \return true if at least one block is dirty, false otherwise. 25810249Sstephan.diestelhorst@arm.com */ 25910249Sstephan.diestelhorst@arm.com virtual bool isDirty() const = 0; 26010249Sstephan.diestelhorst@arm.com 26110249Sstephan.diestelhorst@arm.com /** Block size of this cache */ 26210249Sstephan.diestelhorst@arm.com const unsigned blkSize; 26310249Sstephan.diestelhorst@arm.com 26410249Sstephan.diestelhorst@arm.com /** 26510249Sstephan.diestelhorst@arm.com * The latency of tag lookup of a cache. It occurs when there is 26610249Sstephan.diestelhorst@arm.com * an access to the cache. 2679793Sakash.bagdia@arm.com */ 2689793Sakash.bagdia@arm.com const Cycles lookupLatency; 2699793Sakash.bagdia@arm.com 2709793Sakash.bagdia@arm.com /** 2719793Sakash.bagdia@arm.com * This is the forward latency of the cache. It occurs when there 2729793Sakash.bagdia@arm.com * is a cache miss and a request is forwarded downstream, in 2739793Sakash.bagdia@arm.com * particular an outbound miss. 2749793Sakash.bagdia@arm.com */ 2759793Sakash.bagdia@arm.com const Cycles forwardLatency; 2769793Sakash.bagdia@arm.com 2779793Sakash.bagdia@arm.com /** The latency to fill a cache block */ 2789793Sakash.bagdia@arm.com const Cycles fillLatency; 2799793Sakash.bagdia@arm.com 2809793Sakash.bagdia@arm.com /** 2819793Sakash.bagdia@arm.com * The latency of sending reponse to its upper level cache/core on 2829793Sakash.bagdia@arm.com * a linefill. The responseLatency parameter captures this 2839793Sakash.bagdia@arm.com * latency. 2849793Sakash.bagdia@arm.com */ 2859793Sakash.bagdia@arm.com const Cycles responseLatency; 2869793Sakash.bagdia@arm.com 2879793Sakash.bagdia@arm.com /** The number of targets for each MSHR. */ 2889793Sakash.bagdia@arm.com const int numTarget; 2899793Sakash.bagdia@arm.com 2909793Sakash.bagdia@arm.com /** Do we forward snoops from mem side port through to cpu side port? */ 2919793Sakash.bagdia@arm.com const bool forwardSnoops; 2929793Sakash.bagdia@arm.com 2939793Sakash.bagdia@arm.com /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should 2949793Sakash.bagdia@arm.com * never try to forward ownership and similar optimizations to the cpu 2959793Sakash.bagdia@arm.com * side */ 2969793Sakash.bagdia@arm.com const bool isTopLevel; 2979793Sakash.bagdia@arm.com 2989793Sakash.bagdia@arm.com /** 2999793Sakash.bagdia@arm.com * Bit vector of the blocking reasons for the access path. 3009793Sakash.bagdia@arm.com * @sa #BlockedCause 3019793Sakash.bagdia@arm.com */ 3029793Sakash.bagdia@arm.com uint8_t blocked; 3039793Sakash.bagdia@arm.com 3049793Sakash.bagdia@arm.com /** Increasing order number assigned to each incoming request. */ 305 uint64_t order; 306 307 /** Stores time the cache blocked for statistics. */ 308 Cycles blockedCycle; 309 310 /** Pointer to the MSHR that has no targets. */ 311 MSHR *noTargetMSHR; 312 313 /** The number of misses to trigger an exit event. */ 314 Counter missCount; 315 316 /** 317 * The address range to which the cache responds on the CPU side. 318 * Normally this is all possible memory addresses. */ 319 const AddrRangeList addrRanges; 320 321 public: 322 /** System we are currently operating in. */ 323 System *system; 324 325 // Statistics 326 /** 327 * @addtogroup CacheStatistics 328 * @{ 329 */ 330 331 /** Number of hits per thread for each type of command. @sa Packet::Command */ 332 Stats::Vector hits[MemCmd::NUM_MEM_CMDS]; 333 /** Number of hits for demand accesses. */ 334 Stats::Formula demandHits; 335 /** Number of hit for all accesses. */ 336 Stats::Formula overallHits; 337 338 /** Number of misses per thread for each type of command. @sa Packet::Command */ 339 Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; 340 /** Number of misses for demand accesses. */ 341 Stats::Formula demandMisses; 342 /** Number of misses for all accesses. */ 343 Stats::Formula overallMisses; 344 345 /** 346 * Total number of cycles per thread/command spent waiting for a miss. 347 * Used to calculate the average miss latency. 348 */ 349 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS]; 350 /** Total number of cycles spent waiting for demand misses. */ 351 Stats::Formula demandMissLatency; 352 /** Total number of cycles spent waiting for all misses. */ 353 Stats::Formula overallMissLatency; 354 355 /** The number of accesses per command and thread. */ 356 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 357 /** The number of demand accesses. */ 358 Stats::Formula demandAccesses; 359 /** The number of overall accesses. */ 360 Stats::Formula overallAccesses; 361 362 /** The miss rate per command and thread. */ 363 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 364 /** The miss rate of all demand accesses. */ 365 Stats::Formula demandMissRate; 366 /** The miss rate for all accesses. */ 367 Stats::Formula overallMissRate; 368 369 /** The average miss latency per command and thread. */ 370 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 371 /** The average miss latency for demand misses. */ 372 Stats::Formula demandAvgMissLatency; 373 /** The average miss latency for all misses. */ 374 Stats::Formula overallAvgMissLatency; 375 376 /** The total number of cycles blocked for each blocked cause. */ 377 Stats::Vector blocked_cycles; 378 /** The number of times this cache blocked for each blocked cause. */ 379 Stats::Vector blocked_causes; 380 381 /** The average number of cycles blocked for each blocked cause. */ 382 Stats::Formula avg_blocked; 383 384 /** The number of fast writes (WH64) performed. */ 385 Stats::Scalar fastWrites; 386 387 /** The number of cache copies performed. */ 388 Stats::Scalar cacheCopies; 389 390 /** Number of blocks written back per thread. */ 391 Stats::Vector writebacks; 392 393 /** Number of misses that hit in the MSHRs per command and thread. */ 394 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS]; 395 /** Demand misses that hit in the MSHRs. */ 396 Stats::Formula demandMshrHits; 397 /** Total number of misses that hit in the MSHRs. */ 398 Stats::Formula overallMshrHits; 399 400 /** Number of misses that miss in the MSHRs, per command and thread. */ 401 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS]; 402 /** Demand misses that miss in the MSHRs. */ 403 Stats::Formula demandMshrMisses; 404 /** Total number of misses that miss in the MSHRs. */ 405 Stats::Formula overallMshrMisses; 406 407 /** Number of misses that miss in the MSHRs, per command and thread. */ 408 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 409 /** Total number of misses that miss in the MSHRs. */ 410 Stats::Formula overallMshrUncacheable; 411 412 /** Total cycle latency of each MSHR miss, per command and thread. */ 413 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 414 /** Total cycle latency of demand MSHR misses. */ 415 Stats::Formula demandMshrMissLatency; 416 /** Total cycle latency of overall MSHR misses. */ 417 Stats::Formula overallMshrMissLatency; 418 419 /** Total cycle latency of each MSHR miss, per command and thread. */ 420 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 421 /** Total cycle latency of overall MSHR misses. */ 422 Stats::Formula overallMshrUncacheableLatency; 423 424#if 0 425 /** The total number of MSHR accesses per command and thread. */ 426 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 427 /** The total number of demand MSHR accesses. */ 428 Stats::Formula demandMshrAccesses; 429 /** The total number of MSHR accesses. */ 430 Stats::Formula overallMshrAccesses; 431#endif 432 433 /** The miss rate in the MSHRs pre command and thread. */ 434 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 435 /** The demand miss rate in the MSHRs. */ 436 Stats::Formula demandMshrMissRate; 437 /** The overall miss rate in the MSHRs. */ 438 Stats::Formula overallMshrMissRate; 439 440 /** The average latency of an MSHR miss, per command and thread. */ 441 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 442 /** The average latency of a demand MSHR miss. */ 443 Stats::Formula demandAvgMshrMissLatency; 444 /** The average overall latency of an MSHR miss. */ 445 Stats::Formula overallAvgMshrMissLatency; 446 447 /** The average latency of an MSHR miss, per command and thread. */ 448 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 449 /** The average overall latency of an MSHR miss. */ 450 Stats::Formula overallAvgMshrUncacheableLatency; 451 452 /** The number of times a thread hit its MSHR cap. */ 453 Stats::Vector mshr_cap_events; 454 /** The number of times software prefetches caused the MSHR to block. */ 455 Stats::Vector soft_prefetch_mshr_full; 456 457 Stats::Scalar mshr_no_allocate_misses; 458 459 /** 460 * @} 461 */ 462 463 /** 464 * Register stats for this object. 465 */ 466 virtual void regStats(); 467 468 public: 469 typedef BaseCacheParams Params; 470 BaseCache(const Params *p); 471 ~BaseCache() {} 472 473 virtual void init(); 474 475 virtual BaseMasterPort &getMasterPort(const std::string &if_name, 476 PortID idx = InvalidPortID); 477 virtual BaseSlavePort &getSlavePort(const std::string &if_name, 478 PortID idx = InvalidPortID); 479 480 /** 481 * Query block size of a cache. 482 * @return The block size 483 */ 484 unsigned 485 getBlockSize() const 486 { 487 return blkSize; 488 } 489 490 491 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); } 492 493 494 const AddrRangeList &getAddrRanges() const { return addrRanges; } 495 496 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 497 { 498 assert(!pkt->req->isUncacheable()); 499 return allocateBufferInternal(&mshrQueue, 500 blockAlign(pkt->getAddr()), blkSize, 501 pkt, time, requestBus); 502 } 503 504 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus) 505 { 506 assert(pkt->isWrite() && !pkt->isRead()); 507 return allocateBufferInternal(&writeBuffer, 508 pkt->getAddr(), pkt->getSize(), 509 pkt, time, requestBus); 510 } 511 512 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus) 513 { 514 assert(pkt->req->isUncacheable()); 515 assert(pkt->isRead()); 516 return allocateBufferInternal(&mshrQueue, 517 pkt->getAddr(), pkt->getSize(), 518 pkt, time, requestBus); 519 } 520 521 /** 522 * Returns true if the cache is blocked for accesses. 523 */ 524 bool isBlocked() const 525 { 526 return blocked != 0; 527 } 528 529 /** 530 * Marks the access path of the cache as blocked for the given cause. This 531 * also sets the blocked flag in the slave interface. 532 * @param cause The reason for the cache blocking. 533 */ 534 void setBlocked(BlockedCause cause) 535 { 536 uint8_t flag = 1 << cause; 537 if (blocked == 0) { 538 blocked_causes[cause]++; 539 blockedCycle = curCycle(); 540 cpuSidePort->setBlocked(); 541 } 542 blocked |= flag; 543 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 544 } 545 546 /** 547 * Marks the cache as unblocked for the given cause. This also clears the 548 * blocked flags in the appropriate interfaces. 549 * @param cause The newly unblocked cause. 550 * @warning Calling this function can cause a blocked request on the bus to 551 * access the cache. The cache must be in a state to handle that request. 552 */ 553 void clearBlocked(BlockedCause cause) 554 { 555 uint8_t flag = 1 << cause; 556 blocked &= ~flag; 557 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 558 if (blocked == 0) { 559 blocked_cycles[cause] += curCycle() - blockedCycle; 560 cpuSidePort->clearBlocked(); 561 } 562 } 563 564 /** 565 * Request the master bus for the given cause and time. 566 * @param cause The reason for the request. 567 * @param time The time to make the request. 568 */ 569 void requestMemSideBus(RequestCause cause, Tick time) 570 { 571 memSidePort->requestBus(cause, time); 572 } 573 574 /** 575 * Clear the master bus request for the given cause. 576 * @param cause The request reason to clear. 577 */ 578 void deassertMemSideBusRequest(RequestCause cause) 579 { 580 // Obsolete... we no longer signal bus requests explicitly so 581 // we can't deassert them. Leaving this in as a no-op since 582 // the prefetcher calls it to indicate that it no longer wants 583 // to request a prefetch, and someday that might be 584 // interesting again. 585 } 586 587 virtual unsigned int drain(DrainManager *dm); 588 589 virtual bool inCache(Addr addr, bool is_secure) const = 0; 590 591 virtual bool inMissQueue(Addr addr, bool is_secure) const = 0; 592 593 void incMissCount(PacketPtr pkt) 594 { 595 assert(pkt->req->masterId() < system->maxMasters()); 596 misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 597 pkt->req->incAccessDepth(); 598 if (missCount) { 599 --missCount; 600 if (missCount == 0) 601 exitSimLoop("A cache reached the maximum miss count"); 602 } 603 } 604 void incHitCount(PacketPtr pkt) 605 { 606 assert(pkt->req->masterId() < system->maxMasters()); 607 hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 608 609 } 610 611}; 612 613#endif //__BASE_CACHE_HH__ 614