base.cc revision 12730:6c2ea88bf129
1/*
2 * Copyright (c) 2012-2013, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 *          Nikos Nikoleris
42 */
43
44/**
45 * @file
46 * Definition of BaseCache functions.
47 */
48
49#include "mem/cache/base.hh"
50
51#include "base/compiler.hh"
52#include "base/logging.hh"
53#include "debug/Cache.hh"
54#include "debug/CachePort.hh"
55#include "debug/CacheVerbose.hh"
56#include "mem/cache/mshr.hh"
57#include "mem/cache/prefetch/base.hh"
58#include "mem/cache/queue_entry.hh"
59#include "params/BaseCache.hh"
60#include "sim/core.hh"
61
62class BaseMasterPort;
63class BaseSlavePort;
64
65using namespace std;
66
67BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
68                                          BaseCache *_cache,
69                                          const std::string &_label)
70    : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label),
71      blocked(false), mustSendRetry(false),
72      sendRetryEvent([this]{ processSendRetry(); }, _name)
73{
74}
75
76BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size)
77    : MemObject(p),
78      cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"),
79      memSidePort(p->name + ".mem_side", this, "MemSidePort"),
80      mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below
81      writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below
82      tags(p->tags),
83      prefetcher(p->prefetcher),
84      prefetchOnAccess(p->prefetch_on_access),
85      writebackClean(p->writeback_clean),
86      tempBlockWriteback(nullptr),
87      writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); },
88                                    name(), false,
89                                    EventBase::Delayed_Writeback_Pri),
90      blkSize(blk_size),
91      lookupLatency(p->tag_latency),
92      dataLatency(p->data_latency),
93      forwardLatency(p->tag_latency),
94      fillLatency(p->data_latency),
95      responseLatency(p->response_latency),
96      numTarget(p->tgts_per_mshr),
97      forwardSnoops(true),
98      clusivity(p->clusivity),
99      isReadOnly(p->is_read_only),
100      blocked(0),
101      order(0),
102      noTargetMSHR(nullptr),
103      missCount(p->max_miss_count),
104      addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
105      system(p->system)
106{
107    // the MSHR queue has no reserve entries as we check the MSHR
108    // queue on every single allocation, whereas the write queue has
109    // as many reserve entries as we have MSHRs, since every MSHR may
110    // eventually require a writeback, and we do not check the write
111    // buffer before committing to an MSHR
112
113    // forward snoops is overridden in init() once we can query
114    // whether the connected master is actually snooping or not
115
116    tempBlock = new TempCacheBlk();
117    tempBlock->data = new uint8_t[blkSize];
118
119    tags->setCache(this);
120    if (prefetcher)
121        prefetcher->setCache(this);
122}
123
124BaseCache::~BaseCache()
125{
126    delete [] tempBlock->data;
127    delete tempBlock;
128}
129
130void
131BaseCache::CacheSlavePort::setBlocked()
132{
133    assert(!blocked);
134    DPRINTF(CachePort, "Port is blocking new requests\n");
135    blocked = true;
136    // if we already scheduled a retry in this cycle, but it has not yet
137    // happened, cancel it
138    if (sendRetryEvent.scheduled()) {
139        owner.deschedule(sendRetryEvent);
140        DPRINTF(CachePort, "Port descheduled retry\n");
141        mustSendRetry = true;
142    }
143}
144
145void
146BaseCache::CacheSlavePort::clearBlocked()
147{
148    assert(blocked);
149    DPRINTF(CachePort, "Port is accepting new requests\n");
150    blocked = false;
151    if (mustSendRetry) {
152        // @TODO: need to find a better time (next cycle?)
153        owner.schedule(sendRetryEvent, curTick() + 1);
154    }
155}
156
157void
158BaseCache::CacheSlavePort::processSendRetry()
159{
160    DPRINTF(CachePort, "Port is sending retry\n");
161
162    // reset the flag and call retry
163    mustSendRetry = false;
164    sendRetryReq();
165}
166
167Addr
168BaseCache::regenerateBlkAddr(CacheBlk* blk)
169{
170    if (blk != tempBlock) {
171        return tags->regenerateBlkAddr(blk);
172    } else {
173        return tempBlock->getAddr();
174    }
175}
176
177void
178BaseCache::init()
179{
180    if (!cpuSidePort.isConnected() || !memSidePort.isConnected())
181        fatal("Cache ports on %s are not connected\n", name());
182    cpuSidePort.sendRangeChange();
183    forwardSnoops = cpuSidePort.isSnooping();
184}
185
186BaseMasterPort &
187BaseCache::getMasterPort(const std::string &if_name, PortID idx)
188{
189    if (if_name == "mem_side") {
190        return memSidePort;
191    }  else {
192        return MemObject::getMasterPort(if_name, idx);
193    }
194}
195
196BaseSlavePort &
197BaseCache::getSlavePort(const std::string &if_name, PortID idx)
198{
199    if (if_name == "cpu_side") {
200        return cpuSidePort;
201    } else {
202        return MemObject::getSlavePort(if_name, idx);
203    }
204}
205
206bool
207BaseCache::inRange(Addr addr) const
208{
209    for (const auto& r : addrRanges) {
210        if (r.contains(addr)) {
211            return true;
212       }
213    }
214    return false;
215}
216
217void
218BaseCache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time)
219{
220    if (pkt->needsResponse()) {
221        pkt->makeTimingResponse();
222        // @todo: Make someone pay for this
223        pkt->headerDelay = pkt->payloadDelay = 0;
224
225        // In this case we are considering request_time that takes
226        // into account the delay of the xbar, if any, and just
227        // lat, neglecting responseLatency, modelling hit latency
228        // just as lookupLatency or or the value of lat overriden
229        // by access(), that calls accessBlock() function.
230        cpuSidePort.schedTimingResp(pkt, request_time, true);
231    } else {
232        DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__,
233                pkt->print());
234
235        // queue the packet for deletion, as the sending cache is
236        // still relying on it; if the block is found in access(),
237        // CleanEvict and Writeback messages will be deleted
238        // here as well
239        pendingDelete.reset(pkt);
240    }
241}
242
243void
244BaseCache::handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk,
245                               Tick forward_time, Tick request_time)
246{
247    if (mshr) {
248        /// MSHR hit
249        /// @note writebacks will be checked in getNextMSHR()
250        /// for any conflicting requests to the same block
251
252        //@todo remove hw_pf here
253
254        // Coalesce unless it was a software prefetch (see above).
255        if (pkt) {
256            assert(!pkt->isWriteback());
257            // CleanEvicts corresponding to blocks which have
258            // outstanding requests in MSHRs are simply sunk here
259            if (pkt->cmd == MemCmd::CleanEvict) {
260                pendingDelete.reset(pkt);
261            } else if (pkt->cmd == MemCmd::WriteClean) {
262                // A WriteClean should never coalesce with any
263                // outstanding cache maintenance requests.
264
265                // We use forward_time here because there is an
266                // uncached memory write, forwarded to WriteBuffer.
267                allocateWriteBuffer(pkt, forward_time);
268            } else {
269                DPRINTF(Cache, "%s coalescing MSHR for %s\n", __func__,
270                        pkt->print());
271
272                assert(pkt->req->masterId() < system->maxMasters());
273                mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
274
275                // We use forward_time here because it is the same
276                // considering new targets. We have multiple
277                // requests for the same address here. It
278                // specifies the latency to allocate an internal
279                // buffer and to schedule an event to the queued
280                // port and also takes into account the additional
281                // delay of the xbar.
282                mshr->allocateTarget(pkt, forward_time, order++,
283                                     allocOnFill(pkt->cmd));
284                if (mshr->getNumTargets() == numTarget) {
285                    noTargetMSHR = mshr;
286                    setBlocked(Blocked_NoTargets);
287                    // need to be careful with this... if this mshr isn't
288                    // ready yet (i.e. time > curTick()), we don't want to
289                    // move it ahead of mshrs that are ready
290                    // mshrQueue.moveToFront(mshr);
291                }
292            }
293        }
294    } else {
295        // no MSHR
296        assert(pkt->req->masterId() < system->maxMasters());
297        mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
298
299        if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean) {
300            // We use forward_time here because there is an
301            // writeback or writeclean, forwarded to WriteBuffer.
302            allocateWriteBuffer(pkt, forward_time);
303        } else {
304            if (blk && blk->isValid()) {
305                // If we have a write miss to a valid block, we
306                // need to mark the block non-readable.  Otherwise
307                // if we allow reads while there's an outstanding
308                // write miss, the read could return stale data
309                // out of the cache block... a more aggressive
310                // system could detect the overlap (if any) and
311                // forward data out of the MSHRs, but we don't do
312                // that yet.  Note that we do need to leave the
313                // block valid so that it stays in the cache, in
314                // case we get an upgrade response (and hence no
315                // new data) when the write miss completes.
316                // As long as CPUs do proper store/load forwarding
317                // internally, and have a sufficiently weak memory
318                // model, this is probably unnecessary, but at some
319                // point it must have seemed like we needed it...
320                assert((pkt->needsWritable() && !blk->isWritable()) ||
321                       pkt->req->isCacheMaintenance());
322                blk->status &= ~BlkReadable;
323            }
324            // Here we are using forward_time, modelling the latency of
325            // a miss (outbound) just as forwardLatency, neglecting the
326            // lookupLatency component.
327            allocateMissBuffer(pkt, forward_time);
328        }
329    }
330}
331
332void
333BaseCache::recvTimingReq(PacketPtr pkt)
334{
335    // anything that is merely forwarded pays for the forward latency and
336    // the delay provided by the crossbar
337    Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
338
339    // We use lookupLatency here because it is used to specify the latency
340    // to access.
341    Cycles lat = lookupLatency;
342    CacheBlk *blk = nullptr;
343    bool satisfied = false;
344    {
345        PacketList writebacks;
346        // Note that lat is passed by reference here. The function
347        // access() calls accessBlock() which can modify lat value.
348        satisfied = access(pkt, blk, lat, writebacks);
349
350        // copy writebacks to write buffer here to ensure they logically
351        // proceed anything happening below
352        doWritebacks(writebacks, forward_time);
353    }
354
355    // Here we charge the headerDelay that takes into account the latencies
356    // of the bus, if the packet comes from it.
357    // The latency charged it is just lat that is the value of lookupLatency
358    // modified by access() function, or if not just lookupLatency.
359    // In case of a hit we are neglecting response latency.
360    // In case of a miss we are neglecting forward latency.
361    Tick request_time = clockEdge(lat) + pkt->headerDelay;
362    // Here we reset the timing of the packet.
363    pkt->headerDelay = pkt->payloadDelay = 0;
364    // track time of availability of next prefetch, if any
365    Tick next_pf_time = MaxTick;
366
367    if (satisfied) {
368        // if need to notify the prefetcher we have to do it before
369        // anything else as later handleTimingReqHit might turn the
370        // packet in a response
371        if (prefetcher &&
372            (prefetchOnAccess || (blk && blk->wasPrefetched()))) {
373            if (blk)
374                blk->status &= ~BlkHWPrefetched;
375
376            // Don't notify on SWPrefetch
377            if (!pkt->cmd.isSWPrefetch()) {
378                assert(!pkt->req->isCacheMaintenance());
379                next_pf_time = prefetcher->notify(pkt);
380            }
381        }
382
383        handleTimingReqHit(pkt, blk, request_time);
384    } else {
385        handleTimingReqMiss(pkt, blk, forward_time, request_time);
386
387        // We should call the prefetcher reguardless if the request is
388        // satisfied or not, reguardless if the request is in the MSHR
389        // or not. The request could be a ReadReq hit, but still not
390        // satisfied (potentially because of a prior write to the same
391        // cache line. So, even when not satisfied, there is an MSHR
392        // already allocated for this, we need to let the prefetcher
393        // know about the request
394
395        // Don't notify prefetcher on SWPrefetch or cache maintenance
396        // operations
397        if (prefetcher && pkt &&
398            !pkt->cmd.isSWPrefetch() &&
399            !pkt->req->isCacheMaintenance()) {
400            next_pf_time = prefetcher->notify(pkt);
401        }
402    }
403
404    if (next_pf_time != MaxTick) {
405        schedMemSideSendEvent(next_pf_time);
406    }
407}
408
409void
410BaseCache::handleUncacheableWriteResp(PacketPtr pkt)
411{
412    Tick completion_time = clockEdge(responseLatency) +
413        pkt->headerDelay + pkt->payloadDelay;
414
415    // Reset the bus additional time as it is now accounted for
416    pkt->headerDelay = pkt->payloadDelay = 0;
417
418    cpuSidePort.schedTimingResp(pkt, completion_time, true);
419}
420
421void
422BaseCache::recvTimingResp(PacketPtr pkt)
423{
424    assert(pkt->isResponse());
425
426    // all header delay should be paid for by the crossbar, unless
427    // this is a prefetch response from above
428    panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp,
429             "%s saw a non-zero packet delay\n", name());
430
431    const bool is_error = pkt->isError();
432
433    if (is_error) {
434        DPRINTF(Cache, "%s: Cache received %s with error\n", __func__,
435                pkt->print());
436    }
437
438    DPRINTF(Cache, "%s: Handling response %s\n", __func__,
439            pkt->print());
440
441    // if this is a write, we should be looking at an uncacheable
442    // write
443    if (pkt->isWrite()) {
444        assert(pkt->req->isUncacheable());
445        handleUncacheableWriteResp(pkt);
446        return;
447    }
448
449    // we have dealt with any (uncacheable) writes above, from here on
450    // we know we are dealing with an MSHR due to a miss or a prefetch
451    MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState());
452    assert(mshr);
453
454    if (mshr == noTargetMSHR) {
455        // we always clear at least one target
456        clearBlocked(Blocked_NoTargets);
457        noTargetMSHR = nullptr;
458    }
459
460    // Initial target is used just for stats
461    MSHR::Target *initial_tgt = mshr->getTarget();
462    int stats_cmd_idx = initial_tgt->pkt->cmdToIndex();
463    Tick miss_latency = curTick() - initial_tgt->recvTime;
464
465    if (pkt->req->isUncacheable()) {
466        assert(pkt->req->masterId() < system->maxMasters());
467        mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] +=
468            miss_latency;
469    } else {
470        assert(pkt->req->masterId() < system->maxMasters());
471        mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] +=
472            miss_latency;
473    }
474
475    PacketList writebacks;
476
477    bool is_fill = !mshr->isForward &&
478        (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp);
479
480    CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure());
481
482    if (is_fill && !is_error) {
483        DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n",
484                pkt->getAddr());
485
486        blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill());
487        assert(blk != nullptr);
488    }
489
490    if (blk && blk->isValid() && pkt->isClean() && !pkt->isInvalidate()) {
491        // The block was marked not readable while there was a pending
492        // cache maintenance operation, restore its flag.
493        blk->status |= BlkReadable;
494    }
495
496    if (blk && blk->isWritable() && !pkt->req->isCacheInvalidate()) {
497        // If at this point the referenced block is writable and the
498        // response is not a cache invalidate, we promote targets that
499        // were deferred as we couldn't guarrantee a writable copy
500        mshr->promoteWritable();
501    }
502
503    serviceMSHRTargets(mshr, pkt, blk, writebacks);
504
505    if (mshr->promoteDeferredTargets()) {
506        // avoid later read getting stale data while write miss is
507        // outstanding.. see comment in timingAccess()
508        if (blk) {
509            blk->status &= ~BlkReadable;
510        }
511        mshrQueue.markPending(mshr);
512        schedMemSideSendEvent(clockEdge() + pkt->payloadDelay);
513    } else {
514        // while we deallocate an mshr from the queue we still have to
515        // check the isFull condition before and after as we might
516        // have been using the reserved entries already
517        const bool was_full = mshrQueue.isFull();
518        mshrQueue.deallocate(mshr);
519        if (was_full && !mshrQueue.isFull()) {
520            clearBlocked(Blocked_NoMSHRs);
521        }
522
523        // Request the bus for a prefetch if this deallocation freed enough
524        // MSHRs for a prefetch to take place
525        if (prefetcher && mshrQueue.canPrefetch()) {
526            Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(),
527                                         clockEdge());
528            if (next_pf_time != MaxTick)
529                schedMemSideSendEvent(next_pf_time);
530        }
531    }
532
533    // if we used temp block, check to see if its valid and then clear it out
534    if (blk == tempBlock && tempBlock->isValid()) {
535        evictBlock(blk, writebacks);
536    }
537
538    const Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
539    // copy writebacks to write buffer
540    doWritebacks(writebacks, forward_time);
541
542    DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print());
543    delete pkt;
544}
545
546
547Tick
548BaseCache::recvAtomic(PacketPtr pkt)
549{
550    // We are in atomic mode so we pay just for lookupLatency here.
551    Cycles lat = lookupLatency;
552
553    // follow the same flow as in recvTimingReq, and check if a cache
554    // above us is responding
555    if (pkt->cacheResponding() && !pkt->isClean()) {
556        assert(!pkt->req->isCacheInvalidate());
557        DPRINTF(Cache, "Cache above responding to %s: not responding\n",
558                pkt->print());
559
560        // if a cache is responding, and it had the line in Owned
561        // rather than Modified state, we need to invalidate any
562        // copies that are not on the same path to memory
563        assert(pkt->needsWritable() && !pkt->responderHadWritable());
564        lat += ticksToCycles(memSidePort.sendAtomic(pkt));
565
566        return lat * clockPeriod();
567    }
568
569    // should assert here that there are no outstanding MSHRs or
570    // writebacks... that would mean that someone used an atomic
571    // access in timing mode
572
573    CacheBlk *blk = nullptr;
574    PacketList writebacks;
575    bool satisfied = access(pkt, blk, lat, writebacks);
576
577    if (pkt->isClean() && blk && blk->isDirty()) {
578        // A cache clean opearation is looking for a dirty
579        // block. If a dirty block is encountered a WriteClean
580        // will update any copies to the path to the memory
581        // until the point of reference.
582        DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n",
583                __func__, pkt->print(), blk->print());
584        PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id);
585        writebacks.push_back(wb_pkt);
586        pkt->setSatisfied();
587    }
588
589    // handle writebacks resulting from the access here to ensure they
590    // logically proceed anything happening below
591    doWritebacksAtomic(writebacks);
592    assert(writebacks.empty());
593
594    if (!satisfied) {
595        lat += handleAtomicReqMiss(pkt, blk, writebacks);
596    }
597
598    // Note that we don't invoke the prefetcher at all in atomic mode.
599    // It's not clear how to do it properly, particularly for
600    // prefetchers that aggressively generate prefetch candidates and
601    // rely on bandwidth contention to throttle them; these will tend
602    // to pollute the cache in atomic mode since there is no bandwidth
603    // contention.  If we ever do want to enable prefetching in atomic
604    // mode, though, this is the place to do it... see timingAccess()
605    // for an example (though we'd want to issue the prefetch(es)
606    // immediately rather than calling requestMemSideBus() as we do
607    // there).
608
609    // do any writebacks resulting from the response handling
610    doWritebacksAtomic(writebacks);
611
612    // if we used temp block, check to see if its valid and if so
613    // clear it out, but only do so after the call to recvAtomic is
614    // finished so that any downstream observers (such as a snoop
615    // filter), first see the fill, and only then see the eviction
616    if (blk == tempBlock && tempBlock->isValid()) {
617        // the atomic CPU calls recvAtomic for fetch and load/store
618        // sequentuially, and we may already have a tempBlock
619        // writeback from the fetch that we have not yet sent
620        if (tempBlockWriteback) {
621            // if that is the case, write the prevoius one back, and
622            // do not schedule any new event
623            writebackTempBlockAtomic();
624        } else {
625            // the writeback/clean eviction happens after the call to
626            // recvAtomic has finished (but before any successive
627            // calls), so that the response handling from the fill is
628            // allowed to happen first
629            schedule(writebackTempBlockAtomicEvent, curTick());
630        }
631
632        tempBlockWriteback = evictBlock(blk);
633    }
634
635    if (pkt->needsResponse()) {
636        pkt->makeAtomicResponse();
637    }
638
639    return lat * clockPeriod();
640}
641
642void
643BaseCache::functionalAccess(PacketPtr pkt, bool from_cpu_side)
644{
645    Addr blk_addr = pkt->getBlockAddr(blkSize);
646    bool is_secure = pkt->isSecure();
647    CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure);
648    MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure);
649
650    pkt->pushLabel(name());
651
652    CacheBlkPrintWrapper cbpw(blk);
653
654    // Note that just because an L2/L3 has valid data doesn't mean an
655    // L1 doesn't have a more up-to-date modified copy that still
656    // needs to be found.  As a result we always update the request if
657    // we have it, but only declare it satisfied if we are the owner.
658
659    // see if we have data at all (owned or otherwise)
660    bool have_data = blk && blk->isValid()
661        && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize,
662                                blk->data);
663
664    // data we have is dirty if marked as such or if we have an
665    // in-service MSHR that is pending a modified line
666    bool have_dirty =
667        have_data && (blk->isDirty() ||
668                      (mshr && mshr->inService && mshr->isPendingModified()));
669
670    bool done = have_dirty ||
671        cpuSidePort.checkFunctional(pkt) ||
672        mshrQueue.checkFunctional(pkt, blk_addr) ||
673        writeBuffer.checkFunctional(pkt, blk_addr) ||
674        memSidePort.checkFunctional(pkt);
675
676    DPRINTF(CacheVerbose, "%s: %s %s%s%s\n", __func__,  pkt->print(),
677            (blk && blk->isValid()) ? "valid " : "",
678            have_data ? "data " : "", done ? "done " : "");
679
680    // We're leaving the cache, so pop cache->name() label
681    pkt->popLabel();
682
683    if (done) {
684        pkt->makeResponse();
685    } else {
686        // if it came as a request from the CPU side then make sure it
687        // continues towards the memory side
688        if (from_cpu_side) {
689            memSidePort.sendFunctional(pkt);
690        } else if (cpuSidePort.isSnooping()) {
691            // if it came from the memory side, it must be a snoop request
692            // and we should only forward it if we are forwarding snoops
693            cpuSidePort.sendFunctionalSnoop(pkt);
694        }
695    }
696}
697
698
699void
700BaseCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt)
701{
702    assert(pkt->isRequest());
703
704    uint64_t overwrite_val;
705    bool overwrite_mem;
706    uint64_t condition_val64;
707    uint32_t condition_val32;
708
709    int offset = pkt->getOffset(blkSize);
710    uint8_t *blk_data = blk->data + offset;
711
712    assert(sizeof(uint64_t) >= pkt->getSize());
713
714    overwrite_mem = true;
715    // keep a copy of our possible write value, and copy what is at the
716    // memory address into the packet
717    pkt->writeData((uint8_t *)&overwrite_val);
718    pkt->setData(blk_data);
719
720    if (pkt->req->isCondSwap()) {
721        if (pkt->getSize() == sizeof(uint64_t)) {
722            condition_val64 = pkt->req->getExtraData();
723            overwrite_mem = !std::memcmp(&condition_val64, blk_data,
724                                         sizeof(uint64_t));
725        } else if (pkt->getSize() == sizeof(uint32_t)) {
726            condition_val32 = (uint32_t)pkt->req->getExtraData();
727            overwrite_mem = !std::memcmp(&condition_val32, blk_data,
728                                         sizeof(uint32_t));
729        } else
730            panic("Invalid size for conditional read/write\n");
731    }
732
733    if (overwrite_mem) {
734        std::memcpy(blk_data, &overwrite_val, pkt->getSize());
735        blk->status |= BlkDirty;
736    }
737}
738
739QueueEntry*
740BaseCache::getNextQueueEntry()
741{
742    // Check both MSHR queue and write buffer for potential requests,
743    // note that null does not mean there is no request, it could
744    // simply be that it is not ready
745    MSHR *miss_mshr  = mshrQueue.getNext();
746    WriteQueueEntry *wq_entry = writeBuffer.getNext();
747
748    // If we got a write buffer request ready, first priority is a
749    // full write buffer, otherwise we favour the miss requests
750    if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) {
751        // need to search MSHR queue for conflicting earlier miss.
752        MSHR *conflict_mshr =
753            mshrQueue.findPending(wq_entry->blkAddr,
754                                  wq_entry->isSecure);
755
756        if (conflict_mshr && conflict_mshr->order < wq_entry->order) {
757            // Service misses in order until conflict is cleared.
758            return conflict_mshr;
759
760            // @todo Note that we ignore the ready time of the conflict here
761        }
762
763        // No conflicts; issue write
764        return wq_entry;
765    } else if (miss_mshr) {
766        // need to check for conflicting earlier writeback
767        WriteQueueEntry *conflict_mshr =
768            writeBuffer.findPending(miss_mshr->blkAddr,
769                                    miss_mshr->isSecure);
770        if (conflict_mshr) {
771            // not sure why we don't check order here... it was in the
772            // original code but commented out.
773
774            // The only way this happens is if we are
775            // doing a write and we didn't have permissions
776            // then subsequently saw a writeback (owned got evicted)
777            // We need to make sure to perform the writeback first
778            // To preserve the dirty data, then we can issue the write
779
780            // should we return wq_entry here instead?  I.e. do we
781            // have to flush writes in order?  I don't think so... not
782            // for Alpha anyway.  Maybe for x86?
783            return conflict_mshr;
784
785            // @todo Note that we ignore the ready time of the conflict here
786        }
787
788        // No conflicts; issue read
789        return miss_mshr;
790    }
791
792    // fall through... no pending requests.  Try a prefetch.
793    assert(!miss_mshr && !wq_entry);
794    if (prefetcher && mshrQueue.canPrefetch()) {
795        // If we have a miss queue slot, we can try a prefetch
796        PacketPtr pkt = prefetcher->getPacket();
797        if (pkt) {
798            Addr pf_addr = pkt->getBlockAddr(blkSize);
799            if (!tags->findBlock(pf_addr, pkt->isSecure()) &&
800                !mshrQueue.findMatch(pf_addr, pkt->isSecure()) &&
801                !writeBuffer.findMatch(pf_addr, pkt->isSecure())) {
802                // Update statistic on number of prefetches issued
803                // (hwpf_mshr_misses)
804                assert(pkt->req->masterId() < system->maxMasters());
805                mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
806
807                // allocate an MSHR and return it, note
808                // that we send the packet straight away, so do not
809                // schedule the send
810                return allocateMissBuffer(pkt, curTick(), false);
811            } else {
812                // free the request and packet
813                delete pkt->req;
814                delete pkt;
815            }
816        }
817    }
818
819    return nullptr;
820}
821
822void
823BaseCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, bool, bool)
824{
825    assert(pkt->isRequest());
826
827    assert(blk && blk->isValid());
828    // Occasionally this is not true... if we are a lower-level cache
829    // satisfying a string of Read and ReadEx requests from
830    // upper-level caches, a Read will mark the block as shared but we
831    // can satisfy a following ReadEx anyway since we can rely on the
832    // Read requester(s) to have buffered the ReadEx snoop and to
833    // invalidate their blocks after receiving them.
834    // assert(!pkt->needsWritable() || blk->isWritable());
835    assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize);
836
837    // Check RMW operations first since both isRead() and
838    // isWrite() will be true for them
839    if (pkt->cmd == MemCmd::SwapReq) {
840        cmpAndSwap(blk, pkt);
841    } else if (pkt->isWrite()) {
842        // we have the block in a writable state and can go ahead,
843        // note that the line may be also be considered writable in
844        // downstream caches along the path to memory, but always
845        // Exclusive, and never Modified
846        assert(blk->isWritable());
847        // Write or WriteLine at the first cache with block in writable state
848        if (blk->checkWrite(pkt)) {
849            pkt->writeDataToBlock(blk->data, blkSize);
850        }
851        // Always mark the line as dirty (and thus transition to the
852        // Modified state) even if we are a failed StoreCond so we
853        // supply data to any snoops that have appended themselves to
854        // this cache before knowing the store will fail.
855        blk->status |= BlkDirty;
856        DPRINTF(CacheVerbose, "%s for %s (write)\n", __func__, pkt->print());
857    } else if (pkt->isRead()) {
858        if (pkt->isLLSC()) {
859            blk->trackLoadLocked(pkt);
860        }
861
862        // all read responses have a data payload
863        assert(pkt->hasRespData());
864        pkt->setDataFromBlock(blk->data, blkSize);
865    } else if (pkt->isUpgrade()) {
866        // sanity check
867        assert(!pkt->hasSharers());
868
869        if (blk->isDirty()) {
870            // we were in the Owned state, and a cache above us that
871            // has the line in Shared state needs to be made aware
872            // that the data it already has is in fact dirty
873            pkt->setCacheResponding();
874            blk->status &= ~BlkDirty;
875        }
876    } else {
877        assert(pkt->isInvalidate());
878        invalidateBlock(blk);
879        DPRINTF(CacheVerbose, "%s for %s (invalidation)\n", __func__,
880                pkt->print());
881    }
882}
883
884/////////////////////////////////////////////////////
885//
886// Access path: requests coming in from the CPU side
887//
888/////////////////////////////////////////////////////
889
890bool
891BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
892                  PacketList &writebacks)
893{
894    // sanity check
895    assert(pkt->isRequest());
896
897    chatty_assert(!(isReadOnly && pkt->isWrite()),
898                  "Should never see a write in a read-only cache %s\n",
899                  name());
900
901    // Here lat is the value passed as parameter to accessBlock() function
902    // that can modify its value.
903    blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat);
904
905    DPRINTF(Cache, "%s for %s %s\n", __func__, pkt->print(),
906            blk ? "hit " + blk->print() : "miss");
907
908    if (pkt->req->isCacheMaintenance()) {
909        // A cache maintenance operation is always forwarded to the
910        // memory below even if the block is found in dirty state.
911
912        // We defer any changes to the state of the block until we
913        // create and mark as in service the mshr for the downstream
914        // packet.
915        return false;
916    }
917
918    if (pkt->isEviction()) {
919        // We check for presence of block in above caches before issuing
920        // Writeback or CleanEvict to write buffer. Therefore the only
921        // possible cases can be of a CleanEvict packet coming from above
922        // encountering a Writeback generated in this cache peer cache and
923        // waiting in the write buffer. Cases of upper level peer caches
924        // generating CleanEvict and Writeback or simply CleanEvict and
925        // CleanEvict almost simultaneously will be caught by snoops sent out
926        // by crossbar.
927        WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(),
928                                                          pkt->isSecure());
929        if (wb_entry) {
930            assert(wb_entry->getNumTargets() == 1);
931            PacketPtr wbPkt = wb_entry->getTarget()->pkt;
932            assert(wbPkt->isWriteback());
933
934            if (pkt->isCleanEviction()) {
935                // The CleanEvict and WritebackClean snoops into other
936                // peer caches of the same level while traversing the
937                // crossbar. If a copy of the block is found, the
938                // packet is deleted in the crossbar. Hence, none of
939                // the other upper level caches connected to this
940                // cache have the block, so we can clear the
941                // BLOCK_CACHED flag in the Writeback if set and
942                // discard the CleanEvict by returning true.
943                wbPkt->clearBlockCached();
944                return true;
945            } else {
946                assert(pkt->cmd == MemCmd::WritebackDirty);
947                // Dirty writeback from above trumps our clean
948                // writeback... discard here
949                // Note: markInService will remove entry from writeback buffer.
950                markInService(wb_entry);
951                delete wbPkt;
952            }
953        }
954    }
955
956    // Writeback handling is special case.  We can write the block into
957    // the cache without having a writeable copy (or any copy at all).
958    if (pkt->isWriteback()) {
959        assert(blkSize == pkt->getSize());
960
961        // we could get a clean writeback while we are having
962        // outstanding accesses to a block, do the simple thing for
963        // now and drop the clean writeback so that we do not upset
964        // any ordering/decisions about ownership already taken
965        if (pkt->cmd == MemCmd::WritebackClean &&
966            mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) {
967            DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, "
968                    "dropping\n", pkt->getAddr());
969            return true;
970        }
971
972        if (!blk) {
973            // need to do a replacement
974            blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks);
975            if (!blk) {
976                // no replaceable block available: give up, fwd to next level.
977                incMissCount(pkt);
978                return false;
979            }
980            tags->insertBlock(pkt, blk);
981
982            blk->status |= (BlkValid | BlkReadable);
983        }
984        // only mark the block dirty if we got a writeback command,
985        // and leave it as is for a clean writeback
986        if (pkt->cmd == MemCmd::WritebackDirty) {
987            // TODO: the coherent cache can assert(!blk->isDirty());
988            blk->status |= BlkDirty;
989        }
990        // if the packet does not have sharers, it is passing
991        // writable, and we got the writeback in Modified or Exclusive
992        // state, if not we are in the Owned or Shared state
993        if (!pkt->hasSharers()) {
994            blk->status |= BlkWritable;
995        }
996        // nothing else to do; writeback doesn't expect response
997        assert(!pkt->needsResponse());
998        pkt->writeDataToBlock(blk->data, blkSize);
999        DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
1000        incHitCount(pkt);
1001        // populate the time when the block will be ready to access.
1002        blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
1003            pkt->payloadDelay;
1004        return true;
1005    } else if (pkt->cmd == MemCmd::CleanEvict) {
1006        if (blk) {
1007            // Found the block in the tags, need to stop CleanEvict from
1008            // propagating further down the hierarchy. Returning true will
1009            // treat the CleanEvict like a satisfied write request and delete
1010            // it.
1011            return true;
1012        }
1013        // We didn't find the block here, propagate the CleanEvict further
1014        // down the memory hierarchy. Returning false will treat the CleanEvict
1015        // like a Writeback which could not find a replaceable block so has to
1016        // go to next level.
1017        return false;
1018    } else if (pkt->cmd == MemCmd::WriteClean) {
1019        // WriteClean handling is a special case. We can allocate a
1020        // block directly if it doesn't exist and we can update the
1021        // block immediately. The WriteClean transfers the ownership
1022        // of the block as well.
1023        assert(blkSize == pkt->getSize());
1024
1025        if (!blk) {
1026            if (pkt->writeThrough()) {
1027                // if this is a write through packet, we don't try to
1028                // allocate if the block is not present
1029                return false;
1030            } else {
1031                // a writeback that misses needs to allocate a new block
1032                blk = allocateBlock(pkt->getAddr(), pkt->isSecure(),
1033                                    writebacks);
1034                if (!blk) {
1035                    // no replaceable block available: give up, fwd to
1036                    // next level.
1037                    incMissCount(pkt);
1038                    return false;
1039                }
1040                tags->insertBlock(pkt, blk);
1041
1042                blk->status |= (BlkValid | BlkReadable);
1043            }
1044        }
1045
1046        // at this point either this is a writeback or a write-through
1047        // write clean operation and the block is already in this
1048        // cache, we need to update the data and the block flags
1049        assert(blk);
1050        // TODO: the coherent cache can assert(!blk->isDirty());
1051        if (!pkt->writeThrough()) {
1052            blk->status |= BlkDirty;
1053        }
1054        // nothing else to do; writeback doesn't expect response
1055        assert(!pkt->needsResponse());
1056        pkt->writeDataToBlock(blk->data, blkSize);
1057        DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
1058
1059        incHitCount(pkt);
1060        // populate the time when the block will be ready to access.
1061        blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
1062            pkt->payloadDelay;
1063        // if this a write-through packet it will be sent to cache
1064        // below
1065        return !pkt->writeThrough();
1066    } else if (blk && (pkt->needsWritable() ? blk->isWritable() :
1067                       blk->isReadable())) {
1068        // OK to satisfy access
1069        incHitCount(pkt);
1070        satisfyRequest(pkt, blk);
1071        maintainClusivity(pkt->fromCache(), blk);
1072
1073        return true;
1074    }
1075
1076    // Can't satisfy access normally... either no block (blk == nullptr)
1077    // or have block but need writable
1078
1079    incMissCount(pkt);
1080
1081    if (!blk && pkt->isLLSC() && pkt->isWrite()) {
1082        // complete miss on store conditional... just give up now
1083        pkt->req->setExtraData(0);
1084        return true;
1085    }
1086
1087    return false;
1088}
1089
1090void
1091BaseCache::maintainClusivity(bool from_cache, CacheBlk *blk)
1092{
1093    if (from_cache && blk && blk->isValid() && !blk->isDirty() &&
1094        clusivity == Enums::mostly_excl) {
1095        // if we have responded to a cache, and our block is still
1096        // valid, but not dirty, and this cache is mostly exclusive
1097        // with respect to the cache above, drop the block
1098        invalidateBlock(blk);
1099    }
1100}
1101
1102CacheBlk*
1103BaseCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks,
1104                      bool allocate)
1105{
1106    assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq);
1107    Addr addr = pkt->getAddr();
1108    bool is_secure = pkt->isSecure();
1109#if TRACING_ON
1110    CacheBlk::State old_state = blk ? blk->status : 0;
1111#endif
1112
1113    // When handling a fill, we should have no writes to this line.
1114    assert(addr == pkt->getBlockAddr(blkSize));
1115    assert(!writeBuffer.findMatch(addr, is_secure));
1116
1117    if (!blk) {
1118        // better have read new data...
1119        assert(pkt->hasData());
1120
1121        // only read responses and write-line requests have data;
1122        // note that we don't write the data here for write-line - that
1123        // happens in the subsequent call to satisfyRequest
1124        assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq);
1125
1126        // need to do a replacement if allocating, otherwise we stick
1127        // with the temporary storage
1128        blk = allocate ? allocateBlock(addr, is_secure, writebacks) : nullptr;
1129
1130        if (!blk) {
1131            // No replaceable block or a mostly exclusive
1132            // cache... just use temporary storage to complete the
1133            // current request and then get rid of it
1134            assert(!tempBlock->isValid());
1135            blk = tempBlock;
1136            tempBlock->insert(addr, is_secure);
1137            DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr,
1138                    is_secure ? "s" : "ns");
1139        } else {
1140            tags->insertBlock(pkt, blk);
1141        }
1142
1143        // we should never be overwriting a valid block
1144        assert(!blk->isValid());
1145    } else {
1146        // existing block... probably an upgrade
1147        assert(blk->tag == tags->extractTag(addr));
1148        assert(blk->isSecure() == is_secure);
1149        // either we're getting new data or the block should already be valid
1150        assert(pkt->hasData() || blk->isValid());
1151        // don't clear block status... if block is already dirty we
1152        // don't want to lose that
1153    }
1154
1155    blk->status |= BlkValid | BlkReadable;
1156
1157    // sanity check for whole-line writes, which should always be
1158    // marked as writable as part of the fill, and then later marked
1159    // dirty as part of satisfyRequest
1160    if (pkt->cmd == MemCmd::WriteLineReq) {
1161        assert(!pkt->hasSharers());
1162    }
1163
1164    // here we deal with setting the appropriate state of the line,
1165    // and we start by looking at the hasSharers flag, and ignore the
1166    // cacheResponding flag (normally signalling dirty data) if the
1167    // packet has sharers, thus the line is never allocated as Owned
1168    // (dirty but not writable), and always ends up being either
1169    // Shared, Exclusive or Modified, see Packet::setCacheResponding
1170    // for more details
1171    if (!pkt->hasSharers()) {
1172        // we could get a writable line from memory (rather than a
1173        // cache) even in a read-only cache, note that we set this bit
1174        // even for a read-only cache, possibly revisit this decision
1175        blk->status |= BlkWritable;
1176
1177        // check if we got this via cache-to-cache transfer (i.e., from a
1178        // cache that had the block in Modified or Owned state)
1179        if (pkt->cacheResponding()) {
1180            // we got the block in Modified state, and invalidated the
1181            // owners copy
1182            blk->status |= BlkDirty;
1183
1184            chatty_assert(!isReadOnly, "Should never see dirty snoop response "
1185                          "in read-only cache %s\n", name());
1186        }
1187    }
1188
1189    DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n",
1190            addr, is_secure ? "s" : "ns", old_state, blk->print());
1191
1192    // if we got new data, copy it in (checking for a read response
1193    // and a response that has data is the same in the end)
1194    if (pkt->isRead()) {
1195        // sanity checks
1196        assert(pkt->hasData());
1197        assert(pkt->getSize() == blkSize);
1198
1199        pkt->writeDataToBlock(blk->data, blkSize);
1200    }
1201    // We pay for fillLatency here.
1202    blk->whenReady = clockEdge() + fillLatency * clockPeriod() +
1203        pkt->payloadDelay;
1204
1205    return blk;
1206}
1207
1208CacheBlk*
1209BaseCache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks)
1210{
1211    // Find replacement victim
1212    CacheBlk *blk = tags->findVictim(addr);
1213
1214    // It is valid to return nullptr if there is no victim
1215    if (!blk)
1216        return nullptr;
1217
1218    if (blk->isValid()) {
1219        Addr repl_addr = regenerateBlkAddr(blk);
1220        MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure());
1221        if (repl_mshr) {
1222            // must be an outstanding upgrade or clean request
1223            // on a block we're about to replace...
1224            assert((!blk->isWritable() && repl_mshr->needsWritable()) ||
1225                   repl_mshr->isCleaning());
1226            // too hard to replace block with transient state
1227            // allocation failed, block not inserted
1228            return nullptr;
1229        } else {
1230            DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx "
1231                    "(%s): %s\n", repl_addr, blk->isSecure() ? "s" : "ns",
1232                    addr, is_secure ? "s" : "ns",
1233                    blk->isDirty() ? "writeback" : "clean");
1234
1235            if (blk->wasPrefetched()) {
1236                unusedPrefetches++;
1237            }
1238            evictBlock(blk, writebacks);
1239            replacements++;
1240        }
1241    }
1242
1243    return blk;
1244}
1245
1246void
1247BaseCache::invalidateBlock(CacheBlk *blk)
1248{
1249    if (blk != tempBlock)
1250        tags->invalidate(blk);
1251    blk->invalidate();
1252}
1253
1254PacketPtr
1255BaseCache::writebackBlk(CacheBlk *blk)
1256{
1257    chatty_assert(!isReadOnly || writebackClean,
1258                  "Writeback from read-only cache");
1259    assert(blk && blk->isValid() && (blk->isDirty() || writebackClean));
1260
1261    writebacks[Request::wbMasterId]++;
1262
1263    Request *req = new Request(regenerateBlkAddr(blk), blkSize, 0,
1264                               Request::wbMasterId);
1265    if (blk->isSecure())
1266        req->setFlags(Request::SECURE);
1267
1268    req->taskId(blk->task_id);
1269
1270    PacketPtr pkt =
1271        new Packet(req, blk->isDirty() ?
1272                   MemCmd::WritebackDirty : MemCmd::WritebackClean);
1273
1274    DPRINTF(Cache, "Create Writeback %s writable: %d, dirty: %d\n",
1275            pkt->print(), blk->isWritable(), blk->isDirty());
1276
1277    if (blk->isWritable()) {
1278        // not asserting shared means we pass the block in modified
1279        // state, mark our own block non-writeable
1280        blk->status &= ~BlkWritable;
1281    } else {
1282        // we are in the Owned state, tell the receiver
1283        pkt->setHasSharers();
1284    }
1285
1286    // make sure the block is not marked dirty
1287    blk->status &= ~BlkDirty;
1288
1289    pkt->allocate();
1290    pkt->setDataFromBlock(blk->data, blkSize);
1291
1292    return pkt;
1293}
1294
1295PacketPtr
1296BaseCache::writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id)
1297{
1298    Request *req = new Request(regenerateBlkAddr(blk), blkSize, 0,
1299                               Request::wbMasterId);
1300    if (blk->isSecure()) {
1301        req->setFlags(Request::SECURE);
1302    }
1303    req->taskId(blk->task_id);
1304
1305    PacketPtr pkt = new Packet(req, MemCmd::WriteClean, blkSize, id);
1306
1307    if (dest) {
1308        req->setFlags(dest);
1309        pkt->setWriteThrough();
1310    }
1311
1312    DPRINTF(Cache, "Create %s writable: %d, dirty: %d\n", pkt->print(),
1313            blk->isWritable(), blk->isDirty());
1314
1315    if (blk->isWritable()) {
1316        // not asserting shared means we pass the block in modified
1317        // state, mark our own block non-writeable
1318        blk->status &= ~BlkWritable;
1319    } else {
1320        // we are in the Owned state, tell the receiver
1321        pkt->setHasSharers();
1322    }
1323
1324    // make sure the block is not marked dirty
1325    blk->status &= ~BlkDirty;
1326
1327    pkt->allocate();
1328    pkt->setDataFromBlock(blk->data, blkSize);
1329
1330    return pkt;
1331}
1332
1333
1334void
1335BaseCache::memWriteback()
1336{
1337    tags->forEachBlk([this](CacheBlk &blk) { writebackVisitor(blk); });
1338}
1339
1340void
1341BaseCache::memInvalidate()
1342{
1343    tags->forEachBlk([this](CacheBlk &blk) { invalidateVisitor(blk); });
1344}
1345
1346bool
1347BaseCache::isDirty() const
1348{
1349    return tags->anyBlk([](CacheBlk &blk) { return blk.isDirty(); });
1350}
1351
1352void
1353BaseCache::writebackVisitor(CacheBlk &blk)
1354{
1355    if (blk.isDirty()) {
1356        assert(blk.isValid());
1357
1358        Request request(regenerateBlkAddr(&blk),
1359                        blkSize, 0, Request::funcMasterId);
1360        request.taskId(blk.task_id);
1361        if (blk.isSecure()) {
1362            request.setFlags(Request::SECURE);
1363        }
1364
1365        Packet packet(&request, MemCmd::WriteReq);
1366        packet.dataStatic(blk.data);
1367
1368        memSidePort.sendFunctional(&packet);
1369
1370        blk.status &= ~BlkDirty;
1371    }
1372}
1373
1374void
1375BaseCache::invalidateVisitor(CacheBlk &blk)
1376{
1377    if (blk.isDirty())
1378        warn_once("Invalidating dirty cache lines. " \
1379                  "Expect things to break.\n");
1380
1381    if (blk.isValid()) {
1382        assert(!blk.isDirty());
1383        invalidateBlock(&blk);
1384    }
1385}
1386
1387Tick
1388BaseCache::nextQueueReadyTime() const
1389{
1390    Tick nextReady = std::min(mshrQueue.nextReadyTime(),
1391                              writeBuffer.nextReadyTime());
1392
1393    // Don't signal prefetch ready time if no MSHRs available
1394    // Will signal once enoguh MSHRs are deallocated
1395    if (prefetcher && mshrQueue.canPrefetch()) {
1396        nextReady = std::min(nextReady,
1397                             prefetcher->nextPrefetchReadyTime());
1398    }
1399
1400    return nextReady;
1401}
1402
1403
1404bool
1405BaseCache::sendMSHRQueuePacket(MSHR* mshr)
1406{
1407    assert(mshr);
1408
1409    // use request from 1st target
1410    PacketPtr tgt_pkt = mshr->getTarget()->pkt;
1411
1412    DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print());
1413
1414    CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure);
1415
1416    // either a prefetch that is not present upstream, or a normal
1417    // MSHR request, proceed to get the packet to send downstream
1418    PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable());
1419
1420    mshr->isForward = (pkt == nullptr);
1421
1422    if (mshr->isForward) {
1423        // not a cache block request, but a response is expected
1424        // make copy of current packet to forward, keep current
1425        // copy for response handling
1426        pkt = new Packet(tgt_pkt, false, true);
1427        assert(!pkt->isWrite());
1428    }
1429
1430    // play it safe and append (rather than set) the sender state,
1431    // as forwarded packets may already have existing state
1432    pkt->pushSenderState(mshr);
1433
1434    if (pkt->isClean() && blk && blk->isDirty()) {
1435        // A cache clean opearation is looking for a dirty block. Mark
1436        // the packet so that the destination xbar can determine that
1437        // there will be a follow-up write packet as well.
1438        pkt->setSatisfied();
1439    }
1440
1441    if (!memSidePort.sendTimingReq(pkt)) {
1442        // we are awaiting a retry, but we
1443        // delete the packet and will be creating a new packet
1444        // when we get the opportunity
1445        delete pkt;
1446
1447        // note that we have now masked any requestBus and
1448        // schedSendEvent (we will wait for a retry before
1449        // doing anything), and this is so even if we do not
1450        // care about this packet and might override it before
1451        // it gets retried
1452        return true;
1453    } else {
1454        // As part of the call to sendTimingReq the packet is
1455        // forwarded to all neighbouring caches (and any caches
1456        // above them) as a snoop. Thus at this point we know if
1457        // any of the neighbouring caches are responding, and if
1458        // so, we know it is dirty, and we can determine if it is
1459        // being passed as Modified, making our MSHR the ordering
1460        // point
1461        bool pending_modified_resp = !pkt->hasSharers() &&
1462            pkt->cacheResponding();
1463        markInService(mshr, pending_modified_resp);
1464
1465        if (pkt->isClean() && blk && blk->isDirty()) {
1466            // A cache clean opearation is looking for a dirty
1467            // block. If a dirty block is encountered a WriteClean
1468            // will update any copies to the path to the memory
1469            // until the point of reference.
1470            DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n",
1471                    __func__, pkt->print(), blk->print());
1472            PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(),
1473                                             pkt->id);
1474            PacketList writebacks;
1475            writebacks.push_back(wb_pkt);
1476            doWritebacks(writebacks, 0);
1477        }
1478
1479        return false;
1480    }
1481}
1482
1483bool
1484BaseCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry)
1485{
1486    assert(wq_entry);
1487
1488    // always a single target for write queue entries
1489    PacketPtr tgt_pkt = wq_entry->getTarget()->pkt;
1490
1491    DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print());
1492
1493    // forward as is, both for evictions and uncacheable writes
1494    if (!memSidePort.sendTimingReq(tgt_pkt)) {
1495        // note that we have now masked any requestBus and
1496        // schedSendEvent (we will wait for a retry before
1497        // doing anything), and this is so even if we do not
1498        // care about this packet and might override it before
1499        // it gets retried
1500        return true;
1501    } else {
1502        markInService(wq_entry);
1503        return false;
1504    }
1505}
1506
1507void
1508BaseCache::serialize(CheckpointOut &cp) const
1509{
1510    bool dirty(isDirty());
1511
1512    if (dirty) {
1513        warn("*** The cache still contains dirty data. ***\n");
1514        warn("    Make sure to drain the system using the correct flags.\n");
1515        warn("    This checkpoint will not restore correctly " \
1516             "and dirty data in the cache will be lost!\n");
1517    }
1518
1519    // Since we don't checkpoint the data in the cache, any dirty data
1520    // will be lost when restoring from a checkpoint of a system that
1521    // wasn't drained properly. Flag the checkpoint as invalid if the
1522    // cache contains dirty data.
1523    bool bad_checkpoint(dirty);
1524    SERIALIZE_SCALAR(bad_checkpoint);
1525}
1526
1527void
1528BaseCache::unserialize(CheckpointIn &cp)
1529{
1530    bool bad_checkpoint;
1531    UNSERIALIZE_SCALAR(bad_checkpoint);
1532    if (bad_checkpoint) {
1533        fatal("Restoring from checkpoints with dirty caches is not "
1534              "supported in the classic memory system. Please remove any "
1535              "caches or drain them properly before taking checkpoints.\n");
1536    }
1537}
1538
1539void
1540BaseCache::regStats()
1541{
1542    MemObject::regStats();
1543
1544    using namespace Stats;
1545
1546    // Hit statistics
1547    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1548        MemCmd cmd(access_idx);
1549        const string &cstr = cmd.toString();
1550
1551        hits[access_idx]
1552            .init(system->maxMasters())
1553            .name(name() + "." + cstr + "_hits")
1554            .desc("number of " + cstr + " hits")
1555            .flags(total | nozero | nonan)
1556            ;
1557        for (int i = 0; i < system->maxMasters(); i++) {
1558            hits[access_idx].subname(i, system->getMasterName(i));
1559        }
1560    }
1561
1562// These macros make it easier to sum the right subset of commands and
1563// to change the subset of commands that are considered "demand" vs
1564// "non-demand"
1565#define SUM_DEMAND(s) \
1566    (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::WriteLineReq] + \
1567     s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq])
1568
1569// should writebacks be included here?  prior code was inconsistent...
1570#define SUM_NON_DEMAND(s) \
1571    (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq])
1572
1573    demandHits
1574        .name(name() + ".demand_hits")
1575        .desc("number of demand (read+write) hits")
1576        .flags(total | nozero | nonan)
1577        ;
1578    demandHits = SUM_DEMAND(hits);
1579    for (int i = 0; i < system->maxMasters(); i++) {
1580        demandHits.subname(i, system->getMasterName(i));
1581    }
1582
1583    overallHits
1584        .name(name() + ".overall_hits")
1585        .desc("number of overall hits")
1586        .flags(total | nozero | nonan)
1587        ;
1588    overallHits = demandHits + SUM_NON_DEMAND(hits);
1589    for (int i = 0; i < system->maxMasters(); i++) {
1590        overallHits.subname(i, system->getMasterName(i));
1591    }
1592
1593    // Miss statistics
1594    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1595        MemCmd cmd(access_idx);
1596        const string &cstr = cmd.toString();
1597
1598        misses[access_idx]
1599            .init(system->maxMasters())
1600            .name(name() + "." + cstr + "_misses")
1601            .desc("number of " + cstr + " misses")
1602            .flags(total | nozero | nonan)
1603            ;
1604        for (int i = 0; i < system->maxMasters(); i++) {
1605            misses[access_idx].subname(i, system->getMasterName(i));
1606        }
1607    }
1608
1609    demandMisses
1610        .name(name() + ".demand_misses")
1611        .desc("number of demand (read+write) misses")
1612        .flags(total | nozero | nonan)
1613        ;
1614    demandMisses = SUM_DEMAND(misses);
1615    for (int i = 0; i < system->maxMasters(); i++) {
1616        demandMisses.subname(i, system->getMasterName(i));
1617    }
1618
1619    overallMisses
1620        .name(name() + ".overall_misses")
1621        .desc("number of overall misses")
1622        .flags(total | nozero | nonan)
1623        ;
1624    overallMisses = demandMisses + SUM_NON_DEMAND(misses);
1625    for (int i = 0; i < system->maxMasters(); i++) {
1626        overallMisses.subname(i, system->getMasterName(i));
1627    }
1628
1629    // Miss latency statistics
1630    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1631        MemCmd cmd(access_idx);
1632        const string &cstr = cmd.toString();
1633
1634        missLatency[access_idx]
1635            .init(system->maxMasters())
1636            .name(name() + "." + cstr + "_miss_latency")
1637            .desc("number of " + cstr + " miss cycles")
1638            .flags(total | nozero | nonan)
1639            ;
1640        for (int i = 0; i < system->maxMasters(); i++) {
1641            missLatency[access_idx].subname(i, system->getMasterName(i));
1642        }
1643    }
1644
1645    demandMissLatency
1646        .name(name() + ".demand_miss_latency")
1647        .desc("number of demand (read+write) miss cycles")
1648        .flags(total | nozero | nonan)
1649        ;
1650    demandMissLatency = SUM_DEMAND(missLatency);
1651    for (int i = 0; i < system->maxMasters(); i++) {
1652        demandMissLatency.subname(i, system->getMasterName(i));
1653    }
1654
1655    overallMissLatency
1656        .name(name() + ".overall_miss_latency")
1657        .desc("number of overall miss cycles")
1658        .flags(total | nozero | nonan)
1659        ;
1660    overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency);
1661    for (int i = 0; i < system->maxMasters(); i++) {
1662        overallMissLatency.subname(i, system->getMasterName(i));
1663    }
1664
1665    // access formulas
1666    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1667        MemCmd cmd(access_idx);
1668        const string &cstr = cmd.toString();
1669
1670        accesses[access_idx]
1671            .name(name() + "." + cstr + "_accesses")
1672            .desc("number of " + cstr + " accesses(hits+misses)")
1673            .flags(total | nozero | nonan)
1674            ;
1675        accesses[access_idx] = hits[access_idx] + misses[access_idx];
1676
1677        for (int i = 0; i < system->maxMasters(); i++) {
1678            accesses[access_idx].subname(i, system->getMasterName(i));
1679        }
1680    }
1681
1682    demandAccesses
1683        .name(name() + ".demand_accesses")
1684        .desc("number of demand (read+write) accesses")
1685        .flags(total | nozero | nonan)
1686        ;
1687    demandAccesses = demandHits + demandMisses;
1688    for (int i = 0; i < system->maxMasters(); i++) {
1689        demandAccesses.subname(i, system->getMasterName(i));
1690    }
1691
1692    overallAccesses
1693        .name(name() + ".overall_accesses")
1694        .desc("number of overall (read+write) accesses")
1695        .flags(total | nozero | nonan)
1696        ;
1697    overallAccesses = overallHits + overallMisses;
1698    for (int i = 0; i < system->maxMasters(); i++) {
1699        overallAccesses.subname(i, system->getMasterName(i));
1700    }
1701
1702    // miss rate formulas
1703    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1704        MemCmd cmd(access_idx);
1705        const string &cstr = cmd.toString();
1706
1707        missRate[access_idx]
1708            .name(name() + "." + cstr + "_miss_rate")
1709            .desc("miss rate for " + cstr + " accesses")
1710            .flags(total | nozero | nonan)
1711            ;
1712        missRate[access_idx] = misses[access_idx] / accesses[access_idx];
1713
1714        for (int i = 0; i < system->maxMasters(); i++) {
1715            missRate[access_idx].subname(i, system->getMasterName(i));
1716        }
1717    }
1718
1719    demandMissRate
1720        .name(name() + ".demand_miss_rate")
1721        .desc("miss rate for demand accesses")
1722        .flags(total | nozero | nonan)
1723        ;
1724    demandMissRate = demandMisses / demandAccesses;
1725    for (int i = 0; i < system->maxMasters(); i++) {
1726        demandMissRate.subname(i, system->getMasterName(i));
1727    }
1728
1729    overallMissRate
1730        .name(name() + ".overall_miss_rate")
1731        .desc("miss rate for overall accesses")
1732        .flags(total | nozero | nonan)
1733        ;
1734    overallMissRate = overallMisses / overallAccesses;
1735    for (int i = 0; i < system->maxMasters(); i++) {
1736        overallMissRate.subname(i, system->getMasterName(i));
1737    }
1738
1739    // miss latency formulas
1740    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1741        MemCmd cmd(access_idx);
1742        const string &cstr = cmd.toString();
1743
1744        avgMissLatency[access_idx]
1745            .name(name() + "." + cstr + "_avg_miss_latency")
1746            .desc("average " + cstr + " miss latency")
1747            .flags(total | nozero | nonan)
1748            ;
1749        avgMissLatency[access_idx] =
1750            missLatency[access_idx] / misses[access_idx];
1751
1752        for (int i = 0; i < system->maxMasters(); i++) {
1753            avgMissLatency[access_idx].subname(i, system->getMasterName(i));
1754        }
1755    }
1756
1757    demandAvgMissLatency
1758        .name(name() + ".demand_avg_miss_latency")
1759        .desc("average overall miss latency")
1760        .flags(total | nozero | nonan)
1761        ;
1762    demandAvgMissLatency = demandMissLatency / demandMisses;
1763    for (int i = 0; i < system->maxMasters(); i++) {
1764        demandAvgMissLatency.subname(i, system->getMasterName(i));
1765    }
1766
1767    overallAvgMissLatency
1768        .name(name() + ".overall_avg_miss_latency")
1769        .desc("average overall miss latency")
1770        .flags(total | nozero | nonan)
1771        ;
1772    overallAvgMissLatency = overallMissLatency / overallMisses;
1773    for (int i = 0; i < system->maxMasters(); i++) {
1774        overallAvgMissLatency.subname(i, system->getMasterName(i));
1775    }
1776
1777    blocked_cycles.init(NUM_BLOCKED_CAUSES);
1778    blocked_cycles
1779        .name(name() + ".blocked_cycles")
1780        .desc("number of cycles access was blocked")
1781        .subname(Blocked_NoMSHRs, "no_mshrs")
1782        .subname(Blocked_NoTargets, "no_targets")
1783        ;
1784
1785
1786    blocked_causes.init(NUM_BLOCKED_CAUSES);
1787    blocked_causes
1788        .name(name() + ".blocked")
1789        .desc("number of cycles access was blocked")
1790        .subname(Blocked_NoMSHRs, "no_mshrs")
1791        .subname(Blocked_NoTargets, "no_targets")
1792        ;
1793
1794    avg_blocked
1795        .name(name() + ".avg_blocked_cycles")
1796        .desc("average number of cycles each access was blocked")
1797        .subname(Blocked_NoMSHRs, "no_mshrs")
1798        .subname(Blocked_NoTargets, "no_targets")
1799        ;
1800
1801    avg_blocked = blocked_cycles / blocked_causes;
1802
1803    unusedPrefetches
1804        .name(name() + ".unused_prefetches")
1805        .desc("number of HardPF blocks evicted w/o reference")
1806        .flags(nozero)
1807        ;
1808
1809    writebacks
1810        .init(system->maxMasters())
1811        .name(name() + ".writebacks")
1812        .desc("number of writebacks")
1813        .flags(total | nozero | nonan)
1814        ;
1815    for (int i = 0; i < system->maxMasters(); i++) {
1816        writebacks.subname(i, system->getMasterName(i));
1817    }
1818
1819    // MSHR statistics
1820    // MSHR hit statistics
1821    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1822        MemCmd cmd(access_idx);
1823        const string &cstr = cmd.toString();
1824
1825        mshr_hits[access_idx]
1826            .init(system->maxMasters())
1827            .name(name() + "." + cstr + "_mshr_hits")
1828            .desc("number of " + cstr + " MSHR hits")
1829            .flags(total | nozero | nonan)
1830            ;
1831        for (int i = 0; i < system->maxMasters(); i++) {
1832            mshr_hits[access_idx].subname(i, system->getMasterName(i));
1833        }
1834    }
1835
1836    demandMshrHits
1837        .name(name() + ".demand_mshr_hits")
1838        .desc("number of demand (read+write) MSHR hits")
1839        .flags(total | nozero | nonan)
1840        ;
1841    demandMshrHits = SUM_DEMAND(mshr_hits);
1842    for (int i = 0; i < system->maxMasters(); i++) {
1843        demandMshrHits.subname(i, system->getMasterName(i));
1844    }
1845
1846    overallMshrHits
1847        .name(name() + ".overall_mshr_hits")
1848        .desc("number of overall MSHR hits")
1849        .flags(total | nozero | nonan)
1850        ;
1851    overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits);
1852    for (int i = 0; i < system->maxMasters(); i++) {
1853        overallMshrHits.subname(i, system->getMasterName(i));
1854    }
1855
1856    // MSHR miss statistics
1857    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1858        MemCmd cmd(access_idx);
1859        const string &cstr = cmd.toString();
1860
1861        mshr_misses[access_idx]
1862            .init(system->maxMasters())
1863            .name(name() + "." + cstr + "_mshr_misses")
1864            .desc("number of " + cstr + " MSHR misses")
1865            .flags(total | nozero | nonan)
1866            ;
1867        for (int i = 0; i < system->maxMasters(); i++) {
1868            mshr_misses[access_idx].subname(i, system->getMasterName(i));
1869        }
1870    }
1871
1872    demandMshrMisses
1873        .name(name() + ".demand_mshr_misses")
1874        .desc("number of demand (read+write) MSHR misses")
1875        .flags(total | nozero | nonan)
1876        ;
1877    demandMshrMisses = SUM_DEMAND(mshr_misses);
1878    for (int i = 0; i < system->maxMasters(); i++) {
1879        demandMshrMisses.subname(i, system->getMasterName(i));
1880    }
1881
1882    overallMshrMisses
1883        .name(name() + ".overall_mshr_misses")
1884        .desc("number of overall MSHR misses")
1885        .flags(total | nozero | nonan)
1886        ;
1887    overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses);
1888    for (int i = 0; i < system->maxMasters(); i++) {
1889        overallMshrMisses.subname(i, system->getMasterName(i));
1890    }
1891
1892    // MSHR miss latency statistics
1893    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1894        MemCmd cmd(access_idx);
1895        const string &cstr = cmd.toString();
1896
1897        mshr_miss_latency[access_idx]
1898            .init(system->maxMasters())
1899            .name(name() + "." + cstr + "_mshr_miss_latency")
1900            .desc("number of " + cstr + " MSHR miss cycles")
1901            .flags(total | nozero | nonan)
1902            ;
1903        for (int i = 0; i < system->maxMasters(); i++) {
1904            mshr_miss_latency[access_idx].subname(i, system->getMasterName(i));
1905        }
1906    }
1907
1908    demandMshrMissLatency
1909        .name(name() + ".demand_mshr_miss_latency")
1910        .desc("number of demand (read+write) MSHR miss cycles")
1911        .flags(total | nozero | nonan)
1912        ;
1913    demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency);
1914    for (int i = 0; i < system->maxMasters(); i++) {
1915        demandMshrMissLatency.subname(i, system->getMasterName(i));
1916    }
1917
1918    overallMshrMissLatency
1919        .name(name() + ".overall_mshr_miss_latency")
1920        .desc("number of overall MSHR miss cycles")
1921        .flags(total | nozero | nonan)
1922        ;
1923    overallMshrMissLatency =
1924        demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency);
1925    for (int i = 0; i < system->maxMasters(); i++) {
1926        overallMshrMissLatency.subname(i, system->getMasterName(i));
1927    }
1928
1929    // MSHR uncacheable statistics
1930    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1931        MemCmd cmd(access_idx);
1932        const string &cstr = cmd.toString();
1933
1934        mshr_uncacheable[access_idx]
1935            .init(system->maxMasters())
1936            .name(name() + "." + cstr + "_mshr_uncacheable")
1937            .desc("number of " + cstr + " MSHR uncacheable")
1938            .flags(total | nozero | nonan)
1939            ;
1940        for (int i = 0; i < system->maxMasters(); i++) {
1941            mshr_uncacheable[access_idx].subname(i, system->getMasterName(i));
1942        }
1943    }
1944
1945    overallMshrUncacheable
1946        .name(name() + ".overall_mshr_uncacheable_misses")
1947        .desc("number of overall MSHR uncacheable misses")
1948        .flags(total | nozero | nonan)
1949        ;
1950    overallMshrUncacheable =
1951        SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable);
1952    for (int i = 0; i < system->maxMasters(); i++) {
1953        overallMshrUncacheable.subname(i, system->getMasterName(i));
1954    }
1955
1956    // MSHR miss latency statistics
1957    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1958        MemCmd cmd(access_idx);
1959        const string &cstr = cmd.toString();
1960
1961        mshr_uncacheable_lat[access_idx]
1962            .init(system->maxMasters())
1963            .name(name() + "." + cstr + "_mshr_uncacheable_latency")
1964            .desc("number of " + cstr + " MSHR uncacheable cycles")
1965            .flags(total | nozero | nonan)
1966            ;
1967        for (int i = 0; i < system->maxMasters(); i++) {
1968            mshr_uncacheable_lat[access_idx].subname(
1969                i, system->getMasterName(i));
1970        }
1971    }
1972
1973    overallMshrUncacheableLatency
1974        .name(name() + ".overall_mshr_uncacheable_latency")
1975        .desc("number of overall MSHR uncacheable cycles")
1976        .flags(total | nozero | nonan)
1977        ;
1978    overallMshrUncacheableLatency =
1979        SUM_DEMAND(mshr_uncacheable_lat) +
1980        SUM_NON_DEMAND(mshr_uncacheable_lat);
1981    for (int i = 0; i < system->maxMasters(); i++) {
1982        overallMshrUncacheableLatency.subname(i, system->getMasterName(i));
1983    }
1984
1985#if 0
1986    // MSHR access formulas
1987    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1988        MemCmd cmd(access_idx);
1989        const string &cstr = cmd.toString();
1990
1991        mshrAccesses[access_idx]
1992            .name(name() + "." + cstr + "_mshr_accesses")
1993            .desc("number of " + cstr + " mshr accesses(hits+misses)")
1994            .flags(total | nozero | nonan)
1995            ;
1996        mshrAccesses[access_idx] =
1997            mshr_hits[access_idx] + mshr_misses[access_idx]
1998            + mshr_uncacheable[access_idx];
1999    }
2000
2001    demandMshrAccesses
2002        .name(name() + ".demand_mshr_accesses")
2003        .desc("number of demand (read+write) mshr accesses")
2004        .flags(total | nozero | nonan)
2005        ;
2006    demandMshrAccesses = demandMshrHits + demandMshrMisses;
2007
2008    overallMshrAccesses
2009        .name(name() + ".overall_mshr_accesses")
2010        .desc("number of overall (read+write) mshr accesses")
2011        .flags(total | nozero | nonan)
2012        ;
2013    overallMshrAccesses = overallMshrHits + overallMshrMisses
2014        + overallMshrUncacheable;
2015#endif
2016
2017    // MSHR miss rate formulas
2018    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2019        MemCmd cmd(access_idx);
2020        const string &cstr = cmd.toString();
2021
2022        mshrMissRate[access_idx]
2023            .name(name() + "." + cstr + "_mshr_miss_rate")
2024            .desc("mshr miss rate for " + cstr + " accesses")
2025            .flags(total | nozero | nonan)
2026            ;
2027        mshrMissRate[access_idx] =
2028            mshr_misses[access_idx] / accesses[access_idx];
2029
2030        for (int i = 0; i < system->maxMasters(); i++) {
2031            mshrMissRate[access_idx].subname(i, system->getMasterName(i));
2032        }
2033    }
2034
2035    demandMshrMissRate
2036        .name(name() + ".demand_mshr_miss_rate")
2037        .desc("mshr miss rate for demand accesses")
2038        .flags(total | nozero | nonan)
2039        ;
2040    demandMshrMissRate = demandMshrMisses / demandAccesses;
2041    for (int i = 0; i < system->maxMasters(); i++) {
2042        demandMshrMissRate.subname(i, system->getMasterName(i));
2043    }
2044
2045    overallMshrMissRate
2046        .name(name() + ".overall_mshr_miss_rate")
2047        .desc("mshr miss rate for overall accesses")
2048        .flags(total | nozero | nonan)
2049        ;
2050    overallMshrMissRate = overallMshrMisses / overallAccesses;
2051    for (int i = 0; i < system->maxMasters(); i++) {
2052        overallMshrMissRate.subname(i, system->getMasterName(i));
2053    }
2054
2055    // mshrMiss latency formulas
2056    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2057        MemCmd cmd(access_idx);
2058        const string &cstr = cmd.toString();
2059
2060        avgMshrMissLatency[access_idx]
2061            .name(name() + "." + cstr + "_avg_mshr_miss_latency")
2062            .desc("average " + cstr + " mshr miss latency")
2063            .flags(total | nozero | nonan)
2064            ;
2065        avgMshrMissLatency[access_idx] =
2066            mshr_miss_latency[access_idx] / mshr_misses[access_idx];
2067
2068        for (int i = 0; i < system->maxMasters(); i++) {
2069            avgMshrMissLatency[access_idx].subname(
2070                i, system->getMasterName(i));
2071        }
2072    }
2073
2074    demandAvgMshrMissLatency
2075        .name(name() + ".demand_avg_mshr_miss_latency")
2076        .desc("average overall mshr miss latency")
2077        .flags(total | nozero | nonan)
2078        ;
2079    demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses;
2080    for (int i = 0; i < system->maxMasters(); i++) {
2081        demandAvgMshrMissLatency.subname(i, system->getMasterName(i));
2082    }
2083
2084    overallAvgMshrMissLatency
2085        .name(name() + ".overall_avg_mshr_miss_latency")
2086        .desc("average overall mshr miss latency")
2087        .flags(total | nozero | nonan)
2088        ;
2089    overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses;
2090    for (int i = 0; i < system->maxMasters(); i++) {
2091        overallAvgMshrMissLatency.subname(i, system->getMasterName(i));
2092    }
2093
2094    // mshrUncacheable latency formulas
2095    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2096        MemCmd cmd(access_idx);
2097        const string &cstr = cmd.toString();
2098
2099        avgMshrUncacheableLatency[access_idx]
2100            .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency")
2101            .desc("average " + cstr + " mshr uncacheable latency")
2102            .flags(total | nozero | nonan)
2103            ;
2104        avgMshrUncacheableLatency[access_idx] =
2105            mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx];
2106
2107        for (int i = 0; i < system->maxMasters(); i++) {
2108            avgMshrUncacheableLatency[access_idx].subname(
2109                i, system->getMasterName(i));
2110        }
2111    }
2112
2113    overallAvgMshrUncacheableLatency
2114        .name(name() + ".overall_avg_mshr_uncacheable_latency")
2115        .desc("average overall mshr uncacheable latency")
2116        .flags(total | nozero | nonan)
2117        ;
2118    overallAvgMshrUncacheableLatency =
2119        overallMshrUncacheableLatency / overallMshrUncacheable;
2120    for (int i = 0; i < system->maxMasters(); i++) {
2121        overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i));
2122    }
2123
2124    replacements
2125        .name(name() + ".replacements")
2126        .desc("number of replacements")
2127        ;
2128}
2129
2130///////////////
2131//
2132// CpuSidePort
2133//
2134///////////////
2135bool
2136BaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt)
2137{
2138    // Snoops shouldn't happen when bypassing caches
2139    assert(!cache->system->bypassCaches());
2140
2141    assert(pkt->isResponse());
2142
2143    // Express snoop responses from master to slave, e.g., from L1 to L2
2144    cache->recvTimingSnoopResp(pkt);
2145    return true;
2146}
2147
2148
2149bool
2150BaseCache::CpuSidePort::tryTiming(PacketPtr pkt)
2151{
2152    if (cache->system->bypassCaches() || pkt->isExpressSnoop()) {
2153        // always let express snoop packets through even if blocked
2154        return true;
2155    } else if (blocked || mustSendRetry) {
2156        // either already committed to send a retry, or blocked
2157        mustSendRetry = true;
2158        return false;
2159    }
2160    mustSendRetry = false;
2161    return true;
2162}
2163
2164bool
2165BaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt)
2166{
2167    assert(pkt->isRequest());
2168
2169    if (cache->system->bypassCaches()) {
2170        // Just forward the packet if caches are disabled.
2171        // @todo This should really enqueue the packet rather
2172        bool M5_VAR_USED success = cache->memSidePort.sendTimingReq(pkt);
2173        assert(success);
2174        return true;
2175    } else if (tryTiming(pkt)) {
2176        cache->recvTimingReq(pkt);
2177        return true;
2178    }
2179    return false;
2180}
2181
2182Tick
2183BaseCache::CpuSidePort::recvAtomic(PacketPtr pkt)
2184{
2185    if (cache->system->bypassCaches()) {
2186        // Forward the request if the system is in cache bypass mode.
2187        return cache->memSidePort.sendAtomic(pkt);
2188    } else {
2189        return cache->recvAtomic(pkt);
2190    }
2191}
2192
2193void
2194BaseCache::CpuSidePort::recvFunctional(PacketPtr pkt)
2195{
2196    if (cache->system->bypassCaches()) {
2197        // The cache should be flushed if we are in cache bypass mode,
2198        // so we don't need to check if we need to update anything.
2199        cache->memSidePort.sendFunctional(pkt);
2200        return;
2201    }
2202
2203    // functional request
2204    cache->functionalAccess(pkt, true);
2205}
2206
2207AddrRangeList
2208BaseCache::CpuSidePort::getAddrRanges() const
2209{
2210    return cache->getAddrRanges();
2211}
2212
2213
2214BaseCache::
2215CpuSidePort::CpuSidePort(const std::string &_name, BaseCache *_cache,
2216                         const std::string &_label)
2217    : CacheSlavePort(_name, _cache, _label), cache(_cache)
2218{
2219}
2220
2221///////////////
2222//
2223// MemSidePort
2224//
2225///////////////
2226bool
2227BaseCache::MemSidePort::recvTimingResp(PacketPtr pkt)
2228{
2229    cache->recvTimingResp(pkt);
2230    return true;
2231}
2232
2233// Express snooping requests to memside port
2234void
2235BaseCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt)
2236{
2237    // Snoops shouldn't happen when bypassing caches
2238    assert(!cache->system->bypassCaches());
2239
2240    // handle snooping requests
2241    cache->recvTimingSnoopReq(pkt);
2242}
2243
2244Tick
2245BaseCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt)
2246{
2247    // Snoops shouldn't happen when bypassing caches
2248    assert(!cache->system->bypassCaches());
2249
2250    return cache->recvAtomicSnoop(pkt);
2251}
2252
2253void
2254BaseCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt)
2255{
2256    // Snoops shouldn't happen when bypassing caches
2257    assert(!cache->system->bypassCaches());
2258
2259    // functional snoop (note that in contrast to atomic we don't have
2260    // a specific functionalSnoop method, as they have the same
2261    // behaviour regardless)
2262    cache->functionalAccess(pkt, false);
2263}
2264
2265void
2266BaseCache::CacheReqPacketQueue::sendDeferredPacket()
2267{
2268    // sanity check
2269    assert(!waitingOnRetry);
2270
2271    // there should never be any deferred request packets in the
2272    // queue, instead we resly on the cache to provide the packets
2273    // from the MSHR queue or write queue
2274    assert(deferredPacketReadyTime() == MaxTick);
2275
2276    // check for request packets (requests & writebacks)
2277    QueueEntry* entry = cache.getNextQueueEntry();
2278
2279    if (!entry) {
2280        // can happen if e.g. we attempt a writeback and fail, but
2281        // before the retry, the writeback is eliminated because
2282        // we snoop another cache's ReadEx.
2283    } else {
2284        // let our snoop responses go first if there are responses to
2285        // the same addresses
2286        if (checkConflictingSnoop(entry->blkAddr)) {
2287            return;
2288        }
2289        waitingOnRetry = entry->sendPacket(cache);
2290    }
2291
2292    // if we succeeded and are not waiting for a retry, schedule the
2293    // next send considering when the next queue is ready, note that
2294    // snoop responses have their own packet queue and thus schedule
2295    // their own events
2296    if (!waitingOnRetry) {
2297        schedSendEvent(cache.nextQueueReadyTime());
2298    }
2299}
2300
2301BaseCache::MemSidePort::MemSidePort(const std::string &_name,
2302                                    BaseCache *_cache,
2303                                    const std::string &_label)
2304    : CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue),
2305      _reqQueue(*_cache, *this, _snoopRespQueue, _label),
2306      _snoopRespQueue(*_cache, *this, _label), cache(_cache)
2307{
2308}
2309