base.cc revision 11484:08b33c52a16d
17586SAli.Saidi@arm.com/* 27586SAli.Saidi@arm.com * Copyright (c) 2012-2013 ARM Limited 37586SAli.Saidi@arm.com * All rights reserved. 47586SAli.Saidi@arm.com * 57586SAli.Saidi@arm.com * The license below extends only to copyright in the software and shall 67586SAli.Saidi@arm.com * not be construed as granting a license to any other intellectual 77586SAli.Saidi@arm.com * property including but not limited to intellectual property relating 87586SAli.Saidi@arm.com * to a hardware implementation of the functionality of the software 97586SAli.Saidi@arm.com * licensed hereunder. You may use the software subject to the license 107586SAli.Saidi@arm.com * terms below provided that you ensure that this notice is replicated 117586SAli.Saidi@arm.com * unmodified and in its entirety in all distributions of the software, 127586SAli.Saidi@arm.com * modified or unmodified, in source code or in binary form. 137905SBrad.Beckmann@amd.com * 145323Sgblack@eecs.umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 152934Sktlim@umich.edu * All rights reserved. 162934Sktlim@umich.edu * 172934Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 182934Sktlim@umich.edu * modification, are permitted provided that the following conditions are 192934Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 202934Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 212934Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 222934Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 232934Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 242934Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 252934Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 262934Sktlim@umich.edu * this software without specific prior written permission. 272934Sktlim@umich.edu * 282934Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292934Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302934Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312934Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322934Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332934Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342934Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352934Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362934Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372934Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382934Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392934Sktlim@umich.edu * 402934Sktlim@umich.edu * Authors: Erik Hallnor 412934Sktlim@umich.edu */ 422934Sktlim@umich.edu 432995Ssaidi@eecs.umich.edu/** 442934Sktlim@umich.edu * @file 452934Sktlim@umich.edu * Definition of BaseCache functions. 462934Sktlim@umich.edu */ 472934Sktlim@umich.edu 482934Sktlim@umich.edu#include "debug/Cache.hh" 492934Sktlim@umich.edu#include "debug/Drain.hh" 502934Sktlim@umich.edu#include "mem/cache/tags/fa_lru.hh" 512934Sktlim@umich.edu#include "mem/cache/tags/lru.hh" 526122SSteve.Reinhardt@amd.com#include "mem/cache/tags/random_repl.hh" 536122SSteve.Reinhardt@amd.com#include "mem/cache/base.hh" 546122SSteve.Reinhardt@amd.com#include "mem/cache/cache.hh" 556122SSteve.Reinhardt@amd.com#include "mem/cache/mshr.hh" 566122SSteve.Reinhardt@amd.com#include "sim/full_system.hh" 574520Ssaidi@eecs.umich.edu 584520Ssaidi@eecs.umich.eduusing namespace std; 594982Ssaidi@eecs.umich.edu 604520Ssaidi@eecs.umich.eduBaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, 614520Ssaidi@eecs.umich.edu BaseCache *_cache, 622934Sktlim@umich.edu const std::string &_label) 632934Sktlim@umich.edu : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label), 643005Sstever@eecs.umich.edu blocked(false), mustSendRetry(false), sendRetryEvent(this) 653005Sstever@eecs.umich.edu{ 663304Sstever@eecs.umich.edu} 672995Ssaidi@eecs.umich.edu 682934Sktlim@umich.eduBaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size) 696122SSteve.Reinhardt@amd.com : MemObject(p), 704965Ssaidi@eecs.umich.edu cpuSidePort(nullptr), memSidePort(nullptr), 715266Sksewell@umich.edu mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below 722934Sktlim@umich.edu writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below 732934Sktlim@umich.edu blkSize(blk_size), 742934Sktlim@umich.edu lookupLatency(p->hit_latency), 752934Sktlim@umich.edu forwardLatency(p->hit_latency), 762934Sktlim@umich.edu fillLatency(p->response_latency), 772995Ssaidi@eecs.umich.edu responseLatency(p->response_latency), 782934Sktlim@umich.edu numTarget(p->tgts_per_mshr), 792934Sktlim@umich.edu forwardSnoops(true), 802934Sktlim@umich.edu isReadOnly(p->is_read_only), 812934Sktlim@umich.edu blocked(0), 822934Sktlim@umich.edu order(0), 832995Ssaidi@eecs.umich.edu noTargetMSHR(nullptr), 842934Sktlim@umich.edu missCount(p->max_miss_count), 852934Sktlim@umich.edu addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 862953Sktlim@umich.edu system(p->system) 875478Snate@binkert.org{ 882934Sktlim@umich.edu // the MSHR queue has no reserve entries as we check the MSHR 893449Shsul@eecs.umich.edu // queue on every single allocation, whereas the write queue has 902934Sktlim@umich.edu // as many reserve entries as we have MSHRs, since every MSHR may 912934Sktlim@umich.edu // eventually require a writeback, and we do not check the write 922934Sktlim@umich.edu // buffer before committing to an MSHR 932934Sktlim@umich.edu 942934Sktlim@umich.edu // forward snoops is overridden in init() once we can query 957014SBrad.Beckmann@amd.com // whether the connected master is actually snooping or not 966765SBrad.Beckmann@amd.com} 976765SBrad.Beckmann@amd.com 986765SBrad.Beckmann@amd.comvoid 996765SBrad.Beckmann@amd.comBaseCache::CacheSlavePort::setBlocked() 1006765SBrad.Beckmann@amd.com{ 1017014SBrad.Beckmann@amd.com assert(!blocked); 1027014SBrad.Beckmann@amd.com DPRINTF(CachePort, "Port is blocking new requests\n"); 1036765SBrad.Beckmann@amd.com blocked = true; 1046765SBrad.Beckmann@amd.com // if we already scheduled a retry in this cycle, but it has not yet 1056765SBrad.Beckmann@amd.com // happened, cancel it 1066765SBrad.Beckmann@amd.com if (sendRetryEvent.scheduled()) { 1076765SBrad.Beckmann@amd.com owner.deschedule(sendRetryEvent); 1086765SBrad.Beckmann@amd.com DPRINTF(CachePort, "Port descheduled retry\n"); 1096765SBrad.Beckmann@amd.com mustSendRetry = true; 1106893SBrad.Beckmann@amd.com } 1116893SBrad.Beckmann@amd.com} 1126893SBrad.Beckmann@amd.com 1136893SBrad.Beckmann@amd.comvoid 1146893SBrad.Beckmann@amd.comBaseCache::CacheSlavePort::clearBlocked() 1156893SBrad.Beckmann@amd.com{ 1167014SBrad.Beckmann@amd.com assert(blocked); 1176893SBrad.Beckmann@amd.com DPRINTF(CachePort, "Port is accepting new requests\n"); 1186765SBrad.Beckmann@amd.com blocked = false; 1196765SBrad.Beckmann@amd.com if (mustSendRetry) { 1206765SBrad.Beckmann@amd.com // @TODO: need to find a better time (next cycle?) 1216765SBrad.Beckmann@amd.com owner.schedule(sendRetryEvent, curTick() + 1); 1226765SBrad.Beckmann@amd.com } 1236765SBrad.Beckmann@amd.com} 1246765SBrad.Beckmann@amd.com 1256765SBrad.Beckmann@amd.comvoid 1266765SBrad.Beckmann@amd.comBaseCache::CacheSlavePort::processSendRetry() 1276893SBrad.Beckmann@amd.com{ 1287633SBrad.Beckmann@amd.com DPRINTF(CachePort, "Port is sending retry\n"); 1297633SBrad.Beckmann@amd.com 1306893SBrad.Beckmann@amd.com // reset the flag and call retry 1317633SBrad.Beckmann@amd.com mustSendRetry = false; 1326765SBrad.Beckmann@amd.com sendRetryReq(); 1336765SBrad.Beckmann@amd.com} 1346765SBrad.Beckmann@amd.com 1356765SBrad.Beckmann@amd.comvoid 1366765SBrad.Beckmann@amd.comBaseCache::init() 1376765SBrad.Beckmann@amd.com{ 1386765SBrad.Beckmann@amd.com if (!cpuSidePort->isConnected() || !memSidePort->isConnected()) 1396765SBrad.Beckmann@amd.com fatal("Cache ports on %s are not connected\n", name()); 1406765SBrad.Beckmann@amd.com cpuSidePort->sendRangeChange(); 1416765SBrad.Beckmann@amd.com forwardSnoops = cpuSidePort->isSnooping(); 1426765SBrad.Beckmann@amd.com} 1436765SBrad.Beckmann@amd.com 1446765SBrad.Beckmann@amd.comBaseMasterPort & 1453584Ssaidi@eecs.umich.eduBaseCache::getMasterPort(const std::string &if_name, PortID idx) 1464486Sbinkertn@umich.edu{ 1474486Sbinkertn@umich.edu if (if_name == "mem_side") { 1484486Sbinkertn@umich.edu return *memSidePort; 1494486Sbinkertn@umich.edu } else { 1504486Sbinkertn@umich.edu return MemObject::getMasterPort(if_name, idx); 1514486Sbinkertn@umich.edu } 1524486Sbinkertn@umich.edu} 1533584Ssaidi@eecs.umich.edu 1543584Ssaidi@eecs.umich.eduBaseSlavePort & 1553584Ssaidi@eecs.umich.eduBaseCache::getSlavePort(const std::string &if_name, PortID idx) 1563584Ssaidi@eecs.umich.edu{ 1573584Ssaidi@eecs.umich.edu if (if_name == "cpu_side") { 1583743Sgblack@eecs.umich.edu return *cpuSidePort; 1596122SSteve.Reinhardt@amd.com } else { 1604972Ssaidi@eecs.umich.edu return MemObject::getSlavePort(if_name, idx); 1613743Sgblack@eecs.umich.edu } 1624104Ssaidi@eecs.umich.edu} 1633743Sgblack@eecs.umich.edu 1643823Ssaidi@eecs.umich.edubool 1653814Ssaidi@eecs.umich.eduBaseCache::inRange(Addr addr) const 1663743Sgblack@eecs.umich.edu{ 1673743Sgblack@eecs.umich.edu for (const auto& r : addrRanges) { 1683584Ssaidi@eecs.umich.edu if (r.contains(addr)) { 1693814Ssaidi@eecs.umich.edu return true; 1703584Ssaidi@eecs.umich.edu } 1713745Sgblack@eecs.umich.edu } 1723745Sgblack@eecs.umich.edu return false; 1733745Sgblack@eecs.umich.edu} 1743584Ssaidi@eecs.umich.edu 1753898Ssaidi@eecs.umich.eduvoid 1763898Ssaidi@eecs.umich.eduBaseCache::regStats() 1773898Ssaidi@eecs.umich.edu{ 1784103Ssaidi@eecs.umich.edu using namespace Stats; 1794103Ssaidi@eecs.umich.edu 1804103Ssaidi@eecs.umich.edu // Hit statistics 1813745Sgblack@eecs.umich.edu for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1823745Sgblack@eecs.umich.edu MemCmd cmd(access_idx); 1833745Sgblack@eecs.umich.edu const string &cstr = cmd.toString(); 1843584Ssaidi@eecs.umich.edu 1853584Ssaidi@eecs.umich.edu hits[access_idx] 1863584Ssaidi@eecs.umich.edu .init(system->maxMasters()) 1878061SAli.Saidi@ARM.com .name(name() + "." + cstr + "_hits") 1888061SAli.Saidi@ARM.com .desc("number of " + cstr + " hits") 1898061SAli.Saidi@ARM.com .flags(total | nozero | nonan) 1907586SAli.Saidi@arm.com ; 1917586SAli.Saidi@arm.com for (int i = 0; i < system->maxMasters(); i++) { 1927586SAli.Saidi@arm.com hits[access_idx].subname(i, system->getMasterName(i)); 1937586SAli.Saidi@arm.com } 1947586SAli.Saidi@arm.com } 1957586SAli.Saidi@arm.com 1967586SAli.Saidi@arm.com// These macros make it easier to sum the right subset of commands and 1977586SAli.Saidi@arm.com// to change the subset of commands that are considered "demand" vs 1987586SAli.Saidi@arm.com// "non-demand" 1997586SAli.Saidi@arm.com#define SUM_DEMAND(s) \ 2007586SAli.Saidi@arm.com (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::WriteLineReq] + \ 2017586SAli.Saidi@arm.com s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq]) 2027586SAli.Saidi@arm.com 2037586SAli.Saidi@arm.com// should writebacks be included here? prior code was inconsistent... 2047586SAli.Saidi@arm.com#define SUM_NON_DEMAND(s) \ 2057586SAli.Saidi@arm.com (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq]) 2067586SAli.Saidi@arm.com 2077586SAli.Saidi@arm.com demandHits 2087586SAli.Saidi@arm.com .name(name() + ".demand_hits") 2097586SAli.Saidi@arm.com .desc("number of demand (read+write) hits") 2107586SAli.Saidi@arm.com .flags(total | nozero | nonan) 2117586SAli.Saidi@arm.com ; 2127586SAli.Saidi@arm.com demandHits = SUM_DEMAND(hits); 2137586SAli.Saidi@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2147586SAli.Saidi@arm.com demandHits.subname(i, system->getMasterName(i)); 2157586SAli.Saidi@arm.com } 2167586SAli.Saidi@arm.com 2178212SAli.Saidi@ARM.com overallHits 2188212SAli.Saidi@ARM.com .name(name() + ".overall_hits") 2198212SAli.Saidi@ARM.com .desc("number of overall hits") 2208212SAli.Saidi@ARM.com .flags(total | nozero | nonan) 2218212SAli.Saidi@ARM.com ; 2228212SAli.Saidi@ARM.com overallHits = demandHits + SUM_NON_DEMAND(hits); 2238212SAli.Saidi@ARM.com for (int i = 0; i < system->maxMasters(); i++) { 2248061SAli.Saidi@ARM.com overallHits.subname(i, system->getMasterName(i)); 2258061SAli.Saidi@ARM.com } 2268061SAli.Saidi@ARM.com 2278212SAli.Saidi@ARM.com // Miss statistics 2288212SAli.Saidi@ARM.com for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2298061SAli.Saidi@ARM.com MemCmd cmd(access_idx); 2308212SAli.Saidi@ARM.com const string &cstr = cmd.toString(); 2317586SAli.Saidi@arm.com 2328212SAli.Saidi@ARM.com misses[access_idx] 2338212SAli.Saidi@ARM.com .init(system->maxMasters()) 2348212SAli.Saidi@ARM.com .name(name() + "." + cstr + "_misses") 2358212SAli.Saidi@ARM.com .desc("number of " + cstr + " misses") 2368212SAli.Saidi@ARM.com .flags(total | nozero | nonan) 2378212SAli.Saidi@ARM.com ; 2388287SAli.Saidi@ARM.com for (int i = 0; i < system->maxMasters(); i++) { 2398287SAli.Saidi@ARM.com misses[access_idx].subname(i, system->getMasterName(i)); 2408287SAli.Saidi@ARM.com } 2418287SAli.Saidi@ARM.com } 2428287SAli.Saidi@ARM.com 2438287SAli.Saidi@ARM.com demandMisses 2448287SAli.Saidi@ARM.com .name(name() + ".demand_misses") 2458212SAli.Saidi@ARM.com .desc("number of demand (read+write) misses") 2468212SAli.Saidi@ARM.com .flags(total | nozero | nonan) 2478212SAli.Saidi@ARM.com ; 2488212SAli.Saidi@ARM.com demandMisses = SUM_DEMAND(misses); 2498212SAli.Saidi@ARM.com for (int i = 0; i < system->maxMasters(); i++) { 2508212SAli.Saidi@ARM.com demandMisses.subname(i, system->getMasterName(i)); 2518212SAli.Saidi@ARM.com } 2528212SAli.Saidi@ARM.com 2538212SAli.Saidi@ARM.com overallMisses 2548287SAli.Saidi@ARM.com .name(name() + ".overall_misses") 2558212SAli.Saidi@ARM.com .desc("number of overall misses") 2568212SAli.Saidi@ARM.com .flags(total | nozero | nonan) 2578212SAli.Saidi@ARM.com ; 2587586SAli.Saidi@arm.com overallMisses = demandMisses + SUM_NON_DEMAND(misses); 2598145SAli.Saidi@ARM.com for (int i = 0; i < system->maxMasters(); i++) { 2607586SAli.Saidi@arm.com overallMisses.subname(i, system->getMasterName(i)); 2617586SAli.Saidi@arm.com } 2627586SAli.Saidi@arm.com 2637586SAli.Saidi@arm.com // Miss latency statistics 2647586SAli.Saidi@arm.com for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2657949SAli.Saidi@ARM.com MemCmd cmd(access_idx); 2667586SAli.Saidi@arm.com const string &cstr = cmd.toString(); 2677586SAli.Saidi@arm.com 2687586SAli.Saidi@arm.com missLatency[access_idx] 2697586SAli.Saidi@arm.com .init(system->maxMasters()) 2705222Sksewell@umich.edu .name(name() + "." + cstr + "_miss_latency") 2715222Sksewell@umich.edu .desc("number of " + cstr + " miss cycles") 2725222Sksewell@umich.edu .flags(total | nozero | nonan) 2735222Sksewell@umich.edu ; 2745222Sksewell@umich.edu for (int i = 0; i < system->maxMasters(); i++) { 2755222Sksewell@umich.edu missLatency[access_idx].subname(i, system->getMasterName(i)); 2765222Sksewell@umich.edu } 2775222Sksewell@umich.edu } 2785222Sksewell@umich.edu 2795222Sksewell@umich.edu demandMissLatency 2805222Sksewell@umich.edu .name(name() + ".demand_miss_latency") 2815222Sksewell@umich.edu .desc("number of demand (read+write) miss cycles") 2826122SSteve.Reinhardt@amd.com .flags(total | nozero | nonan) 2835222Sksewell@umich.edu ; 2845222Sksewell@umich.edu demandMissLatency = SUM_DEMAND(missLatency); 2855222Sksewell@umich.edu for (int i = 0; i < system->maxMasters(); i++) { 2865222Sksewell@umich.edu demandMissLatency.subname(i, system->getMasterName(i)); 2875222Sksewell@umich.edu } 2885222Sksewell@umich.edu 2895222Sksewell@umich.edu overallMissLatency 2905222Sksewell@umich.edu .name(name() + ".overall_miss_latency") 2915222Sksewell@umich.edu .desc("number of overall miss cycles") 2925222Sksewell@umich.edu .flags(total | nozero | nonan) 2935222Sksewell@umich.edu ; 2945222Sksewell@umich.edu overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 2955222Sksewell@umich.edu for (int i = 0; i < system->maxMasters(); i++) { 2965222Sksewell@umich.edu overallMissLatency.subname(i, system->getMasterName(i)); 2975222Sksewell@umich.edu } 2985222Sksewell@umich.edu 2995222Sksewell@umich.edu // access formulas 3005478Snate@binkert.org for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3015222Sksewell@umich.edu MemCmd cmd(access_idx); 3025222Sksewell@umich.edu const string &cstr = cmd.toString(); 3035222Sksewell@umich.edu 3045222Sksewell@umich.edu accesses[access_idx] 3055222Sksewell@umich.edu .name(name() + "." + cstr + "_accesses") 3065222Sksewell@umich.edu .desc("number of " + cstr + " accesses(hits+misses)") 3075323Sgblack@eecs.umich.edu .flags(total | nozero | nonan) 3085357Sgblack@eecs.umich.edu ; 3095323Sgblack@eecs.umich.edu accesses[access_idx] = hits[access_idx] + misses[access_idx]; 3105323Sgblack@eecs.umich.edu 3117905SBrad.Beckmann@amd.com for (int i = 0; i < system->maxMasters(); i++) { 3127905SBrad.Beckmann@amd.com accesses[access_idx].subname(i, system->getMasterName(i)); 3137905SBrad.Beckmann@amd.com } 3147905SBrad.Beckmann@amd.com } 3157905SBrad.Beckmann@amd.com 3167905SBrad.Beckmann@amd.com demandAccesses 3177905SBrad.Beckmann@amd.com .name(name() + ".demand_accesses") 3187905SBrad.Beckmann@amd.com .desc("number of demand (read+write) accesses") 3197905SBrad.Beckmann@amd.com .flags(total | nozero | nonan) 3207905SBrad.Beckmann@amd.com ; 3217905SBrad.Beckmann@amd.com demandAccesses = demandHits + demandMisses; 3227905SBrad.Beckmann@amd.com for (int i = 0; i < system->maxMasters(); i++) { 3237905SBrad.Beckmann@amd.com demandAccesses.subname(i, system->getMasterName(i)); 3247905SBrad.Beckmann@amd.com } 3257905SBrad.Beckmann@amd.com 3267905SBrad.Beckmann@amd.com overallAccesses 3277905SBrad.Beckmann@amd.com .name(name() + ".overall_accesses") 3287905SBrad.Beckmann@amd.com .desc("number of overall (read+write) accesses") 3297905SBrad.Beckmann@amd.com .flags(total | nozero | nonan) 3307905SBrad.Beckmann@amd.com ; 3317905SBrad.Beckmann@amd.com overallAccesses = overallHits + overallMisses; 3327905SBrad.Beckmann@amd.com for (int i = 0; i < system->maxMasters(); i++) { 3337905SBrad.Beckmann@amd.com overallAccesses.subname(i, system->getMasterName(i)); 3347905SBrad.Beckmann@amd.com } 3357905SBrad.Beckmann@amd.com 3367905SBrad.Beckmann@amd.com // miss rate formulas 3377905SBrad.Beckmann@amd.com for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3387905SBrad.Beckmann@amd.com MemCmd cmd(access_idx); 3395613Sgblack@eecs.umich.edu const string &cstr = cmd.toString(); 3405613Sgblack@eecs.umich.edu 3415613Sgblack@eecs.umich.edu missRate[access_idx] 3425133Sgblack@eecs.umich.edu .name(name() + "." + cstr + "_miss_rate") 3435133Sgblack@eecs.umich.edu .desc("miss rate for " + cstr + " accesses") 3445133Sgblack@eecs.umich.edu .flags(total | nozero | nonan) 3455133Sgblack@eecs.umich.edu ; 3465133Sgblack@eecs.umich.edu missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 3476802Sgblack@eecs.umich.edu 3486802Sgblack@eecs.umich.edu for (int i = 0; i < system->maxMasters(); i++) { 3495133Sgblack@eecs.umich.edu missRate[access_idx].subname(i, system->getMasterName(i)); 3505450Sgblack@eecs.umich.edu } 3515613Sgblack@eecs.umich.edu } 3525613Sgblack@eecs.umich.edu 3535638Sgblack@eecs.umich.edu demandMissRate 3547905SBrad.Beckmann@amd.com .name(name() + ".demand_miss_rate") 3557905SBrad.Beckmann@amd.com .desc("miss rate for demand accesses") 3567905SBrad.Beckmann@amd.com .flags(total | nozero | nonan) 3577905SBrad.Beckmann@amd.com ; 3587937SBrad.Beckmann@amd.com demandMissRate = demandMisses / demandAccesses; 3597937SBrad.Beckmann@amd.com for (int i = 0; i < system->maxMasters(); i++) { 3607937SBrad.Beckmann@amd.com demandMissRate.subname(i, system->getMasterName(i)); 3617905SBrad.Beckmann@amd.com } 3627905SBrad.Beckmann@amd.com 3635613Sgblack@eecs.umich.edu overallMissRate 3645613Sgblack@eecs.umich.edu .name(name() + ".overall_miss_rate") 3655613Sgblack@eecs.umich.edu .desc("miss rate for overall accesses") 3665841Sgblack@eecs.umich.edu .flags(total | nozero | nonan) 3675841Sgblack@eecs.umich.edu ; 3685841Sgblack@eecs.umich.edu overallMissRate = overallMisses / overallAccesses; 3695841Sgblack@eecs.umich.edu for (int i = 0; i < system->maxMasters(); i++) { 3705841Sgblack@eecs.umich.edu overallMissRate.subname(i, system->getMasterName(i)); 3715841Sgblack@eecs.umich.edu } 3725841Sgblack@eecs.umich.edu 3735615Sgblack@eecs.umich.edu // miss latency formulas 3745615Sgblack@eecs.umich.edu for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3755615Sgblack@eecs.umich.edu MemCmd cmd(access_idx); 3765615Sgblack@eecs.umich.edu const string &cstr = cmd.toString(); 3775641Sgblack@eecs.umich.edu 3786135Sgblack@eecs.umich.edu avgMissLatency[access_idx] 3796135Sgblack@eecs.umich.edu .name(name() + "." + cstr + "_avg_miss_latency") 3806135Sgblack@eecs.umich.edu .desc("average " + cstr + " miss latency") 3816135Sgblack@eecs.umich.edu .flags(total | nozero | nonan) 3826135Sgblack@eecs.umich.edu ; 3836135Sgblack@eecs.umich.edu avgMissLatency[access_idx] = 3846135Sgblack@eecs.umich.edu missLatency[access_idx] / misses[access_idx]; 3855644Sgblack@eecs.umich.edu 3866135Sgblack@eecs.umich.edu for (int i = 0; i < system->maxMasters(); i++) { 3875644Sgblack@eecs.umich.edu avgMissLatency[access_idx].subname(i, system->getMasterName(i)); 3885644Sgblack@eecs.umich.edu } 3895644Sgblack@eecs.umich.edu } 3906135Sgblack@eecs.umich.edu 3915644Sgblack@eecs.umich.edu demandAvgMissLatency 3925644Sgblack@eecs.umich.edu .name(name() + ".demand_avg_miss_latency") 3935644Sgblack@eecs.umich.edu .desc("average overall miss latency") 3945843Sgblack@eecs.umich.edu .flags(total | nozero | nonan) 3955843Sgblack@eecs.umich.edu ; 3965843Sgblack@eecs.umich.edu demandAvgMissLatency = demandMissLatency / demandMisses; 3975843Sgblack@eecs.umich.edu for (int i = 0; i < system->maxMasters(); i++) { 3985843Sgblack@eecs.umich.edu demandAvgMissLatency.subname(i, system->getMasterName(i)); 3995843Sgblack@eecs.umich.edu } 4005843Sgblack@eecs.umich.edu 4015843Sgblack@eecs.umich.edu overallAvgMissLatency 4025843Sgblack@eecs.umich.edu .name(name() + ".overall_avg_miss_latency") 4035843Sgblack@eecs.umich.edu .desc("average overall miss latency") 4045843Sgblack@eecs.umich.edu .flags(total | nozero | nonan) 4056044Sgblack@eecs.umich.edu ; 4065843Sgblack@eecs.umich.edu overallAvgMissLatency = overallMissLatency / overallMisses; 4076074Sgblack@eecs.umich.edu for (int i = 0; i < system->maxMasters(); i++) { 4086135Sgblack@eecs.umich.edu overallAvgMissLatency.subname(i, system->getMasterName(i)); 4096135Sgblack@eecs.umich.edu } 4106135Sgblack@eecs.umich.edu 4116135Sgblack@eecs.umich.edu blocked_cycles.init(NUM_BLOCKED_CAUSES); 4126135Sgblack@eecs.umich.edu blocked_cycles 4136135Sgblack@eecs.umich.edu .name(name() + ".blocked_cycles") 4146135Sgblack@eecs.umich.edu .desc("number of cycles access was blocked") 4156135Sgblack@eecs.umich.edu .subname(Blocked_NoMSHRs, "no_mshrs") 4166135Sgblack@eecs.umich.edu .subname(Blocked_NoTargets, "no_targets") 4176135Sgblack@eecs.umich.edu ; 4186135Sgblack@eecs.umich.edu 4196135Sgblack@eecs.umich.edu 4206135Sgblack@eecs.umich.edu blocked_causes.init(NUM_BLOCKED_CAUSES); 4216135Sgblack@eecs.umich.edu blocked_causes 4226135Sgblack@eecs.umich.edu .name(name() + ".blocked") 4236135Sgblack@eecs.umich.edu .desc("number of cycles access was blocked") 4246135Sgblack@eecs.umich.edu .subname(Blocked_NoMSHRs, "no_mshrs") 4256135Sgblack@eecs.umich.edu .subname(Blocked_NoTargets, "no_targets") 4266135Sgblack@eecs.umich.edu ; 4276135Sgblack@eecs.umich.edu 4286135Sgblack@eecs.umich.edu avg_blocked 4296135Sgblack@eecs.umich.edu .name(name() + ".avg_blocked_cycles") 4306135Sgblack@eecs.umich.edu .desc("average number of cycles each access was blocked") 4315641Sgblack@eecs.umich.edu .subname(Blocked_NoMSHRs, "no_mshrs") 4327925Sgblack@eecs.umich.edu .subname(Blocked_NoTargets, "no_targets") 4337925Sgblack@eecs.umich.edu ; 4347925Sgblack@eecs.umich.edu 4357925Sgblack@eecs.umich.edu avg_blocked = blocked_cycles / blocked_causes; 4367925Sgblack@eecs.umich.edu 4377925Sgblack@eecs.umich.edu unusedPrefetches 4387925Sgblack@eecs.umich.edu .name(name() + ".unused_prefetches") 4397925Sgblack@eecs.umich.edu .desc("number of HardPF blocks evicted w/o reference") 4407925Sgblack@eecs.umich.edu .flags(nozero) 4417925Sgblack@eecs.umich.edu ; 4427925Sgblack@eecs.umich.edu 4437925Sgblack@eecs.umich.edu writebacks 4447925Sgblack@eecs.umich.edu .init(system->maxMasters()) 4457925Sgblack@eecs.umich.edu .name(name() + ".writebacks") 4467925Sgblack@eecs.umich.edu .desc("number of writebacks") 4477925Sgblack@eecs.umich.edu .flags(total | nozero | nonan) 4487925Sgblack@eecs.umich.edu ; 4497925Sgblack@eecs.umich.edu for (int i = 0; i < system->maxMasters(); i++) { 4505613Sgblack@eecs.umich.edu writebacks.subname(i, system->getMasterName(i)); 4515613Sgblack@eecs.umich.edu } 4527905SBrad.Beckmann@amd.com 4537905SBrad.Beckmann@amd.com // MSHR statistics 4545613Sgblack@eecs.umich.edu // MSHR hit statistics 4555450Sgblack@eecs.umich.edu for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4565450Sgblack@eecs.umich.edu MemCmd cmd(access_idx); 4577069Snate@binkert.org const string &cstr = cmd.toString(); 4585450Sgblack@eecs.umich.edu 4595450Sgblack@eecs.umich.edu mshr_hits[access_idx] 4605450Sgblack@eecs.umich.edu .init(system->maxMasters()) 4615450Sgblack@eecs.umich.edu .name(name() + "." + cstr + "_mshr_hits") 4625450Sgblack@eecs.umich.edu .desc("number of " + cstr + " MSHR hits") 4635450Sgblack@eecs.umich.edu .flags(total | nozero | nonan) 4645450Sgblack@eecs.umich.edu ; 4655450Sgblack@eecs.umich.edu for (int i = 0; i < system->maxMasters(); i++) { 4665450Sgblack@eecs.umich.edu mshr_hits[access_idx].subname(i, system->getMasterName(i)); 4675450Sgblack@eecs.umich.edu } 4686072Sgblack@eecs.umich.edu } 4695450Sgblack@eecs.umich.edu 4705450Sgblack@eecs.umich.edu demandMshrHits 4715330Sgblack@eecs.umich.edu .name(name() + ".demand_mshr_hits") 4725847Sgblack@eecs.umich.edu .desc("number of demand (read+write) MSHR hits") 4735845Sgblack@eecs.umich.edu .flags(total | nozero | nonan) 4745133Sgblack@eecs.umich.edu ; 4755133Sgblack@eecs.umich.edu demandMshrHits = SUM_DEMAND(mshr_hits); 4763584Ssaidi@eecs.umich.edu for (int i = 0; i < system->maxMasters(); i++) { 4773025Ssaidi@eecs.umich.edu demandMshrHits.subname(i, system->getMasterName(i)); 4782934Sktlim@umich.edu } 4792995Ssaidi@eecs.umich.edu 4802995Ssaidi@eecs.umich.edu overallMshrHits 4814981Ssaidi@eecs.umich.edu .name(name() + ".overall_mshr_hits") 4824981Ssaidi@eecs.umich.edu .desc("number of overall MSHR hits") 4834981Ssaidi@eecs.umich.edu .flags(total | nozero | nonan) 4844981Ssaidi@eecs.umich.edu ; 4853025Ssaidi@eecs.umich.edu overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 4863025Ssaidi@eecs.umich.edu for (int i = 0; i < system->maxMasters(); i++) { 4873025Ssaidi@eecs.umich.edu overallMshrHits.subname(i, system->getMasterName(i)); 4882934Sktlim@umich.edu } 4892934Sktlim@umich.edu 4905253Sksewell@umich.edu // MSHR miss statistics 4915263Sksewell@umich.edu for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4925253Sksewell@umich.edu MemCmd cmd(access_idx); 4935253Sksewell@umich.edu const string &cstr = cmd.toString(); 4945253Sksewell@umich.edu 4955253Sksewell@umich.edu mshr_misses[access_idx] 4965253Sksewell@umich.edu .init(system->maxMasters()) 4975253Sksewell@umich.edu .name(name() + "." + cstr + "_mshr_misses") 4985253Sksewell@umich.edu .desc("number of " + cstr + " MSHR misses") 4995253Sksewell@umich.edu .flags(total | nozero | nonan) 5005253Sksewell@umich.edu ; 5015253Sksewell@umich.edu for (int i = 0; i < system->maxMasters(); i++) { 5025253Sksewell@umich.edu mshr_misses[access_idx].subname(i, system->getMasterName(i)); 5035253Sksewell@umich.edu } 5045253Sksewell@umich.edu } 5055253Sksewell@umich.edu 5065253Sksewell@umich.edu demandMshrMisses 5075253Sksewell@umich.edu .name(name() + ".demand_mshr_misses") 5085253Sksewell@umich.edu .desc("number of demand (read+write) MSHR misses") 5095253Sksewell@umich.edu .flags(total | nozero | nonan) 5105253Sksewell@umich.edu ; 5115253Sksewell@umich.edu demandMshrMisses = SUM_DEMAND(mshr_misses); 5125253Sksewell@umich.edu for (int i = 0; i < system->maxMasters(); i++) { 5135253Sksewell@umich.edu demandMshrMisses.subname(i, system->getMasterName(i)); 5145253Sksewell@umich.edu } 5155253Sksewell@umich.edu 5165253Sksewell@umich.edu overallMshrMisses 5175253Sksewell@umich.edu .name(name() + ".overall_mshr_misses") 5185253Sksewell@umich.edu .desc("number of overall MSHR misses") 5195253Sksewell@umich.edu .flags(total | nozero | nonan) 5205253Sksewell@umich.edu ; 5215253Sksewell@umich.edu overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 5225253Sksewell@umich.edu for (int i = 0; i < system->maxMasters(); i++) { 5235253Sksewell@umich.edu overallMshrMisses.subname(i, system->getMasterName(i)); 5245253Sksewell@umich.edu } 5255253Sksewell@umich.edu 5265253Sksewell@umich.edu // MSHR miss latency statistics 5275253Sksewell@umich.edu for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5285253Sksewell@umich.edu MemCmd cmd(access_idx); 5295253Sksewell@umich.edu const string &cstr = cmd.toString(); 5305253Sksewell@umich.edu 5315253Sksewell@umich.edu mshr_miss_latency[access_idx] 5325253Sksewell@umich.edu .init(system->maxMasters()) 5335253Sksewell@umich.edu .name(name() + "." + cstr + "_mshr_miss_latency") 5345253Sksewell@umich.edu .desc("number of " + cstr + " MSHR miss cycles") 5355253Sksewell@umich.edu .flags(total | nozero | nonan) 5365253Sksewell@umich.edu ; 5375253Sksewell@umich.edu for (int i = 0; i < system->maxMasters(); i++) { 5385253Sksewell@umich.edu mshr_miss_latency[access_idx].subname(i, system->getMasterName(i)); 5395253Sksewell@umich.edu } 5405253Sksewell@umich.edu } 5415253Sksewell@umich.edu 5425253Sksewell@umich.edu demandMshrMissLatency 5435253Sksewell@umich.edu .name(name() + ".demand_mshr_miss_latency") 5445253Sksewell@umich.edu .desc("number of demand (read+write) MSHR miss cycles") 5455253Sksewell@umich.edu .flags(total | nozero | nonan) 5465253Sksewell@umich.edu ; 5475253Sksewell@umich.edu demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 5485253Sksewell@umich.edu for (int i = 0; i < system->maxMasters(); i++) { 5495253Sksewell@umich.edu demandMshrMissLatency.subname(i, system->getMasterName(i)); 5505253Sksewell@umich.edu } 5515253Sksewell@umich.edu 5525253Sksewell@umich.edu overallMshrMissLatency 5535253Sksewell@umich.edu .name(name() + ".overall_mshr_miss_latency") 5545253Sksewell@umich.edu .desc("number of overall MSHR miss cycles") 5555253Sksewell@umich.edu .flags(total | nozero | nonan) 5565253Sksewell@umich.edu ; 5575253Sksewell@umich.edu overallMshrMissLatency = 5585253Sksewell@umich.edu demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 5595253Sksewell@umich.edu for (int i = 0; i < system->maxMasters(); i++) { 560 overallMshrMissLatency.subname(i, system->getMasterName(i)); 561 } 562 563 // MSHR uncacheable statistics 564 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 565 MemCmd cmd(access_idx); 566 const string &cstr = cmd.toString(); 567 568 mshr_uncacheable[access_idx] 569 .init(system->maxMasters()) 570 .name(name() + "." + cstr + "_mshr_uncacheable") 571 .desc("number of " + cstr + " MSHR uncacheable") 572 .flags(total | nozero | nonan) 573 ; 574 for (int i = 0; i < system->maxMasters(); i++) { 575 mshr_uncacheable[access_idx].subname(i, system->getMasterName(i)); 576 } 577 } 578 579 overallMshrUncacheable 580 .name(name() + ".overall_mshr_uncacheable_misses") 581 .desc("number of overall MSHR uncacheable misses") 582 .flags(total | nozero | nonan) 583 ; 584 overallMshrUncacheable = 585 SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 586 for (int i = 0; i < system->maxMasters(); i++) { 587 overallMshrUncacheable.subname(i, system->getMasterName(i)); 588 } 589 590 // MSHR miss latency statistics 591 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 592 MemCmd cmd(access_idx); 593 const string &cstr = cmd.toString(); 594 595 mshr_uncacheable_lat[access_idx] 596 .init(system->maxMasters()) 597 .name(name() + "." + cstr + "_mshr_uncacheable_latency") 598 .desc("number of " + cstr + " MSHR uncacheable cycles") 599 .flags(total | nozero | nonan) 600 ; 601 for (int i = 0; i < system->maxMasters(); i++) { 602 mshr_uncacheable_lat[access_idx].subname( 603 i, system->getMasterName(i)); 604 } 605 } 606 607 overallMshrUncacheableLatency 608 .name(name() + ".overall_mshr_uncacheable_latency") 609 .desc("number of overall MSHR uncacheable cycles") 610 .flags(total | nozero | nonan) 611 ; 612 overallMshrUncacheableLatency = 613 SUM_DEMAND(mshr_uncacheable_lat) + 614 SUM_NON_DEMAND(mshr_uncacheable_lat); 615 for (int i = 0; i < system->maxMasters(); i++) { 616 overallMshrUncacheableLatency.subname(i, system->getMasterName(i)); 617 } 618 619#if 0 620 // MSHR access formulas 621 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 622 MemCmd cmd(access_idx); 623 const string &cstr = cmd.toString(); 624 625 mshrAccesses[access_idx] 626 .name(name() + "." + cstr + "_mshr_accesses") 627 .desc("number of " + cstr + " mshr accesses(hits+misses)") 628 .flags(total | nozero | nonan) 629 ; 630 mshrAccesses[access_idx] = 631 mshr_hits[access_idx] + mshr_misses[access_idx] 632 + mshr_uncacheable[access_idx]; 633 } 634 635 demandMshrAccesses 636 .name(name() + ".demand_mshr_accesses") 637 .desc("number of demand (read+write) mshr accesses") 638 .flags(total | nozero | nonan) 639 ; 640 demandMshrAccesses = demandMshrHits + demandMshrMisses; 641 642 overallMshrAccesses 643 .name(name() + ".overall_mshr_accesses") 644 .desc("number of overall (read+write) mshr accesses") 645 .flags(total | nozero | nonan) 646 ; 647 overallMshrAccesses = overallMshrHits + overallMshrMisses 648 + overallMshrUncacheable; 649#endif 650 651 // MSHR miss rate formulas 652 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 653 MemCmd cmd(access_idx); 654 const string &cstr = cmd.toString(); 655 656 mshrMissRate[access_idx] 657 .name(name() + "." + cstr + "_mshr_miss_rate") 658 .desc("mshr miss rate for " + cstr + " accesses") 659 .flags(total | nozero | nonan) 660 ; 661 mshrMissRate[access_idx] = 662 mshr_misses[access_idx] / accesses[access_idx]; 663 664 for (int i = 0; i < system->maxMasters(); i++) { 665 mshrMissRate[access_idx].subname(i, system->getMasterName(i)); 666 } 667 } 668 669 demandMshrMissRate 670 .name(name() + ".demand_mshr_miss_rate") 671 .desc("mshr miss rate for demand accesses") 672 .flags(total | nozero | nonan) 673 ; 674 demandMshrMissRate = demandMshrMisses / demandAccesses; 675 for (int i = 0; i < system->maxMasters(); i++) { 676 demandMshrMissRate.subname(i, system->getMasterName(i)); 677 } 678 679 overallMshrMissRate 680 .name(name() + ".overall_mshr_miss_rate") 681 .desc("mshr miss rate for overall accesses") 682 .flags(total | nozero | nonan) 683 ; 684 overallMshrMissRate = overallMshrMisses / overallAccesses; 685 for (int i = 0; i < system->maxMasters(); i++) { 686 overallMshrMissRate.subname(i, system->getMasterName(i)); 687 } 688 689 // mshrMiss latency formulas 690 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 691 MemCmd cmd(access_idx); 692 const string &cstr = cmd.toString(); 693 694 avgMshrMissLatency[access_idx] 695 .name(name() + "." + cstr + "_avg_mshr_miss_latency") 696 .desc("average " + cstr + " mshr miss latency") 697 .flags(total | nozero | nonan) 698 ; 699 avgMshrMissLatency[access_idx] = 700 mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 701 702 for (int i = 0; i < system->maxMasters(); i++) { 703 avgMshrMissLatency[access_idx].subname( 704 i, system->getMasterName(i)); 705 } 706 } 707 708 demandAvgMshrMissLatency 709 .name(name() + ".demand_avg_mshr_miss_latency") 710 .desc("average overall mshr miss latency") 711 .flags(total | nozero | nonan) 712 ; 713 demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 714 for (int i = 0; i < system->maxMasters(); i++) { 715 demandAvgMshrMissLatency.subname(i, system->getMasterName(i)); 716 } 717 718 overallAvgMshrMissLatency 719 .name(name() + ".overall_avg_mshr_miss_latency") 720 .desc("average overall mshr miss latency") 721 .flags(total | nozero | nonan) 722 ; 723 overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 724 for (int i = 0; i < system->maxMasters(); i++) { 725 overallAvgMshrMissLatency.subname(i, system->getMasterName(i)); 726 } 727 728 // mshrUncacheable latency formulas 729 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 730 MemCmd cmd(access_idx); 731 const string &cstr = cmd.toString(); 732 733 avgMshrUncacheableLatency[access_idx] 734 .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 735 .desc("average " + cstr + " mshr uncacheable latency") 736 .flags(total | nozero | nonan) 737 ; 738 avgMshrUncacheableLatency[access_idx] = 739 mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 740 741 for (int i = 0; i < system->maxMasters(); i++) { 742 avgMshrUncacheableLatency[access_idx].subname( 743 i, system->getMasterName(i)); 744 } 745 } 746 747 overallAvgMshrUncacheableLatency 748 .name(name() + ".overall_avg_mshr_uncacheable_latency") 749 .desc("average overall mshr uncacheable latency") 750 .flags(total | nozero | nonan) 751 ; 752 overallAvgMshrUncacheableLatency = 753 overallMshrUncacheableLatency / overallMshrUncacheable; 754 for (int i = 0; i < system->maxMasters(); i++) { 755 overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i)); 756 } 757 758} 759